Memory device, flash memory controller and associated control method

Abstract

This invention discloses a control method for a flash memory controller, comprising the following steps: receiving multiple data entries from a host device; encoding the multiple data entries to generate multiple codewords, wherein each codeword contains corresponding data and a check code; writing the multiple codewords into a data page of a block of a flash memory module; receiving a read command from the host device, wherein the read command requests to read the multiple codewords stored in the data page; reading the multiple codewords from the data page; sequentially decoding the multiple codewords to generate a decoding result; and if the decoding result indicates that at least one of the multiple codewords cannot be successfully decoded, then using information from the successfully decoded codewords to decode the undecoded codewords.

Description

[Technical Field]

[0001] This invention relates to a flash memory controller. [Previous Technology]

[0002] With the development of Low-Density Parity-Check (LDPC) codes, encoders in flash memory controllers can encode data to generate error correction codes (ECCs) with more bits, and can also encode data with more bits to generate longer codewords, further improving their error correction capabilities. For example, common encoders may include 4-kilobyte (KB) LDPC encoders, which encode 4KB of data into corresponding codewords. The latest 16KB LDPC encoders can encode 16KB of data into a codeword with better error correction performance.

[0003] However, while the codewords generated by 16KB LDPC encoders provide better error correction capabilities during subsequent decoding, they occupy a larger chip area and may encounter decoding efficiency issues in certain situations. For example, the data size from the host device may be less than 16KB, such as 4KB. In this case, the 16KB LDPC encoder needs to encode four 4KB data entries to generate the corresponding 16KB codeword and store this 16KB codeword in a data page of a block in the flash memory module. Then, if the host device sends a read request to read 4KB of data from the flash memory module, the decoder still needs to read the entire 16KB codeword from the data page and decode it, instead of just decoding the 4KB codeword. Therefore, decoding efficiency is affected in this case. In particular, if the host device frequently sends read requests that only require 4KB of data, the decoder efficiency will be severely reduced in this case. [Summary of the Invention]

[0004] Therefore, the object of the present invention is to provide a control method for a flash memory controller, which utilizes a cooperative codeword mechanism for encoding and decoding operations to solve the problems described in the prior art.

[0005] In one embodiment of the present invention, a control method for a flash memory controller is disclosed, comprising the following steps: receiving multiple data entries from a host device; encoding the multiple data entries to generate multiple codewords, wherein each codeword includes corresponding data and a check code; writing the multiple codewords into a data page of a block of a flash memory module; receiving a read command from the host device, wherein the read command requests to read the multiple codewords stored in the data page; reading the multiple codewords from the data page; sequentially decoding the multiple codewords to generate a decoding result; and if the decoding result indicates that at least one of the multiple codewords cannot be successfully decoded, then using information from the successfully decoded codewords to decode the undecoded codewords.

[0006] In one embodiment of the present invention, a flash memory controller is disclosed, comprising a read-only memory, a microprocessor, an encoder, and a decoder. The microprocessor, the encoder, and the decoder are configured to perform the following steps: receiving multiple data entries from a host device; encoding the multiple data entries to generate multiple codewords, wherein each codeword contains corresponding data and a check code; writing the multiple codewords into a data page of a block of the flash memory module; receiving a read command from the host device, wherein the read command requests the reading of the multiple codewords stored in the data page; reading the multiple codewords from the data page; sequentially decoding the multiple codewords to generate a decoding result; and if the decoding result indicates that at least one of the multiple codewords cannot be successfully decoded, then using information from the successfully decoded codewords to decode the undecoded codewords.

[0007] In one embodiment of the present invention, a memory device is disclosed, comprising a flash memory module and a flash memory controller. The flash memory controller is configured to perform the following operations: receive multiple data entries from a host device; encode the multiple data entries to generate multiple codewords, wherein each codeword contains corresponding data and a check code; write the multiple codewords into a data page of a block of the flash memory module; receive a read command from the host device, wherein the read command requests to read the multiple codewords stored in the data page; read the multiple codewords from the data page; sequentially decode the multiple codewords to generate a decoding result; and if the decoding result indicates that at least one of the multiple codewords cannot be successfully decoded, then use information from the successfully decoded codewords to decode the undecoded codewords.

Implementation Method

[0009] Figure 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, wherein the flash memory controller 110 is used to access the flash memory module 120. The flash memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory 112M is used to store program code 112C, and the microprocessor 112 executes the program code 112C to control the access of the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a randomizer 136, and a derandomizer 138. Encoder 132 is used to encode the data written to flash memory module 120 to generate a corresponding parity check code (also known as an error correction code (ECC)); decoder 134 is used to decode the data read from flash memory module 120. Randomizer 136 is used to randomize the data written to flash memory module 120, while derandomizer 138 is used to derandomize the data read from flash memory module 120.

[0010] In general, the flash memory module 120 includes multiple flash memory chips, and each flash memory chip includes multiple blocks. A controller (e.g., a flash memory controller 110 executing code 112C via microprocessor 112) can copy, erase, and merge data in the flash memory module 120 in blocks. Furthermore, a block can record a certain number of data pages, where the controller (e.g., the flash memory controller 110 executing code 112C via microprocessor 112) can perform data write operations on the flash memory module 120 in pages. In other words, a block is the smallest unit of erasure in the flash memory module 120, and a data page is the smallest unit of write in the flash memory module 120.

[0011] In actual operation, the flash memory controller 110, which executes program code 112C through the microprocessor 112, can use its internal components to perform many control operations. For example, the microprocessor 112 uses control logic 114 to control the access of flash memory module 120 (more specifically, access at least one block or at least one data page), uses buffer memory 116 and / or dynamic random access memory (DRAM) 140 to perform the required buffering operations, and uses interface logic 118 to communicate with the host device 130.

[0012] In one embodiment, the memory device 100 may be a portable memory device conforming to SD / MMC, CF, MS, and XD specifications, such as a memory card, while the host device 130 is an electronic device capable of connecting to the memory device 100, such as a mobile phone, laptop, or desktop computer. In another embodiment, the memory device 100 may be a solid-state drive (SSD) or embedded storage device conforming to Universal Flash Storage (UFS) or embedded Multi-Media Card (eMMC) specifications, and may be installed in an electronic device. For example, the memory device 100 may be installed in a mobile phone, watch, portable medical monitoring device (e.g., medical wristband), laptop, or desktop computer. In this case, the host device 130 may be a processor in the electronic device.

[0013] In this embodiment, the flash memory module 120 is a three-dimensional (3D) NAND flash memory, wherein each block consists of multiple word lines, multiple bit lines, and multiple memory cells. Since the 3D NAND flash memory architecture is well known to those skilled in the art, related descriptions are omitted in the specification.

[0014] Figure 2 is a schematic diagram of block 200 in a flash memory module 120 according to an embodiment of the present invention, wherein the flash memory module 120 may be a 3D NAND flash memory module. As shown in Figure 2, block 200 includes multiple memory cells (e.g., floating gate transistors 202 or other charge trapping elements), which form a 3D NAND flash memory mechanism through multiple bit lines (e.g., bit lines BL1-BL3 shown in the figure) and word lines (e.g., word lines WL0-WL2, WL4-WL6 shown in the figure). Taking the uppermost plane in Figure 2 as an example, all floating gate transistors on word line WL0 form at least one data page, all floating gate transistors on word line WL1 form another data page, all floating gate transistors on word line WL2 further form at least another data page, and so on. Furthermore, the relationship between word lines WL0 and data pages (i.e., logical data pages) differs depending on the writing method of flash memory. Specifically, when using Single-Level Cell (SLC) writing, all floating-gate transistors on word lines WL0 correspond to only one logical data page (i.e., each memory cell stores only one bit, and block 200 is an SLC block); when using Multi-Level Cell (MLC) writing, all floating-gate transistors on word lines WL0 correspond to two logical data pages (i.e., each memory cell stores two bits, and block 200 is an MLC block); when using Triple-Level Cell (TLC) writing, all floating-gate transistors on word lines WL0 correspond to three logical data pages (i.e., each memory cell stores three bits, and block 200 is a TLC block); when using Quad-Level Cell (TLC) writing, the relationship between word lines WL0 and data pages differs depending on the writing method of flash memory. When writing to a Cell (QLC), all floating gate transistors on the word line WL0 correspond to four logic data pages (that is, each memory cell stores four bits, and block 200 is a QLC block). Since those skilled in the art should easily understand the structure of 3D NAND flash memory and the relationship between word lines and data pages, a detailed description is omitted here for the sake of brevity.

[0015] Encoder 132 is an LDPC encoder that encodes data from autonomous device 130 to generate at least one codeword (i.e., encoded data) and stores the codeword in flash memory module 120. In this embodiment, to reduce the chip area of ​​encoder 132, a cooperative codeword mechanism is employed, which can achieve near-high-bit-count encoding operations using lower-bit-count encoding operations. For example, encoder 132 is a 4KB encoder with a smaller chip area and is configured to use the cooperative codeword mechanism to encode data to generate data with 16KB of encoded information. Therefore, when flash memory controller 110 needs to read data from flash memory module 120, decoder 134 (which is the 4KB encoder with a smaller chip area) can provide better error correction capabilities when decoding data.

[0016] Figure 3 is a schematic diagram of an encoder 132 encoding data to generate codewords and writing the codewords into a flash memory module according to an embodiment of the present invention. As shown in Figure 3, the main device 130 sends at least one write command, and the microprocessor 112 executes at least one write command to allow the autonomous device 130 to read multiple 4KB data. Then, the encoder 132 sequentially encodes the multiple 4KB data to generate corresponding codewords. In this embodiment, since the encoder 132 is a 4KB encoder that encodes 4KB of data at a time, the encoder 132 uses a specially designed checksum checking matrix and checksum generation matrix to generate the corresponding codewords.

[0017] The encoder 132 includes a check code checking matrix and a check code generation matrix. The check code generation matrix is ​​used to perform multiplication with 4KB of data to generate corresponding codewords (the codewords contain 4KB of data and the corresponding check code (also called ECC)). The check code checking matrix is ​​used to check whether the codewords generated by the encoder 132 are correct. For example, after the encoder 132 encodes 4KB of data to generate the corresponding codewords, it multiplies the 4KB of data containing the check code with the check code checking matrix to generate a multiplication result. If the multiplication result is "0", the encoding is considered correct; if the multiplication result is not equal to "0", the encoding is considered incorrect. There is a specific relationship between the check code generation matrix and the check code checking matrix. Figure 4 is a schematic diagram of the check code checking matrix and the check code generation matrix according to an embodiment of the present invention. As shown in Figure 4, the check code checking matrix is ​​a c*t matrix, which can be divided into a c*(tc) matrix M on the left and a c*c matrix K on the right. To find the checksum generation matrix corresponding to the checksum check matrix, the inverse matrix K-1 of matrix K can first be found. Then, the inverse matrix K-1 is multiplied by matrix M to generate matrix P. The transpose of matrix P combined with an identity matrix can then be used as the checksum generation matrix. In other words, encoder 132 can multiply the 4KB data from main device 130 with the transpose and identity matrix of matrix P to obtain the codeword corresponding to the 4KB data, and then multiply this codeword by the checksum check matrix to determine if the encoding is correct.

[0018] In this embodiment, the design of the check code generation matrix and the check code checking matrix allows the 4KB codewords generated by the encoder 132 to satisfy the checks of two check code checking matrices with different codeword lengths. The 4KB codeword contains 4KB of data and the corresponding check code, so its actual size is slightly larger than 4KB. Taking Figure 3 as an example, each 4KB codeword is encoded using a 4KB check code generation matrix; therefore, the product of the 4KB codeword and the 4KB check code checking matrix is ​​"0". Furthermore, four 4KB codewords can be considered as a single 16KB codeword. The product of this 16KB codeword and the 16KB check code checking matrix is ​​also "0". The 16KB check code checking matrix can be considered as a virtual large matrix, containing four 4KB check code checking matrices on its diagonal, with the remaining parts being a zero matrix.

[0019] In the embodiment shown in Figure 3, after four 4KB codewords are successfully generated, the encoder 132 writes these four 4KB codewords (i.e., a single 16KB codeword) into a data page of a block in the flash memory module 120 (assuming that the size of each data page is 16KB).

[0020] Figure 5 is a flowchart of a control method for a flash memory controller 110 according to an embodiment of the present invention. Referring to the above embodiment, the process is as follows.

[0021] Step 500: Process begins.

[0022] Step 502: Receive multiple data from the main device in sequence.

[0023] Step 504: Encode the multiple data entries to generate multiple codewords.

[0024] Step 506: Write the multiple codewords into a data page of a block in the flash memory module.

[0025] Figure 6 is a flowchart of a control method for a flash memory controller 110 according to an embodiment of the present invention, wherein the flowchart in Figure 6 is located after step 506. At step 600, the process begins. At step 602, the flash memory controller 110 autonomous device 130 receives a read command requesting the reading of data corresponding to the four codewords (four 4KB codewords) shown in Figure 3, wherein these four codewords are stored in a data page of the flash memory module 120. At step 604, in response to the read command, the flash memory controller 110 reads the four 4KB codewords from the data page in the flash memory module 120. At step 606, the decoder 134 uses the aforementioned 4KB checksum check matrix to sequentially decode the four 4KB codewords in an attempt to generate decoded data. In step 608, decoder 134 determines whether any of the four 4KB codewords cannot be successfully decoded. If so, the process proceeds to step 612; otherwise, the process proceeds to step 610.

[0026] In step 610, since all 4KB codewords have been successfully decoded, the microprocessor 112 transmits the decoded data to the host device 130.

[0027] In step 612, decoder 134 uses information from successfully decoded codewords to decode codewords that failed to be decoded. For example, if only one of the four codewords failed to be decoded, decoder 134 uses information from three successfully decoded codewords to decode the failed codeword. In another example, if two of the four codewords failed to be decoded, decoder 134 uses information from two successfully decoded codewords to decode the two failed codewords. In yet another example, if three of the four codewords failed to be decoded, decoder 134 uses information from one successfully decoded codeword to decode the three failed codewords.

[0028] Specifically, the LDPC decoding method is based on the principle of updating check node information and bit node information, where check nodes correspond to columns of the parity check matrix, and bit nodes correspond to rows of the parity check matrix. In this embodiment, since each 4KB codeword corresponds to a 4KB parity check matrix, and the entire 16KB codeword containing four 4KB codewords corresponds to a 16KB parity check matrix, the decoder 134 can update the check node information corresponding to the 16KB parity check matrix during the decoding process, and use this check node information to decode codewords that were not successfully decoded.

[0029] In addition, if all four 4KB codewords cannot be successfully decoded, or if the decoder 134 still cannot decode some codewords, the microprocessor 112 will send a message to the host device 130 to notify that the reading has failed.

[0030] In brief, by using the encoding and decoding methods of this invention, the decoder 134 can decode each codeword using a faster 4KB decoding method and achieve 16KB decoding performance. Furthermore, compared to a 16KB decoder, the decoder 134 has a smaller chip area. Therefore, the flash memory controller 110 can achieve good decoding performance with a smaller chip area. The above description is only a preferred embodiment of this invention. All equivalent variations and modifications made within the scope of the claims of this invention should be considered within the scope of this invention. [Simplified Explanation of the Diagram]

[0008] Figure 1 is a schematic diagram of a memory device according to an embodiment of the present invention. Figure 2 is a schematic diagram of a block in a flash memory module according to an embodiment of the present invention. Figure 3 is a schematic diagram of an encoder encoding data to generate codewords and writing the codewords to the flash memory module according to an embodiment of the present invention. Figure 4 is a schematic diagram of a checksum checking matrix and a checksum generation matrix according to an embodiment of the present invention. Figure 5 is a flowchart of a control method for a flash memory controller according to an embodiment of the present invention. Figure 6 is a flowchart of a control method for a flash memory controller according to an embodiment of the present invention.

Claims

1. A control method for a flash memory controller, comprising: receiving multiple data entries from a host device; encoding the multiple data entries to generate multiple codewords, wherein each codeword includes corresponding data and a check code; writing the multiple codewords into a data page of a block of a flash memory module; receiving a read command from the host device, wherein the read command requests reading the multiple codewords stored in the data page; reading the multiple codewords from the data page; sequentially decoding the multiple codewords to generate a decoding result; and if the decoding result indicates that at least one of the multiple codewords cannot be successfully decoded, then using information from the successfully decoded codewords to decode the undecoded codewords; wherein the step of encoding the multiple data entries to generate the multiple codewords includes: encoding the multiple data entries using a first check code generation matrix and a first check code checking matrix to generate the multiple codewords; The product of each of the plurality of codewords and the first check matrix is ​​equal to zero, and the product of all the plurality of codewords and the second check matrix is ​​equal to zero. The first check matrix and the second check matrix correspond to different codeword lengths.

2. The control method as described in claim 1, wherein the multiple data entries are four 4-kilobyte (KB) data entries, the first checksum check matrix is ​​a 4KB checksum check matrix, and the second checksum check matrix is ​​a 16KB checksum check matrix.

3. The control method as described in claim 1, wherein if the decoding result indicates that at least one of the plurality of codewords cannot be successfully decoded, the step of using information of the successfully decoded codewords to decode the undecoded codewords includes: updating a check node information corresponding to the second check matrix during the decoding of the plurality of codewords; and using the check node information corresponding to the second check matrix to decode the undecoded codewords.

4. The control method as described in claim 3, wherein the multiple data entries are four 4KB data entries, the first checksum check matrix is ​​a 4KB checksum check matrix, and the second checksum check matrix is ​​a 16KB checksum check matrix.

5. A flash memory controller, comprising: a read-only memory for storing code; and a microprocessor for executing the code to control access to a flash memory module. The microprocessor, encoder, and decoder are configured to perform the following steps: receiving multiple data entries from a host device; encoding the multiple data entries to generate multiple codewords, each codeword containing corresponding data and a checksum; writing the multiple codewords into a data page of a block of the flash memory module; receiving a read command from the host device, wherein the read command requests the reading of the multiple codewords stored in the data page; reading the multiple codewords from the data page; and sequentially decoding the multiple codewords to generate a decoding result. And if the decoding result indicates that at least one of the multiple codewords cannot be successfully decoded, then the information of the successfully decoded codewords is used to decode the undecoded codewords; wherein the step of encoding the multiple data to generate the multiple codewords includes: encoding the multiple data using a first check code generation matrix and a first check code checking matrix to generate the multiple codewords; wherein the product of each of the multiple codewords with the first check code checking matrix is ​​equal to zero, and the product of all the multiple codewords with a second check code checking matrix is ​​equal to zero, and the first check code checking matrix and the second check code checking matrix correspond to different codeword lengths.

6. The flash memory controller as described in claim 5, wherein the multiple data entries are four 4-kilobyte (KB) data entries, the first checksum check matrix is ​​a 4KB checksum check matrix, and the second checksum check matrix is ​​a 16KB checksum check matrix.

7. The flash memory controller as described in claim 5, wherein if the decoding result indicates that at least one of the plurality of codewords cannot be successfully decoded, the step of using information of the successfully decoded codewords to decode the undecoded codewords includes: updating a check node information corresponding to the second check matrix during the decoding of the plurality of codewords; and using the check node information corresponding to the second check matrix to decode the undecoded codewords.

8. The flash memory controller as described in claim 7, wherein the multiple data entries are four 4KB data entries, the first checksum check matrix is ​​a 4KB checksum check matrix, and the second checksum check matrix is ​​a 16KB checksum check matrix.

9. A memory device comprising: a flash memory module; and a flash memory controller for accessing the flash memory module; wherein the flash memory controller is configured to perform the following operations: receiving multiple data entries from a host device; encoding the multiple data entries to generate multiple codewords, wherein each codeword includes corresponding data and a check code; writing the multiple codewords into a data page of a block of the flash memory module; receiving a read command from the host device, wherein the read command requests reading the multiple codewords stored in the data page; reading the multiple codewords from the data page; sequentially decoding the multiple codewords to generate a decoding result; and if the decoding result indicates that at least one of the multiple codewords cannot be successfully decoded, decoding the undecoded codeword using information from the successfully decoded codeword; wherein the step of encoding the multiple data entries to generate the multiple codewords includes: encoding the multiple data entries using a first check code generation matrix and a first check code checking matrix to generate the multiple codewords; The product of each of the plurality of codewords and the first check matrix is ​​equal to zero, and the product of all the plurality of codewords and the second check matrix is ​​equal to zero. The first check matrix and the second check matrix correspond to different codeword lengths.

10. The memory device as described in claim 9, wherein the multiple data entries are four 4-kilobyte (KB) data entries, the first checksum check matrix is ​​a 4KB checksum check matrix, and the second checksum check matrix is ​​a 16KB checksum check matrix.

11. The memory device as described in claim 9, wherein if the decoding result indicates that at least one of the plurality of codewords cannot be successfully decoded, the step of decoding the undecoded codeword using information of the successfully decoded codeword includes: updating a check node information corresponding to the second check matrix during the decoding of the plurality of codewords; and using the check node information corresponding to the second check matrix to decode the undecoded codeword.

12. The memory device as described in claim 11, wherein the plurality of data entries are four 4KB data entries, the first checksum check matrix is ​​a 4KB checksum check matrix, and the second checksum check matrix is ​​a 16KB checksum check matrix.

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