Semiconductor device and forming method thereof

Abstract

This disclosure describes a method for forming a semiconductor device, including forming an opening in a nanostructure stack, wherein gate spacers and internal spacers serve as sidewalls of the opening. The method may further include applying an oxide plasma to the nanostructure stack in the opening, and to the surfaces of the gate spacers and internal spacers serving as sidewalls of the opening. In some embodiments, the oxide plasma forms a uniformly thick oxide surface on the nanostructure stack in the opening, the surface of the gate spacers, and the surface of the internal spacers. The method may further include forming a high-dielectric-constant gate dielectric on the uniformly thick oxide surface on the nanostructure stack in the opening, the surface of the gate spacers, and the surface of the internal spacers, and forming a gate electrode on the high-dielectric-constant gate dielectric.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. [Summary of the Invention]

[0004] None

Implementation Method

[0006] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, this document may use spatial relative terms such as "below," "under," "lower," "above," "upper," etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0008] In various embodiments, methods and structures for spacer treatment and interfacial layer (IL) formation in stacked nanostructure devices are described. For example, in some embodiments of the method, spacer treatment and interfacial layer formation on the nanostructure are performed simultaneously, wherein the spacer treatment and interfacial layer formation treatment include radical oxidation. In some embodiments, radical oxidation of the spacer treatment may be applied to gate spacers and / or internal spacers within a nanostructure stack including nanostructure channels and gate all-around (GAA) gate structure devices. In some embodiments, a plasma oxidation process provides uniform radical oxidation of the spacers. In some embodiments, a plasma oxidation process provides non-uniform oxidation, resulting in the formation of V-shaped spacer oxide spacers.

[0009] In some embodiments, when the plasma oxidation process applied to the spacer is performed simultaneously with the formation of the interface layer on the nanostructure, the methods described herein can reduce parasitic capacitance and enhance the integrity of the interface layer. In some embodiments, reducing parasitic capacitance can improve the alternating circuit (AC) performance of the device circuitry. Furthermore, the oxidation method used to form the interface layer can improve the reliability of the device.

[0010] The following describes embodiments of a die including a nanostructure field-effect transistor (nano-FET) in a specific context. However, various embodiments may be applied to dies including other types of transistors (e.g., stacked transistors or the like) instead of or in combination with nano-FETs.

[0011] Figure 1 illustrates a three-dimensional view of an example of a nano-FET (e.g., a nanowire field-effect transistor, a nanosheet field-effect transistor, or the like) according to some embodiments. For ease of illustration, certain features are simplified and / or omitted in Figure 1. The nano-FET includes a nanostructure 54 (e.g., a nanosheet, nanowire, or the like) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 54 acts as a channel region of the nano-FET. The nanostructure 54 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 (also referred to as STI structures or STI regions) are disposed between adjacent fins 66, wherein the fins 66 may protrude above and between adjacent STI regions 68. Although the STI regions 68 are described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom portion of fin 66 is depicted as being made of a single continuous material with substrate 50, the bottom portion of fin 66 and / or substrate 50 may comprise a single material or a plurality of materials. In this context, fin 66 refers to the portion extending between adjacent STI regions 68.

[0012] The gate dielectric layer 100 is located above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 54. The gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102. Depending on the context, the (multiple) source / drain regions 92 may individually or collectively represent a source or drain.

[0013] Figure 1 further illustrates reference cross sections used in subsequent figures. Cross section AA′ is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current direction between the epitaxial source / drain regions 92 of the nano-FET. Cross section BB′ is perpendicular to cross section AA′ and parallel to the longitudinal axis of the fin 66 of the nano-FET, for example, in the current direction between the epitaxial source / drain regions 92 of the nano-FET. Cross section CC′ is parallel to cross section AA′ and extends through the epitaxial source / drain regions of the nano-FET. For clarity, subsequent figures refer to these reference cross sections.

[0014] Some embodiments discussed herein are described in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments are envisioned for use in planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0015] Figures 2 through 20C are cross-sectional views of intermediate stages in the fabrication of a nano-FET according to some embodiments. Figures 2 through 20A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 15C, 15E, 17A, 17C, 17E, 18A, 18C, 18E, 19A, and 20A illustrate the reference cross-section AA′ shown in Figure 1. Figures 5B, 6B, 7B, 8B, 9B, 10B, 10C, 10D, 11B, 12B, 13B, 14B, 15B, 15D, 15F, 17B, 17D, 17C, 17F, 18B, 18D, 18F, 19B, and 20B illustrate the reference cross section BB′ shown in Figure 1. Figures 7C, 11C, 11D, 19C, and 20C illustrate the reference cross section CC′ shown in Figure 1.

[0016] A substrate 50 is provided in Figure 2. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, wherein the semiconductor substrate may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium arsenide phosphide), or combinations thereof.

[0017] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an n-type metal oxide semiconductor (NMOS) transistor, for example, an n-type nano-FET. The p-type region 50P can be used to form a p-type device, such as a p-type metal oxide semiconductor (PMOS) transistor, for example, a p-type nano-FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided. Unless otherwise stated, the following figures describe processing steps that can be performed in either the n-type region 50N or the p-type region 50P.

[0018] In Figure 2, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, as discussed in more detail below, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form channel regions for a nano-FET in both the n-type region 50N and the p-type region 50P. However, in some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions for a nano-FET in both the n-type region 50N and the p-type region 50P. For example, the channel regions in the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or other semiconductor materials) and may be formed simultaneously.

[0019] In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region for a nano-FET in the p-type region 50P, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region for a nano-FET in the n-type region 50N. In still other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region for a nano-FET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region for a nano-FET in the p-type region 50P. In such embodiments, the channel region of the n-type region 50N may have a different material composition than the channel region of the p-type region 50P. The first semiconductor layer 51 and the second semiconductor layer 53 may be selectively removed from each of the n-type region 50N and the p-type region 50P through additional masking and etching steps. For example, the channel region of the n-type region 50N can be a silicon channel region, while the channel region of the p-type region 50P can be a silicon-germanium channel region.

[0020] For illustrative purposes, the multilayer stack 64 is illustrated as including three first semiconductor layers 51 and three second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. The layers in the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods.

[0021] In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material (such as silicon germanium or the like), and the second semiconductor layer 53 may be formed of a second semiconductor material (such as silicon, silicon carbon, or the like). The first semiconductor material and the second semiconductor material may be materials that have high etch selectivity to each other. Thus, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nano-FET.

[0022] Referring now to Figure 3, according to some embodiments, fins 66 are formed in a substrate 50, and nanostructures 55 are formed in a multilayer stack 64. In some embodiments, the nanostructures 55 and fins 66 may be formed in the multilayer stack 64 and substrate 50, respectively, by etching trenches 58 in the multilayer stack 64 and substrate 50. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or combinations thereof. The etching may be anisotropic. During the etching process, a hard mask may be used to define the patterning of the fins 66 and nanostructures 55. The hard mask may include any suitable insulating material, such as oxides, nitrides, oxynitrides, and carbon oxynitrides or the like. In some embodiments (not specifically shown), the hard mask may be a multilayer structure. Forming a hard mask over the nanostructure 55 can be achieved using acceptable processes such as thermal oxidation, physical vapor deposition (PVD), CVD, ALD, combinations thereof, or similar methods.

[0023] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more optical lithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine optical lithography with a self-aligned process, thereby allowing the pitch of the pattern to be smaller than that achievable, for example, using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins 66 and nanostructures 55.

[0024] By etching and stacking multiple layers 64 to form a nanostructure 55, a first nanostructure 52A to a first nanostructure 52C (collectively referred to as the first nanostructure 52) can be further defined from a first semiconductor layer 51, and a second nanostructure 54A to a second nanostructure 54C (collectively referred to as the second nanostructure 54) can be defined from a second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can be further collectively referred to as nanostructure 55.

[0025] For ease of illustration, Figure 3 illustrates fins 66 with substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the width of the fins 66 in the p-type region 50P. Furthermore, although Figure 3 illustrates that the individual fins 66 and nanostructures 55 have consistently uniform widths, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each of the fins 66 or nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, the nanostructures 55 may have different widths and be trapezoidal in shape.

[0026] In Figure 4, the STI region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66, to fill the trench 58. The insulating material can be an oxide, nitride, or similar combination thereof, such as silicon oxide, and can be formed by high-density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), or similar combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, forming the insulating material will cause excess insulating material to cover the nanostructure 55. Although the insulating material is drawn as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 50, fins 66, and nanostructures 55. A filler material, such as those discussed above, may then be formed over the liner.

[0027] Next, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etching back, a combination thereof, or the like, may be used. The planarization process exposes the nanostructure 55 such that the nanostructure 55 is flush with the top surface of the insulating material after the planarization process is completed.

[0028] Next, the insulating material is recessed to form the STI region 68. The recessed insulating material causes the upper portion of the fin 66 to protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (such as a dish shape), or a combination thereof, as shown. The top surface of the STI region 68 may be formed as flat, convex, and / or concave by appropriate etching. Acceptable etching processes can be used to recess the STI region 68, such as etching processes selectively applied to the insulating material (e.g., etching the insulating material at a faster rate than etching the material of the fin 66 and the nanostructure 55). For example, dilute hydrofluoric acid (dHF) can be used to remove oxides.

[0029] Furthermore, in Figure 4, suitable traps (not specifically shown) may be formed in the fins 66 and / or nanostructures 55. In embodiments with different trap types, photoresist or other masks (not specifically shown) may be used to achieve different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist may be formed over the fins 66 and nanostructures 55 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin-coating technique and may be patterned using an acceptable optical lithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted in the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, or the like in the implantation region, and the concentration of the n-type impurity may be in the range of about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist is removed using an acceptable ashing process.

[0030] Before or after implantation of the p-type region 50P, a photoresist or other mask (not specifically shown) is formed over the fins 66 and nanostructures 55 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin-coating technique and can be patterned using an acceptable optical lithography technique. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from implanting into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, or the like in the implantation region, and the p-type impurity concentration is in the range of about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist can be removed by an acceptable ashing process.

[0031] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, thus omitting the implantation step, but in-situ doping and implantation doping may also be used together.

[0032] In Figures 5A and 5B, a dummy gate is formed above the nanostructure 55 and the fin 66 and along their sidewalls. To form the dummy gate, a dummy dielectric layer is first formed above the fin 66 and / or the nanostructure 55. The dummy dielectric layer may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed above the dummy dielectric layer, and a masking layer is formed above the dummy gate layer. The dummy gate layer may be deposited above the dummy dielectric layer, followed by planarization, such as by CMP. The masking layer may be deposited above the dummy gate layer. The dummy gate layer may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicates, metal oxides, and metals. The dummy gate layer can be deposited using PVD, CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer can be made of other materials that have high etch selectivity for the etch isolation region. The masking layer can include, for example, silicon nitride, silicon oxynitride, or the like.

[0033] Subsequently, the mask layer can be patterned using acceptable optical lithography and etching techniques to form mask 78. The pattern of mask 78 can then be transferred to a dummy gate layer and a dummy dielectric layer to form dummy gate 76 and dummy gate dielectric 70, respectively. The dummy gate 76 covers individual channel regions of the fin 66. The pattern of mask 78 can be used to separate each of the dummy gates 76 from adjacent dummy gate 76 entities. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the individual fin 66. It should be noted that, for illustrative purposes only, the dummy gate dielectric 70 covering only the fin 66 and nanostructure 55 is shown. In some embodiments, the dummy gate dielectric 70 may be deposited such that the dummy gate dielectric 70 covers the STI region 68, thus extending between the dummy gate 76 and the STI region 68.

[0034] In Figures 6A and 6B, a gate spacer 81 is formed over the nanostructure 55 and the STI region 68, and on the exposed sidewalls of the mask 78 (if present), the dummy gate 76, and the dummy gate dielectric 70. The gate spacer 81 can be formed by conformally forming one or more dielectric materials and subsequently etching the dielectric materials(s). Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or the like, which can be formed by chemical vapor deposition, atomic layer deposition, or similar deposition processes. Other insulating materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, wet etching, the like, or combinations thereof, can be performed to pattern the dielectric materials(s). The etching may be anisotropic. During etching, the dielectric material leaves a portion of the material on the sidewalls of the dummy gate 76, thereby forming a gate spacer 81. As described in more detail later, during etching, the dielectric material may also leave a portion of the material on the sidewalls of the semiconductor fin 66 and / or nanostructure 55, thereby forming a fin spacer 83 (refer to Figure 7C). After etching, the fin spacer 83 and / or the gate spacer 81 may have straight sidewalls (as shown) or may have curved sidewalls (not specifically shown).

[0035] Further, implantation for a lightly doped source / drain (LDD) region (not specifically shown) can be performed. LDD implantation can be performed prior to the formation of the gate spacer 81. In embodiments with different device types, similar to the previously described well implantation, a mask (such as a photoresist) can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the exposed semiconductor fin 66 and nanostructure 55 in the p-type region 50P. The mask can then be removed. Subsequently, a mask (such as a photoresist) can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the exposed semiconductor fin 66 and nanostructure 55 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the previously discussed n-type impurities, and the p-type impurity can be any of the previously discussed p-type impurities. Lightly doped source / drain regions can have impurity concentrations ranging from 10¹⁵ atoms / cm³ to 10¹⁹ atoms / cm³. Annealing can be used to repair implantation damage and activate implanted impurities.

[0036] It should be noted that the previously disclosed content generally describes the process for forming spacers and LDD regions. Other processes and sequences may also be used. For example, fewer or more spacers may be used, different step sequences may be used, and additional spacers and / or similar elements may be formed and removed. Furthermore, n-type devices and p-type devices may be formed using different structures and steps.

[0037] In Figures 7A to 7C, according to some embodiments, a first groove 86 is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region is then formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. As shown in Figure 7C, the top surface of the STI region 68 may be flush with the bottom surface of the first groove 86. In other embodiments, the fin 66 may be etched such that the bottom surface of the first groove 86 is disposed above or below the top surface of the STI region 68. The first groove 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process (such as RIE, NBE, or similar). During the etching process used to form the first groove 86, a gate spacer 81, a fin spacer 83, and a mask 78 shield a portion of the fin 66, nanostructure 55, and substrate 50. The layers in the nanostructure 55 and / or fin 66 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to terminate the etching of the first groove 86 after the first groove 86 has reached the desired depth.

[0038] In Figures 8A to 9B, the first nanostructure 52 is replaced by a sacrificial material 72 (also referred to as a disposable oxide interposer, DOI). Replacing the first nanostructure 52 may include etching away the first nanostructure 52 using a suitable etching process (such as an isotropic etching process), which is performed via the first groove 86, as shown in Figures 8A to 9B. The etching process may be selective in the material of the first nanostructure 52, removing the first nanostructure 52 without significantly removing the second nanostructure 54 or the semiconductor fin 66. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructure 52.

[0039] Subsequently, a sacrificial material layer 71 is deposited in the first recess 86 and in the space where the first nanostructure 52 has been removed. The deposition of the sacrificial material layer 71 may be performed by a conformal deposition process, such as CVD, ALD, or the like. The sacrificial material layer may include an insulating material, such as silicon oxide (e.g., SiO2) or the like, wherein the insulating material may be selectively etched relative to the second nanostructure 54. In Figures 9A and 9B, the sacrificial material layer 71 is then etched to form a sacrificial material 72. The etching may be isotropic or anisotropic. For example, the sacrificial material layer may be etched by a wet etching process using diluted HF or the like as an etchant. In some embodiments, etching is performed until the sidewalls of the sacrificial material 72 are recessed beyond the sidewalls of the nanostructure 54. Although the sidewalls of the sacrificial material 72 are shown as straight in Figure 9B, the sidewalls may be concave or convex (e.g., refer to Figure 10C).

[0040] Replacing the first nanostructure 52 with a sacrificial material 72 offers advantages. For example, in subsequent source / drain formation steps, one or more high-temperature processes can be performed to, for example, activate dopants in the source / drain regions. When the material of the first nanostructure 52 (e.g., SiGe) is exposed to high temperatures, germanium mixing may occur, increasing the roughness at the interface between the first nanostructure 52 and the second nanostructure 54. Such manufacturing defects can degrade the performance of the resulting transistor device. For example, when germanium diffuses into the second nanostructure 54, germanium residue may remain in the channel region of the resulting transistor device, negatively impacting the performance of the channel region. By replacing the first nanostructure 52 with an insulating material prior to high-temperature processes (e.g., source / drain annealing), manufacturing defects can be reduced and device performance improved (e.g., increased current drive, reduced capacitance, and improved short-channel effects).

[0041] In Figures 10A and 10B, an internal spacer 90 is formed on the sidewall of the sacrificial material 72 in the first recess 86. The internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the sacrificial material 72 will be replaced by the corresponding gate structure. The internal spacer 90 can also be used to prevent subsequent etching processes (such as etching processes for forming the gate structure) from damaging the subsequently formed source / drain regions. In some embodiments, a portion of the internal spacer 90 may extend to the sidewall of the gate spacer 81.

[0042] The internal spacer 90 can be formed by depositing an internal spacer layer (not specifically shown) over the structure shown in Figures 9A and 9B. The internal spacer layer can be deposited by a conformal deposition process, such as CVD, ALD, or the like. The internal spacer layer may include materials such as silicon nitride or silicon oxynitride, but any suitable material may also be used, such as a low-k material having a dielectric constant (k value) of less than about 3.5. The internal spacer layer can then be anisotropically etched to form the internal spacer 90. The internal spacer layer can be etched by anisotropic etching processes (such as RIE, NBE, or the like).

[0043] Although the outer wall of the internal spacer 90 is shown flush with the sidewall of the second nanostructure 54, the outer wall of the internal spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54 (e.g., refer to Figure 10C). Furthermore, although the outer wall of the internal spacer 90 is shown straight in Figure 10B, the outer wall of the internal spacer 90 may be concave or convex. As an example, Figure 10C illustrates an embodiment in which the sidewall of the sacrificial material 72 is concave, the outer wall of the internal spacer 90 is concave, and the internal spacer 90 is recessed from the sidewall of the second nanostructure 54. Other configurations are also possible. For example, Figure 10D illustrates an embodiment in which the sidewall of the sacrificial material 72 is concave, the outer wall of the internal spacer 90 is straight, and the internal spacer 90 is flush with the sidewall of the second nanostructure 54. Furthermore, in some embodiments, a portion of the internal spacer 90 may extend to the sidewall of the gate spacer 81, as illustrated in the figures.

[0044] In Figures 11A to 11D, epitaxial source / drain regions 92 are formed in the first recess 86. In some embodiments, the source / drain regions 92 may apply stress to the second nanostructure 54 in the n-type region 50N and / or the first nanostructure 52 in the p-type region 50P, thereby improving performance. As shown in Figure 11B, the epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between individual adjacent pairs of epitaxial source / drain regions 92. In some embodiments, gate spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and internal spacers 90 are used to separate the epitaxial source / drain regions 92 from the sacrificial material 72 by an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit with the gate subsequently formed of the resulting nano-FET.

[0045] An epitaxial source / drain region 92 in an n-type region 50N (e.g., an NMOS region) can be formed by shielding the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may comprise any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 in the n-type region 50N may comprise a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0046] The epitaxial source / drain region 92 in the p-type region 50P (e.g., PMOS region) can be formed by shielding the n-type region 50N (e.g., NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material suitable for a p-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 in the p-type region 50P can include a material that applies compressive strain to the second nanostructure 54, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like.

[0047] The epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 may be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain region may have an impurity concentration between about 1 x 10¹⁹ atoms / cm³ and about 1 x 10²¹ atoms / cm³. The n-type and / or p-type impurities used for the source / drain region may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain region 92 may be in-situ doped during growth.

[0048] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nano-FET to merge, as shown in Figure 11C. In other embodiments, as shown in Figure 11D, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed. In the embodiments shown in Figures 11C and 11D, fin spacers 83 may be formed on the top surface of the STI region 68. In some other embodiments, the fin spacers 83 may cover a portion of the sidewalls of the nanostructure 55, further hindering epitaxial growth. In some other embodiments, the spacer etching used to form the fin spacers 83 may be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0049] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0050] In Figures 12A and 12B, a first interlayer dielectric (ILD) 96 is deposited over the structures shown in Figures 11A and 11B, respectively. The first interlayer dielectric 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric 96 and the epitaxial source / drain region 92, the mask 78, and the gate spacer 81. The contact etch stop layer 94 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and has an etch rate different from that of the overlying first interlayer dielectric 96.

[0051] After depositing the first interlayer dielectric 96, a planarization process such as CMP can be performed to make the top surface of the first interlayer dielectric 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and a portion of the gate spacer 81 along the sidewall of the mask 78. After the planarization process, the top surface of the dummy gate 76, the gate spacer 81, and the first interlayer dielectric 96 are flush within process tolerances. Therefore, the first interlayer dielectric 96 exposes the top surface of the dummy gate 76. In some embodiments, the mask 78 may be retained. In this case, the planarization process makes the top surface of the first interlayer dielectric 96 flush with the top surfaces of the mask 78 and the gate spacer 81.

[0052] In Figures 13A and 13B, the dummy gate 76 and mask 78 (if present) are removed in one or more etching steps to form a second recess 98. A portion of the dummy gate dielectric 70 may also be removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 70 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (multiple) reactive gases that selectively etch the dummy gate 76 at a faster rate than etching the first interlayer dielectric 96 or the gate spacer 81. Each second recess 98 exposes and / or covers a portion of nanostructures 55, which serve as channel regions in the subsequently completed nano-FET. The portion of the nanostructures 55 serving as channel regions is disposed between adjacent pairs of epitaxial source / drain regions 92. During etching to remove the dummy gate 76, the dummy gate dielectric 70 may be used as an etch stop layer. Next, the dummy gate dielectric 70 can be removed after the dummy gate 76 is removed.

[0053] In Figures 14A and 14B, sacrificial material 72 is removed, thereby extending the second groove 98. Removing sacrificial material 72 may include performing an isotropic etching process (such as wet etching or the like) using an etchant selective for the material of sacrificial material 72, while the second nanostructure 54 remains relatively unetched compared to sacrificial material 72. Sacrificial material 72 may be completely removed, or residue of sacrificial material 72 may remain on the sidewalls of the internal spacers in the second groove 98 (e.g., refer to Figure 15C).

[0054] In some embodiments, the STI region 68 may be etched while the sacrificial material 72 is being removed, but the total loss of the STI region 68 may be reduced by controlling the etching parameters (e.g., timing) while removing the sacrificial material 72. In other embodiments, the STI region 68 may include a hard mask (not specifically shown) at its top surface to protect the underlying STI region 68 from etching during patterning and removal of the sacrificial material 72. In such embodiments, the hard mask may include, for example, a nitride.

[0055] Figures 15A to 15F illustrate some embodiments of free radical plasma oxidation for spacer treatment (e.g., treatment of internal spacer 90 and gate spacer 81) and formation of interface layer 200 on second nanostructures 54A, 54B, and 54C. Plasma oxidation of the spacer treatment and formation of interface layer 200 can reduce parasitic capacitance and improve the AC performance of device circuit operation. Furthermore, in some embodiments, free radical oxidation can improve the oxide integrity of interface layer 200, thus improving device reliability.

[0056] Figures 15A and 15B illustrate spacer treatment (e.g., treatment of gate spacer 81 and internal spacer 90) using uniform free radical plasma oxidation, and the formation of interface layer 200 on second nanostructures 54A, 54B, and 54C. In some embodiments, gate spacer 81 and internal spacer 90 may be composed of nitride-containing dielectrics. In some instances, internal spacer 90 and gate spacer 81 may be composed of dielectrics including SiOCN, Si3N4, SiC, SiCN, or combinations thereof. In some embodiments, to reduce parasitic capacitance, a high-dielectric-constant dielectric material may be formed on the surfaces of internal spacer 90 and gate spacer 81 exposed by removing the dummy gate 76. The presence of an oxide surface is advantageous for forming a high-dielectric-constant dielectric material. However, in some embodiments, the nitrogen concentration of internal spacer 90 and gate spacer 81 may be high enough to produce antioxidant properties. In some embodiments, an inductively coupled plasma (ICP) system 500 (refer to Figure 16) is used to oxidize the exposed surfaces of spacers (e.g., the exposed surfaces of gate spacers 81 and internal spacers 90), which may produce O2 plasma or a combination of Ar and O2 plasma.

[0057] An example of an inductively coupled plasma system 500 is illustrated in Figure 16. In some embodiments, the inductively coupled plasma system 500 generates inductively coupled plasma by coupling energy from a radio frequency generator to a suitable gas via a magnetic field (induced through a two- or three-turn water-cooled copper coil). In some instances, the radio frequency energy is typically supplied at a frequency of 27.12 MHz, providing positive power at a power between 500 W and 2000 W. In some instances, two gas streams, typically containing argon (Ar), flow tangentially through the outer tube of a concentric three-tube quartz torch, which is axially positioned within the copper coil. The gas flows tangentially through the outer and middle tubes (i.e., in a vortex state as it passes through the torch), thus the plasma continuously rotates and has a "weak point" at the center of the substrate through which an inner tube gas stream containing a sample for generating oxidizing free radicals (e.g., oxygen) can be introduced. In some embodiments, the conditions for oxygen radical (O*) generation (conditions for radical plasma oxidation) are temperatures ranging from 200°C to approximately 600°C. If the temperature is too high, the oxygen radical plasma will produce an excessively thick oxide layer, unsuitable for use in interface layer 200, and the process may be difficult to control. If the temperature is too low, the energy may be too weak to generate enough oxide to meet the basic electrical requirements, and leakage current may therefore occur.

[0058] In some embodiments, a spark is used to provide electrons to oxygen, which are then accelerated in a magnetic field to an energy sufficient to ionize gaseous atoms (e.g., oxygen and OH radicals) in the field. Subsequent collisions with other gaseous atoms lead to further ionization, thereby forming a self-sustaining plasma.

[0059] The plasma generated in the inductively coupled plasma system 500, such as oxidative radical plasma, can be collimated onto the deposition substrate 101 via collimator 501. In some embodiments, collimator 501 can remove any ions from the generated plasma that may damage the coated surface. The deposition substrate 101 may include any of the structures illustrated in Figures 15A through 15F.

[0060] In some embodiments, the lifetime of oxygen free radicals can be 1000 times longer than that of O2+ ions. In some embodiments, due to the longer lifetime of oxygen free radicals, they can diffuse downwards to achieve uniform oxidation.

[0061] In the embodiments illustrated in Figures 15A and 15B, the gate spacer 81 and the inner spacer 90 are oxidized to provide a uniform thickness oxide surface 201 extending from the upper surface of the uppermost gate spacer 81 to the lowermost surface of the inner spacer 90. Uniform thickness means that the thickness of the oxide material is substantially the same along the entire length of the oxide surface, for example, a uniform thickness oxide surface 201 formed on the gate spacer 81 and the inner spacer 90.

[0062] As described above, while forming oxide surfaces on the spacers (e.g., gate spacer 81 and internal spacer 90), the same oxygen free radical oxidation plasma is used to form interface layers 200 on the second nanostructures 54A, 54B, and 54C. Referring to Figure 15B, the oxide surface of interface layer 200A on the uppermost nanostructure 54C has the same thickness as the oxide surface of interface layer 200C on the lowermost nanostructure 54A. The nanostructure 54B between the upper nanostructure 54C and the lower nanostructure 54A also has an oxide surface of interface layer 200B, which has the same thickness as the oxide surfaces of the other nanostructures (e.g., interface layers 200A and 200C). It should be noted that this example only illustrates three second nanostructures (second nanostructure 54A, second nanostructure 54B, and second nanostructure 54C), and the embodiments disclosed herein are not intended to be limited to this example. Any number of nanostructures and any number of interface layers are suitable for use with the methods and structures described herein. It should be noted that the uniformly thick oxide surface 201 on the interface layer 200, gate spacer 81, and internal spacer 90 may be silicon oxide with a low dielectric constant. However, the subsequently formed high dielectric constant dielectric will have a dielectric constant suitable for reducing parasitic capacitance. Furthermore, for the embodiments shown in Figures 15A to 15B, the gate spacer 81 and internal spacer 90 are not consumed by the oxide surface generated by oxygen radicals of the plasma.

[0063] In some instances, the uniform oxidation illustrated in Figures 15A to 15B offers several advantages and benefits. For example, the simultaneous formation of the interface layer 200 and the spacer treatment allows for easy integration into replacement gate process flows, such as post-gate process flows. Uniform oxidation can provide reduced parasitic capacitance (Ceff) for device AC operation. Furthermore, the uniform interface layer 200 is better suited for gate control. Interface layer integrity provides higher reliability and supports an expanded process window.

[0064] Figures 15C to 15D illustrate another embodiment employing oxygen-ion plasma oxidation to create a V-shaped spatial plasma oxide surface 202 on the spacers (e.g., gate spacer 81 and internal spacer 90). The V-shaped spatial plasma oxide surface 202 reduces parasitic capacitance. Further, similar to the embodiment described with reference to Figures 15A to 15B, plasma oxidation can form an interface layer 200 on the second nanostructures 54A, 54B, and 54C simultaneously with forming the oxide surface of the spacers (e.g., gate spacer 81 and internal spacer 90). The interface layer 200 improves oxide integrity, thereby enhancing reliability.

[0065] Similar to the embodiments described in Figures 15A to 15B, the oxide surfaces of the second nanostructures 54A, 54B, 54C, internal spacer 90, and gate spacer 81 can be generated by oxygen radicals including inductively coupled plasma, which can be generated by the inductively coupled plasma system 500 illustrated in Figure 16. In some embodiments, for oxygen (O) ion plasma oxidation, the lifetime of O* radicals is 1000 times longer than that of O2+ ions. In some instances, due to the shorter lifetime of O2+ ions, V-shaped oxides can be formed. One process condition for generating the V-shaped spatial plasma oxide surface 202 using the oxygen plasma of the inductively coupled plasma system 500 is that the temperature applied to the oxygen-containing gas is in the range of about 200°C to about 600°C.

[0066] In the embodiments illustrated in Figures 15C and 15D, the gate spacer 81 and the inner spacer 90 are oxidized to provide a V-shaped spatial plasma oxide surface 202 extending from the upper surface of the uppermost gate spacer 81 to the lowermost surface of the inner spacer 90. The V-shaped spatial plasma oxide surface 202 has a non-uniform thickness, for example, a non-uniform thickness extending along the height direction of the V-shaped spatial plasma oxide surface 202. More specifically, the V-shaped spatial plasma oxide surface 202 formed on the gate spacer 81 and the inner spacer 90 has the maximum thickness, for example, the maximum width, at the uppermost portion of the gate spacer 81. For example, the oxidation process providing the V-shaped spatial plasma oxide surface 202 may consume the entire upper portion of the gate spacer 81. Further, the V-shaped spatial plasma oxide surface 202 formed on the gate spacer 81 and the inner spacer 90 may have its minimum thickness, for example, the minimum width, at the base of the lowermost inner spacer 90.

[0067] As described above, while forming oxide surfaces on spacers (e.g., gate spacer 81 and internal spacer 90), an interface layer 200 is formed on the second nanostructures 54A, 54B, and 54C using an oxidizing plasma with the same oxygen free radicals. Referring to Figure 15D, the oxide surface of the interface layer 200A′ on the uppermost nanostructure 54C has a greater thickness than the oxide surface of the interface layer 200C′ on the lowermost nanostructure 54A. The nanostructure 54B between the upper nanostructure 54C and the lower nanostructure 54A has an oxide surface of the interface layer 200B′, the thickness of which is less than the thickness of the oxide surface of the uppermost interface layer 200A′ but greater than the thickness of the oxide surface of the lowermost interface layer 200C′. It should be noted that this example illustrates only three second nanostructures (second nanostructure 54A, second nanostructure 54B, and second nanostructure 54C), but the embodiments disclosed herein are not intended to be limited to this example. Any number of nanostructures and any number of interface layers are also suitable for use with the methods and structures described herein.

[0068] The gate spacer 81 and the internal spacer 90 may be silicon oxide with a low dielectric constant. However, the subsequently formed high dielectric constant dielectric will have a dielectric constant suitable for reducing parasitic capacitance. Furthermore, for the embodiments illustrated in Figures 15C to 15D, the gate spacer 81 and the internal spacer 90 as a whole do not need to be consumed by the oxide surface generated by oxygen free radicals of the plasma.

[0069] In some instances, the oxidation illustrated in Figures 15C to 15D offers several advantages and benefits. For example, the simultaneous formation of the interface layer 200 and spacer treatment allows for easy integration into replacement gate process flows, such as post-gate process flows. The V-shaped spacer plasma oxide surface 202 can actively reduce parasitic capacitance for device AC operation (e.g., more actively than the uniform oxidation illustrated in Figures 15A to 15B). Additionally, the interface layer 200 is better suited for gate control. Interface layer integrity provides higher reliability and supports an expanded process window.

[0070] Figures 15E to 15F illustrate another embodiment in which oxygen-ion plasma oxidation is used to completely consume spacers, such as internal spacer 90 and gate spacer 81, to produce a plasma oxide surface 203. The plasma oxide surface 203, which completely consumes internal spacer 90 and gate spacer 81, reduces parasitic capacitance. Further, similar to the embodiment described with reference to Figures 15A to 15D, while forming the oxide surface on the spacers (e.g., gate spacer 81 and internal spacer 90), plasma oxidation can form an interface layer 200 on the second nanostructures 54A, 54B, and 54C. The interface layer 200 contributes to the integrity of the oxide, thereby improving reliability.

[0071] Similar to the embodiments described in Figures 15A to 15D, the oxide surfaces of the second nanostructures 54A, 54B, and 54C, the internal spacer 90, and the gate spacer 81 can be generated by oxygen radicals, including an inductively coupled plasma, which can be generated by the inductively coupled plasma system 500 illustrated in Figure 16. In some embodiments, for oxygen (O) ion plasma oxidation, the lifetime of O* radicals is 1000 times longer than that of O2+ ions. In some instances, due to the shorter lifetime of O2+ ions, a plasma oxide surface 203 that completely consumes the internal spacer 90 and the gate spacer 81 can be formed. Furthermore, to generate a plasma oxide surface 203 that completely consumes the internal spacer 90 and the gate spacer 81, sufficient process time and pressure may be required to completely convert the spacers into SiO2. For example, the process time for completely consuming the spacers can be in the range of 1 minute to 5 minutes. If the time is too short, oxidation may be insufficient. If the time is too long, oxidation may be excessive. For example, the pressure range for completely consuming the spacer can be from about 0.1 Torr to about 4 Torr. If the pressure is too low, the amount of ions / radicals may not be sufficient to oxidize the spacer. If the pressure is too high, oxidation may be excessive. Another process condition for producing the plasma oxide surface 203 of completely consuming the internal spacer 90 and the gate spacer 81 using the inductively coupled plasma system 500 is a temperature range of about 200°C to about 600°C applied to the oxygen-containing gas. In the embodiments illustrated in Figures 15E and 15F, the gate spacer 81 and the internal spacer 90 are oxidized until completely consumed.

[0072] As described above, while forming oxide surfaces on the spacers (e.g., gate spacer 81 and internal spacer 90), an interface layer 200 is formed on the second nanostructures 54A, 54B, and 54C using the same oxygen free radical oxidizing plasma. Referring to Figure 15E, the oxide surface of the interface layer 200A′ on the uppermost nanostructure 54C has a thickness greater than that of the oxide surface of the interface layer 200C′ on the lowermost nanostructure 54A. The nanostructure 54B between the upper nanostructure 54C and the lower nanostructure 54A has an oxide surface of the interface layer 200B′, the thickness of which is less than the thickness of the oxide surface of the uppermost interface layer 200A′ but greater than the thickness of the oxide surface of the lowermost interface layer 200C′. It should be noted that this example illustrates only three second nanostructures (second nanostructure 54A, second nanostructure 54B, and second nanostructure 54C), but the embodiments disclosed herein are not intended to be limited to this example. Any number of nanostructures and any number of interface layers are suitable for use with the methods and structures described herein. Note that the uniformly thick oxide surface 201 on the interface layer 200, gate spacer 81, and internal spacer 90 may be silicon oxide with a low dielectric constant. However, a subsequently formed high dielectric constant dielectric will have a dielectric constant suitable for reducing parasitic capacitance.

[0073] In some instances, the oxidation illustrated in Figures 15E to 15F offers several advantages and benefits. For example, the simultaneous formation of the interface layer 200 and spacer treatment allows for easy integration into replacement gate process flows, such as post-gate process flows. The plasma oxide surface 203, which completely consumes the internal spacer 90 and the gate spacer 81, can aggressively reduce parasitic capacitance for device AC operation (e.g., more aggressively than the V-shaped spacer plasma oxide surface 202 illustrated in Figures 15C to 15D). Additionally, the interface layer 200 is better suited for gate control. Interface layer integrity provides higher reliability and supports an expanded process window.

[0074] In some embodiments, a wet cleaning process may be applied to the oxide surface after plasma oxidation as described with reference to Figures 15A to 15F. The wet cleaning process can increase the concentration of OH groups on the oxide surface. In embodiments, the wet cleaning process may include standard clean 1 (SC1) at a temperature ranging from 30°C to 90°C. In one example, standard clean 1 comprises 5 parts deionized water, 1 part ammonia (29% NH3), and 1 part hydrogen peroxide (30% H2O2). In some embodiments, after wet cleaning, the oxide surface has -OH groups for subsequent ALD processes to deposit a high-dielectric-constant dielectric.

[0075] In Figures 17A to 17F, a high-dielectric-constant gate dielectric layer 100 is formed to replace the gate. Figures 17A to 17B illustrate the formation of a high-dielectric-constant dielectric layer 100 on the uniform-thickness oxide surface 201 of the interface layer 200 and the spacers shown in Figures 15A to 15B. Figures 17C to 17D illustrate the formation of a high-dielectric-constant dielectric layer 100 on the V-shaped space plasma oxide surface 202 of the interface layer 200 and the spacers shown in Figures 15C to 15D. Figures 17E to 17F illustrate the formation of a high-dielectric-constant dielectric layer 100 on the interface layer 200 and the plasma oxide surface 203, wherein the plasma oxide surface 203 completely consumes the internal spacers 90 and the gate spacers 81 shown in Figures 15E to 15F.

[0076] The high dielectric constant gate dielectric layer 100 is conformally deposited on the oxide surface of the spacers (e.g., gate spacers 81 and internal spacers 90) in the second groove 98 and on the oxide surface of the interface layer 200. The gate dielectric layer 100 may be further deposited on the top surface of the first interlayer dielectric 96, the contact etch stop layer 94, the gate spacers 81, and the STI region 68.

[0077] According to some embodiments, the gate dielectric layer 100 comprises a high dielectric constant dielectric material. In these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, and lead, or combinations thereof. In one example, the high dielectric constant gate dielectric layer 100 is composed of hafnium oxide. The structure of the high dielectric constant gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The gate dielectric layer 100 may be formed by atomic layer deposition. However, other deposition methods may also be used to form the high dielectric constant gate dielectric layer 100, including molecular beam deposition (MBD), PECVD, and the like.

[0078] Figures 18A to 18F illustrate gate electrodes 102 deposited above the gate dielectric layer 100 and filling the remaining portion of the second groove 98. Figures 18A to 18B illustrate gate electrodes 102 formed on the high-dielectric-constant gate dielectric layer 100 illustrated in Figures 17A to 17B. Figures 18C to 18D illustrate gate electrodes 102 formed on the high-dielectric-constant gate dielectric layer 100 illustrated in Figures 17C to 17D. Figures 18E to 18F illustrate gate electrodes 102 formed on the high-dielectric-constant gate dielectric layer 100 of the structure illustrated in Figures 17E to 17F.

[0079] The gate electrode 102 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 102 is shown in Figures 18A to 18E, the gate electrode 102 may include any number of liner layers, any number of work function tuning layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 in the n-type region 50N and between the second nanostructure 54A and the substrate 50, and may be deposited between adjacent first nanostructures 52 in the p-type region 50P.

[0080] Gate dielectric layers 100 in both the n-type region 50N and the p-type region 50P can be formed simultaneously, such that the gate dielectric layers 100 in each region are formed of the same material, and gate electrodes 102 can be formed simultaneously, such that the gate electrodes 102 in each region are formed of the same material. In some embodiments, the gate dielectric layers 100 in each region can be formed by different processes, such that the gate dielectric layers 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrodes 102 in each region can be formed by different processes, such that the gate electrodes 102 can be made of different materials and / or have different numbers of layers. When different processes are used, various masking steps can be used to mask and expose appropriate regions.

[0081] After filling the second recess 98, a planarization process such as CMP can be performed to remove excess material portions of the gate dielectric layer 100 and the gate electrode 102 located above the top surface of the first interlayer dielectric 96. Thus, the remaining material portions of the gate electrode 102 and the gate dielectric layer 100 form an alternative gate structure for the resulting nano-FET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0082] The gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed, thereby forming a groove between the gate structure and the opposite portion of the gate spacer 81. A gate shield 104 comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like) is filled into the groove, followed by a planarization process to remove excess dielectric material extending above the first interlayer dielectric 96. The subsequently formed gate contacts (such as gate contacts 114 discussed below with reference to Figures 20A to 20C) penetrate the gate shield 104 to contact the top surface of the recessed gate electrode 102.

[0083] As further shown in Figures 18A to 18F, a second interlayer dielectric 106 is deposited over the first interlayer dielectric 96 and over the gate shield 104. In some embodiments, the second interlayer dielectric 106 is a flowable film formed by FCVD. In some embodiments, the second interlayer dielectric 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method, such as CVD, PECVD, or the like.

[0084] In Figures 19A to 19C, the second interlayer dielectric 106, the first interlayer dielectric 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a third groove 108 that exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third groove 108 may be formed by etching using an anisotropic etching process (such as RIE, NBE, or the like). In some embodiments, the third groove 108 may be etched through the second interlayer dielectric 106 and the first interlayer dielectric 96 using a first etching process, etched through the gate mask 104 using a second etching process, and then etched through the contact etch stop layer 94 using a third etching process. A mask (such as a photoresist) may be formed over the second interlayer dielectric 106 and patterned to mask a portion of the second interlayer dielectric 106 during the first and second etching processes. In some embodiments, the etching process may over-etch, so the third groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third groove 108 may be flush with the epitaxial source / drain region 92 and / or gate structure (e.g., on the same level or at the same distance from the substrate) or lower than the epitaxial source / drain region 92 and / or gate structure (e.g., closer to the substrate).

[0085] After forming the third groove 108, a silicate region 110 is formed above the epitaxial source / drain region 92. In some embodiments, the silicate region 110 is formed by first depositing a metal (not shown, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or alloys thereof) capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicate or germanide region above the exposed portion of the epitaxial source / drain region 92, followed by performing a thermal annealing process to form the silicate region 110. Then, unreacted portions of the deposited metal are removed, for example, by an etching process. Although the silicate region 110 is referred to as a silicate region, the silicate region 110 may also be a germanide region, or a germanide silicate region (e.g., a region including both silicate and germanide). In an embodiment, the silicate region 110 comprises TiSi and has a thickness ranging from about 2 nm to about 10 nm.

[0086] Next, in Figures 20A to 20C, contacts 112 and 114 (also referred to as contacts) are formed in the third groove 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, each of contacts 112 and 114 includes a barrier layer and a conductive material, and is electrically coupled to an underlying conductive feature (e.g., the gate electrode 102 and / or the silicate region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate electrode 102 and may be referred to as a gate contact. Contact 112 is electrically coupled to the silicate region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP can be performed to remove excess material from the surface of the second interlayer dielectric 106.

[0087] In various embodiments, methods and structures for spacer treatment and interface layer formation in stacked nanosheet devices are described. For example, in some embodiments of the methods, spacer treatment and interface layer formation on the nanostructure are performed simultaneously, wherein the spacer treatment and interface layer formation include radical oxidation. In some embodiments, radical oxidation of the spacer treatment may be applied to gate spacers and / or spacers within a stack of nanosheets, including nanosheet channels and gate-around-gate structure devices. In some embodiments, when an interface layer on the nanostructure is formed simultaneously (e.g., forming an oxide), uniform radical oxidation of the spacers or non-uniform oxidation resulting in the formation of V-shaped spacer oxide spacers can reduce parasitic capacitance and enhance the integrity of the interface layer. In some embodiments, reducing parasitic capacitance can improve the AC performance of device circuit operation. Further, the oxidation method for forming the interface layer can improve the reliability of the device.

[0088] In one embodiment, a method of forming a semiconductor device includes the following steps: forming an opening to a nanostructure stack, wherein gate spacers and internal spacers serve as sidewalls of the opening; applying an oxidizing plasma to the nanostructure stack in the opening and to the surfaces of the gate spacers and internal spacers serving as sidewalls of the opening, wherein the oxidizing plasma forms a uniform thickness oxide surface on the nanostructure stack in the opening and on the surfaces of the gate spacers and internal spacers; forming a high dielectric constant gate dielectric on the uniform thickness oxide surface on the nanostructure stack in the opening, the surface of the gate spacers, and the surface of the internal spacers; and forming a gate electrode on the high dielectric constant gate dielectric. In one embodiment, forming the opening to the nanostructure stack includes removing a replacement gate structure. In one embodiment, applying the oxidizing plasma consumes only a portion of the gate spacers and internal spacers to form a uniform thickness oxide surface, wherein the remaining portions of the gate spacers and internal spacers are free of oxide. In one embodiment, a wet cleaning process is applied to the uniform thickness oxide surface to increase the concentration of -OH groups on the uniform thickness oxide surface. In one embodiment, the uniform-thickness oxide surface has a uniform thickness across its entire height from the upper surface of the gate spacer to the lower surface of the inner spacer. In another embodiment, the uniform-thickness oxide surface has the same thickness on each nanostructure in the nanostructure stack. In one embodiment, a high-dielectric-constant gate dielectric is formed using atomic layer deposition. In one embodiment, the method includes forming source / drain regions that contact the nanostructure stack on opposite sides of the gate electrodes.

[0089] In another embodiment, a method of forming a semiconductor device includes the steps of: forming an opening to a nanostructure stack, wherein gate spacers and internal spacers serve as sidewalls of the opening; applying an oxide plasma to the nanostructure stack in the opening and the surfaces of the gate spacers and internal spacers serving as sidewalls of the opening, wherein the oxide plasma forms a non-uniform thickness oxide surface on the nanostructure stack in the opening; forming a high dielectric constant gate dielectric on the non-uniform thickness oxide surface on the nanostructure stack in the opening; and forming a gate electrode on the high dielectric constant gate dielectric. In one embodiment, forming the opening to the nanostructure stack includes removing a replacement gate structure. In one embodiment, applying the oxide plasma consumes the bulk material of the gate spacers and internal spacers. In one embodiment, the non-uniform thickness oxide surface on the nanostructure stack includes a first thickness oxide surface on an upper nanostructure in the nanostructure stack and a second thickness oxide surface on a lower nanostructure in the nanostructure stack, wherein the thickness of the first thickness oxide surface is greater than the thickness of the second thickness oxide surface. In one embodiment, a non-uniform thickness oxide surface is formed on the surface of the gate spacer and the surface of the inner spacer. In another embodiment, the non-uniform thickness oxide surface has a first width at the upper surface of the gate spacer and a second width at the lower surface of the inner spacer, wherein the first width is greater than the second width. In one embodiment, the method further includes a wet cleaning process applied to the uniform thickness oxide surface to increase the concentration of -OH groups on the uniform thickness oxide surface. In one embodiment, a high dielectric constant gate dielectric is formed using atomic layer deposition. In another embodiment, the method further includes forming source / drain regions of a contact nanostructure stack on opposite sides of the gate electrode.

[0090] In yet another embodiment, a semiconductor device includes a nanostructure stack; a gate structure including a high-dielectric-constant gate dielectric on a first portion of the nanostructure stack and a gate electrode on the high-dielectric-constant gate dielectric; source / drain regions located on opposite sides of the gate structure; and spacers located on sidewalls of the gate electrode, wherein the spacers separate the gate electrode from the source / drain regions in spaces between separated nanostructures in the nanostructure stack, wherein the spacers include an oxide surface having a first width at an upper surface of the nanostructure stack and a second width at a lower surface of the nanostructure stack, wherein the first width is greater than the second width. In one embodiment, the spacers include a nitride-containing material. In one embodiment, the nanostructure stack includes a first interface layer and a second interface layer, the first interface layer having a first thickness for a first nanostructure at an upper surface of the nanostructure stack, and the second interface layer having a second thickness for a second nanostructure at a lower surface of the nanostructure stack.

[0091] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of discussion. Figure 1 illustrates a three-dimensional view of an example of a nanostructure field-effect transistor (nano-FET) according to some embodiments. Figures 2, 3, 4, 5A, 5B, 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11A, 11B, 11C, 11D, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 15C, 15D, 15E, and 15F are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Figure 16 illustrates a cross-sectional view of an example of an inductively coupled plasma system according to some embodiments. Figures 17A, 17B, 17C, 17D, 17E, 17F, 18A, 18B, 18C, 18D, 18E, 18F, 19A, 19B, 19C, 20A, 20B, and 20C are cross-sectional views of intermediate stages in the fabrication of a nano-FET according to some embodiments. [Biomaterial Storage]

[0093] Domestic temporary storage information (please note in order of storage institution, date, and number): None. Foreign temporary storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method of forming a semiconductor device, comprising: An opening is formed into a nanostructure stack, wherein a gate spacer and an internal spacer serve as multiple sidewalls of the opening; An oxide plasma is applied to the nanostructure stack in the opening and to a plurality of surfaces of the gate spacers and the inner spacers that serve as the sidewalls of the opening, wherein the oxide plasma forms a uniform thickness oxide surface on the nanostructure stack in the opening, and forms the uniform thickness oxide surface on the surfaces of the gate spacers and the inner spacers; a high dielectric constant gate dielectric is formed on the uniform thickness oxide surface on the nanostructure stack in the opening and on the surfaces of the gate spacers and the inner spacers; and a gate electrode is formed on the high dielectric constant gate dielectric.

2. The method as claimed in claim 1, wherein applying the oxide plasma consumes only a portion of the gate spacer and the inner spacer to form the uniform thickness oxide surface, wherein a remaining portion of the gate spacer and the inner spacer does not have the uniform thickness oxide surface.

3. The method as described in claim 1, wherein the uniform thickness oxide surface has a uniform thickness over the entire height from an upper surface of the gate spacer to a lower surface of the inner spacer.

4. The method as described in claim 1, wherein the uniform thickness oxide surface has the same thickness on each nanostructure in the nanostructure stack.

5. A method of forming a semiconductor device, comprising: An opening is formed into a nanostructure stack, wherein a gate spacer and an internal spacer serve as multiple sidewalls of the opening; An oxide plasma is applied to the nanostructure stack in the opening and to a plurality of surfaces of the gate spacers and the internal spacers that serve as the sidewalls of the opening, wherein the oxide plasma forms a non-uniform thickness oxide surface on the nanostructure stack in the opening; a high dielectric constant gate dielectric is formed on the non-uniform thickness oxide surface on the nanostructure stack in the opening; and a gate electrode is formed on the high dielectric constant gate dielectric.

6. The method as described in claim 5, wherein applying the oxidizing plasma consumes the entire material of the gate spacer and the internal spacer.

7. The method as described in claim 6, wherein the non-uniform thickness oxide surface on the nanostructure stack includes a first thickness oxide surface on an upper nanostructure in the nanostructure stack and a second thickness oxide surface on a lower nanostructure in the nanostructure stack, wherein a thickness of the first thickness oxide surface is greater than a thickness of the second thickness oxide surface.

8. The method as described in claim 5, wherein the non-uniform thickness oxide surface is formed on the surfaces of the gate spacer and the internal spacer.

9. A semiconductor device, comprising: A nanostructure stack; a gate structure including a high-dielectric-constant gate dielectric and a gate electrode on the high-dielectric-constant gate dielectric; a plurality of source / drain regions on opposite sides of the gate structure; and a spacer on a plurality of sidewalls of the gate electrode, wherein the spacer separates the gate electrode from the source / drain regions in a space between the plurality of separate nanostructures in the nanostructure stack, wherein the spacer includes an oxide surface having a first width at an upper surface of the nanostructure stack and a second width at a lower surface of the nanostructure stack, wherein the first width is greater than the second width.

10. The semiconductor device of claim 9, wherein the nanostructure stack includes a first interface layer and a second interface layer, the first interface layer being used for a first nanostructure at the upper surface of the nanostructure stack and having a first thickness, and the second interface layer being used for a second nanostructure at the lower surface of the nanostructure stack and having a second thickness.

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