Memory device and manufacturing method thereof

Abstract

A method for manufacturing a memory element includes forming a stacked structure on a substrate, wherein the stacked structure includes alternately stacked insulating layers and intermediate layers, and the stacked structure has a stepped structure; forming a first opening, a second opening, and a third opening in the stacked structure, wherein the first, second, and third openings have the same depth; forming a first insulating pillar in the first, second, and third openings; replacing the first insulating pillar in the first opening with a channel pillar; replacing the first insulating pillar in the third opening with a second insulating pillar; removing the first insulating pillar in the second opening; replacing the intermediate layer with a conductor layer from the second opening; forming a slit structure in the second opening; and replacing the second insulating pillar in the third opening with a contact.

Claims

1. A method for manufacturing a memory element, comprising: forming a stacked structure on a substrate, wherein the stacked structure includes a first region, a second region, and a third region, the stacked structure includes a plurality of insulating layers and a plurality of intermediate layers stacked alternately, and the stacked structure has a stepped structure in the third region; forming a plurality of first openings in the first region of the stacked structure, a plurality of second openings in the second region, and a plurality of third openings in the third region, wherein the depths of the first openings, second openings, and third openings are substantially equal; forming a plurality of first insulating pillars in the first openings, second openings, and third openings; replacing the first insulating pillars in the first openings with a plurality of channel pillars; replacing the first insulating pillars in the third openings with a plurality of second insulating pillars; removing the first insulating pillars in the second openings; replacing the intermediate layers with a plurality of conductor layers from the second openings; forming a slit structure in the second openings; and replacing the second insulating pillars in the third openings with a plurality of contacts.

2. The manufacturing method as described in claim 1 further comprises: after removing the first insulating pillars from the second openings, laterally etching the conductor layers such that the second openings are interconnected.

3. The manufacturing method as claimed in claim 1, wherein replacing the first insulating pillars in the third openings with the second insulating pillars comprises: removing the first insulating pillars in the third openings; laterally etching the intermediate layers; forming a plurality of pad insulating layers along the sidewalls of the third openings; and forming the second insulating pillars in the third openings.

4. The manufacturing method as claimed in claim 3, wherein replacing the second insulating pillars in the third openings with the contacts comprises: removing the second insulating pillars in the third openings; laterally etching the pad insulating layer; and forming the contacts in the third openings.

5. The manufacturing method as claimed in claim 3, wherein in the stepped structure of the stacked structure, the outermost portion of any of the intermediate layers of the stacked structure has a dummy contact pad, such that the outermost portion of any of the intermediate layers of the stacked structure has the greatest thickness.

6. The manufacturing method as claimed in claim 5, wherein the intermediate layers are etched laterally while the dummy contact pads are etched laterally to form a plurality of first horizontal openings and a second horizontal opening corresponding to any of the third openings, the thickness of any of the first horizontal openings being less than the thickness of the second horizontal opening, the pad insulating layers completely filling the first horizontal openings and conforming to the second horizontal openings.

7. The manufacturing method as claimed in claim 6, wherein replacing the second insulating pillars in the third openings with the contacts comprises: removing the second insulating pillars in the third openings; laterally etching the pad insulating layers to remove the pad insulating layers in the second horizontal openings and leave the pad insulating layers in the first horizontal openings; and forming the contacts in the third openings.

8. A memory element comprising: a semiconductor substrate; a stacked structure on the semiconductor substrate, wherein the stacked structure includes alternating stacked insulating layers and conductive layers, and the stacked structure has a first region, a second region, and a third region, the stacked structure having a stepped structure in the third region; a plurality of channel pillars in the first region of the stacked structure; a slit structure in the second region of the stacked structure; and a plurality of contacts in the third region of the stacked structure, wherein the contacts penetrate the insulating layers and conductive layers of the stacked structure, the contacts are electrically connected to one of the conductive layers and electrically isolated from the remaining conductive layers, the contacts each having a first portion electrically connected to the corresponding conductive layer and a second portion electrically isolated from the remaining conductive layers, the width of the first portion being greater than the width of the second portion, and the heights of the channel pillars, the slit structure, and the contacts being substantially the same.

9. The memory element as claimed in claim 8, wherein the outline of one of the conductor layers of the slit structure and the stacked structure is composed of a plurality of arcs.

10. The memory element as claimed in claim 8 further comprises: a common source line layer electrically connected to the channel pillars and electrically isolated from the contacts.

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