Wiring layer of package substrate, package substrate and semiconductor package structure

Abstract

A wiring layer of a packaging substrate includes signal vias, isolation pads, a venting hide zone, vents, a buffer zone, and multiple ground vias. The isolation pads are arranged around the signal vias and have a first radius. The venting hide zone is arranged around the signal vias and has a second radius, wherein the second radius is larger than the first radius. The distance between the vents and the signal vias is greater than or equal to the second radius. The buffer zone is arranged around the signal vias and has a third radius, wherein the third radius is greater than or equal to the first radius and less than or equal to the second radius. Ground vias are disposed within the buffer zone.

Claims

1. A wiring layer of a packaging substrate, comprising: a signal via; an isolation pad disposed around the signal via and having a first radius; a venting area disposed around the signal via and having a second radius, wherein the second radius is greater than the first radius; a vent, wherein the distance between the vent and the signal via is greater than or equal to the second radius; a buffer zone disposed around the signal via and having a third radius, wherein the third radius is greater than or equal to the first radius and less than or equal to the second radius; and a plurality of ground vias disposed in the buffer zone and symmetrically and uniformly distributed in the buffer zone around the signal via.

2. The wiring layer as described in claim 1, wherein the difference between the second radius and the first radius is 100 micrometers to 1000 micrometers.

3. The wiring layer as described in claim 1, wherein the number of grounding vias is between 4 and 30.

4. The wiring layer as described in claim 1, wherein the total area of ​​the grounding vias in the buffer zone is between 10% and 100%.

5. A packaging substrate, comprising: a first wiring layer; a second wiring layer; a signal via having a first portion and a second portion, the first portion being disposed on the first wiring layer and the second portion being disposed on the second wiring layer, wherein the diameter of the second portion is smaller than that of the first portion; an isolation pad disposed on the first wiring layer, surrounding the first portion of the signal via and having a first radius; a venting area disposed on the first wiring layer, surrounding the first portion of the signal via and having a second radius, wherein the second radius is larger than the first radius; and a venting hole disposed on the first wiring layer, wherein the distance between the venting hole and the first portion of the signal via is greater than or equal to the second radius. A buffer zone is disposed in the first wiring layer, surrounding the first portion of the signal via as the center, and having a third radius, wherein the third radius is greater than or equal to the first radius and less than or equal to the second radius; and a plurality of ground vias are disposed in the buffer zone of the first wiring layer, and are symmetrically and uniformly distributed in the buffer zone around the first portion of the signal via as the center.

6. The packaging substrate as claimed in claim 5, wherein the first portion of the signal via is a core via, and the second portion of the signal via is a laser via.

7. The packaging substrate as claimed in claim 5, wherein the difference between the second radius and the first radius is 100 micrometers to 1000 micrometers.

8. The package substrate as described in claim 5, wherein the number of grounding vias is between 4 and 30.

9. The package substrate as described in claim 5, wherein the total area of ​​the ground vias in the buffer zone is between 10% and 100%.

10. A semiconductor package structure comprising: a first wafer having a measurement pin; a package substrate having a plurality of wiring layers, one of the wiring layers comprising: a signal via coupled to the measurement pin; an isolation pad disposed around the signal via and having a first radius; an venting barrier disposed around the signal via and having a second radius, wherein the second radius is greater than the first radius; a vent, wherein the distance between the vent and the signal via is greater than or equal to the second radius; a buffer zone disposed around the signal via and having a third radius, wherein the third radius is greater than or equal to the first radius and less than or equal to the second radius; and a plurality of ground vias disposed in the buffer zone and symmetrically and uniformly distributed in the buffer zone around the signal via.

11. The semiconductor package structure as described in claim 10 further includes an interposer layer disposed between the first wafer and the package substrate, and coupled to the measurement pin and the signal via.

12. The semiconductor package structure as described in claim 10, wherein the difference between the second radius and the first radius is 100 micrometers to 1000 micrometers.

13. The semiconductor package structure as described in claim 10, wherein the number of ground vias is between 4 and 30.

14. The semiconductor package structure as described in claim 10, wherein the total area of ​​the ground vias in the buffer zone is between 10% and 100%.

15. The semiconductor package structure as claimed in claim 10, wherein the signal via has a first portion and a second portion, the first portion being disposed on a first wiring layer and the second portion being disposed on a second wiring layer, wherein the diameter of the second portion is smaller than that of the first portion.

16. The semiconductor package structure as described in claim 15, wherein the first portion is a core via and the second portion is a laser via.

17. The semiconductor package structure as described in claim 10 further includes a second chip, the second chip being coupled to the first chip through the package substrate.

18. The semiconductor package structure as described in claim 11 further includes a second wafer coupled to the first wafer through the interposer.

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