Inductor structures in hybrid bonded devices or apparatus and method for forming the same

Abstract

The present invention provides an apparatus comprising: a first semiconductor structure disposed on a second semiconductor structure; and a plurality of metal structures disposed at an interface portion between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first portion of an inductor structure, and the second semiconductor structure includes a second portion of the inductor structure. The plurality of metal structures connect the first portion of the inductor structure to the second portion of the inductor structure.

Description

Technical Field

[0001] The present invention relates generally to hybrid bonding structures, and more specifically to the manufacture of inductors for hybrid bonding semiconductor structures. Prior Technology

[0002] Innovations in semiconductor manufacturing and packaging technologies have enabled the development of smaller, higher-density semiconductor integrated circuit (IC) chips, as well as highly integrated chip modules with high wiring and area array input / output (I / O) contact densities, thus achieving dense packaging of IC chips. For certain applications, high-performance electronic devices are constructed by manufacturing semiconductor devices on individual wafers and bonding these wafers together to build integrated semiconductor device packages. [ ]

[0003] Various conventional techniques, such as two-dimensional (2-D) packaging and three-dimensional (3-D) packaging, can be used to construct semiconductor device package structures. In the case of 2-D packaging, a package structure can be constructed by directly attaching multiple semiconductor IC chips to a package substrate using direct die attachment (DCA) technology (e.g., flip-chip bonding), wherein these semiconductor IC chips are mounted in the package laterally adjacent to each other (e.g., in a single plane, or coplanar with each other). In this respect, 2-D packaging technology may require a relatively large package footprint to accommodate multiple semiconductor IC chips. In addition, the I / O communication paths between adjacent chips can be very long because chip-to-chip I / O communication is performed via chip-substrate-chip connections and interfaces, which can lead to noise and long interconnect lengths, which can reduce signal integrity.

[0004] On the other hand, in the case of 3D packaging, two or more semiconductor IC chips are vertically stacked on top of each other and interconnected. Although 3D packaging can provide improved communication bandwidth between stacked chips, there are various intractable problems associated with 3D packaging.

[0005] For example, some of the problems associated with current 3D packaging methods include, but are not limited to: (i) low capacitance structure; (ii) increased noise from high-frequency power supplies due to high-speed circuit switching; (iii) reduced stack-up yield, requiring more wafer area to mitigate yield loss through, for example, redundancy; (iv) the need for additional wafer processing such as back-side thinning to keep the stacked wafers as thin as possible; and (v) wafer stacking limitations, etc. Summary of the Invention

[0006] The embodiments disclosed herein include hybrid bonding structures and techniques for hybrid bonding of portions of semiconductor and inductor structures to form an inductor.

[0007] In one embodiment, an apparatus includes: a first semiconductor structure disposed on a second semiconductor structure; and a plurality of metal structures at an interface portion of the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first portion of an inductor structure, and the second semiconductor structure includes a second portion of the inductor structure. The plurality of metal structures connect the first portion of the inductor structure to the second portion of the inductor structure.

[0008] In another embodiment, an apparatus includes a first semiconductor die disposed on a second semiconductor die. The first semiconductor die includes a first portion of an inductor structure, and the second semiconductor die includes a second portion of the inductor structure. The first portion of the inductor structure is connected to the second portion of the inductor structure through an interface portion between the first semiconductor die and the second semiconductor die.

[0009] In another embodiment, a device includes: a first semiconductor die bonded to a second semiconductor die; an inductor structure including a first portion disposed within the first semiconductor die and a second portion disposed within the second semiconductor die; and a plurality of metal structures disposed along an interface between the first semiconductor die and the second semiconductor die. The first portion of the inductor structure, the plurality of metal structures, and the second portion of the inductor structure are in electrical contact with each other.

[0010] In another embodiment, a device includes a first semiconductor structure disposed on top of and facing a second semiconductor structure. The device further includes a plurality of metal structures spanning an interface portion between the first and second semiconductor structures. The plurality of metal structures connect a first portion of an inductor on the first semiconductor structure to a second portion of an inductor on the second semiconductor structure.

[0011] In another embodiment, a method includes forming a first semiconductor structure on a first semiconductor substrate, wherein the first semiconductor structure includes a first portion of an inductor structure and a first plurality of metal pads connected to the first portion of the inductor structure. The method further includes forming a second semiconductor structure on a second semiconductor substrate, wherein the second semiconductor structure includes a second portion of the inductor structure and a second plurality of metal pads connected to the second portion of the inductor structure. Each of the first plurality of metal pads is aligned with each of the second plurality of metal pads, and a hybrid bonding process is performed to bond the first semiconductor structure to the second semiconductor structure, wherein the hybrid bonding process integrates the first plurality of metal pads and the second plurality of metal pads to create a plurality of metal structures spanning an interface between the first semiconductor structure and the second semiconductor structure.

[0012] These and other features and advantages of the embodiments described herein will become more apparent from the accompanying drawings and the following detailed description. Simple Explanation of the Diagram

[0013] Figures 1 and 2 depict cross-sectional views of a first semiconductor structure and a second semiconductor structure, each including a portion of an inductor circuit, according to one embodiment of the present invention.

[0014] Figures 3 and 4 depict cross-sectional views of a first semiconductor structure and a second semiconductor structure after the deposition of a bonding-level dielectric layer according to one embodiment of the present invention.

[0015] Figures 5 and 6 depict cross-sectional views of a first semiconductor structure and a second semiconductor structure after photoresist patterning and removal of portions of the bonding layer dielectric layer to form an opening for a metal pad, according to one embodiment of the present invention.

[0016] Figures 7 and 8 depict cross-sectional views of a first semiconductor structure and a second semiconductor structure after photoresist removal and seed / liner deposition according to one embodiment of the present invention.

[0017] Figures 9 and 10 depict cross-sectional views of a first semiconductor structure and a second semiconductor structure after a deposited metal fill layer, according to one embodiment of the present invention.

[0018] Figures 11 and 12 depict cross-sectional views of a first semiconductor structure and a second semiconductor structure after a planarized metal fill layer according to an embodiment of the present invention.

[0019] Figures 13 and 14 depict cross-sectional views of the first semiconductor structure and the second semiconductor structure after the first semiconductor structure is flipped onto the second semiconductor structure and the first semiconductor structure and the second semiconductor structure are aligned, according to one embodiment of the present invention.

[0020] Figure 15 depicts a cross-sectional view of a hybrid bonding process of a first semiconductor structure and a second semiconductor structure according to an embodiment of the present invention.

[0021] Figure 16 depicts a cross-sectional view of a first semiconductor structure and a second semiconductor structure after hybrid bonding according to one embodiment of the present invention.

[0022] Figure 17 depicts a three-dimensional view of a first semiconductor structure and a second semiconductor structure comprising a hybrid bonding of through-silicon vias (TSVs) on a first semiconductor structure and a second semiconductor structure according to an embodiment of the present invention.

[0023] Figures 18A, 18B, and 18C depict respective first three-dimensional views, second three-dimensional views, and top views of a hybrid-connected inductor circuit portion in a first alternative configuration according to an embodiment of the present invention.

[0024] Figures 19A, 19B, and 19C depict respective first three-dimensional views, second three-dimensional views, and top views of a hybrid-connected inductor circuit portion in a second alternative configuration according to an embodiment of the present invention.

[0025] Figures 20A, 20B, and 20C depict respective first three-dimensional views, second three-dimensional views, and top views of a hybrid-connected inductor circuit portion in a third alternative configuration according to an embodiment of the present invention.

[0026] Figures 21A, 21B, and 21C depict respective first three-dimensional views, second three-dimensional views, and top views of a hybrid-connected inductor circuit portion in a fourth alternative configuration according to an embodiment of the present invention.

[0027] Figures 22A, 22B, and 22C depict a first three-dimensional view, a second three-dimensional view, and a top view of a hybrid-connected inductor circuit portion in a fifth alternative configuration according to an embodiment of the present invention.

[0028] Figures 23A, 23B, and 23C depict respective first three-dimensional views, second three-dimensional views, and top views of a hybrid-connected inductor circuit portion in a sixth alternative configuration according to an embodiment of the present invention. Implementation

[0029] The embodiments disclosed herein are discussed in more detail regarding the structures and techniques used for partially combining semiconductor and inductor structures to form inductors. It should be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic illustrations not drawn to scale. Furthermore, for ease of interpretation, one or more layers, structures, and regions of types commonly used to form semiconductor devices or structures may not be explicitly shown in the given figures. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structure. Moreover, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. Specifically, with respect to semiconductor processing steps, it should be emphasized that the description provided herein is not intended to cover all processing steps that may be required to form a functional semiconductor integrated circuit device. More precisely, certain processing steps commonly used to form semiconductor devices, such as wet cleaning and annealing steps, are intentionally omitted herein for the sake of descriptive economy.

[0030] Furthermore, the same or similar element symbols are used throughout the drawings to indicate the same or similar features, elements, or structures, and therefore, detailed explanations of the same or similar features, elements, or structures will not be repeated for each of the figures. It should be understood that the terms "about" or "substantially" used herein with respect to thickness, width, percentage, range, etc., mean approximately or approximate, but not precisely. For example, the terms "about" or "substantially" used herein imply that small margins of error may exist, such as 1% or less than the stated amount. The term "illustrative" used herein means "serving as an example, example, or illustration." Any embodiment or design described herein as "illustrative" should not be construed as superior or more advantageous than other embodiments or designs. The phrase “above” as used herein to describe the formation of a feature (e.g., a layer) “on” a side or surface means that the feature (e.g., a layer) may be formed “directly” on the implied side or surface (i.e., in direct contact with the implied side or surface), or that the feature (e.g., a layer) may be formed “indirectly” on the implied side or surface, wherein one or more additional layers are disposed between the feature (e.g., a layer) and the implied side or surface.

[0031] Furthermore, as used herein, the term "semiconductor die" or "die" refers to a block of semiconductor material on which a given functional circuit (e.g., memory circuitry, processor circuitry, etc.) and metallization layers (e.g., front-end online (FEOL), mid-end online (MOL), and back-end online (BEOL) metallization layers) are fabricated. Similarly, a semiconductor structure can also refer to a block of semiconductor material on which a given functional circuit and metallization layers are fabricated.

[0032] To provide spatial context for the different structural orientations of the semiconductor structures shown in the diagrams, XYZ Cartesian coordinates are displayed in these diagrams. The terms "vertical," "vertical direction," or "vertical height" as used herein refer to the Z-direction of the Cartesian coordinates shown in the diagrams, and the terms "horizontal," "horizontal direction," "lateral," or "lateral direction" as used herein refer to the X-direction and / or Y-direction of the Cartesian coordinates shown in the diagrams.

[0033] As used in this article, "high K" refers to a dielectric material having a relative permittivity greater than 7.

[0034] As used in this article, "low k" refers to a dielectric material having a relative permittivity of less than 7, and includes ultra-low k dielectric materials.

[0035] As used herein, "hybrid bonding" refers to a 3D filling technique for connecting semiconductor structures. Hybrid bonding forms connections between semiconductor structures via metal pads embedded in a dielectric layer at the bonding interfaces of the semiconductor structures being bonded. Fusion bonding forms connections between semiconductor structures via dielectric layers at the bonding interfaces of the bonded semiconductor structures.

[0036] Referring to Figures 1 and 2, a first semiconductor structure 100 and a second semiconductor structure 200 (or "first semiconductor die" and "second semiconductor die") are formed on a first semiconductor substrate 101 and a second semiconductor substrate 201, respectively. The first semiconductor substrate 101 and the second semiconductor substrate 201 include semiconductor materials, including but not limited to silicon, III-V, II-V compound semiconductor materials, or other similar semiconductor materials. Additionally, multiple semiconductor material layers may be used as semiconductor materials for the first semiconductor substrate 101 and the second semiconductor substrate 201. A first substrate dielectric layer 103 and a second substrate dielectric layer 203 are each formed on the first semiconductor substrate 101 and the second semiconductor substrate 201. The first substrate dielectric layer 103 and the second substrate dielectric layer 203 include, for example, a silicon nitride (SiN) layer, which is disposed on top of the first semiconductor substrate 101 and the second semiconductor substrate 201 prior to processing.

[0037] The first semiconductor structure 100 and the second semiconductor structure 200 each include a first portion 110 and a second portion 210 of an inductor circuit, respectively. The inductor circuit may also be referred to herein as an "inductor structure". As can be seen, the first portion 110 and the second portion 210 of the inductor circuit each include a plurality of metallization levels (e.g., FEOL, MOL, and BEOL metallization levels) in the first dielectric layer stack 105 and the second dielectric layer stack 205. The first semiconductor structure 100 further includes an additional metallization structure 120 formed in the first dielectric layer stack 105.

[0038] The first dielectric layer stack 105 and the second dielectric layer stack 205 include, but are not limited to, porous forms of tetraethyl orthosilicate (TEOS), silicon dioxide (SiO2), carbon-doped silicon oxide (SiCOH), SiLK® dielectrics, and / or such low-k dielectrics. The first dielectric layer stack 105 and the second dielectric layer stack 205 include multiple layers of the same or different materials deposited in multiple deposition steps depending on the design and manufacturing processes associated with the first semiconductor structure 100 and the second semiconductor structure 200. As will be understood by those skilled in the art, the first dielectric layer stack 105 and the second dielectric layer stack 205 may have an intervening layer (e.g., an under-conductor line, device, etc.) on the first semiconductor substrate 101 and the second semiconductor substrate 201, between the first dielectric layer stack 105 and the second dielectric layer stack 205 and the first semiconductor substrate 101 and the second semiconductor substrate 201. A plurality of devices, such as transistors, capacitors, and resistors, may be on or within the first semiconductor substrate 101 and the second semiconductor substrate 201. For example, in the illustrative embodiment, there are additional wiring layers and structures, as well as devices (e.g., transistors), within the first dielectric layer stack 105 and the second dielectric layer stack 205, and connected to devices disposed in the first semiconductor substrate 101 and the second semiconductor substrate 201 through the first substrate dielectric dense layer 103 and the second substrate dielectric dense layer 203.

[0039] The first portion 110 and the second portion 210 of the inductor circuit each include a plurality of metallization levels, each including a plurality of first metal layers 112 and a plurality of second metal layers 212 as shown by horizontal lines. The first metal layers 112 and the second metal layers 212 may include, for example, wiring present on a wafer.

[0040] The first metal layer 112 is interconnected by one or more first vias 111, and the second metal layer is interconnected by one or more second vias 211. The first vias 111 and the second vias 211 are illustrated as vertical lines between horizontal lines representing the first metal layer 112 and the second metal layer 212. Similarly, the additional metallization structure 120 formed in the first dielectric layer stack 105 includes a plurality of metallization levels comprising a plurality of additional metal layers 122 as shown by horizontal lines. These additional metal layers may also include, for example, wiring present on the wafer. The additional metal layers 122 are interconnected by one or more additional vias 121, which are also illustrated as vertical lines between horizontal lines representing the additional metal layers 122.

[0041] Additionally, as explained in more detail herein, a first through-silicon via (TSV) 113 extends from one of the first metal layers 112 of the first portion 110 of the inductor circuit, through the first dielectric layer stack 105, and through the first substrate dielectric layer 103 into the first semiconductor substrate 101. As explained in more detail herein, the first TSV 113 may be connected to one or more circuits (not shown) to deliver an output signal (e.g., voltage) from the inductor circuit. Similarly, as explained in more detail with respect to FIG. 17, a second TSV 213 extends from one of the second metal layers 212 of the second portion 210 of the inductor circuit and is connected to one or more circuits (not shown) to receive an input signal (e.g., voltage) for the inductor circuit.

[0042] In the illustrative embodiment, the first via 111 and the second via 211, the first metal layer 112 and the second metal layer 212, the additional via 121, the additional metal layer 122, and the first TSV 113 and the second TSV 213 include, for example: a silica layer, such as silica formed with Ni, Ti, NiPt, etc.; a metal adhesion layer, such as TiN; and a conductive metal filling layer, such as Cu, W, Al, Co, Ru, etc., and can be deposited using deposition techniques such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), radio frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source atomized chemical deposition (LSMCD), sputtering and / or plating, followed by a planarization process such as chemical mechanical planarization (CMP) to remove excess metal material from the top of the dielectric layer.

[0043] As shown in Figures 3 and 4, a first hybrid bonding layer 125 is deposited on the top surface of the first dielectric layer stack 105. Similarly, a second hybrid bonding layer 225 is deposited on the top surface of the second dielectric layer stack 205. The first hybrid bonding layer 125 and the second hybrid bonding layer 225 include, but are not limited to, TEOS, silicon carbonitride (SiCN), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), and / or high-k dielectrics, such as, but not limited to, HfO2 (hafnium oxide), ZrO2 (zirconia), and / or Ta2O5 (tantalum pentoxide), and / or other dielectric films. The first hybrid bonding layer 125 and the second hybrid bonding layer 225 may include the same dielectric material or different dielectric materials.

[0044] Referring to Figures 5 and 6, a first photoresist 130 and a second photoresist 230 are deposited on a first hybrid bonding level dielectric layer 125 and a second hybrid bonding level dielectric layer 225, respectively. The first photoresist 130 and the second photoresist 230 are patterned to create openings corresponding to the locations where metal pads are to be formed. The openings in the first photoresist 130 and the second photoresist 230 expose portions of the first hybrid bonding level dielectric layer 125 and the second hybrid bonding level dielectric layer 225 that have been etched to create the first opening 135 and the second opening 235. These first and second openings expose the upper first metal layer of the first metal layer 112 of the first portion 110 of the inductor circuit and the upper second metal layer of the second metal layer 212 of the second portion 210 of the inductor circuit. The etching can be performed using a reactive ion etching (RIE) procedure.

[0045] Referring to Figures 7 and 8, after etching the exposed portions of the first hybrid bonding level dielectric layer 125 and the second hybrid bonding level dielectric layer 225 to create the first opening 135 and the second opening 235, the first photoresist 130 and the second photoresist 230 are removed. After removing the first photoresist 130 and the second photoresist 230, a first seed / liner layer 139 is deposited on the remaining portion of the first hybrid bonding level dielectric layer 125 and the exposed portion of the first metal layer 112. Similarly, a second seed / liner layer 239 is deposited on the remaining portion of the second hybrid bonding level dielectric layer 225 and the exposed portion of the second metal layer 212. According to the illustrative embodiment, the first seed / liner layer 139 and the second seed / liner layer 239 each comprise, for example, Ti / TiW, Ti / TiN, Ta / TaN, TaN / Co, CuMn, Cu, and other copper alloys.

[0046] Referring to Figures 9 and 10, after depositing the first seed / liner layer 139 and the second seed / liner layer 239, a first metal filler layer 140 is formed on the first seed / liner layer 139, and a second metal filler layer 240 is formed on the second seed / liner layer 239. As can be seen in Figures 9 and 10, the first metal filler layer 140 and the second metal filler layer 240 fill the remaining portions of the first opening 135 and the second opening 235 in the first hybrid bonding level dielectric layer 125 and the second hybrid bonding level dielectric layer 225. In the illustrative embodiment, the metal filler layer is formed by the plating process or other deposition process mentioned above for metal deposition, and includes, for example, Cu, W, Al, Co, Ru, etc.

[0047] Referring to Figures 11 and 12, using, for example, CMP, a first metal filler layer 140 and a second metal filler layer 240, as well as a first seed / liner layer 139 and a second seed / liner layer 239, are planarized from the top surfaces of a first hybrid bonding level dielectric layer 125 and a second hybrid bonding level dielectric layer 225, thereby creating a first metal pad 140' and a second metal pad 240' in the first opening 135 and the second opening 235, respectively. Next, referring to Figures 13 and 14, a first semiconductor structure 100 is flipped (e.g., rotated 180 degrees) onto a second semiconductor structure 200 such that the first semiconductor structure 100 faces the second semiconductor structure 200. As used herein, the term "face" refers to the result of rotating one of the two structures 180 degrees such that the top surfaces of the structures are positioned and aligned relative to each other.

[0048] When the first semiconductor structure 100 is flipped onto the second semiconductor structure 200, the first metal pad 140' of the first semiconductor structure 100 is aligned with the second metal pad 240' of the second semiconductor structure 200. The first metal pad 140' is connected to the first metal layer 112 on the first hybrid bonding level dielectric layer 125 in the orientation shown in FIG. 13. The second metal pad 240' is connected to the second metal layer 212 below the second hybrid bonding level dielectric layer 225 in the orientation shown in FIG. 14. Each first metal pad 140' and each second metal pad 240' are positioned opposite each other. The first metal pad 140' is embedded in the first hybrid bonding level dielectric layer 125, and the second metal pad 240' is embedded in the second hybrid bonding level dielectric layer 225. In an illustrative embodiment, a first metal pad 140' is recessed within a first hybrid bonding level dielectric layer 125 to allow the first metal pad 140' to expand during annealing to form a hybrid bond. Similarly, a second metal pad 240' is recessed within a second hybrid bonding level dielectric layer 225 to allow the second metal pad 240' to expand during annealing to form a hybrid bond. In a non-limiting illustrative embodiment, the recess amount may range from about 3 nm to about 5 nm.

[0049] Referring to FIG. 15, a hybrid bonding process H is performed on the first semiconductor structure 100 and the second semiconductor structure 200 to anneal the metal materials of the first metal pad 140' and the second metal pad 240'. Referring to the semiconductor device 300 in FIG. 16, due to annealing, the opposing first metal pad 140' and second metal pad 240' are formed (e.g., integrated) into respective metal structures 340 that span (e.g., bridge) the interface between the first semiconductor structure 100 and the second semiconductor structure 200. The metal structures 340 are respectively connected to the first metal layer 112 of the first semiconductor structure 100 and the second metal layer 212 of the second semiconductor structure 200 on opposite sides of the metal structures 340. By means of connecting to the first metal layer 112 and the second metal layer 212, the metal structures 340 connect the first portion 110 of the inductor circuit to the second portion 210 of the inductor circuit to form a complete inductor circuit. Metal structure 340 is formed in a first hybrid bonding level dielectric layer 125 and a second hybrid bonding level dielectric layer 225. The first hybrid bonding level dielectric layer 125 and the second hybrid bonding level dielectric layer 225 may contain the same dielectric material or different dielectric materials. Conditions for the hybrid bonding process include, for example, heat treatment at about 200°C to about 400°C for about 1 hour to 3 hours. In an illustrative embodiment, heat treatment is performed at about 300°C to about 400°C for about 1 hour to about 2 hours. In the illustrative embodiment, hybrid bonding uses heat and mechanical force to create the bond.

[0050] As can be seen in the three-dimensional view of semiconductor device 300 in Figure 17, and as explained in more detail herein, a first TSV 113 extends from one of the first metal layers 112 of the first portion 110 of the inductor circuit, through the first dielectric layer stack 105, and through the first substrate dielectric layer 103 into the first semiconductor substrate 101. The first TSV 113 is connected to one or more circuits (not shown) to deliver an output signal (e.g., voltage) from the inductor circuit (signal exit). A second TSV 213 extends from one of the second metal layers 212 of the second portion 210 of the inductor circuit and is connected to one or more circuits (not shown) to receive an input signal (e.g., voltage) for the inductor circuit (signal entry). The second TSV 213 extends through the first hybrid bonding level dielectric layer 125 and the second hybrid bonding level dielectric layer 225, through the first dielectric layer stack 105, through the first substrate dielectric layer 103, and into the first semiconductor substrate 101.

[0051] As can be seen in Figures 16 and 17, the first portion 110 and the second portion 210 of the inductor circuit have the same configuration (e.g., coil). Alternatively, since the first semiconductor structure 100 and the second semiconductor structure 200 can be manufactured separately and later hybridized to each other, the first and second portions of the inductor circuit can have different configurations, provided they are connected to each other by integrated metal structures formed by heat-treating the first and second metal pads of the opposing semiconductor structures during the hybridization process. In the illustrative embodiment, the coil or loop structure extends upward and / or downward through the BEOL dielectric stack (e.g., the first dielectric layer stack 105 and the second dielectric layer stack 205) to increase the effective inductance.

[0052] Figures 18A to 23C illustrate different possible configurations of the inductor circuit portion formed on the opposing semiconductor die. Referring to Figures 18A, 18B, and 18C, which depict the semiconductor device 400 in respective first three-dimensional views, second three-dimensional views, and top views, the first inductor circuit portion 410-A and the second inductor circuit portion 410-B are connected to each other by a hybrid bonding metal structure 440. The first inductor circuit portion 410B-A is formed on the first semiconductor die, and the second inductor circuit portion 410-B is formed on the second semiconductor die, which is hybrid bonded to the first semiconductor die through the hybrid bonding metal structure 440.

[0053] Referring to Figures 19A, 19B, and 19C, which depict the semiconductor device 500 in a first three-dimensional view, a second three-dimensional view, and a top view, the first inductor circuit portion 510-A and the second inductor circuit portion 510-B are connected to each other by a hybrid bonding metal structure 540. The first inductor circuit portion 510-A is formed on a first semiconductor die, and the second inductor circuit portion 510-B is formed on a second semiconductor die, which is hybrid bonded to the first semiconductor die through the hybrid bonding metal structure 540.

[0054] Referring to Figures 20A, 20B, and 20C, which depict the semiconductor device 600 in a first three-dimensional view, a second three-dimensional view, and a top view, the first inductor circuit portion 610-A and the second inductor circuit portion 610-B are connected to each other by a hybrid bonding metal structure 640. The first inductor circuit portion 610-A is formed on a first semiconductor die, and the second inductor circuit portion 610-B is formed on a second semiconductor die, which is hybrid bonded to the first semiconductor die through the hybrid bonding metal structure 640.

[0055] Referring to Figures 21A, 21B, and 21C, which depict the semiconductor device 700 in a first three-dimensional view, a second three-dimensional view, and a top view, a first inductor circuit portion 710-A and a second inductor circuit portion 710-B are connected to each other via a hybrid-bonded metal structure 740. The first inductor circuit portion 710-A is formed on a first semiconductor die, and the second inductor circuit portion 710-B is formed on a second semiconductor die, which is hybrid-bonded to the first semiconductor die via the hybrid-bonded metal structure 740. The first metal layer 712-A and the second metal layer 712-B represent the metal layers from which the first TSV and the second TSV extend.

[0056] Referring to Figures 22A, 22B, and 22C, which depict the semiconductor device 800 in a first three-dimensional view, a second three-dimensional view, and a top view, a first inductor circuit portion 810-A and a second inductor circuit portion 810-B are connected to each other via a hybrid-bonded metal structure 840. The first inductor circuit portion 810-A is formed on a first semiconductor die, and the second inductor circuit portion 810-B is formed on a second semiconductor die, which is hybrid-bonded to the first semiconductor die via the hybrid-bonded metal structure 840. The first metal layer 812-A represents the metal layer from which the first TSV extends.

[0057] Referring to Figures 23A, 23B, and 23C, which depict the semiconductor device 900 in a first three-dimensional view, a second three-dimensional view, and a top view, the first inductor circuit portion 910-A and the second inductor circuit portion 910-B are connected to each other by a hybrid bonding metal structure 940. The first inductor circuit portion 910-A is formed on a first semiconductor die, and the second inductor circuit portion 910-B is formed on a second semiconductor die, which is hybrid bonded to the first semiconductor die through the hybrid bonding metal structure 940.

[0058] The hybrid bonding metal structures 440, 540, 640, 740, 840 and 940 are similar to the metal structure 340 described above, in order to physically connect and electrically connect portions of the inductor circuit to each other.

[0059] In one embodiment, an apparatus includes: a first semiconductor structure disposed on a second semiconductor structure; and a plurality of metal structures at an interface portion of the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first portion of an inductor structure, and the second semiconductor structure includes a second portion of the inductor structure. The plurality of metal structures connect the first portion of the inductor structure to the second portion of the inductor structure.

[0060] The first part of the inductor structure may have a different configuration or the same configuration as the second part of the inductor structure.

[0061] The first semiconductor structure may include at least one first conductive contact, and the device further includes a first via connected to one of the first conductive contacts. The first via can be connected to the second portion of the inductor structure through one of the plurality of metal structures. The second semiconductor structure may include at least one second conductive contact, and the device further includes a second via connected to one of the second conductive contacts. The second via can be connected to the first portion of the inductor structure through another of the plurality of metal structures. The first via and the second via may each include a first TSV and a second TSV. One of the first via and the second via can receive an input voltage, and the other of the first via and the second via can output an output voltage.

[0062] The plurality of metal structures may be disposed in a dielectric layer, wherein the dielectric layer comprises at least two dielectric materials that are different from each other.

[0063] In another embodiment, an apparatus includes a first semiconductor die disposed on a second semiconductor die. The first semiconductor die includes a first portion of an inductor structure, and the second semiconductor die includes a second portion of the inductor structure. The first portion of the inductor structure is connected to the second portion of the inductor structure through an interface portion between the first semiconductor die and the second semiconductor die.

[0064] The device may further include a plurality of metal structures at the interface portion, wherein the plurality of metal structures connect the first portion of the inductor structure to the second portion of the inductor structure. The first semiconductor die may include at least one first conductive contact, wherein the device further includes a first via connected to one of the first conductive contacts. The first via may be connected to the second portion of the inductor structure through one of the plurality of metal structures. The second semiconductor die may include at least one second conductive contact, wherein the device further includes a second via connected to one of the second conductive contacts. The second via may be connected to the first portion of the inductor structure through another of the plurality of metal structures. The first via and the second via may each include a first TSV and a second TSV. One of the first via and the second via may receive an input voltage, and the other of the first via and the second via may output an output voltage.

[0065] In another embodiment, a device includes: a first semiconductor die bonded to a second semiconductor die; an inductor structure including a first portion disposed within the first semiconductor die and a second portion disposed within the second semiconductor die; and a plurality of metal structures disposed along an interface between the first semiconductor die and the second semiconductor die. The first portion of the inductor structure, the plurality of metal structures, and the second portion of the inductor structure are in electrical contact with each other.

[0066] The first portion of the inductor structure may have a different configuration from the second portion of the inductor structure. The first semiconductor die may include a first TSV, which is connected to the second portion of the inductor structure through one of the plurality of metal structures. The second semiconductor die may include a second TSV, which is connected to the first portion of the inductor structure through another of the plurality of metal structures.

[0067] In another embodiment, a device includes a first semiconductor structure disposed on top of and facing a second semiconductor structure. The device further includes a plurality of metal structures spanning an interface portion between the first and second semiconductor structures. The plurality of metal structures connect a first portion of an inductor on the first semiconductor structure to a second portion of an inductor on the second semiconductor structure.

[0068] The first semiconductor structure may include a first TSV, which is connected to the second portion of the inductor through one of the plurality of metal structures. The second semiconductor structure may include a second TSV, which is connected to the first portion of the inductor through another of the plurality of metal structures.

[0069] In another embodiment, a method includes forming a first semiconductor structure on a first semiconductor substrate, wherein the first semiconductor structure includes a first portion of an inductor structure and a first plurality of metal pads connected to the first portion of the inductor structure. The method further includes forming a second semiconductor structure on a second semiconductor substrate, wherein the second semiconductor structure includes a second portion of the inductor structure and a second plurality of metal pads connected to the second portion of the inductor structure. Each of the first plurality of metal pads is aligned with each of the second plurality of metal pads, and a hybrid bonding process is performed to bond the first semiconductor structure to the second semiconductor structure, wherein the hybrid bonding process integrates the first plurality of metal pads and the second plurality of metal pads to create a plurality of metal structures spanning an interface between the first semiconductor structure and the second semiconductor structure.

[0070] The method may further include forming a TSV on the first semiconductor structure, wherein the TSV is connected to the second portion of the inductor structure through one of the plurality of metal structures. The hybrid bonding process includes annealing the first plurality of metal pads and the second plurality of metal pads.

[0071] It should be understood that the hybrid bonding technology disclosed herein enables the construction of inductor structures that offer various advantages over conventional 2-D and 3-D packaging structures and technologies discussed above. For example, this structure advantageously provides a technique for fabricating a first inductor portion on a first semiconductor die, a second inductor portion on a second semiconductor die, and connecting the first and second semiconductor dies via a hybrid bonding interface to form a multi-level inductor with electrical connections between the inductor portions. The hybrid bonding interface facilitates electrical connections between the first and second inductor portions. As an additional advantage, the bifurcated structure of the inductor spanning two semiconductor dies allows for modular design. This modularity allows for design flexibility, independent optimization of each semiconductor die, and easier integration with other components or systems.

[0072] Unlike conventional designs, this inductor structure includes several possible multi-level inductor structure configurations, in which metal wires and bonding pads are patterned to form loops extending upward and / or downward through the BEOL dielectric stack to increase effective inductance, while providing a compact structure that optimizes substrate area and allows for advanced circuit design and integration with other semiconductor devices.

[0073] Advantageously, the inductor structure of the illustrative embodiments can be used for radio frequency (RF) transmission and reception, and can be applied to both RF and analog devices, which have become increasingly prevalent with the growth of the wireless communication market. Furthermore, the hybrid bonding method facilitates scalable and cost-effective manufacturing processes, enabling production scalability to align with demand.

[0074] Novel inductor designs with hybrid bonding interfaces between two semiconductor dies result in enhanced electrical performance, compact integration, and scalable manufacturing. The inductance can be described using the free space permeability (σ0), number of turns (N), area in the internal core (A), and coil length (σ) according to Equation (1).

[0075] (1)

[0076] The value of L can be changed by simple alterations in the manufacturing process.

[0077] As an added advantage, the modular design of the illustrative embodiments is suitable for evolving wireless communication standards, thereby facilitating the development of multi-band or reconfigurable communication systems. Applications of the structures disclosed herein include, but are not limited to, cellular telephones, wireless local area networks (LANs), radio frequency identification (RFID), and radio frequency integrated circuits (RFICs).

[0078] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that this disclosure is not limited to those precise embodiments, and various other changes and modifications can be made therein by those skilled in the art without departing from the scope of the appended claims.

[0079] 100: First semiconductor structure 101: First Semiconductor Substrate 103: First substrate dielectric layer 105: First dielectric layer stack 110: Part One of Inductor Circuits 111: First through hole 112: First metal layer 113: First silicon perforation 120: Additional metallization structure 121: Additional through hole 122: Additional metal layer 125: First hybrid bonding level dielectric layer 130: First photoresist 135: First Opening 139: First seed crystal / inner liner 140: First metal filler layer 140': First metal gasket 200: Second semiconductor structure 201: Second semiconductor substrate 203: Second substrate dielectric dense layer 205: Second dielectric layer stack 210: Part Two of Inductor Circuits 211: Second through hole 212: Second metal layer 213: Second TSV 225: Second hybrid bonding level dielectric layer 230: Second photoresist 235: Second opening 239: Second seed crystal / inner liner 240: Second metal filler layer 240': Second metal gasket 300: Semiconductor Devices 340: Metal Structure 400: Semiconductor Device 410-A: First Inductor Circuit Section 410-B: Second Inductor Circuit Section 440: Hybrid joint metal structure 500: Semiconductor Devices 510-A: First Inductor Circuit Section 510-B: Second Inductor Circuit Section 540: Hybrid joint metal structure 600: Semiconductor Devices 610-A: First Inductor Circuit Section 610-B: Second Inductor Circuit Section 640: Hybrid joint metal structure 700: Semiconductor Devices 710-A: First Inductor Circuit Section 710-B: Second Inductor Circuit Section 712-A: First metal layer 712-B: Second metal layer 740: Hybrid joint metal structure 800: Semiconductor Device 810-A: First Inductor Circuit Section 810-B: Second Inductor Circuit Section 812-A: First metal layer 840: Hybrid Joint Metal Structure 900: Semiconductor Device 910-A: First Inductor Circuit Section 910-B: Second Inductor Circuit Section 940: Hybrid joint metal structure H: Hybrid Joining Procedure

Claims

1. A semiconductor device comprising: a first semiconductor structure disposed on a second semiconductor structure; wherein the first semiconductor structure includes a first portion of an inductor structure, and the second semiconductor structure includes a second portion of the inductor structure; a plurality of metal structures at an interface portion of the first semiconductor structure and the second semiconductor structure; and a silicon through-hole extending from the second portion of the inductor structure and into the first semiconductor structure, wherein the plurality of metal structures connect the first portion of the inductor structure and the second portion of the inductor structure.

2. The semiconductor device of claim 1, wherein the first portion of the inductor structure and the second portion of the inductor structure have a different configuration.

3. The semiconductor device of claim 1, wherein the first portion of the inductor structure and the second portion of the inductor structure have the same configuration.

4. The semiconductor device as claimed in claim 1, wherein: The first semiconductor structure includes at least one first conductive contact; the device further includes a first through-hole connected to one of the first conductive contacts; and the first through-hole is connected to the second portion of the inductor structure through one of the plurality of metal structures.

5. The semiconductor device as claimed in claim 4, wherein: The second semiconductor structure includes at least one second conductive contact; the device further includes a second via connected to one of the second conductive contacts; and the second via is connected to the first portion of the inductor structure through another of the plurality of metal structures.

6. The semiconductor device of claim 5, wherein the first via and the second via respectively include a first silicon through-hole and a second silicon through-hole.

7. The semiconductor device as claimed in claim 5, wherein: One of the first through-hole and the second through-hole receives an input voltage; and the other of the first through-hole and the second through-hole outputs an output voltage.

8. The semiconductor device of claim 1, wherein the plurality of metal structures are disposed in a dielectric layer.

9. The semiconductor device of claim 8, wherein the dielectric layer comprises at least two dielectric materials that are different from each other.

10. A semiconductor device comprising: a first semiconductor die disposed on a second semiconductor die, wherein the first semiconductor die includes a first portion of an inductor structure, and the second semiconductor die includes a second portion of the inductor structure, wherein the first portion of the inductor structure is connected to the second portion of the inductor structure through an interface portion of the first semiconductor die and the second semiconductor die; and a silicon through-hole extending from the second portion of the inductor structure and into the first semiconductor die.

11. The semiconductor device of claim 10, further comprising a plurality of metal structures at the interface portion, wherein the plurality of metal structures connect the first portion of the inductor structure to the second portion of the inductor structure.

12. The semiconductor device as claimed in claim 11, wherein: The first semiconductor die includes at least one first conductive contact; the device further includes a first through-hole connected to one of the first conductive contacts; and the first through-hole is connected to the second portion of the inductor structure through one of the plurality of metal structures.

13. The semiconductor device as claimed in claim 12, wherein: The second semiconductor die includes at least one second conductive contact; the device further includes a second through-hole connected to one of the second conductive contacts; and the second through-hole is connected to the first portion of the inductor structure through another of the plurality of metal structures.

14. The semiconductor device of claim 13, wherein the first via and the second via respectively include a first silicon through-hole and a second silicon through-hole.

15. The semiconductor device as claimed in claim 13, wherein: One of the first through-hole and the second through-hole receives an input voltage; and the other of the first through-hole and the second through-hole outputs an output voltage.

16. A semiconductor device comprising: a first semiconductor die bonded to a second semiconductor die; an inductor structure including a first portion disposed within the first semiconductor die and a second portion disposed within the second semiconductor die; a plurality of metal structures disposed along an interface between the first semiconductor die and the second semiconductor die, wherein the first portion of the inductor structure, the plurality of metal structures and the second portion of the inductor structure are electrically in contact with each other; and a silicon through-hole extending from the second portion of the inductor structure and into the first semiconductor die.

17. The semiconductor device of claim 16, wherein the first portion of the inductor structure and the second portion of the inductor structure have a different configuration.

18. The apparatus of claim 16, wherein the first semiconductor die includes a first silicon through-hole, the first silicon through-hole being connected to the second portion of the inductor structure through one of the plurality of metal structures.

19. The apparatus of claim 18, wherein the second semiconductor die includes a second silicon through-hole, the second silicon through-hole being connected to the first portion of the inductor structure through another of the plurality of metal structures.

20. A semiconductor device comprising: a first semiconductor structure disposed on top of and facing a second semiconductor structure; a plurality of metal structures spanning an interface portion between the first semiconductor structure and the second semiconductor structure, wherein the plurality of metal structures connect the first portion of an inductor on the first semiconductor structure to a second portion of an inductor on the second semiconductor structure; and a silicon through-hole extending from the second portion of the inductor structure and into the first semiconductor structure.

21. The device of claim 20, wherein the first semiconductor structure includes a first silicon through-hole, the first silicon through-hole being connected to the second portion of the inductor through one of the plurality of metal structures.

22. The device of claim 21, wherein the second semiconductor structure includes a second silicon through-hole, the second silicon through-hole being connected to the first portion of the inductor through another of the plurality of metal structures.

23. A method for forming a semiconductor device, comprising: forming a first semiconductor structure on a first semiconductor substrate, wherein the first semiconductor structure includes a first portion of an inductor structure and a first plurality of metal pads connected to the first portion of the inductor structure; forming a second semiconductor structure on a second semiconductor substrate, wherein the second semiconductor structure includes a second portion of the inductor structure and a second plurality of metal pads connected to the second portion of the inductor structure; forming a silicon through-hole extending from the second portion of the inductor structure and into the first semiconductor structure; aligning each of the first plurality of metal pads with each of the second plurality of metal pads; and performing a hybrid bonding process to bond the first semiconductor structure to the second semiconductor structure, wherein the hybrid bonding process integrates the first plurality of metal pads and the second plurality of metal pads to create a plurality of metal structures spanning an interface between the first semiconductor structure and the second semiconductor structure.

24. The method of claim 23, further comprising forming a silicon through-hole on the first semiconductor structure, wherein the silicon through-hole is connected to the second portion of the inductor structure through one of the plurality of metal structures.

25. The method of claim 23, wherein the hybrid bonding process includes annealing the first plurality of metal gaskets and the second plurality of metal gaskets.

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