Semiconductor device assemblies with multi-reticle dies and reticle-bridging conductors

Abstract

A semiconductor device assembly includes: a multi-mask semiconductor device comprising a continuous semiconductor substrate having a plurality of circuit regions separated from each other by a mask edge region having no electrical conductors; a device connection layer formed above the multi-mask semiconductor device and including a plurality of mask bridging conductors electrically coupling the plurality of circuit regions in the multi-mask semiconductor device to each other; and a plurality of semiconductor devices disposed above the device connection layer and electrically coupled to the multi-mask semiconductor device by vertical conductors extending through the device connection layer.

Description

[Technical Field]

[0001] The present invention relates generally to a semiconductor device assembly, and more particularly to a semiconductor device assembly having multiple photomask dies and photomask bridging conductors. [Previous Technology]

[0002] Microelectronic devices typically have a die (i.e., a chip) containing an integrated circuit system with a high density of extremely small components. Typically, the die includes an array of extremely small bonding pads electrically coupled to the integrated circuit system. These bonding pads are external electrical contacts through which voltage, signals, etc., are transmitted to and from the integrated circuit system. After the die is formed, it is "encapsulated" to couple the bonding pads to a larger array of electrical terminals, which can be more easily coupled to various power supply lines, signal lines, and ground lines. Conventional procedures for encapsulating a die include electrically coupling the bonding pads on the die to an array of leads, ball pads, or other types of electrical terminals and encapsulating the die to protect it from environmental factors such as moisture, particles, static electricity, and physical impacts.

Implementation Method

[0008] Cross-reference to related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 677,955, filed July 31, 2024, the entire contents of which are incorporated herein by reference.

[0009] The demand for higher performance in semiconductor devices appears to be unmet. To improve the performance of a device, more features can be included in a device of a given size by shrinking the feature size through lithography. However, as feature shrinkage approaches its theoretical limit, adding more features has driven an increase in the size of semiconductor devices (i.e., their footprint). As the footprint of semiconductor devices increases to the limit of lithography mask size (a limit that would require extensive reprocessing across the entire industry to overcome), the capabilities of semiconductor devices can be improved by integrating multiple mask-bound semiconductor devices into a single assembly.

[0010] A photomask-confined semiconductor device has an area larger than that of a single photomask field (e.g., current EUV photomask sizes are limited to about 858 mm²) and includes multiple photomask-sized circuit regions. These circuit regions, due to the confinement of precisely aligned two different photomask fields, can be spaced apart from each other by a region of an unpatterned silicon substrate in which there are no conductors or other circuit features (e.g., similar to two discrete dies in an unmonotyped portion of a semiconductor wafer). However, unlike two discrete dies in an unmonotyped portion of a semiconductor substrate, in a photomask-confined semiconductor device, the multiple photomask-confined circuit regions may not be designed in the same way, but may include features intended to connect to each other across the unpatterned regions of the substrate (e.g., by subsequent BEOL metallization or by connection to an interposer).

[0011] One challenge of these methods for coupling discrete circuit regions of a multi-mask semiconductor device is the additional manufacturing cost, package size (e.g., from a dedicated interposer with solder joints), and increased circuit path length (e.g., interposition between the multi-mask semiconductor device and its host and / or between the multi-mask semiconductor device and its integrated auxiliary devices (such as memory). To address these and other disadvantages, embodiments of the present invention provide a semiconductor device assembly having a pre-fabricated device interconnect layer that can be directly bonded to a multi-mask semiconductor device in a wafer-level operation. The device interconnect layer can couple not only discrete circuit regions of the multi-mask semiconductor device to each other, but also the multi-mask semiconductor device to other semiconductor devices in a heterogeneous device assembly (such as memory).

[0012] Figures 1 to 4 are simplified schematic cross-sectional views of different stages of the manufacturing process of an example semiconductor device assembly according to an embodiment of the present technology. Turning to Figure 1, multiple semiconductor memory devices 101 and 102 are still shown in wafer format as disposed in an active area of ​​wafer 100. Wafer 100 may also be referred to as a top memory device wafer. Each memory device 101 or 102 is formed using a separate photomask illumination area. In one embodiment, multiple memory devices are present in each representative memory device 101 and 102. For example, each memory device 101 or 102 may contain at least 4, 6, 8, 10 or more non-monopolized memory devices. In one embodiment, semiconductor memory devices 101 and 102 include a semiconductor substrate (e.g., a silicon substrate) and multiple dielectric and metal layers as part of a back-to-office (BEOL) layer. Memory devices 101 and 102 include contact structures 103 for forming interconnections with additional devices via a wafer-level hybrid bonding process. In one configuration, the contact structures 103 are formed on the front side of memory devices 101 and 102. These contact structures 103 can be formed using a dummy process. The contact structures 103 are connected to the BEOL via vias (e.g., tungsten or copper vias) and probe pads (e.g., aluminum pads). As shown in FIG2, additional wafers 104 to 106 having additional semiconductor devices (delineated by dashed lines) can be hybrid bonded to form a device stack coupled via contact structures 103 and TSVs 107 perpendicularly aligned to contact structures 103. TSVs 107 may contain tungsten or copper material as a conductive core. Furthermore, TSVs 107 may use a back-via process or an intermediate-via process. In one configuration, the additional wafers 104 to 106 are coupled to wafer 100 via wafer-to-wafer (W2W) bonding. Furthermore, in one configuration, similar to the bonding of wafers 104 and 105 and wafers 105 and 106, wafer 100 is bonded to wafer 104 via a front-to-back (F2B) configuration. In one configuration, eight wafers can be bonded together. In another configuration, more than eight wafers can be bonded together, such as at least 12, 16, or 24 wafers. Hybrid bonding occurs between the contact structures 103 on the front side of each wafer 100, 104 to 106 and the corresponding back-side contacts of the wafer being bonded. The back-side contacts are formed using a dummy process after a TSV reveal process.

[0013] As illustrated in Figure 3, a device interconnect layer 108 may be formed over the stack of wafers 100 and 104 to 106 from Figure 2. In one embodiment, the device interconnect layer 108 may be a data access layer comprising a substrate, a dielectric, and a metallization layer. The device interconnect layer 108 may be connected to wafer 106 via wafer-to-wafer bonding and in a face-to-face (F2F) configuration. In one embodiment, the device interconnect layer 108 may be used to connect to memory devices 101 and 102 of the respective wafers 100, 104, and 106. The device interconnect layer may also be used to manage the routing of memory devices 101 and 102 and any repairs associated with TSVs. In one embodiment, vias through the device interconnect layer 108 may have a different pitch than vias through the stack of wafers 100, 104 to 106. Compared to vias through the stack of wafers 100, 104 to 106, vias through device interconnect layer 108 can also have a different conductive composition. The device interconnect layer can be formed as a layer using a back-to-back (BEOL) metallization process well known to those skilled in the art. For example, it can be formed by repeatedly depositing and patterning dielectric material and electroplating metal (such as copper) into the dielectric material, allowing the construction of exposed contacts 103 facing both wafer 106 and outwards from the stack, and a conductive metal structure 109 coupling the wafer-facing (i.e., lower in the orientation of FIG. 3) side of device interconnect layer 108 to the outward-facing (i.e., upper in the orientation of FIG. 3) contact 110 of device interconnect layer 108. In other embodiments, device interconnect layer 108 may be formed with a silicon substrate within it. In another embodiment, a superposition may be formed on the back side of the device connection layer 108. The contacts 110 on the outer face of the device connection layer 108 include a subset (one pair shown in the cross-sectional view of FIG. 3, and an additional pair of this subset illustrated in FIG. 6 below) that are not coupled to the wafer-facing contacts 110 but are coupled via photomask bridging conductors 111. The photomask bridging conductors 111 can provide inter-area connectivity to one of the multi-photomask semiconductor devices having multiple discrete circuit regions, as shown and described in more detail below. In one embodiment, the contacts 110 and the photomask bridging conductors 111 are positioned on the back side of the device connection layer 108. Furthermore, the contacts 110 may be formed using a single damascene process or a dual damascene process.

[0014] Referring to Figure 4, a wafer 112 comprising one of two discrete photomask-limited circuit regions 113 and 114 has been hybrid-bonded (i.e., having a dielectric-dielectric bond in areas without conductive contacts, and a solderless direct metal-metal bond in areas where TSV 115 and contacts align with contacts 110 of device interconnect layer 108) to device interconnect layer 108. In one configuration, the two discrete photomask-limited circuit regions 113 and 114 are graphics processing units (GPUs) or central processing units (CPUs). Wafer 112 is bonded to wafer 108 by wafer-to-wafer bonding (especially in a back-to-forward (B2F) configuration). Due to the photomask-limited size of circuit regions 113 and 114, there are no conductors disposed within the areas of discrete circuit regions 113 and 114, and circuit regions 113 and 114 are electrically isolated from each other before wafer 112 is bonded to device interconnect layer 108. However, after the bonding operation, the photomask bridging conductor 111 operatively couples the contacts from one circuit region 112 to another circuit region 113, thereby providing inter-regional connectivity and allowing multiple photomask semiconductor devices to be used as a single integrated device.

[0015] In this exemplary embodiment, wafer 100 is depicted as an unthinned "thick" wafer that does not contain a TSV, as a full-thickness wafer provides robust mechanical support for a stacking operation, as will be readily understood by those skilled in the art. After the multi-mask semiconductor device wafer 112 is co-bonded to the wafer stack, the thick wafer 100 can be thinned to reduce the overall height of the final assembly, as illustrated in FIG4. In embodiments where the height of the assembly is not critical, wafer 100 can remain thick to provide mechanical strength to the assembly. However, in other embodiments, wafer 100 can be replaced with a thinned wafer (which may include a back-side exposed TSV for external interconnection of the assembly) instead of a thick wafer to support the bonding operations illustrated in FIG2 and FIG4, which is temporarily bonded to a carrier wafer providing the required mechanical support.

[0016] Referring to Figure 5, a simplified schematic cross-sectional view of a semiconductor device assembly after fabrication is illustrated according to one embodiment of the present technology. A redistribution layer (RDL) 113 has been formed on a multi-mask semiconductor device wafer 112, thereby routing signals from exposed contacts 116 of the wafer 112 to external contacts 114 of the assembly. Solder balls 115 may be formed on the external contacts 114 for connection to higher-order devices. The wafer stack can also be simplified at this time, such that the sidewalls illustrated in the figure correspond to the outer surface of the simplified device. In one configuration, more than 10,000 mask bridging conductors 111 may be present.

[0017] Turning to FIG. 6, a simplified schematic partial plan view of a semiconductor device assembly according to an embodiment of the present technology illustrates additional details of the device connection layer 108. As can be seen with reference to FIG. 6, the device connection layer 108 includes a plurality of photomask bridging conductors 111 configured to electrically connect pairs of contacts 110 associated with discrete photomask confinement circuit regions 113 and 114 of a multi-photomask semiconductor device. Although in this exemplary embodiment a multi-photomask semiconductor device is illustrated and described as comprising two discrete circuit regions 113 and 114, in other embodiments a multi-photomask semiconductor device may comprise more than two circuit regions, and the photomask bridging conductors 111 of the device connection layer 108 may couple the contacts 110 to each other in a one-to-one, one-to-many, and / or many-to-many topology, as may be desired for different multi-photomask semiconductor device designs.

[0018] Although in the foregoing exemplary embodiments the semiconductor device assembly has been depicted as having two memory device stacks on a single multimask semiconductor device, in other embodiments more or fewer stacks may be provided above a multimask semiconductor device. Furthermore, the memory devices thus provided may comprise a single type of memory (e.g., NAND or DRAM or PCM or SRAM or MRAM, etc.) or a mixture of one or more different types of memory (e.g., NAND and / or DRAM and / or PCM and / or SRAM and / or MRAM, etc.). Moreover, although the stack has been depicted as having four vertically aligned memory devices, in other embodiments, different stack heights may be implemented using fewer (e.g., one, two, or three) or more (e.g., five, six, eight, ten, twelve, etc.) layers of memory devices. In this regard, wafers 100, 104 to 106 containing the memory devices may be reconstructed wafers with known good dies to limit the yield exponential reduction associated with higher device stacks from non-monopolized wafers. Similarly, the multi-mask semiconductor device wafer 112 can be a reconfigurable or heterogeneous device wafer.

[0019] Although in the foregoing example embodiments the semiconductor device assembly has been depicted as having wafers facing the same direction (e.g., where the active surface is bonded to the non-active surface), in other embodiments a wafer stack may be bonded to active surfaces facing different directions (or, with necessary modifications to the details, all wafers face the opposite direction to the depicted direction, where the back surface faces the external package contacts).

[0020] Although in the foregoing example embodiments the semiconductor device assembly has been depicted as having wafers bonded using only a hybrid bonding method, other wafer bonding methods (e.g., solder interconnects) may be used alternatively or additionally in other embodiments.

[0021] Although in the foregoing exemplary embodiments the semiconductor device assembly has been illustrated and described as being formed by two photomask limiting circuits, in other embodiments the assembly may be formed by more than two such photomask limiting circuits (e.g., an array of 3x1 photomask limiting circuits, an array of 2x2 circuits, or even an array of 3x2, 4x2, 4x3, etc.). In such arrays, the photomask bridging conductors may extend in at least two different directions (e.g., perpendicular to each other).

[0022] According to one embodiment of the present invention, the semiconductor device illustrated in the assemblies of Figures 1 to 6 may be a memory chip, such as a dynamic random access memory (DRAM) chip, a NAND memory chip, a NOR memory chip, a magnetic random access memory (MRAM) chip, a phase change memory (PCM) chip, a ferroelectric random access memory (FeRAM) chip, a static random access memory (SRAM) chip, or the like. In one embodiment in which multiple chips are disposed in a single assembly, the semiconductor device may be memory chips of the same type (e.g., two NAND, two DRAM, etc.) or memory chips of different types (e.g., one DRAM and one NAND, etc.). According to another aspect of the present invention, the semiconductor die of the assembly illustrated and described above may be a logic die (e.g., a controller die, a processor die, an accelerator die, etc.) or a mixture of a logic die and a memory die (e.g., a memory controller die and a memory die controlled by it).

[0023] Figure 7 is a flowchart illustrating one method of fabricating a semiconductor device assembly. The method includes providing a semiconductor device sub-assembly comprising: a plurality of first semiconductor devices; and a device interconnect layer formed over the plurality of first semiconductor devices (box 710). The method further includes bonding a second semiconductor device to a surface of the device interconnect layer, wherein the second semiconductor device includes a continuous semiconductor substrate having first and second circuit regions separated from each other by a photomask edge region without any electrical conductor, such that bonding the second semiconductor device to the semiconductor device sub-assembly electrically couples the first and second circuit regions to each other through a photomask bridging conductor of the device interconnect layer (box 720).

[0024] Any of the semiconductor devices and semiconductor device assemblies described above with reference to Figures 1 to 6 can be incorporated into any of a number of larger and / or more complex systems, a representative example being system 800 schematically shown in Figure 8. System 800 may include a semiconductor device assembly (e.g., or a discrete semiconductor device) 802, a power supply 804, a driver 806, a processor 808, and / or other subsystems or assemblies 810. Semiconductor device assembly 802 may include features generally similar to those of the semiconductor devices described above with reference to Figures 1 to 6. The resulting system 800 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Accordingly, representative system 800 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. The components of system 800 may be housed in a single unit or distributed over multiple interconnected units (e.g., via a communication network). The components of system 800 may also include remote devices and any of a variety of computer-readable media.

[0025] The foregoing describes specific details of several embodiments of semiconductor devices and associated systems and methods. Those skilled in the art will recognize that suitable stages of the methods described herein can be performed at the wafer level or the grain level. Therefore, depending on the context in which it is used, the term "substrate" may refer to a wafer-level substrate or a single-diene-level substrate. Furthermore, unless otherwise indicated in the context, the structures disclosed herein can be formed using known semiconductor manufacturing techniques. For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, electroless plating, spin coating, and / or other suitable techniques can be used to deposit materials. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0026] In other embodiments, the term "substrate" may refer to a package-level substrate on which other semiconductor devices are carried, such as a printed circuit board (PCB), an interposer, or another semiconductor device.

[0027] The devices discussed herein (including a memory device) may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate may be controlled by doping with various chemical species (including but not limited to phosphorus, boron, or arsenic). Doping may be performed during the initial formation or growth of the substrate by ion implantation or any other doping method.

[0028] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this invention and the appended claims. Features implementing the functions may also be physically located at various locations, including portions distributed such that the functions are implemented at different physical locations.

[0029] As used herein (including within the scope of the invention claims), the word "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "...at least one of..." or "...one or more of...") indicates a comprehensive list such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a conditionally closed set. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the invention. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0030] As used herein, the terms “vertical,” “horizontal,” “up,” “down,” “above,” and “below” may refer to the relative orientation or positioning of a feature in a semiconductor device given the orientation shown in the figures. For example, “up” or “top” may refer to a feature positioned closer to the top of a page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations (such as inverted or tilted orientations), where top / bottom, above / below, above / below, up / down, and left / right may be interchanged depending on the orientation.

[0031] It should be noted that the methods described above describe possible implementations, and the operations and steps can be reconfigured or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more methods can be combined.

[0032] As will be understood from the foregoing, specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details are set forth in the foregoing description to provide a comprehensive and feasible description of one embodiment of the present technology. However, those skilled in the art will recognize that the present invention may be practiced without one or more of these specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the present technology. Generally, it should be understood that various other devices, systems, and methods besides those specific embodiments disclosed herein are also within the scope of the present technology. [Simplified Explanation of the Diagram]

[0003] Figures 1 to 4 are simplified schematic cross-sectional views of different stages of the manufacturing process of an example semiconductor device assembly according to an embodiment of the present technology.

[0004] FIG5 is a simplified schematic cross-sectional view of a semiconductor device assembly according to an embodiment of the present technology.

[0005] FIG6 is a simplified schematic partial plan view of a semiconductor device assembly according to an embodiment of the present technology.

[0006] Figure 7 is a flowchart illustrating a method for manufacturing a semiconductor device assembly according to an embodiment of the present technology.

[0007] Figure 8 is a schematic view of a system comprising a semiconductor device assembly configured according to one embodiment of the present technology.

Claims

1. A semiconductor device assembly, comprising: A multi-mask semiconductor device includes a continuous semiconductor substrate having a plurality of circuit regions separated from each other by a mask edge region having no electrical conductors; a device connection layer formed above the multi-mask semiconductor device and including a plurality of mask bridging conductors electrically coupling the plurality of circuit regions in the multi-mask semiconductor device to each other; and a plurality of semiconductor devices disposed above the device connection layer and electrically coupled to the multi-mask semiconductor device by vertical conductors extending through the device connection layer.

2. The semiconductor device assembly of claim 1, further comprising a redistribution layer disposed opposite to the device interconnection layer below the multi-mask semiconductor device and electrically coupling the multi-mask semiconductor device to a plurality of external package contacts.

3. The semiconductor device assembly of claim 1, wherein the plurality of circuit regions of the multi-mask semiconductor device are disposed away from the device interconnect layer in one of the working layers of the multi-mask semiconductor device.

4. The semiconductor device assembly of claim 1, wherein the plurality of photomask bridging conductors extend horizontally over the photomask edge region of the multi-photomask semiconductor device.

5. The semiconductor device assembly as claimed in claim 1, wherein: The device connection layer includes a first bonding surface, the first bonding surface including a first flat dielectric surface and a first plurality of contact pads, the multi-mask semiconductor device includes a second bonding surface, the second bonding surface including a second flat dielectric surface and a second plurality of contact pads, and the first bonding surface and the second bonding surface are mixed and bonded to each other such that the first flat dielectric surface and the second flat dielectric surface are bonded by a dielectric-dielectric bonding and each of the first plurality of contact pads is bonded to a corresponding one of the second plurality of contact pads by a metal-metal bonding without any solder.

6. The semiconductor device assembly of claim 1, wherein the device connection layer further comprises: a first plurality of contact pads, all facing and electrically coupled to the multi-mask semiconductor device; a second plurality of contact pads, all facing and electrically coupled to the plurality of semiconductor devices; and a plurality of metal conductive structures, all of which operatively connect the contact pads of the second plurality of contact pads to the contact pads of the first plurality of contact pads.

7. The semiconductor device assembly of claim 1, wherein at least one of the second plurality of contact pads is not perpendicularly aligned with any of the first plurality of contact pads.

8. The semiconductor device assembly of claim 1, wherein each of the second plurality of contact pads is perpendicularly aligned with a corresponding contact pad of one of the first plurality of contact pads.

9. The semiconductor device assembly of claim 1, wherein the plurality of semiconductor devices comprises a plurality of semiconductor device stacks, each of the plurality of stacks being directly coupled to the device interconnect layer.

10. A semiconductor device assembly comprising: A device connection layer comprising: a first surface; a first plurality of contact pads, etc., on the first surface; a second surface opposite to the first surface; a second plurality of contact pads, etc., on the second surface; a first plurality of conductive structures, etc., electrically coupling each of the first plurality of contact pads to a corresponding contact pad of one of the second plurality of contact pads; and a second plurality of conductive structures, etc., electrically coupling each of a first subset of one of the second plurality of contact pads to a corresponding contact pad of a second subset of one of the second plurality of contact pads; and a plurality of semiconductor devices, etc., carried by the first surface of the device connection layer and electrically coupled to the first plurality of contact pads.

11. The semiconductor device assembly of claim 10, wherein at least one of the first plurality of contact pads is not perpendicularly aligned with any of the second plurality of contact pads.

12. The semiconductor device assembly of claim 10, wherein each of the first plurality of contact pads is perpendicularly aligned with a corresponding contact pad of one of the second plurality of contact pads.

13. The semiconductor device assembly of claim 10, wherein the plurality of semiconductor devices comprises a stack of semiconductor devices operably connected via silicon through-holes.

14. A method of manufacturing a semiconductor device assembly, comprising: A semiconductor device subassembly is provided, the semiconductor device subassembly comprising: a plurality of first semiconductor devices, and a device connection layer formed above the plurality of first semiconductor devices, the device connection layer comprising a first surface facing one of the plurality of first semiconductor devices, and a second surface opposite the first surface having one of a second plurality of contact pads, wherein a first subset of one of the second plurality of contact pads is electrically connected to a second subset of one of the second plurality of contact pads via a plurality of photomask bridging conductors; and a second surface of the device connection layer for bonding a second semiconductor device to the semiconductor device subassembly, wherein the second semiconductor device comprises a continuous semiconductor substrate having first and second circuit regions separated from each other by a photomask edge region having no electrical conductors, such that bonding the second semiconductor device to the semiconductor device subassembly electrically couples the first and second circuit regions to each other via the photomask bridging conductors.

15. The method of claim 14, wherein the first surface of the device connection layer has a first plurality of contact pads operably coupled to the plurality of first semiconductor devices by means of a plurality of metal conductive structures.

16. The method of claim 15, wherein each of the first plurality of contact pads is electrically connected to a corresponding contact pad of one of the second plurality of contact pads, such that bonding the second semiconductor device to the semiconductor device subassembly electrically couples the second semiconductor device to the plurality of first semiconductor devices through the plurality of metallic conductive structures.

17. The method of claim 14, wherein bonding the second semiconductor device to the second surface of the device interconnect layer includes forming a hybrid bonding, comprising dielectric-dielectric bonding and metal-metal bonding.

18. The method of claim 17, wherein the hybrid joint does not contain any welding material.

19. The method of claim 14, wherein providing the semiconductor device sub-assembly includes hybrid bonding of wafers containing the plurality of first semiconductor devices into a vertical stack.

20. The method of claim 14, wherein bonding the second semiconductor device to the semiconductor device subassembly includes a wafer-level bonding operation.

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