A graphene-containing laminate

Abstract

A graphene-containing laminate (100) is provided, comprising: a substrate (105); a graphene layer structure (110) on the substrate (105); a conformal barrier layer (115) on the graphene layer structure (110), wherein the barrier layer (115) is a dielectric metal oxide or silicon nitride and has a first thickness of at least 3 nm; and a dopant layer (120) on the barrier layer (115), wherein the dopant layer (120) is formed of one or more of the following: vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer (120) has a second thickness, and the ratio of the first thickness to the second thickness is 1:1 to 1:10.

Description

[Technical Field]

[0001] This invention relates to a graphene-containing stack and a method for manufacturing the graphene-containing stack, as well as an electronic device comprising the stack, and more particularly, a Hall-sensor. More specifically, the stack comprises a dopant layer having a charge carrier concentration that modulates the graphene layer structure of the stack. [Previous Technology]

[0002] Graphene is a leading two-dimensional material that has been incorporated into many products due to its superior properties. Graphene's electronic properties are particularly remarkable and allow for the production of electronic devices (specifically microelectronic components) that exhibit properties several orders of magnitude better than their non-graphene counterparts. Most notably, graphene is used in electronic devices and their constituent components, including transistors, LEDs, photovoltaic cells, Hall effect sensors, diodes, electro-optic modulators (EOMs), and the like.

[0003] Therefore, a wide range of electronic devices with integrated graphene layer structures (single-layer or multi-layer graphene) are known in the prior art to provide improvements over earlier devices and electronic products. These improvements include structural improvements through the use of thinner and lighter materials (which can produce flexible electronic components) and performance improvements such as increased electrical and thermal conductivity, resulting in higher operating efficiency.

[0004] It is known to provide graphene layer structures with a range of different charge carrier concentrations, and low values ​​are useful for certain applications. The charge carrier concentration can be optimized by changing the growth conditions. The inventors have discovered that the most efficient method for producing high-quality graphene, particularly directly on a substrate providing a non-metallic surface suitable for subsequent use in electronic devices, is disclosed in WO 2017 / 029470 (the contents of which are incorporated herein by reference in their entirety).

[0005] One way to further reduce the charge carrier concentration is through doping, as known from WO 2017 / 029470. This method involves intentionally introducing a dopant to dedope the graphene material and reduce the charge carrier concentration (e.g., n-type doped p-type graphene layers). The method in WO 2017 / 029470 involves directly doping graphene during production, for example, by using CH3Br as a precursor. However, the presence of dopant atoms can lead to a decrease in carrier mobility due to scattering effects.

[0006] Another method for reducing the charge carrier concentration is disclosed in WO 2021 / 008938, which relates to a method for producing a polymer-coated graphene layer structure. This disclosure discloses forming graphene on a substrate by CVD (preferably using the method disclosed in WO 2017 / 029470), the graphene having a first charge carrier concentration, and coating the graphene layer structure with a polymer composition to form an impermeable coating, the coated graphene having a second charge carrier concentration that can be less than 10¹² cm⁻². This low charge carrier concentration is achieved by using a dopant in the coating to counteract the intrinsic doping of the graphene formed directly on the substrate by CVD.

[0007] WO 2019 / 125267 relates to a method for assembling molecules on the surface of a two-dimensional material formed on a substrate, wherein the molecules (e.g., F4TCNQ) have diffused through a spacer layer (e.g., PMMA) by means of an annealing step, thereby providing spacer layer for embedding the molecules assembled on the surface of the 2D material.

[0008] The applicant’s WO 2023 / 237561 relates to graphene-containing stacks, wherein a transition metal oxide with a high work function is directly formed on the graphene layer structure, and the thickness is in the range of 0.1 nm to 5 nm to control the degree of doping.

[0009] In the field of alternative low-dimensional materials, at the 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, 1-4, the "Barrier Booster for Remote Extension Doping and its DTCO for 1D & 2D FETs" proposed a "barrier booster" for remote extension doping in low-dimensional materials (LDMs) (e.g., 1D carbon nanotubes (CNTs) and 2D MoS2).

[0010] Nature Electronics 2021, Vol. 4, 664-670 "Remote modulation doping in van der Waals heterostructure transistors" and EP 4386858, in which the inventor is a co-author, relate to high-mobility atomic-layer semiconductor devices based on modulation doping and methods for fabricating them, which prevent charge scattering caused by ionized impurities by modulating the dopant, thereby spatially separating the dopant from the channel layer of the atomic-layer semiconductor device having an atomic-layer semiconductor heterojunction structure with band alignment.

[0011] US 2024 / 178307 relates to semiconductor devices including multilayer gate dielectric layers and electronic devices including such semiconductor devices.

[0012] Adv. Mater. Interfaces 2017, 4, 1700232 "Atomic Layer Deposition for Graphene Device Integration" provides a review of different methods for achieving uniform deposition of ALD on graphene.

[0013] Appl. Phys. Lett. 2012, 100, 173113 "Substrate-assisted nucleation of ultra-thin dielectric layers on graphene by atomic layer deposition" teaches that, compared with thicker graphite layers or inert SiO2, the wettability of ALD Al2O3 films is significantly increased with the assistance of a metal substrate (Cu, Ni-Au) under the graphene layer. This is said to be conveniently achieved by using metal catalysts commonly used during the CVD growth of graphene.

[0014] 2D Materials 2016, 3, 035027 "Physisorbed-precursor-assisted atomic layer deposition of reliable ultrathin dielectric films on inert graphene surfaces for low-power electronics" describes the process of a physically adsorbed precursor-assisted atomic layer deposition (pALD) and studies its mechanism using density functional theory.

[0015] The applicant's WO 2023 / 067309 (and GB 2613923) relates to a method for producing an electronic device precursor having an ohmic contact that contacts the edge portion of a graphene layer structure covered by a dielectric material. This precursor is suitable for Hall effect sensors.

[0016] Despite such advancements in the prior art, continuous improvements are still needed to allow for the integration of high-quality graphene with desired charge carrier concentrations consistently obtained between wafers and between devices. Furthermore, given the inherent nature of graphene grown directly on a substrate, methods for forming high-quality dielectric layers thereon for device fabrication are also required. The present invention seeks to provide improved graphene-containing laminates and related electronic devices incorporating them, which overcome or substantially reduce various problems associated with the prior art or at least provide commercially available alternatives. [Summary of the Invention]

[0017] Therefore, a first aspect of the present invention provides a graphene-containing laminate comprising: a substrate; a graphene layer structure on the substrate; a conformal barrier layer on the graphene layer structure, wherein the barrier layer is a dielectric metal oxide or silicon nitride and has a first thickness of at least 3 nm; and a dopant layer on the barrier layer, wherein the dopant layer is formed of one or more of the following: vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and the ratio of the first thickness to the second thickness is 1:1 to 1:10.

[0018] This disclosure will now be further elaborated. In the following paragraphs, different variations / implementations of this disclosure are defined in more detail. Unless explicitly indicated otherwise, each variation / implementation so defined may be combined with any other one or more variations / implementations. Specifically, any feature indicated as preferred or advantageous may be combined with any other one or more features indicated as preferred or advantageous.

[0019] A second aspect of the present invention provides a method for manufacturing a graphene-containing multilayer, the method comprising: providing a substrate; forming a graphene layer structure on the substrate; forming a conformal barrier layer on the graphene layer structure by evaporation deposition or ALD, wherein the barrier layer is a dielectric metal oxide or silicon nitride and has a first thickness of at least 3 nm; and forming a dopant layer on the barrier layer by evaporation deposition or ALD, wherein the dopant layer is formed of one or more of the following: vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and the ratio of the first thickness to the second thickness is 1:1 to 1:10.

[0020] This document also describes another aspect, which provides a method for manufacturing a graphene-containing multilayer, the method comprising: providing a sapphire substrate having a c-plane crystalline growth surface; forming a graphene layer structure directly on the growth surface of the substrate by CVD; and forming a conformal barrier layer on the graphene layer structure by ALD, wherein the barrier layer is a dielectric metal oxide and has a first thickness of at least 3 nm; wherein the ALD is performed at a temperature below 80°C.

Implementation Method

[0022] Unless the context clearly indicates otherwise, it is intended that the features revealed by any method may be combined with those revealed with respect to graphene-containing stacks, and vice versa. Thus, graphene-containing stacks can be obtained by this method and this method may also be a method suitable for manufacturing the graphene-containing stacks described herein.

[0023] This invention relates to a graphene-containing multilayer and a method for forming a graphene-containing multilayer. As described in more detail herein, the graphene-containing multilayer comprises a substrate having a graphene layer structure, a first metal oxide (or silicon nitride) layer as a barrier layer, and a second metal oxide layer as a dopant layer formed of one or more metal oxides having a high work function. Therefore, there are no intermediate layers between any given layers referred to as being "on" another layer.

[0024] Graphene is a well-known two-dimensional material, referring to an allotrope of carbon consisting of a single layer of carbon atoms in a hexagonal lattice. As used herein, graphene refers to one or more graphene layers. Therefore, this invention relates to the formation of single-layer and multilayer graphene. As used herein, graphene refers to a graphene layer structure preferably having 1 to 10 single-layer graphene layers. In many subsequent applications of graphene-containing stacks, a single graphene layer is particularly preferred due to its unique electronic properties (especially for Hall sensors). Therefore, a single-layer graphene structure is preferred. However, multilayer graphene may be preferred for certain applications, in which case 2 or 3 layers of graphene may be preferred.

[0025] The graphene layer structure is disposed on a substrate, typically on a non-metallic surface of the substrate. Preferably, the surface is an electrically insulating surface (e.g., the substrate may be a silicon substrate with a silicon dioxide surface). The substrate may also be a CMOS wafer, which may be silicon-based and have associated circuitry embedded within the substrate. The substrate may also contain one or more layers (e.g., regions or channels of embedded waveguide materials such as silicon nitride suitable for EOM).

[0026] Preferably, the non-metallic surface on which the graphene layer structure is disposed is silicon (Si), silicon carbide (SiC), silicon nitride (Si3N4), silicon dioxide (SiO2), sapphire (Al2O3), aluminum gallium oxide (AGO), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), yttrium oxide-stabilized hafnium dioxide (YSH), yttrium oxide-stabilized zirconium oxide (YSZ), magnesium aluminate (MgAl2O4), yttrium orthoaluminate (YAlO3), or strontium titanate. The non-metallic surface is composed of silicon nitride, silicon dioxide, sapphire, aluminum nitride, scandium aluminum oxide, gallium scandium oxide, erbium oxide (Er2O3), magnesium difluoride (MgF2), calcium difluoride (CaF2), strontium difluoride (SrF2), barium difluoride (BaF2), scandium trifluoride (ScF3), germanium (Ge), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN), and / or III / V semiconductors, such as aluminum nitride (AlN) and gallium nitride (GaN). Preferably, the non-metallic surface is silicon nitride, silicon dioxide, sapphire, aluminum nitride, YSZ, scandium oxide, aluminum scandium oxide, gallium scandium oxide, germanium, h-BN, and / or calcium difluoride. More preferably, the non-metallic surface is sapphire or a rare-earth metal oxide (e.g., yttrium-stabilized zirconium oxide, scandium oxide, scandium aluminum oxide, or scandium gallium oxide). In some embodiments, the non-metallic surface may have a specific crystal orientation, wherein a <111> cubic crystal system (e.g., for rare-earth metal oxides YSZ or Sc2O3, or CaF2) or a <1-102> hexagonal crystal system (i.e., the r-plane, e.g., for sapphire) is preferred.

[0027] According to some aspects of the present invention, the inventors have found that c-plane sapphire (i.e., <0001>) is ideal in cases where the barrier layer is to be formed by low-temperature ALD as further described herein.

[0028] In some preferred embodiments, the substrate includes, or is composed of, a first layer providing a non-metallic surface and a support layer. In some embodiments, the substrate may be composed of such a material. In some preferred embodiments, the substrate includes, or is composed of, a first (or upper) layer providing a non-metallic surface and a support layer. Preferably, the support layer comprises silicon. The silicon support layer includes a "pure" silicon wafer (consisting substantially of doped or undoped silicon) or may be referred to as a CMOS wafer, which includes additional associated circuitry embedded therein. The first layer may preferably be formed of an inorganic oxide or nitride (such as those described herein) and provide a non-metallic surface. Preferably, the substrate does not contain native silicon oxide that can be removed from the surface of the silicon support prior to the formation of the first layer.

[0029] The silicon support layer is typically much thicker than the layers above it. When present and in the presence of the support layer, it typically has a thickness of 250 µm to 1.5 mm, for example, 400 µm to 1 mm. On the other hand, the layers above it are substantially thinner. Preferably, the thickness of the layer is at least 2 nm, preferably at least 5 nm and / or less than 500 nm, preferably less than 100 nm. A suitable range for the layer thickness is preferably 5 nm to 100 nm, preferably 10 to 50 nm. In some embodiments, an extremely thin layer is preferred and the layer thickness may preferably be 2 nm to 10 nm.

[0030] The graphene-containing stack comprises a conformal barrier layer on the graphene layer structure. That is, the barrier layer provides a uniform layer that completely covers the graphene layer structure. The barrier layer is formed of dielectric metal oxide or silicon nitride and has a thickness of at least 3 nm to ensure a fully aggregated and conformal layer to isolate the graphene layer structure from other layer entities (and to provide desired protection from atmospheric contamination, which could otherwise cause electronic properties to drift over time).

[0031] In a preferred embodiment, the barrier layer is formed of aluminum oxide or hafnium dioxide. These dielectric metal oxides are common in microelectronic manufacturing processes with high dielectric constants (so-called high-k dielectrics). To avoid doubt, at least in the case of a dopant layer, the barrier layer is not formed of a metal oxide suitable for a dopant layer, and therefore generally has a lower work function, and when directly disposed on the graphene surface, has no significant effect on the charge carrier concentration.

[0032] Advantageously, both the barrier layer and the dopant layer (as further explained below) can be deposited to the desired thickness using evaporation deposition techniques, thereby simplifying the manufacturing process compared to other techniques such as chemical deposition (e.g., ALD). Preferred evaporation techniques include thermal evaporation and electron beam evaporation.

[0033] In some embodiments, the barrier layer is a dielectric metal oxide, which is formed on the graphene layer structure by low-temperature ALD, specifically at a temperature below 80°C.

[0034] ALD is a known technique. It comprises at least two precursors (a metallic precursor and a non-metallic (i.e., oxygen) precursor) reacting in a sequential, self-limiting manner. Due to the layer-by-layer growth mechanism, repeated cycles of individual precursors allow layers to grow in a conformal manner (i.e., a uniform thickness across the entire surface).

[0035] Suitable precursors for the required metal element (e.g., aluminum or hafnium atoms for alumina and hafnium dioxide) are well known, commercially available, and not particularly limited. Preferably, the second metal oxide layer is formed by ALD using an alkyl metal, metal alkoxide, or metal halide as a metal precursor (i.e., the alkyl metal is (R)nM, the metal alkoxide is (RO)nM, and the metal halide is (X)nM). Metal halides, such as metal chlorides (e.g., AlCl3 and HfCl4), can be used. Alternatively, metal amides, metal alkoxides, or organometallic precursors can be used. Hafnium precursors include, for example, tetra(dimethylamino)hafnium (IV), tetra(diethylamino)hafnium (IV), tributanol hafnium (IV), and dimethylbis(cyclopentadienyl)hafnium (IV). Preferably, the barrier layer is aluminum oxide, and more preferably, other precursors used for ALD are trialkylaluminum or trialkylaluminum, such as trimethylaluminum, trimethylaminoaluminum, trimethylaluminum (2,2,6,6-tetramethyl-3,5-heptanediol), or trimethylaluminum (acetylacetonate).

[0036] Suitable oxygen precursors include one or more of water (H2O), O2 (e.g., O2 plasma) and ozone (O3), and preferably, the oxygen precursor is water.

[0037] Typically, the deposition temperature for ALD is between 100°C and 300°C. However, the inventors have discovered that temperatures below 80°C are preferable for growth on pristine graphene (i.e., substantially defect-free graphene that has been directly grown on a substrate by CVD without transfer) and provide a barrier layer with superior quality and improved dielectric properties. This is particularly relevant to the barrier layers directly deposited on graphene layer structures described herein, as low-temperature deposition facilitates growth on materials that would otherwise lack nucleation sites (e.g., from defects or impurities).

[0038] Preferably, ALD is performed at a temperature of at least 60°C, for example, 60°C to 70°C. Although significant improvements have been observed at lower temperatures, at 50°C, the surface roughness of the barrier layer begins to increase and the formation of pinholes in the layer becomes more prevalent. The range of 60°C to 70°C provides a specific window suitable for growing metal oxides on CVD-grown graphene. Therefore, the barrier layer preferably has a root mean square (RMS) roughness of less than 0.5 nm, even at a thickness of less than 10 nm, for example, less than 7 nm. The barrier layer can be characterized using AFM and / or elliptic polarization (these are conventional techniques in this art).

[0039] More specifically, this low-temperature ALD process on pristine graphene can be described as atomic layer deposition assisted by physicoadsorption precursors, and is not expected to be limited by theory. It is believed that the use of c-plane sapphire, especially near the surface of the graphene layer structure, provides better polarization-induced physicoadsorption of the metal precursor. That is, the inventors believe that crystal orientation can have a significant impact on the ALD deposition process and can be used to enhance low-temperature growth. Polarization can lead to stronger dipole-induced dipole interactions, which in turn retains the adsorbate on the surface, even at the high temperatures inherent to the formation of the dielectric material. Therefore, preferably, the first step of ALD is the metered feeding of the metal precursor (i.e., prior to the metered feeding of the oxygen precursor). Thus, this process is a seedless process (which is an alternative to providing nucleation sites for barrier layer formation, such as aluminum evaporation) and advantageously mitigates the risk of damaging the graphene layer structure.

[0040] In some preferred embodiments, the ALD includes a purging step after each step of metered feeding of the metal precursor and metered feeding of the oxygen precursor, wherein the purging duration is at least 15 seconds, for example, 20 to 60 seconds. This is significantly longer than the purging duration typically required for ALD growth at higher temperatures, which is typically less than 10 seconds, for example, about 6 seconds. With low-temperature ALD, the desorption rate of excess reactants from the ALD chamber (reactor) is significantly reduced, making a longer purging time desirable to effectively remove unreacted precursors and byproducts from the chamber to avoid CVD (gas phase) reactions and layer contamination in each alternating ALD step.

[0041] In view of the foregoing, a particular embodiment of any of the methods described herein includes: providing a sapphire substrate having a c-plane crystalline growth surface; forming a graphene layer structure directly on the growth surface of the substrate by CVD; and forming a conformal barrier layer on the graphene layer structure by ALD, wherein the barrier layer is a dielectric metal oxide and has a first thickness of at least 3 nm; wherein the ALD is performed at a temperature above 60°C and below 80°C; wherein the ALD is performed by metering a metal precursor and H2O as an oxygen precursor (e.g., for forming alumina and / or hafnium oxide); and preferably, wherein the ALD includes a purging step after each step of metering the metal precursor and metering the oxygen precursor, the purging duration being at least 15 seconds.

[0042] At least the graphene-containing stack of the first state sample herein further includes a dopant layer on the barrier layer, wherein the dopant layer is formed of one or more of the following: vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide. The inventors have discovered that these metal oxides have a high work function, large enough to influence the observed charge carrier concentration of the graphene layer structure via the distal end of the barrier layer. This distal doping can be alternatively referred to as a dielectric-induced field, which, with a sufficiently thick dopant layer and / or a thin barrier layer, allows modulation of the charge carrier concentration of the graphene layer structure relative to the stack before the addition of the dopant layer. That is, the stack product of the present invention advantageously has a consistent and stable charge carrier concentration.

[0043] The thickness of the dopant layer is typically adjusted relative to the thickness of the barrier layer. As described herein, the ratio of the thickness of the barrier layer (i.e., the first thickness) to the thickness of the dopant layer (i.e., the second thickness) is 1:1 to 1:10. Thus, the dopant layer has a corresponding thickness of at least 3 nm, and preferably, the ratio is 1:3 to 1:5.

[0044] As the thickness of the barrier layer increases, the thickness of the dopant layer preferably increases to provide an equivalent doping effect on the graphene layer structure. However, it is not desirable to be theoretically limited to a general limit on the thickness of the dopant layer, beyond which the doping effect weakens. Therefore, a careful balance needs to be struck between the thicknesses of the barrier layer and the dopant layer. Preferably, the barrier layer is thin, i.e., at most 15 nm, or even more preferably at most 10 nm (e.g., 5 nm to 10 nm). This thickness allows for conformal deposition of the layer, which substantially isolates the doped layer from the graphene layer structure. The conformal barrier is necessary to ensure consistent doping across the entire region of the two-dimensional material (which is in turn necessary for the mass production of devices with consistent properties between devices). If the barrier layer is too thick, the field effect of the doped layer weakens.

[0045] In the applicant's WO 2023 / 237561, it is crucial to deposit a transition metal oxide (e.g., molybdenum oxide) directly on the surface of graphene. The thickness of this layer is in the range of 0.1 nm to 5 nm, with a thickness of approximately 1 nm being preferred in some examples to provide the desired level of doping. This nominal thickness is typically provided by islands rather than a uniform layer. The inventors have found that accurately depositing thinner layers with the desired nominal thickness can be challenging, and the present invention constructs this process by including a barrier layer, allowing for the deposition of thicker and more conformally oriented and uniformly doped layers of transition metal oxides with better process control.

[0046] By reducing the influence of the doping layer on the charge carrier concentration variation of the graphene layer structure, the present invention advantageously provides a significant increase in control over charge carrier concentration modulation for a given amount of doped layer deposited. Therefore, the thickness of the doped layer can be much greater than anticipated in the prior art, and can be in the range of 5 to 40 nm, preferably 10 to 30 nm. That is, with the presence of the barrier layer, the charge carrier concentration of the graphene layer structure is more finely tuned with respect to the equivalent variation of the doped layer thickness. Due to the weaker dielectric induced field, this process control provides significantly reduced charge carrier concentration variability in the final device, both within the stack (i.e., between devices) and between manufacturing runs (i.e., between wafers), which is crucial for the commercial production of electronic devices.

[0047] Therefore, in a preferred embodiment, the present invention allows selection of a first thickness, a second thickness, and the ratio therebetween to provide a graphene layer structure of a final stack with a charge carrier concentration of less than 5 × 10¹² cm⁻² (as measured at 0 V and 25 °C), preferably less than 1 × 10¹² cm⁻². This charge carrier concentration, close to the Dirac point, allows electronic devices to benefit from the unique electronic properties of graphene, which is particularly advantageous for sensors. As further explained herein, such devices advantageously do not require a gate (contact) and can therefore be provided and used without a gate or with an applied gate voltage.

[0048] In other preferred embodiments, the stacked body is further comprised on and across a passivation layer of a dopant layer. The passivation layer may comprise or consist of aluminum oxide or hafnium dioxide. This layer may be deposited by any conventional method (e.g., evaporation or ALD) and typically completely encapsulates the thin layer on the substrate from atmospheric contamination. This is advantageous for devices in which the graphene, barrier, and dopant layers have been patterned, thereby exposing the edges of the graphene, and the passivation layer encapsulates the edges deposited adjacent to the exposed substrate surface. The passivation layer is typically thicker than the barrier and / or dopant layers and may have a thickness of 50 nm or greater. There is no specific upper limit, but the capping layer is typically not thicker than 500 nm, preferably less than 250 nm.

[0049] Preferably, the graphene layer structure is formed directly on the substrate by CVD. The preparation of sufficiently large areas of graphene with high uniformity has been a major problem in this technology, hindering its application in commercial processes and final electronic devices. The standard in this technology is the fabrication of graphene on copper foil or other catalytic metal substrates via CVD. Subsequently, much research and development has focused on optimizing the process by which graphene is transferred from these substrates to those of interest for use in electronic devices (i.e., non-metallic substrates, such as semiconductors like silicon and insulators like sapphire).

[0050] However, the inventors have found that graphene grown on copper is inevitably contaminated, even if not by copper, by at least other materials necessary for the transfer. These include transfer polymers (e.g., PMMA), metal etchants, and solvents used to remove the polymers. However, polymer residues are never completely removed, and graphene produced by these methods cannot be without transfer polymers and / or copper. Furthermore, the physical manipulation of graphene during transfer results in defects in the atomically thin material. While the addition of barrier layers and dopants, as described herein, can advantageously offset changes in charge carrier concentration caused by transfer, unintentional doping, particularly from the catalytic metal substrate and the etching solution, also leads to insufficient consistency of the produced material between samples. This consistency is required for the commercial production of electronic devices, making the manufacturing methods described herein more consistent between wafers and between devices when graphene is grown directly on a substrate by CVD.

[0051] The solid transfer of two-dimensional materials can introduce many defects that adversely affect physical and electronic properties. Therefore, using conventional techniques in this field (such as AFM and energy-dispersive X-ray (EDX) spectroscopy), those skilled in this field can easily determine whether the graphene layer structure and even the device contain a CVD-grown graphene layer structure that has been directly grown.

[0052] Preferably, the graphene layer structure is formed directly on a substrate by CVD. Formation can be considered synonymous with synthesis, deposition, production, and growth. CVD generally refers to a series of chemical vapor deposition techniques, each of which involves deposition to produce thin film materials, such as two-dimensional crystalline materials like graphene. Volatile precursors (i.e., those in the gas phase or suspended in a gas) are decomposed to release the necessary substances to form the desired material, which in the case of graphene is carbon. As used herein, CVD is intended to refer to thermal CVD, such that the formation of graphene from the decomposition of carbon-containing precursors is a result of the thermal decomposition of said carbon-containing precursors.

[0053] Preferably, the temperature of the growth surface during CVD is 700°C to 1350°C, more preferably 800°C to 1250°C, and even more preferably 1000°C to 1250°C. The inventors have found that these temperatures are particularly effective for providing graphene growth directly on the material described herein by CVD. Preferably, the CVD reaction chamber used in the method disclosed herein is a cold-walled reaction chamber, wherein a heater coupled to the substrate is the sole heat source of the chamber.

[0054] As those skilled in the art will understand, the temperature setting input to some CVD reactors (i.e., the set temperature) is typically higher than the actual wafer temperature (e.g., MOCVD reactors from Aixtron®). The set temperature can be 100°C (or higher) higher than the wafer temperature, for example, 1,300°C to 1,400°C. The wafer temperature can be measured using conventional techniques, such as using an optical probe. Other devices may have temperature feedback control, thereby enabling the reactor to achieve the same wafer temperature as the input temperature (e.g., high-spin-rate MOCVD reactors from Veeco®).

[0055] In a preferred embodiment, the CVD reaction chamber includes a closely coupled nozzle having a plurality of precursor entry points or an array of precursor entry points. Such CVD apparatuses with closely coupled nozzles are known to be used in MOCVD processes. Therefore, the method can alternatively be considered as being implemented using an MOCVD reactor with closely coupled nozzles. In either case, the nozzles are preferably configured to provide a minimum spacing of less than 100 mm, more preferably less than 25 mm, and even more preferably less than 10 mm between the substrate surface and the plurality of precursor entry points. It should be understood that a constant spacing means that the minimum spacing between the substrate surface and each precursor entry point is substantially the same. The minimum spacing refers to the minimum spacing between the precursor entry point and the substrate surface. Therefore, this embodiment relates to a "vertical" configuration whereby the plane containing the precursor entry points is substantially parallel to the plane of the exposed substrate surface (i.e., the growth surface).

[0056] The precursor entry point before entering the reaction chamber is preferably cooled. The inlet or the nozzle during use is preferably actively cooled by an external coolant (e.g., water) to maintain a relatively cool temperature at the precursor entry point, such that the temperature of the precursor after passing through multiple precursor entry points and entering the reaction chamber is below 100°C, preferably below 50°C. For the avoidance of doubt, adding a precursor at a temperature higher than the ambient temperature does not constitute a heated chamber, as it would consume the temperature within the chamber and be partially responsible for establishing the temperature gradient within the chamber.

[0057] Preferably, a sufficiently small spacing between the substrate surface and the plurality of precursor entry points, combined with cooling of the precursor entry points and heating of the substrate to the extent of precursor decomposition, generates a sufficiently steep thermal gradient extending from the substrate surface to the precursor entry points to allow for the formation of graphene on the substrate surface. As disclosed in WO 2017 / 029470, a very steep thermal gradient can be used to facilitate the formation of a high-quality and uniform two-dimensional material layer directly on a non-metallic substrate, preferably across the entire surface of the substrate. The substrate may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches), or at least 30 cm (12 inches). Particularly suitable equipment for the methods described herein includes the Aixtron® Close-Coupled Showerhead® reactor and the Veeco® TurboDisk reactor.

[0058] Therefore, in a preferred embodiment where the method of the present invention relates to the use of the method disclosed in WO 2017 / 029470, forming a graphene layer structure by CVD comprises: providing a substrate on a heated base in a closely coupled reaction chamber having a plurality of cooling inlets configured such that, in use, the inlets are distributed across the entire growth surface of the substrate and are at a constant interval from the substrate; cooling the inlets to below 100°C; introducing a carbon-containing precursor in the gas phase and / or suspended in a gas into the closely coupled reaction chamber via the inlets; and heating the base to achieve a growth surface temperature at least 50°C above the decomposition temperature of the precursor to provide a thermal gradient between the growth surface and the inlets, the gradient being steep enough to allow the carbon released from the decomposed precursor to form graphene; wherein the constant interval is less than 100 mm, preferably less than 25 mm, and even more preferably less than 10 mm.

[0059] In another preferred embodiment where the method involves using the method disclosed in WO 2019 / 138231, forming a graphene layer structure by CVD comprises: providing a substrate on a heating base in a reaction chamber having a plurality of inlets configured such that, in use, the inlets are distributed across the entire growth surface and are at constant intervals from the substrate; rotating the heating base at a rotational speed of at least 600 rpm, preferably up to 3000 rpm; introducing a carbon-containing precursor in the gas phase and / or suspended in a gas into the reaction chamber via the inlets; and heating the base to achieve a growth surface temperature at least 50°C above the decomposition temperature of the precursor; wherein the constant interval is at least 12 cm, preferably up to 20 cm.

[0060] The most common carbon-containing precursor used for graphene growth in this technology is methane (CH4). The inventors have found that, preferably, the carbon-containing precursor used to form graphene is an organic compound, that is, a chemical compound or molecule containing carbon-hydrogen covalent bonds, comprising two or more carbon atoms. The carbon-containing precursor is preferably a C3-C10 organic compound composed of carbon and hydrogen, and, where appropriate, oxygen, nitrogen, fluorine, chlorine, and / or bromine, or even more preferably a C6-C9 organic compound. In a preferred embodiment, the precursor does not contain heteroatoms, such that the precursor is composed of carbon and hydrogen. In other words, the carbon-containing precursor is preferably a hydrocarbon, preferably an alkane. Also preferably, the organic compound contains at least two methyl groups (-CH3). Preferred organic compounds used as carbon-containing precursors and methods for forming graphene from them by CVD are described in GB 2604377.

[0061] Graphene formed directly on a substrate by this method typically has intrinsic n-type doping at the desired level, which is well-suited to be offset by doping of a doped layer with a high work function (whose doping is directly related to the layer thickness), as described herein. The "growth state" doping level of the graphene can be fine-tuned by conventional modifications to the growth process, such as by the selection of the substrate, precursor, and growth / decomposition temperature. Ultimately, the first thickness, the second thickness, and the ratio of the first thickness to the second thickness can be selected to provide a graphene layer structure with a charge carrier concentration of less than 5 × 10¹² cm⁻². However, the graphene layer structure can be provided on a non-metallic surface of the substrate by known transfer techniques, such as copper foil, although this is less suitable for large-scale manufacturing due to the potential variability in the electronic properties of the graphene layer structure provided on the substrate. Furthermore, such directly CVD-grown graphene is typically p-type, which does not allow for low charge carrier concentrations close to the Dirac point.

[0062] According to another aspect of the present invention, an electronic device is provided, which includes a graphene-containing stack (i.e., manufactured from the stack) and has at least first and second electrical contacts electrically connected via the graphene layer structure.

[0063] Graphene-containing stacks comprising doped layers are particularly suitable for the fabrication of sensors, taking advantage of the desired low charge carrier concentration (e.g., below 5 × 10¹² cm⁻²) that can be consistently provided by the combination of the barrier layer and the dopant layer thereon. Examples of sensors that can benefit from the formation of such graphene-containing stacks include Hall sensors, temperature sensors, and magnetoresistive sensors (as described, for example, in WO 2022 / 129606). In a preferred embodiment, the device is a Hall sensor.

[0064] Contacts are standard components in the manufacture of electronic devices, well known to those skilled in the art, and can be deposited during and / or after the fabrication of graphene-containing stacks. Contacts provide connection points to electronic circuitry (e.g., via metal wires bonded to the contacts or by means of soldering using flip-chip solder bumps). Thus, when an electronic device is mounted in electronic circuitry and supplied with current, the electronic device is a functional device.

[0065] Typically, the contacts are metallic contacts, such as those formed of chromium, titanium, aluminum, nickel, tungsten, and / or gold. Typically, multiple contacts are provided that contact the graphene layer structure containing the graphene stack. Typically, at least two contacts are provided that are electrically connected to the graphene layer structure, typically in direct contact with the graphene layer structure, and may be referred to as source and drain contacts. The contacts may have edges and / or surfaces that contact the graphene layer structure, preferably only edge contact. It should be understood that the contacts will be deposited on an adjacent exposed substrate to contact the edges of the graphene layer structure. The contacts may be deposited using PVD technology (e.g., electron beam evaporation).

[0066] Advantageously, the device does not require gate contacts (i.e., for devices where gate contacts are theoretically not necessary, such as sensors as opposed to transistors). Therefore, the preferred device does not include gate contacts. Thus, this disclosure provides for the use of a device comprising the graphene-containing stack described herein without applying a gate voltage. For example, a Hall sensor can be used to detect magnetic fields without applying a gate voltage. The inventors have discovered that the combination of a conformal barrier layer and a dopant layer allows for the construction of devices that do not require gate contacts.

[0067] In other embodiments, given the high-quality dielectric layer properties achieved by low-temperature ALD deposition, graphene-containing stacks produced by the methods described herein are preferably used to fabricate devices including top gate contacts, such as transistors. That is, the gate contacts can be directly disposed on the barrier layer, specifically in areas where they are formed thinner, thereby allowing for proportional scaling of the gate oxide, thereby reducing the transistor size. In any case, other devices (e.g., transistors) where the gate contact is a fundamental component may include doped layers to adjust the charge carrier concentration of the graphene layer structure before forming the top gate contact on those other layers.

[0068] As should be understood, a large area of ​​graphene-containing stack (i.e., a wafer, for example, having a diameter greater than or equal to 5 cm (2 inches)) can be processed to fabricate an array of electronic devices on a common underlying substrate. It can then be diced into individual devices such that the electronic devices comprise a portion of a larger graphene-containing stack. Therefore, it should be understood that each of the layers of the graphene-containing stack can substantially extend over the entire area of ​​the underlying substrate. That is, each layer can be disposed on and across the underlying layer, wherein subsequent processing is used to pattern these layers (e.g., by photolithography). Other layers (e.g., passivation layers as described herein) can be deposited after patterning and contact deposition as a means of encapsulating the patterned layers, the exposed edges of the graphene layer structure, and the contacts.

[0069] Figure 1 illustrates a graphene-containing stack 100 in cross-section, comprising: a substrate 105, a graphene monolayer 110 on and across the surface of the substrate 105, a barrier layer 115 on and across the graphene monolayer 110, and a dopant layer 120 on and across the barrier layer 115. In the embodiment illustrated by the stack 100, the barrier layer is formed of aluminum or hafnium dioxide and has a thickness of about 5 nm, with a conformal and uniform thickness across the region of the substrate (wafer). This is typically a wafer with a diameter of 5 cm (2 inches) or greater. The dopant layer is formed of molybdenum oxide (although other transition metal oxides with high work functions as described herein may be used), and its thickness is at least the same as and may be three times that of the barrier layer (e.g., about 15 nm thick).

[0070] Preferably, the graphene monolayer 110 is grown directly on the surface of the substrate 105 by CVD. The substrate 105 is preferably a sapphire substrate, or includes a silicon support layer having a rare earth metal oxide (e.g., scandium oxide) thereon to provide a growth surface.

[0071] FIG2 illustrates, in cross-section, a sensor 200 fabricated from a portion of a graphene-containing stack 100. The sensor includes a substrate 205, a graphene monolayer 210 thereon, a barrier layer 215 thereon, and a dopant layer 220 thereon. The stack of the graphene monolayer 210, the barrier layer 215, and the dopant layer 220 has been co-patterned on the substrate 205 (so that they have the same cross shape when viewed perpendicularly to the substrate). In the illustrated cross-section that bisects the two arms of the cross shape, two metal contacts 225a and 225b have been deposited such that each contact contacts only contact the edge of the graphene monolayer 210 (i.e., not the surface of the graphene monolayer 210), and contacts 225a and 225b have been deposited on adjacent exposed portions of the growth surface of the substrate 205.

[0072] The sensor further includes a passivation layer 230, which may be formed of aluminum or hafnium dioxide, completely encapsulating a co-patterned stack of graphene monolayer 210, barrier layer 215, dopant layer 220, and metal contacts 225a, 225b. As is well known to those skilled in the art, the shape of the stack can be designed to suit the needs of a given application, for example, having well-known Hall bar geometries and cross shapes for Hall sensors. The passivation layer 230 has a thickness of approximately 65 nm.

[0073] Figure 3 is a graph showing the surface profiles of three alumina barrier layers with thicknesses of approximately 6 to 7 nm deposited according to the method described herein. Alumina was deposited on a graphene monolayer grown in an MOCVD reaction chamber on and across the c-plane of a 5 cm (2 inch) sapphire substrate. Each layer was deposited at different temperatures (i.e., 200 °C, 50 °C, and 70 °C). The graph measures the height of the barrier layer across the approximately 5 µm surface of the stack (x-axis) (normalized to approximately 0 nm, expressed in nm on the y-axis). The graphs measured at 200 °C, 50 °C, and 70 °C are shown by lines 305, 310, and 315, respectively. As can be seen from line 305, the alumina grown at 200°C exhibits a considerable number of pinholes and a relatively large surface roughness, with the height typically varying between approximately ±6 nm. Lines 310 and 315 are significantly smoother, which is attributed to the improved ALD deposition process on CVD-grown graphene due to the lower deposition temperature. However, compared to line 315 deposited at 70°C, line 310 shows increased surface roughness at only 50°C, with the height typically varying between approximately ±1 nm (along with an observable pinhole of approximately -4 nm at approximately 1.75 μm). The height profile of line 315 is substantially constant, with an RMS of less than 0.5 nm (approximately 0.25 nm).

[0074] Unless the context clearly indicates otherwise, the singular forms “a (a, an)” and “the” used herein include plural indicators. The term “comprising” is intended to be understood as including such features but not excluding other features, and is also intended to include options that must be limited to the features described. In other words, unless the context clearly indicates otherwise, the term also includes the limitations of “consistently made up of” (intended to mean that certain other components may be present, provided that they do not materially affect the essential properties of the described feature) and “composed of” (intended to mean that other features may not be included such that if the components are expressed as percentages, the sum of the components is 100%, taking into account any unavoidable impurities).

[0075] It should be understood that although the terms "first," "second," etc., may be used herein to describe, for example, various elements, layers, and / or portions, such elements, layers, and / or portions should not be limited by such terms. These terms are used only to distinguish one element, layer, or portion from another element, layer, or portion. It should be understood that the term "on" means "directly on," such that there is no intermediate layer between materials considered "on" another material. For ease of description, spatially relative terms such as "below," "under," "below," "lower," "above," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature and another element(s). It should be understood that, in addition to the orientations illustrated in the figures, spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device as described herein is flipped, an element described as "below" or "under" another element or feature will then be oriented "above" or "on top" of the other element or feature. Therefore, the instance term "below" can encompass both above and below orientations. Devices can be oriented in other ways and the spatial relative descriptors used herein can be interpreted accordingly.

[0076] The lower and upper limits of the values ​​of the features described herein can be better combined to provide a closed range.

[0077] The foregoing detailed description has been provided by way of explanation and illustration and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments described herein will be apparent to those skilled in the art and remain within the scope of the appended claims and their equivalents.

[0078] For the avoidance of doubt, all contents of all documents herein acknowledged are incorporated herein by reference.

[0079] The invention will now be further described with reference to the following numbered clauses.

[0080] 1. A graphene-containing laminate comprising: a substrate; a graphene layer structure on the substrate; a conformal barrier layer on the graphene layer structure, wherein the barrier layer is a dielectric metal oxide or silicon nitride and has a first thickness of at least 3 nm; and a dopant layer on the barrier layer, wherein the dopant layer is formed of one or more of the following: vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and the ratio of the first thickness to the second thickness is 1:1 to 1:10.

[0081] 2. The graphene-containing laminate as in Clause 1, wherein the barrier layer is aluminum oxide or hafnium dioxide.

[0082] 3. The graphene-containing laminate as in Clause 1 or Clause 2, wherein the ratio of the first thickness to the second thickness is 1:3 to 1:5.

[0083] 4. The graphene-containing laminate as described in any of the preceding clauses, wherein the first thickness is 3 to 15 nm.

[0084] 5. The graphene-containing laminate as described in any of the preceding clauses, wherein the second thickness is 5 to 40 nm, preferably 10 to 30 nm.

[0085] 6. The graphene-containing stack as described in any of the preceding clauses, wherein the dopant layer is conformal and has a uniform thickness.

[0086] 7. The graphene-containing laminate of any of the preceding clauses, wherein the substrate is sapphire or silicon-on-rare-earth metal oxide.

[0087] 8. A graphene-containing multilayer as described in any of the preceding clauses, wherein the graphene layer structure is a graphene monolayer.

[0088] 9. A graphene-containing stack as described in any of the preceding clauses, wherein the graphene layer structure has a charge carrier concentration of less than 5 x 10¹² cm⁻².

[0089] 10. A graphene-containing stack as described in any of the preceding clauses, wherein the stack further comprises a passivation layer on the dopant layer, preferably wherein the passivation layer comprises aluminum oxide or hafnium dioxide.

[0090] 11. An electronic device comprising a graphene-containing stack and having at least first and second electrical contacts electrically connected via the graphene layer structure.

[0091] 12. An electronic device as described in Clause 11, wherein the device is a Hall sensor.

[0092] 13. An electronic device as described in Clause 11 or Clause 12, wherein the device does not contain gate contacts.

[0093] 14. A method for manufacturing a graphene-containing multilayer, the method comprising: providing a substrate; forming a graphene layer structure on the substrate; forming a conformal barrier layer on the graphene layer structure by evaporation deposition or ALD, wherein the barrier layer is a dielectric metal oxide or silicon nitride and has a first thickness of at least 3 nm; and forming a dopant layer on the barrier layer by evaporation deposition or ALD, wherein the dopant layer is formed of one or more of the following: vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and the ratio of the first thickness to the second thickness is 1:1 to 1:10.

[0094] 15. The method of Clause 14, wherein the graphene layer structure is formed directly on the substrate by CVD.

[0095] 16. The method of Clause 14 or Clause 15, wherein the first thickness, the second thickness, and the ratio of the first thickness to the second thickness are selected to provide the graphene layer structure with a charge carrier concentration of less than 5 × 10¹² cm⁻².

[0096] 17. The method of any of Clauses 14 to 16, wherein the substrate is a sapphire having an r-plane or c-plane crystalline growth surface, on which the graphene layer structure is formed.

[0097] 18. The method of any of Clauses 14 to 17, wherein the conformal barrier layer is formed on the graphene layer structure by means of ALD at a temperature below 80°C.

[0098] 19. A method for manufacturing a graphene-containing multilayer, the method comprising: providing a sapphire substrate having a c-plane crystalline growth surface; forming a graphene layer structure directly on the growth surface of the substrate by CVD; and forming a conformal barrier layer on the graphene layer structure by ALD, wherein the barrier layer is a dielectric metal oxide and has a first thickness of at least 3 nm; wherein the ALD is performed at a temperature below 80°C.

[0099] 20. The method of claim 19, further comprising: forming a dopant layer on the barrier layer by means of an evaporation deposition technique or an ALD, wherein the dopant layer is formed of one or more of the following: vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and the ratio of the first thickness to the second thickness is 1:1 to 1:10.

[0100] 21. The method of any of Clauses 18 to 20, wherein the conformal barrier layer is formed on the graphene layer structure by means of ALD at a temperature of at least 60°C, preferably 60°C to 70°C.

[0101] 22. The method of any of clauses 14 to 21, wherein the first thickness is 3 to 15 nm, preferably less than 10 nm, and preferably less than 7 nm.

[0102] 23. The method of any of Clauses 18 to 22, wherein the first metering step of the ALD is carried out by metering a metal precursor.

[0103] 24. The method of any of Clauses 18 to 23, wherein the ALD is carried out by quantitatively feeding H2O as an oxygen precursor.

[0104] 25. The method of any of Clauses 18 to 24, wherein the ALD includes a purging step after each step of metering the metal precursor and metering the oxygen precursor, wherein the purging step has a purging duration of at least 15 seconds, preferably 20 to 60 seconds.

[0105] 26. The method of any of Clauses 14 to 25, wherein the dielectric metal oxide is aluminum oxide and / or hafnium dioxide.

[0106] 27. The method of any of Clauses 18 to 26, wherein the barrier layer has a root mean square (RMS) roughness of less than 0.5 nm. [Simplified Explanation of the Diagram]

[0021] The present invention will now be further described with reference to the following exemplary and non-limiting drawings, in which: FIG1 is a cross-sectional view of a graphene-containing multilayer body according to the present invention. FIG2 is a cross-sectional view of a sensor according to the present invention manufactured from the graphene-containing multilayer body shown in FIG1. ​​FIG3 is a graph showing the surface profiles of barrier layers grown at three different temperatures. [Biomaterial Storage]

[0108] None

Claims

1. A graphene-containing laminate comprising: a substrate; a graphene layer structure on the substrate; a conformal barrier layer on the graphene layer structure, wherein the barrier layer is a dielectric metal oxide or silicon nitride and has a first thickness of at least 3 nm; and a dopant layer on the barrier layer, wherein the dopant layer is formed of one or more of the following: vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and the ratio of the first thickness to the second thickness is from 1:1 to 1:

10.

2. The graphene-containing laminate as described in claim 1, wherein the barrier layer is alumina or hafnium dioxide.

3. The graphene-containing laminate as described in claim 1 or claim 2, wherein the ratio of the first thickness to the second thickness is 1:3 to 1:

5.

4. The graphene-containing stack as described in claim 1 or claim 2, wherein the first thickness is 3 to 15 nm.

5. The graphene-containing stack as described in claim 1 or claim 2, wherein the second thickness is 5 to 40 nm.

6. The graphene-containing stack as described in claim 5, wherein the second thickness is 10 to 30 nm.

7. The graphene-containing stack as described in claim 1 or claim 2, wherein the dopant layer is conformal and has a uniform thickness.

8. The graphene-containing laminate as described in claim 1 or claim 2, wherein the substrate is sapphire or a rare earth metal oxide on silicon.

9. The graphene-containing stack as described in claim 1 or claim 2, wherein the graphene layer structure is a graphene monolayer.

10. A graphene-containing stack as described in claim 1 or claim 2, wherein the graphene layer structure has a charge carrier concentration of less than 5 × 10¹² cm⁻².

11. The graphene-containing stack as described in claim 1 or claim 2, wherein the stack further comprises a passivation layer on the dopant layer.

12. The graphene-containing multilayer as described in claim 11, wherein the passivation layer comprises aluminum oxide or hafnium dioxide.

13. An electronic device comprising a graphene-containing multilayer as described in claim 1 and having at least first and second electrical contacts electrically connected via the graphene layer structure.

14. The electronic device as claimed in claim 13, wherein the device is a Hall sensor.

15. The electronic device as described in claim 13 or claim 14, wherein the device does not include a gate contact.

16. A method for manufacturing a graphene-containing multilayer, the method comprising: providing a substrate; forming a graphene layer structure on the substrate; forming a conformal barrier layer on the graphene layer structure by an evaporation deposition technique or an ALD, wherein the barrier layer is a dielectric metal oxide or silicon nitride and has a first thickness of at least 3 nm; and forming a dopant layer on the barrier layer by an evaporation deposition technique or an ALD, wherein the dopant layer is formed of one or more of the following: vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide; wherein the dopant layer has a second thickness, and the ratio of the first thickness to the second thickness is from 1:1 to 1:

10.

17. The method as described in claim 16, wherein the graphene layer structure is formed directly on the substrate by CVD.

18. The method as described in claim 16 or claim 17, wherein the first thickness, the second thickness, and the ratio of the first thickness to the second thickness are selected to provide a graphene layer structure with a charge carrier concentration of less than 5 × 10¹² cm⁻².

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