Interleaving switch cap integrator dac for low noise ramp generation with lower avdd power supply

Abstract

This invention describes an embodiment of an interleaved switched-capacitor integrator digital-to-analog converter (DAC) for generating a low-noise ramp when operating with a low power supply voltage. In one embodiment, an image sensor includes: a plurality of pixels configured in a pixel array of columns and rows; a bit line electrically coupled to an active pixel; and a switched-capacitor current digital-to-analog converter (IDAC) coupled to the bit line. The IDAC includes a plurality of switch groups, each switch group being configured to receive a control signal for controlling the opening and closing of switches in the switch group. These control signals are time-shifted. An integrator is coupled to the plurality of switch groups. The integrator is configured to generate an output signal based on input signals received from the plurality of switch groups.

Description

Technical Field

[0001] This disclosure generally relates to image sensors, and more particularly to an interleaved switched-capacitor integrator digital-to-analog converter (DAC) for generating a low-noise ramp when operating with a low power supply voltage. Prior Technology

[0002] Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, and in medical, automotive, and other applications. The technologies used to manufacture image sensors are constantly and rapidly advancing. For example, the demand for higher image sensor resolution and lower power consumption has driven further miniaturization and integration of image sensors into digital devices.

[0003] A typical image sensor operates in response to image light incident on it from an external scene. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and immediately generate an image charge upon absorption. The image charge of each pixel can be measured as an output voltage of each photosensitive element, which varies according to the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, thereby generating a digital image (i.e., image data) representing the external scene.

[0004] Integrated circuit (IC) technology for image sensors is constantly being improved, particularly in terms of increasing resolution and reducing power consumption. These improvements typically involve scaling down device geometry to achieve lower manufacturing costs, higher device integration density, higher speed, and better performance. Furthermore, the power supply voltage for image sensor operation (e.g., operation during pixel voltage readout) is generally decreasing with each new manufacturing node. This trend of decreasing power supply voltage leads to a proportional reduction in the budget for voltage noise in the system. Therefore, systems and methods are needed to improve the handling of voltage noise in image sensors. Simple Explanation of the Diagram

[0005] Non-limiting and non-exhaustive embodiments of the invention are illustrated with reference to the following figures, wherein, unless otherwise specified, reference numerals refer to similar parts.

[0006] Figure 1 is an example image sensor according to one embodiment of the technology disclosed herein.

[0007] Figure 2 is a circuit diagram of a sample quad transistor (4T) pixel unit according to one embodiment of the disclosed technology.

[0008] Figure 3 is an instance timing diagram of one of the sample pixel units in Figure 2.

[0009] Figure 4 is a circuit diagram of a current generator based on a sample current mirror according to one embodiment of the technology disclosed herein.

[0010] Figure 5 is a circuit diagram of a switched capacitor current (I) digital-to-analog converter (DAC) according to one embodiment of the technology disclosed herein.

[0011] Figure 6 is an example timing diagram of one of the sample switched capacitor IDACs in Figure 5.

[0012] Figure 7 is a circuit diagram of a switched capacitor IDAC with multiple staggered clock inputs according to one embodiment of the disclosed technology.

[0013] Figure 8 is an example timing diagram of one of the sample switched capacitor IDACs in Figure 7.

[0014] Figure 9 is a circuit diagram of a switched capacitor IDAC according to one embodiment of the technology disclosed herein.

[0015] Figures 10A and 10B illustrate noise analysis of a switched capacitor IDAC according to one embodiment of the technology disclosed herein.

[0016] Figure 11 illustrates the switched capacitor noise analysis of a switched capacitor IDAC according to one embodiment of the disclosed technology.

[0017] Figures 12 and 13 illustrate different capacitor design implementation schemes of a switched capacitor IDAC according to one embodiment of the technology disclosed herein.

[0018] Figure 14 illustrates a voltage mismatch in a switched capacitor IDAC according to one embodiment of the technology disclosed herein.

[0019] Figures 15 and 16 respectively illustrate the sampling and holding stages of buffer registers A, B and C shown in Figure 9.

[0020] Figure 17 is a schematic diagram of one of the exemplary implementation schemes of Figures 15 and 16.

[0021] Figure 18 is a diagram of dual sampling for small and large pixels according to one embodiment of the technology disclosed herein.

[0022] Several views throughout the figures correspond to reference characters indicating the respective components. Those skilled in the art will understand that the elements in each figure are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to aid in understanding the various embodiments of the invention, the dimensions of some elements in each figure may be enlarged relative to others. Furthermore, common and well-known elements useful or necessary in a commercially viable embodiment are generally not shown to facilitate a less obstructed view of one of these various embodiments of the invention. Implementation

[0023] An image sensor with improved photodiode readout, resulting in a more accurate digital-to-analog (DAC) conversion of one of the pixel voltages of the image sensor, is disclosed. In the following description, numerous specific details are set forth to provide a thorough understanding of one embodiment. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring specific aspects.

[0024] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that example is included in at least one example of the invention. Therefore, the appearance of the phrase "in an example" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same example. Furthermore, such particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0025] For ease of explanation, spatially relative terms (such as "below," "under," "lower," "below," "above," "upper," and the like) are used herein to describe the relationship between one element or feature and another element(s), as illustrated in the figures. It should be understood that, in addition to the orientations shown in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. For example, if the device in the figures is rotated, an element described as "below," "below," or "below" other elements or features will be oriented "above" other elements or features. Therefore, the illustrative terms "below" and "below" can encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially relative descriptions used herein will be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0026] Several technical terms are used throughout this specification. These terms will be given their general meaning in the field of their respective domains, unless otherwise specifically defined herein or the context of their use will clearly imply otherwise. It should be noted that in this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, they have the same meaning.

[0027] In short, the examples of teachings in this disclosure pertain to sensing and recording voltage values ​​from a photodiode based on a correlated double sampling (CDS) technique. Generally, the accuracy of a CDS readout depends on the accuracy of Vx (pixel voltage) and the slope of Vy (ramp voltage). However, as the power supply voltage (AVDD) has been reduced in newer image sensor manufacturing nodes, circuit components also have a lower voltage budget for their operation. For example, reducing AVDD from 2.8 V to 2.2 V will correspondingly reduce the voltage budget of a cascaded current source (e.g., an operational amplifier integrator) from 0.7 V to 0.55 V, a voltage reduction of 27.27%. This smaller voltage budget presents a challenge to current source noise performance, requiring transistors with a larger width / length (W / L) and a larger transconductance (gm) if the current remains constant.

[0028] In some embodiments, switched-capacitor-based digital-to-analog converters (DACs) can be used for lower voltage budgets. These switched-capacitor current DACs (IDACs) can be multiplier DAC (MDAC) structures or 1-bit switched-capacitor DAC (SC-DAC) circuits to better handle reduced voltage margins while lowering the noise budget. For example, several switch groups can be configured in parallel and driven by a time offset control signal to provide a higher input current to the integrating capacitor of an operational amplifier-based integrator. This time offset can be selected to correspond to T / N, where T is the period of the input control signal and N is the number of switch groups configured in parallel.

[0029] In some embodiments, the switched capacitor IDAC includes additional buffer registers for better control of the voltage setpoint. These buffer registers can be selectively turned on and off during the sample-and-hold phase of the CDS cycle. In some embodiments, the capacitor of the switched capacitor IDAC is a metal-oxide-metal (MOM) interdigital capacitor with reduced parasitic capacitance.

[0030] Figure 1 illustrates an exemplary imaging system 100 according to one embodiment of the present disclosure. The imaging system 100 includes a pixel array 102, a control circuit system 104, a readout circuit system 106, and functional logic 110. In one example, the pixel array 102 is a two-dimensional (2D) array of photodiodes or image sensor pixels 112 (e.g., pixels P1, P2, ..., Pn). As illustrated, these photodiodes are configured in columns (e.g., columns R1 to Ry) and rows (e.g., rows C1 to Cx). In operation, the photodiodes acquire image data of a person, place, object, etc., which can then be used to reproduce a 2D image of the person, place, object, etc. However, the photodiodes need not be configured in columns and rows and other configurations can be used.

[0031] In embodiments, after each pixel 112 in pixel array 102 has acquired its image data or image charge, the image data is read out via bit line 118 by a readout circuitry system 106 and then transmitted to functional logic 110. In various embodiments, the readout circuitry system 106 may include a signal amplifier, an analog-to-digital converter (ADC) circuitry system, and a data transmission circuitry system. The functional logic 110 may store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others). In some embodiments, the control circuitry system 104 and the functional logic 110 may be combined into a single functional block to control the image capture by pixel 112 and the readout of image data from the readout circuitry system 106. The functional logic 110 may be a digital processor. In one embodiment, the readout circuitry 106 may read out a column of image data one at a time along the readout column line (as illustrated) or may use a variety of other techniques (not illustrated) to read out the image data, such as a series of column readouts or simultaneous full side-by-side readout of one of all pixels.

[0032] In one embodiment, control circuitry 104 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuitry 104 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal used to simultaneously activate all pixels within pixel array 102 to simultaneously capture their individual image data during a single acquisition window. In another embodiment, the shutter signal is a rolling shutter signal, such that pixels in each column, each row, or each group are sequentially activated during consecutive acquisition windows. In yet another embodiment, image acquisition is synchronized with illumination effects such as a flash.

[0033] In one embodiment, the data transmission circuitry 108 may receive image data from an analog-to-digital converter (ADC) and thus convert the analog image data into its digital representation. The digital representation of the image data is then provided to functional logic 110. In some embodiments, the data transmission circuitry 108 may receive the digital representation of the image data in parallel from the ADC and provide it serially to functional logic 110.

[0034] In one example, the imaging system 100 may be included in a digital camera, mobile phone, laptop computer, or the like. Additionally, the imaging system 100 may be coupled to other hardware, such as a processor (general purpose or otherwise), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), lighting devices / flash, electrical inputs (keyboard, touchscreen, tracking pad, mouse, microphone, etc.), and / or a display. The other hardware may send instructions to the imaging system 100, retrieve image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0035] Figure 2 is a circuit diagram of a sample four-transistor (4T) pixel unit according to one embodiment of the present disclosure. It should be understood that pixel unit 210 of Figure 2 may be an example of pixel unit 112 of Figure 1, and the similarly named and numbered elements referred to below may be similarly coupled and function. For example, pixel unit 210 may be coupled to a bit line 118 (e.g., a readout line) that provides image data to a readout circuitry system, such as readout circuitry system 106. Pixel unit 210 may receive signals from a control circuitry system (such as control circuitry system 104) to control the operation of various transistors of pixel unit 210. For example, the control circuitry system may use relative timing to control the operation of the transistors in a desired order so as to reset the pixel to a dark state and read out the image data after integration.

[0036] The illustrated example of pixel unit 210 includes a photosensitive or photoelectric conversion element, such as a photodiode (PD). In operation, the photodiode (PD) responds to incident light and generates an image charge.

[0037] Pixel unit 210 also includes a transfer gate TX and a floating diffuser FD. In operation, the transfer gate TX, in response to a transfer gate signal, transfers image charge from the photodiode PD to the floating diffuser FD. A reset transistor RST couples a power supply voltage PIXVD (also known as VDD) to the floating diffuser FD in response to a reset signal to reset pixel unit 210 (e.g., to discharge or charge the photodiode and floating diffuser to a preset voltage). The gate terminal of an amplifier transistor SF (also known as a source follower) is also coupled to the floating diffuser FD to generate an image data signal in response to the image charge in the floating diffuser FD. A column select transistor SEL (also known as RS) is coupled to the source follower SF to output the image data signal to an output bit line 118.

[0038] The image data signal is further routed to a comparator (e.g., an operational amplifier) ​​OA1, specifically to a capacitor C1. The voltage sensed by comparator OA1 at this input is Vx. Another input to comparator OA1 is a ramp voltage Vy. In operation, comparator OA1 first performs a self-reset (auto-zero or AZ) at the RST level of the pixel PD via a corresponding transmission gate, which is an auto-zero switch that toggles in response to an AZ signal. These switches reset the input and output of OA1 to the same voltage. Subsequently, an AD conversion is performed to digitize the pixel RST voltage. Then, the transmission gate TX is turned on, allowing electrons accumulated in the photodiode PD to be transferred outward to the floating diffuser FD node. Next, using a voltage ramp as further described below, another AD conversion is performed to digitize the pixel's signal voltage level. Finally, the digitized signal can be transmitted to the next stage of the readout circuit.

[0039] Figure 3 is an example timing diagram of one of the sample pixel units in Figure 2. Four signals are shown: Auto-Zero (AZ), Transfer (TX), Vy (ramp voltage), and Vx (pixel voltage). In operation, the comparator first resets itself at the pixel's RST level (Auto-Zero or AZ). In the illustrated embodiment, an AD conversion is performed to digitize the pixel's RST voltage (first "comparator flip" in the timing diagram). Then, the transfer gate TX is turned on, allowing electrons accumulated in the photodiode to be transferred outward to the floating diffuser (FD) node. As electrons accumulate at the FD node, Vx decreases to its stable value, and an AD conversion can begin by decreasing Vy until the two voltages intersect (second "comparator flip" in the timing diagram). These two AD conversions constitute a Correlated Double Sampling (CDS) technique. At this point, the pixel's signal voltage level is determined and can be further processed, for example, by readout circuitry 106 or functional logic 110.

[0040] Figure 4 is a circuit diagram of a current generator based on a sample current mirror according to one embodiment of the present disclosure. The illustrated current (I) digital-to-analog converter (DAC) structure (or simply IDAC) includes a current mirror 300 and an integrator 400 based on an operational amplifier 430. However, the supply voltage AVDD typically decreases from one generation of semiconductor manufacturing technology to another, resulting in, for example, a decrease in AVDD from 2.8 V to 2.2 V. Accordingly, the budget (ΔV) for the non-inverting voltage level V- at the operational amplifier 430 can change from AVDD - V- = 0.7 V to AVDD - V- = 0.55 V, which corresponds to a voltage budget reduction of approximately 27%. Those skilled in the art will understand that the above values ​​are provided only as examples, and other values ​​for the voltage budget reduction are also possible. Those familiar with this technology will also understand that reducing the voltage budget presents a challenge to the noise performance of current sources. This is because a smaller voltage budget requires transistors with a larger width-to-length (W / L) ratio and a larger transconductance (gm) to generate the same amount of current. Therefore, integrators that can operate with a lower voltage budget while also having reduced noise performance are needed.

[0041] Figure 5 is a circuit diagram of a switched capacitor IDAC according to one embodiment of the present disclosure. Specifically, the illustrated switched capacitor IDAC is a 1-bit switched capacitor (1-bit SCDAC) structure. The switched capacitor IDAC includes a switch group 410 and an operational amplifier-based integrator 401. The switch group 410 includes switches (e.g., transistors) 411 and 421 configured on a transmission line connected to the inverting input of the integrator 401, and switches 412 and 422 configured on a transmission line connected to the non-inverting input of the integrator 401. As a naming convention, switch 411 may be referred to as a first switch, switch 412 as a second switch, switch 421 as a third switch, and switch 422 as a fourth switch. A channel sample capacitor (Cs) 415 is configured between the inverting and non-inverting transmission lines. In operation, when switches 421 and 422 are closed, switches 411 and 412 are open, and vice versa. For example, the operation of switches 411 and 412 can be controlled by a control signal Φ, while the operation of switches 421 and 422 is controlled by a control signal Φ_bar, which has a timing sequence opposite to that of control signal Φ. In other words, the control signals Φ and Φ_bar are out of phase by π (180 degrees), therefore, control signals Φ and Φ_bar are sometimes referred to as opposite-phase signals. This opening and closing of the switches generates a current I that charges an integrator capacitor 435 (Ci), as further explained below with reference to Figure 6.

[0042] Figure 6 is an example timing diagram of one of the sample switched capacitor IDACs shown in Figure 5. During operation, capacitor Cs is charged when switches 411 and 412 are closed (on position) by control signal Φ being high and switches 421 and 422 are open (off position) by control signal Φ_bar being low. In the next half-cycle, switches 411 and 412 are open (off position) by control signal Φ being low (thus interrupting the current flowing to Cs), and switches 421 and 422 are closed (on position) by control signal Φ_bar being high (thus allowing current I to flow to Ci 435). Each closing of switches 421 and 422 generates a peak current I, followed by a relatively rapid decrease in current I. Due to the relatively finite total current I, the unity-gain bandwidth (UGB) of integrator 401 is also limited, and the timing of Φ must be relatively slow to maintain an acceptable charging level for Ci 435. Within the context of relevant double sampling (CDS) techniques, slow or insufficient charging of the Ci 435 may not be able to produce an appropriate sloping rate for the ramp voltage Vy.

[0043] Figure 7 is a circuit diagram of a switched capacitor IDAC with multiple staggered clock inputs according to one embodiment of the present disclosure. Compared with the circuit diagram of Figure 5, the illustrated circuit diagram includes a larger number (N) of switch groups 410 configured in parallel. When the switch groups 410 operate in parallel, each group can independently generate a current I, which is interleaved with other currents I generated by other switch groups, as illustrated below with reference to Figure 8.

[0044] Figure 8 is an example timing diagram of one of the sample switched capacitor IDACs of Figure 7. Here, the switch groups 410 operate in parallel. Furthermore, for each switch group 410, the control signals Φ and Φ_bar are time-shifted (staggered). For example, the time shift of the control signals Φ and Φ_bar can be ΔT = T / N, where T is one period of the control signal and N is the number of switch groups 410 operating in parallel. In some embodiments, N may correspond to 16, but other numbers of switch groups 410 operating in parallel are also possible. This timing shift of individual switch groups 410 results in a more "dense" distribution of the peak current I, thereby allowing the capacitor Ci to charge faster. Those skilled in the art will know that the charging of the capacitor Ci is proportional to the sum of the areas under the curves of the individual I contributions for each individual switch group 410.

[0045] Figure 9 is a circuit diagram of a switched capacitor IDAC according to one embodiment of the present disclosure. The illustrated circuit generally corresponds to the circuit shown in Figure 7; however, buffer registers A, B, and C are added to the circuit diagram in Figure 9. For simplicity, a single switch group 410 is illustrated, but those skilled in the art will understand that more switch groups 410 can be added in parallel configuration. For example, it may include 16 switch groups 410 or other numbers of switch groups.

[0046] In operation, buffer A (also referred to as the first buffer) and buffer B (also referred to as the second buffer) provide differential voltage references Vref1 and Vref2 to charge the channel sample capacitor (Cs) 415. These voltage ranges are shown for illustrative purposes only, and other voltage ranges are possible. As previously described, switches 411 and 412 open and close in the opposite phase to switches 421 and 422. Switches 411, 412, 421, and 422 are illustrated as PNP field-effect transistors (FETs); however, other types of transistors are possible in different embodiments. As explained above with respect to Figure 5, the opposite phase of the switch opening charges the integrator capacitor Ci. Furthermore, buffer C (also referred to as a third buffer) provides a voltage to a node A to ensure that the voltage at node A corresponds to the voltage at a node B, thus ensuring that the channel capacitor Cs is fully discharged and the charge carried by Cs is transferred to Ci. In some embodiments, buffer register C provides voltage to node A of switch group 410. The operation of integrator 401 can be controlled by an auto-zero (AZ) signal sent to transistor 448.

[0047] Figures 10A and 10B illustrate noise analysis of a switched capacitor IDAC according to one embodiment of the disclosed technology. Those skilled in the art will understand that the illustrated circuit is simplified to some extent, with an emphasis on noise analysis at the channel sample capacitor Cs and the integrator capacitor Ci; therefore, the switching operation between capacitors Cs and Ci is temporarily ignored.

[0048] Note Figure 10A and assume (for example) that the clock frequency of the control signal Φ (i.e., the frequency of opening and closing switches 411, 412) is 1 GHz, and also assume that there are N=16 interleaved switch groups 410, with a time offset of 1 / 16 GHz for each interleaved switch group (channel). In this scenario, the sample noise and the thermal noise (KT / C) are as follows. For the black level, if it is assumed that approximately 500 dn (DDR) are needed to reach the black level, then 500 / 2 sampling and holding operations are required, and the insertion thermal noise becomes 250*KT / C. dn can be understood as one count of reaching the black flip point. Taking Figure 3 as an example, dn can be understood as one count from the start of the ramp to the comparator flip point. Therefore, the IDAC correlated double sampling (CDS) output noise becomes:

[0049] Vout_rms_noise =

[0050] Furthermore, assuming Cs is approximately 600 fF and Ci is approximately 400 pF, Vout_rms_noise becomes approximately 2.78 μV after CDS. Since Ci is much larger than Cs (by several orders of magnitude), this attenuation reduces output noise without affecting the resolution or accuracy of the CDS output. Therefore, the same conclusion applies to ΔVref_noise_rms, so ΔVref_noise_rms needs to be << KT / C (approximately 164 μV) to make ΔVref_noise_rms relatively insignificant compared to thermal noise.

[0051] Figure 10B illustrates a sample noise analysis for one of the hold phases of a CDS cycle. Assuming the channel sample capacitor 415 has a capacitance of 8 × Cs, it can be shown that:

[0052] Vout_noise = (8*Cs / Ci)*Vref_noise

[0053] Using a 16-phase switch as an example, there are 8 capacitors charged by buffers A and B, and another 8 capacitors discharged by buffer C. Therefore, the equation "Vout_noise = (8*Cs / Ci)*Vref_noise" determines the output noise contribution from buffer C. For the aforementioned Cs value of approximately 600 fF and Ci value of approximately 400 pF, Vout_noise becomes 1 / 83.3 of Vref_noise. In other words, since Ci is significantly higher than Cs, the Vref buffer noise is also suppressed by 1 / 83. Those skilled in the art will understand that the above values ​​are provided for illustrative purposes only, and other values ​​can be applied to different embodiments, provided that the capacitance value of Ci remains significantly higher than the capacitance value of Cs (e.g., by an order of magnitude or more).

[0054] Figure 11 illustrates a switched capacitor noise analysis of a switched capacitor IDAC according to one embodiment of the present disclosure. The illustrated switched capacitor IDAC 401 is similar to the switched capacitors shown in Figures 7 and 9. However, in this embodiment, parasitic capacitance is considered and analyzed. Specifically, parasitic capacitance Cp1 is formed on the inverting input side of the channel sample capacitor 415, and parasitic capacitance Cp2 is formed on the non-inverting side of the channel sample capacitor 415. Those skilled in the art will understand that parasitic capacitance can be formed between different metallization layers in a semiconductor device. In the illustrated embodiment, parasitic capacitance Cp2 typically does not cause any charge error during the sampling and holding phases because Cp2 is not connected to any dummy ground point of integrator 401 (i.e., the inverting input of operational amplifier 430). However, parasitic capacitance Cp1 causes a charge error, which can be expressed as Cp1*(Vref1–V-). In some embodiments, the value of V- may be 1.6 V or 2.1 V, but other values ​​are also possible. For simplicity, a single switch group 410 is illustrated, but those skilled in the art will understand that more switch groups 410 can be added in parallel configuration. For example, it may include 16 switch groups 410 or other numbers of switch groups. Some methods for reducing the effect of parasitic capacitance Cp1 are described below with reference to Figures 12 and 13.

[0055] Figures 12 and 13 illustrate different capacitor design implementations of a switched capacitor IDAC according to one embodiment of the present disclosure. Figure 12 illustrates one layout of a channel sample capacitor 415. In some embodiments, the physical implementation of the channel sample capacitor 415 includes metallization layers (e.g., traces) 416 and 417. However, a relatively close proximity region of a ground plane (i.e., substrate) 418 results in additional capacitance, which is labeled as parasitic capacitances 413 (Cp1) and 423 (Cp2). Since the parasitic capacitance Cp1 causes a charge error Cp1*(Vref1 – V-), the effect of the parasitic capacitance Cp1 can be reduced by making the value of Vref1 as close as possible to the value of V- (the voltage at the inverting input terminal of the operational amplifier). As explained above, the parasitic capacitance Cp2 can be ignored in first-order analysis; however, the parasitic capacitance Cp1 causes a charge error, which remains a problem for CDS operation.

[0056] Figure 13 illustrates another embodiment of the layout of one of the channel sample capacitors 415. In the illustrated embodiment, the channel sample capacitor 415 is again physically implemented as a combination of one of a metallization layer (e.g., a trace) 416 and 417. Therefore, the presence of ground (i.e., substrate) 418 again results in additional parasitic capacitances Cp1 and Cp2. However, in the illustrated embodiment, a metal layer (also referred to as a "shield") 419 is connected to, for example, the metallization layer 417 of the channel sample capacitor 415 via an electrical connection 420 (e.g., a metal via). This electrical connection causes the parasitic capacitance Cp1 to have one 'plate' (e.g., metallization layer 416) electrically connected to the positive terminal of the channel sample capacitor 415 (Cs), and another 'plate' (e.g., metallization layer 419) electrically connected to the negative terminal 417 of the channel sample capacitor 415, thereby effectively connecting capacitors Cp1 and Cs into a single capacitor consisting of two capacitors in a parallel arrangement. Therefore, the parasitic capacitance Cp1 becomes part of the resulting overall Cs. In at least some embodiments, this altered capacitance affects the range of the CDS ramp but does not affect the fine gain of CDS operation.

[0057] Figure 14 illustrates a voltage mismatch in a switched capacitor IDAC according to one embodiment of the disclosed technology. For simplicity, a single switch group 410 is illustrated, but those skilled in the art will understand that more switch groups 410 can be added in parallel configuration. For example, 16 switch groups 410 or other numbers of switch groups may be included. As explained above with respect to Figure 11, in the absence of voltage noise, the values ​​of Vref, Vref-2*ΔVref, and V- should be the same. However, in real-world scenarios with voltage noise, these voltage values ​​are not the same. Therefore, the value of 2*ΔVref must be eliminated or at least adjusted to tune the slope of the switched capacitor IDAC, and also to adjust the coarse and fine gain of the CDS operation. An embodiment of this adjustment of the value of 2*ΔVref is illustrated below with respect to Figures 15 and 16.

[0058] Figures 15 and 16 illustrate the sampling and holding phases of buffer registers A, B, and C shown in Figure 9, respectively. During the sampling phase shown in Figure 15, a voltage source 446 generates a voltage Vos (V offset) based on the voltage mismatch and gain error of operational amplifier 430. This Vos voltage error is sampled and stored as voltage Vos by an offset capacitor 445. During the holding phase illustrated in Figure 16, the offset capacitor 445 applies a voltage Vos in the opposite direction to compensate for the voltage offset, thereby eliminating or at least reducing the voltage mismatch and offset.

[0059] Figure 17 is a schematic diagram of one of the exemplary embodiments of Figures 15 and 16. The schematic diagram is used for simulating the output voltage of a switched capacitor IDAC. In some embodiments, buffers A, B, and / or C may have voltage offsets, which are introduced by the operational amplifiers within these buffers due to differential pair mismatch and a drop in load output voltage. However, different offset compensation techniques can be used to counteract the offsets and make the voltages of buffers A, B, and / or C more accurate. The simulation diagram includes buffers A, B, and C as explained with reference to Figure 9.

[0060] Figure 18 is a diagram illustrating dual sampling for small and large pixels according to one embodiment of the disclosed technology. The horizontal axis represents time in μs, and the vertical axis represents voltage in volts. For the illustrated embodiment, the image sensor includes large pixels that typically improve the dynamic range of the image sensor and small pixels that typically improve the light sensitivity of the image sensor. Before the ramp-down region, the flat region indicates that buffers A, B, and C of Figure 15 are in phase, and then these buffers are in phase again, as shown in Figure 16. The buffers sample their individual offset errors during the "sampling" phase of Figure 15 to compensate for the offset during the "hold" phase of Figure 16. Therefore, before ramp-down, the circuit provides an accurate voltage after compensation, and during ramp-down, the circuit still provides an accurate ramp-down slope.

[0061] In the illustrated embodiment, CDS operation was simulated with AVDD at 2.2 V. The current estimate for integrator 401 is approximately 12 mA. The ramp rate is 1.78 mV / s, and the ramp rate is the same for both conversions (small pixel and large pixel). Simulation results indicate that CDS operation has relatively good accuracy, with a maximum gain error of 0.451% and an output CDS noise of 6.1 μV rms, which is considered relatively low in many embodiments.

[0062] The various embodiments of the disclosed technology described above may take the form of computer or controller executable instructions that are common to a programmable computer or controller and can be executed by a programmable computer or controller. Those skilled in the art will understand that this technology can be practiced on computer / controller systems other than those shown and described above. This technology can be embodied in special-purpose computers, application-specific integrated circuits (ASICs), controllers, or data processors that are specifically programmed, configured, or constructed to execute one or more of the computer executable instructions described above. Of course, any logic or algorithm described herein can be implemented in software or hardware, or a combination of both.

[0063] The above description of the invention, including the illustrative examples set forth in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. As used herein, the terms "approximately," "roughly," "generally," and similar terms may be modified by plus or minus 5% while still remaining within the scope of the disclosed embodiments. Although specific examples of the invention have been set forth herein for illustrative purposes, those skilled in the art will recognize that various modifications can be made within the scope of the invention. Such modifications can be made to the invention in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting the invention to the specific examples disclosed herein, but rather the scope of the invention is determined entirely by the appended claims, which will be interpreted in accordance with established principles of technical solution interpretation.

[0064] 100: Imaging System 102: Pixel Array 104: Control Circuit System 106: Readout Circuit System 110: Functional Logic 112: Image sensor pixels / pixel 118: Bit lines / Output bit lines 210: pixel unit 300: Current Mirror 400: Integrator 401: Integrator / Switched Capacitor Current Digital-to-Analog Converter 410: Switchgear / Interleaved Switchgear 411: Switch / Tronometer 412: Switch 413: Parasitic capacitance 415: Channel Sample Capacitor 416: Metallization layer / trace 417: Metallization layer / trace / negative terminal 418: Grounding plane / substrate / grounding 419: Metallic layer / shielding material / metallization layer 420: Electrical connectors 421: Switch / Tronograph 422: Switch 423: Parasitic capacitance 430: Operational Amplifier 435: Integrator Capacitor 445: Offset capacitor 446: Voltage source 448: Transistor A: Node AVDD: Power Supply Voltage / Supply Voltage AZ: Automatic Zeroing B: Node C1: Capacitor C1-Cx: rows Ci: Integrator capacitor / Capacitor Cp1: Parasitic capacitance / Capacitance Cp2: Parasitic capacitance Cs: Channel sample capacitor / Capacitor / Channel capacitor / Capacitor FD: Floating Diffusion Section I: Switched capacitor current / current / peak current / total current N: Quantity OA1: Comparator / Operational Amplifier P1-Pn: pixels PD: Photodiode / Pixel PIXVD: Power Supply Voltage R1-Ry: Columns RST: Reset transistor SEL: Column Select Transistor SF: Amplifier Transistor / Source Follower T: Time period TX: Gateway V-: Non-inverting voltage level Vos: Voltage Vref1: Differential voltage reference Vref2: Differential voltage reference Vx: Pixel voltage / Voltage Vy: Slope voltage ΔV: Budget Φ: Control signal Φ_bar: Control signal

Claims

1. An image sensor comprising: A plurality of pixels, which are configured into a pixel array of columns and rows; A single-bit line, which is electrically coupled to a pixel; And a switched capacitor current digital-to-analog converter (IDAC) coupled to the bit line, the current digital-to-analog converter comprising: a plurality of switch groups, each switch group configured to receive a control signal for controlling the opening and closing of switches in the switch group, wherein the control signals are time-shifted; and an integrator coupled to the plurality of switch groups, wherein the integrator is configured to generate an output signal based on input signals received from the plurality of switch groups, wherein a time shift between the control signals of two switch groups in the plurality of switch groups satisfies: ΔT=T / N, where T is a period of the control signal and N is a number of switch groups in the plurality of switch groups.

2. The image sensor as requested in item 1, wherein each switch group is configured to generate a peak current offset by ΔT from the next peak current.

3. The image sensor of claim 1, wherein each switch group includes a first switch, a second switch, a third switch and a fourth switch, wherein the first switch and the second switch are controlled by a first control signal, wherein the third switch and the fourth switch are controlled by a second control signal, and wherein a first phase of the first control signal and a second phase of the second control signal differ by π.

4. The image sensor as described in claim 3, wherein each switch group includes a channel sample capacitor.

5. The image sensor as described in claim 4, wherein the integrator includes: An operational amplifier; And an integrator capacitor.

6. The image sensor of claim 5, wherein each switch group includes a first buffer register coupled to the first switch, a second buffer register coupled to the second switch, and a third buffer register coupled between an inverting input and a non-inverting input of the operational amplifier, wherein each first buffer register is configured to provide a first differential voltage reference Vref1 to the first switch, each second buffer register is configured to provide a second differential voltage reference Vref2 to the second switch, and wherein the voltage references Vref1 and Vref2 are configured to charge the sample capacitor of the channel.

7. The image sensor as claimed in claim 5, wherein one of the integrator capacitors has a capacitance that is an order of magnitude larger than one of the channel sample capacitors.

8. The image sensor as claimed in claim 4, wherein the channel sample capacitor is a metal-oxide-metal (MOM) interdigitated capacitor.

9. The image sensor as claimed in claim 8, wherein the channel sample capacitor includes: A first electrode and a second electrode, which are interdigitated in a first metal layer; and an electrical connector located between the first electrode and the second metal layer of the channel sample capacitor.

10. A method for performing a correlated double sampling (CDS) readout of an image sensor having a pixel array of one of a plurality of pixels, the method comprising: Expose one pixel to light; The pixel is coupled to a bit line via a selected transistor (SEL); A ramp voltage is generated by a switched capacitor current digital-to-analog converter (IDAC) coupled to one of the bit lines, wherein generating the ramp voltage includes: controlling the opening and closing of a plurality of switch groups by a control signal, wherein each switch group is configured to receive a control signal, and wherein the control signals are time-shifted; receiving a plurality of current inputs generated by the plurality of switch groups by an integrator; generating an output signal by the integrator; and determining that at least one comparator is flipped by finding an intersection point between the ramp voltage and a pixel voltage from the pixel, wherein a time shift between the control signals of two switch groups in the plurality of switch groups satisfies: ΔT=T / N, where T is a period of the control signal and N is a number of switch groups in the plurality of switch groups.

11. The method of claim 10, further comprising generating a peak current offset by ΔT from the next peak current by each switch group.

12. The method of claim 10, wherein each switch group includes a first switch, a second switch, a third switch and a fourth switch, the method further comprising: The first switch and the second switch are controlled by a first control signal; and the third switch and the fourth switch are controlled by a second control signal, wherein a first phase of the first control signal and a second phase of the second control signal differ by π.

13. The method of claim 12, wherein each switch group includes a channel sample capacitor.

14. The method of claim 13, wherein each switch group includes a first buffer register coupled to the first switch and a second buffer register coupled to the second switch, the method further comprising: A first differential voltage reference Vref1 is provided to the first switch of each switch group; A second differential voltage reference Vref2 is provided to the second switch of each switch group; and the sample capacitor of the channel is charged by the voltage references Vref1 and Vref2.

15. The method of claim 13, wherein the integrator comprises: An operational amplifier; And an integrator capacitor.

16. The method of claim 15, wherein each switch group includes a third buffer register coupled between an inverting input and a non-inverting input of an operational amplifier of the integrator.

17. The method of claim 15, wherein one of the capacitances of the integrator capacitor is an order of magnitude larger than one of the capacitances of the channel sample capacitor.

18. The method of claim 13, wherein the channel sample capacitor is a metal-oxide-metal (MOM) interdigitated capacitor.

19. The method of claim 18, wherein the channel sample capacitor includes a first electrode and a second electrode in a cross-finger configuration in a first metal layer, and an electrical connector located between the first electrode and the second metal layer of the channel sample capacitor.

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