Artificial intelligence chip and pooling method thereof

Abstract

This invention provides an artificial intelligence chip and its pooling method. The artificial intelligence chip includes an instruction scheduling module, an instruction decoding module, a register group, a pooling control circuit, and a floating-point arithmetic unit. The instruction decoding module decodes the pooling instruction from the instruction scheduling module to produce a decoding result. Based on the decoding result, the pooling control circuit determines the number of execution cycles for the pooling instruction and reads feature map values ​​from the register group. The pooling control circuit provides multiple feature points of the receptive field of the execution cycle number and feature map values ​​to the floating-point arithmetic unit. The floating-point arithmetic unit performs a pooling operation on these feature points of the receptive field based on the number of execution cycles to produce a pooling result for the receptive field.

Description

[Technical Field]

[0001] This invention relates to the field of integrated circuit technology, and more particularly to an artificial intelligence chip and its pooling method. [Previous Technology]

[0002] Artificial intelligence (AI) chips can provide enormous computing power. This immense computing power stems from the large number of internal hardware cores. An AI chip typically contains multiple programmable processors, such as a stream processor cluster (SPC). Each programmable processor typically contains multiple compute units (CUs), and each compute unit typically contains multiple execution units (EUs), such as at least one of integer (INT) cores, floating-point (FP) cores, tensor cores (Tcores), and vector cores (Vcores). By organizing these various types of compute units through programming, AI chips can support general-purpose computing, scientific computing, and neural network computing.

[0003] Neural network computation involves operations such as convolution, activation, and pooling. Pooling is very common in convolutional neural networks. Pooling is a non-linear downsampling operation. Originating in computer vision, pooling refers to the merging and integration of resources, mimicking the human visual system's dimensionality reduction of data. The pooling operation moves the pooling window to different positions in the data matrix (e.g., tensors, feature maps) according to a stride, creating different receptive fields. After each movement of the pooling window, pooling calculations (e.g., taking the maximum value or averaging) are performed on multiple data elements (e.g., feature points) within the receptive field to obtain a single data element in the pooled matrix. After the pooling window has completely scanned the entire data matrix according to the stride, the execution unit can store the pooled matrix in memory. Pooling reduces the dimensionality of the data matrix, thereby reducing the number of parameters and computational cost of neural network computation. Pooling operations can control overfitting to some extent.

[0004] Common pooling operations include max pooling, average pooling, or other pooling algorithms. Suppose the receptive field size is K*K, and the data elements in the receptive field are P_1, P_2, P_3, ..., P_k*k. The result of average pooling is (P_1+P_2+P_3+...+P_k*k) / (K*K). It is generally believed that average pooling better preserves the background information of the feature map. The result of max pooling is MAX(P_1, P_2, P_3, ..., P_k*k), which is the maximum value among the K*K feature points. It is generally believed that max pooling better preserves the texture information of the feature map.

[0005] Conventional techniques utilize the regular floating-point hardware of the Central Processing Unit (CPU) or Graphics Processing Unit (GPU) to perform pooling operations. The drawback of this method is that it requires multiple general-purpose floating-point instructions to fulfill application requirements. If the receptive field is 3*3 (assuming the data elements in the receptive field are P1, P2, P3, P4, P5, P6, P7, P8, and P9), then mean pooling requires a total of 9 regular floating-point operations: "tmp1=P1+P2", "tmp2=P3+tmp1", "tmp3=P4+tmp2", "tmp4=P5+tmp3", "tmp5=P6+tmp4", "tmp6=P7+tmp5", "tmp7=P8+tmp6", "tmp8=P9+tmp7", and "result=(1 / 9)*tem8". Max pooling requires "tmp1=MAX(P1, P2)", "tmp2=MAX(P3, tmp1)", "tmp3=MAX(P4, tmp2)", "tmp4=MAX(P5, P9)", and "result=(1 / 9)*tem8". The code contains a total of 8 instructions: "tmp3)," "tmp5=MAX(P6, tmp4)," "tmp6=MAX(P7, tmp5)," "tmp7=MAX(P8, tmp6)," and "result=MAX(P9, tmp7)". It's clear that the conventional technique suffers from a long computation time due to the large number of instructions. How to perform pooling operations is one of the many technical issues in this field. [Summary of the Invention]

[0006] This invention relates to an artificial intelligence (AI) chip and its pooling method, which performs pooling operations on multiple feature points of a feature map value.

[0007] In an embodiment of the present invention, the artificial intelligence chip includes an instruction scheduling module, an instruction decoding module, a register file, a pooling control circuit, and a first floating-point operation unit. The instruction decoding module is coupled to the instruction scheduling module to receive pooling instructions. The instruction decoding module decodes the pooling instructions to generate a decoding result. The pooling control circuit is coupled to the instruction decoding module and the register file. The first floating-point operation unit is coupled to the pooling control circuit. The pooling control circuit determines the number of execution cycles for the pooling instruction based on the decoding result and provides the number of execution cycles to the first floating-point operation unit. The pooling control circuit reads feature map values ​​from the register file based on the decoding result and provides multiple feature points of the first receptive field of the feature map values ​​to the first floating-point operation unit. The first floating-point operation unit performs a pooling operation on these feature points of the first receptive field based on the number of execution cycles to generate a pooling result for the first receptive field.

[0008] In an embodiment of the present invention, the pooling method includes: decoding a pooling instruction by an instruction decoding module of an artificial intelligence chip to generate a decoding result; determining the number of execution cycles of the pooling instruction based on the decoding result by a pooling control circuit of the artificial intelligence chip; providing the number of execution cycles to a first floating-point unit by the pooling control circuit; reading feature map values ​​from a register group by the pooling control circuit based on the decoding result; providing a plurality of feature points of a first receptive field of the feature map values ​​to the first floating-point unit by the pooling control circuit; and performing a pooling operation on these feature points of the first receptive field by the first floating-point unit based on the number of execution cycles to generate a pooling result of the first receptive field.

[0009] Based on the above, the pooling control circuit in the embodiments of the present invention determines the number of execution cycles of the pooling instruction and reads the feature map values ​​based on the decoding result of the pooling instruction, while the pooling control circuit determines the first receptive field by moving the pooling window based on the stride. The pooling control circuit provides multiple feature points of the first receptive field of the feature map values ​​to the first floating-point arithmetic unit, and the first floating-point arithmetic unit performs pooling operations (e.g., mean pooling or maximum pooling) on ​​the feature points of the first receptive field based on the number of execution cycles. In some embodiments, the artificial intelligence chip is arranged with multiple floating-point arithmetic units, and the pooling control circuit determines different receptive fields by moving the pooling window based on the stride. The pooling control circuit provides the feature points of each of the multiple receptive fields to the corresponding floating-point arithmetic unit, so different floating-point arithmetic units can simultaneously perform pooling operations on the feature points of different receptive fields. In some embodiments, a small amount of control and calculation logic is added to the standard floating-point arithmetic unit to implement a dedicated hardware resource for pooling operations (including mean pooling and maximum pooling), thereby accelerating the pooling process.

[0010] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0012] The term "coupled (or connected)" as used throughout the entire specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout the entire specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions. It should be understood that the features of the following embodiments can be combined with each other. For example, the features of the second embodiment can be combined with the features of the first embodiment. Those with general knowledge in the relevant technical field can select appropriate combinations of features based on actual design requirements.

[0013] Furthermore, it should be noted that the parameter type of the artificial intelligence (AI) chip and its pooling method provided in at least one embodiment of this case is floating-point number. The specific physical meaning of the parameter type may differ depending on the application scenario. For example, the AI ​​chip and its pooling method provided in at least one embodiment of this case can be applied in fields such as speech processing, image processing, text processing, and video processing.

[0014] For example, in the field of speech processing, parameters can be any parameters used, input, or generated in tasks such as feature extraction, speech enhancement, and speech recognition, such as speech feature vectors and filtering parameters.

[0015] For example, in the field of image processing, parameters can be any parameters used, input, or generated in tasks such as image preprocessing, feature extraction, image segmentation, and target detection, such as image feature vectors, various edge detection operators (such as Sobel operators, Canny operators, Prewitt operators, etc.), image filtering operators (such as Gaussian filtering, median filtering, bilateral filtering, etc.), morphological operators (such as erosion, dilation, opening operations, closing operations, etc.), etc.

[0016] For example, in the field of text processing, parameters can be any parameters used, input, or generated in tasks such as text classification, sentiment analysis, and text generation, such as the semantic feature vector of the text.

[0017] For example, in the field of video processing, the parameters can be parameters in the field of image processing as described above, or parameters that are specific to the field of video processing, such as optical flow operators (used to estimate motion between video frames) or target tracking operators (used to track specific targets in the video), which are used, input, or generated.

[0018] Of course, this case is not limited to this. For other application scenarios or fields, as long as pooling is required, the pooling method described in at least one embodiment of this case can be applied. Here, they will not be described in detail.

[0019] Figure 1 is a schematic circuit block diagram of an artificial intelligence (AI) chip 100 according to an embodiment of the present invention. In different application examples, the AI ​​chip 100 can be used as a graphics processing unit (GPU), a general-purpose computing on GPU (GPGPU), or other processing circuits. The AI ​​chip 100 can provide huge computing power. The huge computing power of the AI ​​chip 100 comes from a large number of internal hardware cores.

[0020] In the embodiment shown in FIG1, the AI ​​chip 100 includes an instruction scheduling module 110, an instruction decoding module 120, a pooling control circuit 130, a register file 140, and multiple first floating-point operation units, such as floating-point operation units 150_1, 150_2, ..., 150_N shown in FIG1. ​​The number N of floating-point operation units 150_1 to 150_N can be any integer determined based on actual design and application. Floating-point operation units 150_1 to 150_N are coupled to the pooling control circuit 130 and the register file 140. The pooling control circuit 130 is coupled to the instruction decoding module 120 and the register file 140. The instruction decoding module 120 is coupled to the instruction scheduling module 110 to receive pooling instructions. In this embodiment, the pooling instructions include two instructions: POOL.MEAN and POOL.MAX. The POOL.MEAN instruction is used to perform mean pooling, while the POOL.MAX instruction is used to perform maximum pooling.

[0021] Figure 2 is a flowchart illustrating a pooling method for an artificial intelligence (AI) chip according to an embodiment of the present invention. Referring to Figures 1 and 2, in step S210, the instruction decoding module 120 decodes the pooling instruction from the instruction scheduling module 110 to generate a decoding result. The pooling instruction supports different parameter configurations, including pooling type, receptive field size, padding bit width, stride, neural network operation direction (forward or backward), and various data formats (including fp16, fp8, int8, int4), which can adapt to the application requirements of different convolutional neural networks (CNNs). In step S220, the pooling control circuit 130 determines the number of execution cycles of the pooling instruction, the pooling type (enabling mean or maximum value calculation resources), and other related parameters based on the decoding result of the pooling instruction, and reads feature map values ​​(generally a data matrix) from the temporary register group 140.

[0022] Assuming the size of the receptive field is K*K, and any of the floating-point arithmetic units 150_1 to 150_N receives or processes L feature points in each loop of the iterative operation, then the number of execution cycles is (K*K) / L. For example, assuming the size of the receptive field is 3*3 feature points, and any of the floating-point arithmetic units 150_1 to 150_N receives or processes 3 feature points in each loop of the iterative operation, then the number of execution cycles is (3*3) / 3=3, that is, one iterative operation is performed 3 times.

[0023] In step S230, the pooling control circuit 130 provides relevant parameters such as the number of execution cycles and the pooling type (enabling average or maximum value calculation resources) to the floating-point units 150_1 to 150_N. Furthermore, the pooling control circuit 130 moves the pooling window based on the step size parameter of the pooling instruction to determine different receptive fields in the feature map. In step S230, the pooling control circuit 130 also provides each of the floating-point units 150_1 to 150_N with multiple feature points corresponding to the receptive field of the feature map value. For example, the pooling control circuit 130 provides multiple feature points of the first receptive field of the feature map value to the floating-point unit 150_1, and provides multiple feature points of the second receptive field of the feature map value to the floating-point unit 150_2.

[0024] In step S240, floating-point units 150_1 to 150_N perform pooling operations on feature points of different receptive fields based on the number of execution cycles to generate pooling results for different receptive fields. For example, floating-point unit 150_1 performs pooling operations on multiple feature points of the first receptive field based on the number of execution cycles to generate a pooling result for the first receptive field. Similarly, floating-point unit 150_2 performs pooling operations on multiple feature points of the second receptive field based on the number of execution cycles to generate a pooling result for the second receptive field.

[0025] In summary, the pooling control circuit 130 determines the number of execution cycles for the pooling instruction and reads the feature map values ​​based on the decoding result of the pooling instruction. The pooling control circuit 130 moves the pooling window based on the step size parameter to determine the first receptive field. The pooling control circuit 130 provides multiple feature points from one receptive field of the feature map values ​​to the floating-point unit 150_1, which performs pooling operations (e.g., mean pooling or max pooling) on ​​the feature points of this receptive field based on the number of execution cycles to produce a pooling result. Similarly, the pooling control circuit 130 provides multiple feature points from another receptive field of the feature map values ​​to the floating-point unit 150_2, which performs pooling operations on the multiple feature points of this other receptive field based on the number of execution cycles to produce a pooling result. The pooling control circuit 130 provides feature points of multiple receptive fields to floating-point arithmetic units 150_1 to 150_N. Therefore, different floating-point arithmetic units 150_1 to 150_N can simultaneously perform pooling operations on feature points of different receptive fields, thereby accelerating the pooling process.

[0026] Figure 3 is a circuit block diagram of the pooling control circuit 130 according to an embodiment of the present invention. The instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, temporary register group 140, and floating-point arithmetic units 150_1 to 150_N shown in Figure 3 can be referred to the relevant description in Figure 1, and therefore will not be repeated here. The pooling control circuit 130 shown in Figure 3 can be one of many implementation examples of the pooling control circuit 130 shown in Figure 1. In the embodiment shown in Figure 3, the pooling control circuit 130 includes a pooling operation control module 131, an arithmetic element acquisition module 132, and a feature map input control module 133. Depending on the design, in some embodiments, at least one of the instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, operand acquisition module 132, and feature map input control module 133 may be implemented as hardware circuit, firmware, software (i.e., program), or a combination of the foregoing.

[0027] In terms of hardware, at least one of the above-mentioned instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, operand acquisition module 132 and feature map input control module 133 can be implemented as a logic circuit on an integrated circuit. For example, the related functions of at least one of the instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, arithmetic element acquisition module 132, and feature map input control module 133 can be implemented in various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. The related functions of at least one of the instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, operand acquisition module 132, and feature map input control module 133 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in integrated circuits, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0028] In software or firmware form, the functions of at least one of the instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, operand acquisition module 132, and feature map input control module 133 can be implemented as programming codes. For example, at least one of the instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, operand acquisition module 132, and feature map input control module 133 can be implemented using general programming languages ​​(such as C, C++, or assembly languages) or other suitable programming languages. The programming code can be recorded or stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. Electronic devices (such as computers, CPUs, hardware controllers, microcontrollers, hardware processors, or microprocessors) can read and execute the programming code from the non-transitory machine-readable storage medium to realize the related functions of at least one of the instruction scheduling module 110, instruction decoding module 120, pooling control circuit 130, pooling operation control module 131, operand acquisition module 132, and feature map input control module 133.

[0029] The pooling operation control module 131 is coupled to the instruction decoding module 120 to receive the decoding result. Pooling instructions are sent to the pooling operation control module 131 via the instruction scheduling unit 110 and the instruction decoding unit 120 for further decoding of the pooling parameters. Based on the decoding result of the pooling instructions, the pooling operation control module 131 determines the number of execution cycles for the pooling instructions and then provides the number of execution cycles to the floating-point units 150_1 to 150_N. The pooling operation control module 131 also directly broadcasts pooling computational resource control information to all floating-point units 150_1 to 150_N. For example, the pooling operation control module 131 determines the number of execution cycles for the current instruction based on parameters such as the receptive field size and stride in the instruction, and repeatedly emits this instruction until the current channel-wise convolution is completed.

[0030] The arithmetic unit acquisition module 132 is coupled to the pooling operation control module 131 and the register group 140. The arithmetic unit acquisition module 132 reads feature map values ​​from the register group 140 based on the control of the pooling operation control module 131. For example, the pooling operation control module 131 calculates the address of the feature map according to parameters and then sends the address to the arithmetic unit acquisition module 132 so that the arithmetic unit acquisition module 132 reads feature map values ​​from the register group 140. The feature map input control module 133 is coupled to the arithmetic unit acquisition module 132 to receive feature map values. The feature map input control module 133 provides feature points of different receptive fields of the feature map values ​​to the floating-point arithmetic units 150_1 to 150_N. For example, the feature map input control module 133 provides multiple feature points of the first receptive field of the feature map values ​​to the floating-point arithmetic unit 150_1. Similarly, the feature map input control module 133 provides multiple feature points of the second receptive field of the feature map value to the floating-point arithmetic unit 150_2.

[0031] After receiving the relevant feature map, the feature map input control module 133 selects the corresponding feature points for each floating-point arithmetic unit 150_1 to 150_N according to the current loop count. For example, assuming the receptive field size is 3*3 feature points, the data elements (feature points) in a certain receptive field of the feature map value are P1, P2, P3, P4, P5, P6, P7, P8, and P9, and the floating-point arithmetic unit 150_1 receives or processes 3 feature points in each loop of the iterative operation. In the first loop of the iterative operation, the feature map input control module 133 provides feature points P1, P2, and P3 to the floating-point arithmetic unit 150_1. In the second loop of the iterative operation, the feature map input control module 133 provides feature points P4, P5, and P6 to the floating-point arithmetic unit 150_1. In the third loop of the repetitive operation, the feature map input control module 133 provides feature points P7, P8, and P9 to the floating-point arithmetic unit 150_1. The operations of the feature map input control module 133 on the other floating-point arithmetic units 150_2 to 150_N can be deduced by referring to the operation description of the feature map input control module 133 on the floating-point arithmetic unit 150_1, and therefore will not be elaborated further. The floating-point arithmetic units 150_1 to 150_N can receive three feature points from the feature map input control module 133 in each loop cycle and perform pooling operations. After three loop cycles, the floating-point arithmetic units 150_1 to 150_N can complete the pooling operations for different receptive fields and output the pooling results for different receptive fields to the temporary register group 140.

[0032] In some embodiments, a small amount of control and computation logic can be added to the standard floating-point unit to implement floating-point units 150_1 to 150_N as dedicated hardware for pooling operations (including mean pooling and max pooling), thereby accelerating the pooling process. The pooling control circuit 130 supports different parameter configurations, including pooling type, receptive field size, zero-padding width, stride, neural network operation direction (forward or backward), and various data formats (including fp16, fp8, int8, int4). The pooling control circuit 130 is highly flexible and adaptable to the application requirements of different convolutional neural networks (CNNs).

[0033] FIG4 is a circuit block diagram of a floating-point arithmetic unit 400 according to an embodiment of the present invention. The floating-point arithmetic unit 400 shown in FIG4 can be described by analogy with any of the floating-point arithmetic units 150_1 to 150_N shown in FIG1 or FIG3. The floating-point arithmetic unit 400 shown in FIG4 can be one of many implementation examples of any of the floating-point arithmetic units 150_1 to 150_N shown in FIG1 or FIG3. In the embodiment shown in FIG4, the floating-point arithmetic unit 400 includes a carry-save adder (CSA) 410, an adder 420, a multiplexer 430, a multiplexer 440, an adder 450, a floating-point normalization circuit 460, a loop intermediate result memory access circuit 470, a multiplier 480, and a multiplexer 490. In this embodiment, adder 450, floating-point normalization circuit 460, multiplier 480, and multiplexer 490 can be components of a standard floating-point arithmetic unit, while carry-saving adder 410, adder 420, multiplexer 430, multiplexer 440, and loop intermediate result memory access circuit 470 are added to the standard floating-point arithmetic unit to serve as hardware specifically for mean pooling operations.

[0034] Instruction decoding module 120 decodes the pooling instruction POOL.MEAN from instruction scheduling module 110 to produce a decoding result. Pooling control circuit 130, based on the decoding result of pooling instruction POOL.MEAN, determines the number of execution cycles for the pooling instruction and reads feature points from the feature map values ​​from register group 140 to carry-saving adder 410. Carry-saving adder 410 is coupled to pooling control circuit 130 to receive multiple feature points corresponding to the receptive field, such as feature points IN41, IN42, and IN43. Carry-saving adder 410 generates a sum tmp41 and a carry tmp42 based on these feature points, i.e., IN41 + IN42 + IN43 = tmp41 + tmp42. Adder 420 is coupled to carry-saving adder 410 to receive the sum tmp41 and the carry tmp42. Adder 420 generates a sum tmp43 based on the sum tmp41 and the carry tmp42, i.e., tmp41 + tmp42 = tmp43. The first input of multiplexer 430 is coupled to adder 420 to receive the sum tmp43. The output of multiplexer 430 is coupled to the first input of adder 450. The first input of multiplexer 440 is coupled to the output of loop intermediate result memory access circuit 470. Loop intermediate result memory access circuit 470 provides the sum tmp44 from the previous execution cycle in multiple loops (execution cycles) of the average pooling operation. In the first loop of the average pooling operation performed by floating-point unit 400, the sum tmp44 is zero. The output of multiplexer 440 is coupled to the second input of adder 450.

[0035] When the floating-point unit 400 is used as hardware specifically for average pooling operations, the multiplexer 430 transmits the sum tmp43 to the first input of the adder 450, while the multiplexer 440 transmits the sum tmp44 from the previous execution cycle to the second input of the adder 450. When the floating-point unit 400 is used as a standard floating-point unit, and floating-point addition "a + b" is performed on this standard floating-point unit, the second input of the multiplexer 430 receives the floating-point number a, while the second input of the multiplexer 440 receives the floating-point number b. At this time, the multiplexer 430 transmits the floating-point number a to the first input of the adder 450, while the multiplexer 440 transmits the floating-point number b to the second input of the adder 450.

[0036] The input of the floating-point normalization circuit 460 is coupled to the output of the adder 450 to receive the sum tmp45. The output of the floating-point normalization circuit 460 is coupled to the input of the loop intermediate result access circuit 470 and the first input of the multiplexer 490. The floating-point normalization circuit 460 normalizes the sum tmp45 based on the floating-point standard format to generate a normalized sum tmp45' for the loop intermediate result access circuit 470 and the multiplexer 490.

[0037] Instruction decoding module 120 decodes the floating-point multiplication instruction FMUL from instruction scheduling module 110 regarding the mean pooling operation to produce a decoding result. Pooling control circuit 130, based on the decoding result of floating-point multiplication instruction FMUL, reads the feature point summation value SUM41 from register group 140 and assigns it to multiplier 480. The first input of multiplier 480 receives the feature point summation value SUM41 from pooling control circuit 130 regarding the receptive field corresponding to floating-point arithmetic unit 400. The second input of multiplier 480 receives the average coefficient AC41 from pooling control circuit 130 regarding the corresponding receptive field. The second input of multiplexer 490 is coupled to the output of multiplier 480.

[0038] For example, assuming the size of the corresponding receptive field is 3*3 feature points, and assuming the data elements in the corresponding receptive field are P1, P2, P3, P4, P5, P6, P7, P8, and P9, then the mean pooling operation of this corresponding receptive field includes summation iteration and multiplication. The summation iteration includes 3 summation loops, and the average coefficient AC41 of the corresponding receptive field is 1 / (3*3) = 1 / 9. In the first summation loop, feature points IN41, IN42, and IN43 are P1, P2, and P3, respectively. The loop intermediate result memory access circuit 470 provides the sum value tmp44, which is zero, to the multiplexer 440, while the floating-point normalization circuit 460 writes the sum value tmp45' (i.e., P1 + P2 + P3) of the first summation loop into the loop intermediate result memory access circuit 470. In the second summation loop, the feature points IN41, IN42, and IN43 are P4, P5, and P6, respectively. The loop intermediate result memory access circuit 470 provides the sum value tmp44 (i.e., P1 + P2 + P3) of the first summation loop to the multiplexer 440, while the floating-point normalization circuit 460 writes the sum value tmp45' (i.e., P4 + P5 + P6 + tmp44 = P1 + P2 + P3 + P4 + P5 + P6) of the second summation loop into the loop intermediate result memory access circuit 470. In the third summation loop, feature points IN41, IN42, and IN43 are P7, P8, and P9, respectively. The intermediate result memory access circuit 470 provides the sum value tmp44 (i.e., P1 + P2 + P3 + P4 + P5 + P6) from the second summation loop to the multiplexer 440, while the floating-point normalization circuit 460 writes the sum value tmp45' (i.e., SUM41 = P7 + P8 + P9 + tmp44 = P1 + P2 + P3 + P4 + P5 + P6 + P7 + P8 + P9) from the third summation loop into the register group 140 via the multiplexer 490. In the multiplication of the mean pooling operation, the first input of the multiplier 480 receives the feature point summation value SUM41 (i.e., P1 + P2 + P3 + P4 + P5 + P6 + P7 + P8 + P9) from the pooling control circuit 130. The second input of multiplier 480 receives the average coefficient AC41 (e.g., 1 / 9) from pooling control circuit 130. Multiplier 480 writes the mean pooling result (i.e., (P1 + P2 + P3 + P4 + P5 + P6 + P7 + P8 + P9) / 9) to register group 140 via multiplexer 490.

[0039] In summary, conventional techniques require 9 instructions and 9 computation speeds to perform mean pooling operations with a 3x3 receptive field, while the above embodiment only requires 2 instructions, POOL.MEAN and FMUL, to complete the mean pooling operation, consuming a total of 4 computation speeds. That is, the above embodiment can complete the mean pooling operation with fewer instructions and at a faster speed.

[0040] FIG5 is a circuit block diagram of a floating-point arithmetic unit 500 according to another embodiment of the present invention. The floating-point arithmetic unit 500 shown in FIG5 can be described with reference to any of the floating-point arithmetic units 150_1 to 150_N shown in FIG1 or FIG3 and by analogy. The floating-point arithmetic unit 500 shown in FIG5 can be one of many embodiments of any of the floating-point arithmetic units 150_1 to 150_N shown in FIG1 or FIG3. In the embodiment shown in FIG5, the floating-point arithmetic unit 500 includes comparator 510, comparator 520, multiplexer 530, multiplexer 540, comparator 550, and a loop intermediate result memory access circuit 560. In this embodiment, comparator 550 can be a component of a standard floating-point unit, while comparator 510, comparator 520, multiplexer 530, multiplexer 540 and loop intermediate result memory access circuit 560 are added to the standard floating-point unit to implement hardware specifically for maximum pooling operations.

[0041] Instruction decoding module 120 decodes the pooling instruction POOL.MAX from instruction scheduling module 110 to produce a decoding result. Pooling control circuit 130, based on the decoding result of pooling instruction POOL.MAX, determines the number of execution cycles for the pooling instruction and reads feature points from the feature map values ​​from register group 140 to comparators 510 and 520. Comparator 510 is coupled to pooling control circuit 130 to receive a first portion of multiple feature points corresponding to the receptive field, such as feature points IN51 and IN52. Comparator 510 selects the largest feature point tmp52 from the first portion. Comparator 520 is coupled to pooling control circuit 130 to receive a second portion of the multiple feature points corresponding to the receptive field, such as feature point IN53. Comparator 520 is also coupled to the output of loop intermediate result access circuit 560 to receive the largest feature point tmp51 from the previous execution cycle in multiple loops (execution cycles) of the maximum value pooling operation from loop intermediate result access circuit 560. In the first loop of the maximum pooling operation performed by the floating-point unit 500, the initial value of the maximum feature point tmp51 is negative infinity to ensure that the final result does not come from the initial value of the maximum feature point tmp51. The comparator 520 selects the maximum feature point tmp53 from the second part of the current execution cycle (e.g., feature point IN53) and the maximum feature point tmp51 of the previous execution cycle.

[0042] The first input of multiplexer 530 is coupled to the output of comparator 510 to receive the maximum feature point tmp52. The output of multiplexer 530 is coupled to the first input of comparator 550. The first input of multiplexer 540 is coupled to the output of comparator 520 to receive the maximum feature point tmp53. The output of multiplexer 540 is coupled to the second input of comparator 550. When the floating-point unit 500 is used as hardware specifically for maximum pooling operations, multiplexer 530 transmits the maximum feature point tmp52 to the first input of comparator 550, while multiplexer 540 transmits the maximum feature point tmp53 to the second input of comparator 550. When the floating-point unit 500 is used as a standard floating-point unit, and when performing comparison operations within this standard floating-point unit, the second input of multiplexer 530 receives the floating-point number a, while the second input of multiplexer 540 receives the floating-point number b. At this time, multiplexer 530 transmits floating-point number a to the first input of comparator 550, while multiplexer 540 transmits floating-point number b to the second input of comparator 550. Comparator 550 selects the maximum feature point tmp54 from the outputs tmp52 of multiplexer 530 and tmp53 of multiplexer 540. The input of the loop intermediate result memory access circuit 560 is coupled to the output of comparator 550 to receive the maximum feature point tmp54 of the current execution cycle of the maximum value pooling operation.

[0043] For example, assuming the size of the corresponding receptive field is 3*3 feature points, and assuming the data elements in the corresponding receptive field are P1, P2, P3, P4, P5, P6, P7, P8, and P9, then the maximum pooling operation (comparison iterative operation) of this corresponding receptive field includes 3 comparison loops. In the first comparison loop, feature points IN51, IN52, and IN53 are P1, P2, and P3 respectively. The intermediate result memory access circuit 560 provides the largest feature point tmp51 with a value of negative infinity to the comparator 520, and the comparator 550 writes the largest feature point tmp54 of the first comparison loop (i.e., the largest among P1, P2, and P3) into the intermediate result memory access circuit 560. In the second comparison loop, feature points IN51, IN52, and IN53 are P4, P5, and P6, respectively. The intermediate result memory access circuit 560 provides the largest feature point tmp51 (the largest among P1, P2, and P3) from the first comparison loop to comparator 520, while comparator 550 writes the largest feature point tmp54 (the largest among P1, P2, P3, P4, P5, and P6) from the second comparison loop into the intermediate result memory access circuit 560. In the third comparison loop, the feature points IN51, IN52 and IN53 are P7, P8 and P9 respectively. The intermediate result memory access circuit 560 provides the largest feature point tmp51 of the second comparison loop (i.e., the largest among P1, P2, P3, P4, P5 and P6) to the comparator 520, while the comparator 550 writes the largest feature point tmp54 of the third comparison loop (i.e., the largest among P1, P2, P3, P4, P5, P6, P7, P8 and P9) into the temporary register group 140.

[0044] In summary, conventional techniques require 8 instructions and 8 computation speeds to perform maximum pooling operations with a 3x3 receptive field, while the above embodiment only requires 1 instruction, POOL.MAX, to complete the maximum pooling operation, consuming a total of 3 computation speeds. That is, the above embodiment can complete the maximum pooling operation with fewer instructions and at a faster speed.

[0045] FIG6 is a circuit block diagram of a floating-point arithmetic unit 600 according to another embodiment of the present invention. The floating-point arithmetic unit 600 shown in FIG6 can be described with reference to any of the floating-point arithmetic units 150_1 to 150_N shown in FIG1 or 3 and by analogy. The floating-point arithmetic unit 600 shown in FIG6 can be one of many embodiments of any of the floating-point arithmetic units 150_1 to 150_N shown in FIG1 or 3. In the embodiment shown in FIG6, the floating-point arithmetic unit 600 includes an average pooling circuit 610, a maximum pooling circuit 620, a loop intermediate result memory access circuit 630, and a multiplexer 640.

[0046] The average pooling circuit 610 is coupled to the pooling control circuit 130 to receive multiple feature points corresponding to the receptive field, such as feature points IN61, IN62, and IN63. The average pooling circuit 610 selectively performs average pooling operations on the multiple feature points of the corresponding receptive field based on the control of the pooling control circuit 130. The average pooling operation of the average pooling circuit 610 can be deduced by analogy to the relevant description of the average pooling operation in the embodiment shown in Figure 4. The maximum pooling circuit 620 is coupled to the pooling control circuit 130 to receive multiple feature points corresponding to the receptive field. The maximum pooling circuit 620 selectively performs maximum pooling operations on the multiple feature points of the corresponding receptive field based on the control of the pooling control circuit 130. The maximum pooling operation of the maximum pooling circuit 620 can be deduced by analogy to the relevant description of the maximum pooling operation in the embodiment shown in Figure 5.

[0047] The loop intermediate result memory access circuit 630 is coupled to the average pooling circuit 610 to receive the loop intermediate result tmp61 of the current execution cycle in multiple loops (execution cycles) of the average pooling operation. The loop intermediate result memory access circuit 630 is coupled to the average pooling circuit 610 to provide the loop intermediate result tmp62 of the previous execution cycle in the average pooling operation. The loop intermediate result memory access circuit 630 is coupled to the maximum pooling circuit 620 to receive the loop intermediate result tmp63 of the current execution cycle in multiple loops (execution cycles) of the maximum pooling operation. The loop intermediate result memory access circuit 630 is coupled to the maximum pooling circuit 620 to provide the loop intermediate result tmp64 of the previous execution cycle of the maximum pooling operation.

[0048] The first input terminal of the multiplexer 640 is coupled to the output terminal of the average pooling circuit 610. The second input terminal of the multiplexer 640 is coupled to the output terminal of the maximum pooling circuit 620. If the pooling operation in response to the pooling instruction is an average pooling operation, then the maximum pooling circuit 620 is disabled, and the multiplexer 640 writes the average pooling result of the average pooling circuit 610 into the temporary register group 140. If the pooling operation in response to the pooling instruction is a maximum pooling operation, then the average pooling circuit 610 is disabled, and the multiplexer 640 writes the maximum pooling result of the maximum pooling circuit 620 into the temporary register group 140.

[0049] FIG7 is a circuit block diagram illustrating the average pooling circuit 610 and the maximum pooling circuit 620 according to an embodiment of the present invention. The average pooling circuit 610, the maximum pooling circuit 620, the loop intermediate result memory access circuit 630, and the multiplexer 640 shown in FIG7 can be referred to the relevant description in FIG6, and therefore will not be repeated here. The average pooling circuit 610 and the maximum pooling circuit 620 shown in FIG7 can be considered as one of many implementation examples of the average pooling circuit 610 and the maximum pooling circuit 620 shown in FIG6.

[0050] In the embodiment shown in FIG. 7, the mean pooling circuit 610 includes a carry-preserving adder 611, an adder 612, a multiplexer 613, a multiplexer 614, an adder 615, a floating-point normalization circuit 616, a multiplier 617, and a multiplexer 618. The carry-preserving adder 611 is coupled to the pooling control circuit 130 to receive multiple feature points corresponding to the receptive field, such as feature points IN61, IN62, and IN63. The carry-preserving adder 611 generates a sum tmp71 and a carry tmp72 based on feature points IN61, IN62, and IN63. The adder 612 is coupled to the carry-preserving adder 611 to receive the sum tmp71 and the carry tmp72. The adder 612 generates a sum tmp73 based on the sum tmp71 and the carry tmp72. The first input of multiplexer 613 is coupled to adder 612 to receive the sum tmp73. The first input of adder 615 is coupled to the output of multiplexer 613. The second input of adder 615 is coupled to the output of multiplexer 614. The input of floating-point normalization circuit 616 is coupled to the output of adder 616 to receive the sum tmp75. The first input of multiplier 617 receives the sum of feature points SUM41 from pooling control circuit 130 with respect to the corresponding receptive field. The second input of multiplier 617 receives the average coefficient AC41 from pooling control circuit 130 with respect to the corresponding receptive field. The first input of multiplexer 618 is coupled to the output of floating-point normalization circuit 616. The second input of multiplexer 618 is coupled to the output of multiplier 617. The output of multiplexer 618 is coupled to the first input of multiplexer 640.

[0051] The loop intermediate result memory access circuit 630 is coupled to the output of the floating-point normalization circuit 616 to receive the loop intermediate result tmp61 of the current execution cycle in multiple loops (execution cycles) of the average pooling operation. The loop intermediate result memory access circuit 630 is coupled to the first input of the multiplexer 614 to provide the loop intermediate result tmp62 of the previous execution cycle of the average pooling operation. The carry-storage adder 611, adder 612, multiplexer 613, multiplexer 614, adder 615, floating-point normalization circuit 616, multiplier 617, multiplexer 618, and loop intermediate result memory access circuit 630 shown in Figure 7 can be deduced from the relevant descriptions of the carry-storage adder 410, adder 420, multiplexer 430, multiplexer 440, adder 450, floating-point normalization circuit 460, multiplier 480, multiplexer 490, and loop intermediate result memory access circuit 470 shown in Figure 4, and will not be repeated here.

[0052] In the embodiment shown in FIG7, the maximum pooling circuit 620 includes comparator 621, comparator 622, multiplexer 623, multiplexer 624, and comparator 625. Comparator 621 is coupled to the pooling control circuit 130 to receive a first portion of a plurality of feature points corresponding to the receptive field, such as feature points IN61 and IN62. Comparator 621 selects the maximum feature point tmp76 from the first portion. Comparator 622 is coupled to the pooling control circuit 130 to receive a second portion of a plurality of feature points corresponding to the receptive field, such as feature point IN63. Comparator 622 is also coupled to the loop intermediate result memory access circuit 630 to receive the maximum feature point (loop intermediate result tmp64) of the previous execution cycle in multiple loops (execution cycles) of the maximum pooling operation. In the case of the first loop of the maximum pooling operation performed by the floating-point unit 600, the loop intermediate result tmp64 is zero. Comparator 622 selects the maximum feature point tmp77 from the second part of the current execution cycle (e.g., feature point IN63) and the maximum feature point of the previous execution cycle (intermediate result tmp64).

[0053] The first input of multiplexer 623 is coupled to the output of comparator 621 to receive the maximum feature point tmp76. The first input of multiplexer 624 is coupled to the output of comparator 622 to receive the maximum feature point tmp77. The first input of comparator 625 is coupled to the output of multiplexer 623. The second input of comparator 625 is coupled to the output of multiplexer 624. Comparator 625 selects the maximum feature point (loop intermediate result tmp63) from the outputs of multiplexer 623 and multiplexer 624. Loop intermediate result memory access circuit 630 is coupled to the output of comparator 625 to receive the loop intermediate result tmp63 of the current execution cycle in multiple loops (execution cycles) of the maximum pooling operation. Loop intermediate result memory access circuit 630 is coupled to comparator 622 to provide the loop intermediate result tmp64 of the previous execution cycle of the maximum pooling operation. Comparator 622 selects the maximum feature point tmp77 from the second part of the current execution cycle (e.g., feature point IN63) and the loop intermediate result tmp64 of the previous execution cycle of the maximum pooling operation. The comparators 621, 622, 623, 624, 625, and the loop intermediate result memory access circuit 630 shown in Figure 7 can be deduced from the relevant descriptions of comparators 510, 520, 530, 540, 550, and the loop intermediate result memory access circuit 560 shown in Figure 5, and will not be described again.

[0054] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0011] Figure 1 is a circuit block diagram of an artificial intelligence (AI) chip according to an embodiment of the present invention. Figure 2 is a flowchart of a pooling method for an AI chip according to an embodiment of the present invention. Figure 3 is a circuit block diagram of a pooling control circuit according to an embodiment of the present invention. Figure 4 is a circuit block diagram of a floating-point arithmetic unit according to an embodiment of the present invention. Figure 5 is a circuit block diagram of a floating-point arithmetic unit according to another embodiment of the present invention. Figure 6 is a circuit block diagram of a floating-point arithmetic unit according to yet another embodiment of the present invention. Figure 7 is a circuit block diagram of an average pooling circuit and a maximum pooling circuit according to an embodiment of the present invention.

Claims

1. An artificial intelligence chip, comprising: One instruction scheduling module; An instruction decoding module coupled to the instruction scheduling module to receive a pooled instruction, wherein the instruction decoding module decodes the pooled instruction to produce a decoding result; a register group; A pooling control circuit is coupled to the instruction decoding module and the register group; and a first floating-point arithmetic unit is coupled to the pooling control circuit, wherein the pooling control circuit determines an execution cycle number of the pooling instruction based on the decoding result, and provides the execution cycle number to the first floating-point arithmetic unit; the pooling control circuit reads a feature map value from the register group based on the decoding result, and provides multiple feature points of a first receptive field of the feature map value to the first floating-point arithmetic unit; and the first floating-point arithmetic unit performs a pooling operation on the feature points of the first receptive field based on the execution cycle number to generate a pooling result of the first receptive field.

2. The artificial intelligence chip as described in claim 1, further comprising: A second floating-point arithmetic unit is coupled to the pooling control circuit, wherein the pooling control circuit provides the number of execution cycles to the second floating-point arithmetic unit; the pooling control circuit provides multiple feature points of a second receptive field of the feature map value to the second floating-point arithmetic unit based on the decoding result; and the second floating-point arithmetic unit performs a pooling operation on the feature points of the second receptive field based on the number of execution cycles to produce a pooling result of the second receptive field.

3. The artificial intelligence chip as claimed in claim 1, wherein the pooling control circuit comprises: A pooling operation control module is coupled to the instruction decoding module to receive the decoding result, wherein the pooling operation control module determines the number of execution cycles for the pooling instruction based on the decoding result and provides the number of execution cycles to the first floating-point arithmetic unit; an operand acquisition module is coupled to the pooling operation control module and the register group, wherein the operand acquisition module reads the feature map value from the register group based on the control of the pooling operation control module; And a feature map input control module coupled to the arithmetic unit acquisition module to receive the feature map value, wherein the feature map input control module provides the feature points of the first receptive field of the feature map value to the first floating-point arithmetic unit.

4. The artificial intelligence chip as described in claim 1, wherein the first floating-point unit comprises: A carry-store adder, coupled to the pooling control circuit to receive the feature points of the first receptive field, wherein the carry-store adder generates a first sum and a carry value based on the feature points; a first adder, coupled to the carry-store adder to receive the first sum and the carry value, wherein the first adder generates a second sum based on the first sum and the carry value; a first multiplexer, wherein a first input of the first multiplexer is coupled to the first adder to receive the second sum; a second multiplexer; A second adder, wherein a first input terminal of the second adder is coupled to an output terminal of the first multiplexer, and a second input terminal of the second adder is coupled to an output terminal of the second multiplexer; A floating-point normalization circuit, wherein an input of the floating-point normalization circuit is coupled to an output of the second adder; a loop intermediate result memory access circuit, wherein an input of the loop intermediate result memory access circuit is coupled to an output of the floating-point normalization circuit, and an output of the loop intermediate result memory access circuit is coupled to a first input of the second multiplexer; a multiplier, wherein a first input of the multiplier receives a feature point summation value from the pooling control circuit with respect to the first receptive field, and a second input of the multiplier receives an average coefficient from the pooling control circuit with respect to the first receptive field; and a third multiplexer, wherein a first input of the third multiplexer is coupled to the output of the floating-point normalization circuit, and a second input of the third multiplexer is coupled to an output of the multiplier.

5. The artificial intelligence chip as claimed in claim 1, wherein the first floating-point unit comprises: A first comparator, coupled to the pooling control circuit, receives a first portion of the feature points in the first receptive field, wherein the first comparator selects a first maximum feature point from the first portion; a second comparator, coupled to the pooling control circuit, receives a second portion of the feature points in the first receptive field, wherein the second comparator outputs a second maximum feature point; a first multiplexer, wherein a first input of the first multiplexer is coupled to an output of the first comparator to receive the first maximum feature point; and a second multiplexer, wherein a first input of the second multiplexer is coupled to an output of the second comparator. A third comparator, wherein a first input of the third comparator is coupled to an output of the first multiplexer, a second input of the third comparator is coupled to an output of the second multiplexer, and the third comparator selects a third maximum feature point from an output of the first multiplexer and an output of the second multiplexer; and a loop intermediate result memory access circuit, wherein an input of the loop intermediate result memory access circuit is coupled to an output of the third comparator, and an output of the loop intermediate result memory access circuit is coupled to the second comparator to provide the third maximum feature point of a previous execution cycle; wherein the second comparator selects the second maximum feature point from a second portion of a current execution cycle and the third maximum feature point of the previous execution cycle.

6. The artificial intelligence chip as claimed in claim 1, wherein the first floating-point unit comprises: A mean pooling circuit, coupled to the pooling control circuit to receive the feature points of the first receptive field, wherein the mean pooling circuit selectively performs a mean pooling operation on the feature points of the first receptive field based on the control of the pooling control circuit; and a max pooling circuit, coupled to the pooling control circuit to receive the feature points of the first receptive field, wherein the max pooling circuit selectively performs a max pooling operation on the feature points of the first receptive field based on the control of the pooling control circuit. A loop intermediate result memory access circuit, wherein the loop intermediate result memory access circuit is coupled to the mean pooling circuit to receive a loop intermediate result of the mean pooling operation in the current execution cycle, the loop intermediate result memory access circuit is coupled to the mean pooling circuit to provide a loop intermediate result of the mean pooling operation in the previous execution cycle, the loop intermediate result memory access circuit is coupled to the maximum pooling circuit to receive a loop intermediate result of the maximum pooling operation in the current execution cycle, and the loop intermediate result memory access circuit is coupled to the maximum pooling circuit to provide a loop intermediate result of the maximum pooling operation in the previous execution cycle; And a first multiplexer, wherein a first input of the first multiplexer is coupled to an output of the average pooling circuit, and a second input of the first multiplexer is coupled to an output of the maximum pooling circuit.

7. The artificial intelligence chip as claimed in claim 6, wherein the mean pooling circuit comprises: A carry-store adder coupled to the pooling control circuit to receive the feature points of the first receptive field, wherein the carry-store adder generates a first sum and a carry value based on the feature points; a first adder coupled to the carry-store adder to receive the first sum and the carry value, wherein the first adder generates a second sum based on the first sum and the carry value; a second multiplexer, wherein a first input of the second multiplexer is coupled to the first adder to receive the second sum; a third multiplexer; a second adder, wherein a first input of the second adder is coupled to an output of the second multiplexer, and a second input of the second adder is coupled to an output of the third multiplexer; A floating-point normalization circuit, wherein an input of the floating-point normalization circuit is coupled to an output of the second adder; a multiplier, wherein a first input of the multiplier receives a feature point summation value from the pooling control circuit with respect to the first receptive field, and a second input of the multiplier receives an average coefficient from the pooling control circuit with respect to the first receptive field; and a fourth multiplexer, wherein a first input of the fourth multiplexer is coupled to an output of the floating-point normalization circuit, a second input of the fourth multiplexer is coupled to an output of the multiplier, and an output of the fourth multiplexer is coupled to the first input of the first multiplexer; wherein a loop intermediate result memory access circuit is coupled to the output of the floating-point normalization circuit to receive the loop intermediate result of the mean pooling operation in the current execution cycle, and the loop intermediate result memory access circuit is coupled to a first input of the third multiplexer to provide the loop intermediate result of the mean pooling operation in the previous execution cycle.

8. The artificial intelligence chip as claimed in claim 6, wherein the maximum pooling circuit comprises: A first comparator, coupled to the pooling control circuit, receives a first portion of the feature points in the first receptive field, wherein the first comparator selects a first maximum feature point from the first portion; a second comparator, coupled to the pooling control circuit, receives a second portion of the feature points in the first receptive field, wherein the second comparator outputs a second maximum feature point; a second multiplexer, wherein a first input of the second multiplexer is coupled to an output of the first comparator to receive the first maximum feature point; and a third multiplexer, wherein a first input of the third multiplexer is coupled to an output of the second comparator. And a third comparator, wherein a first input of the third comparator is coupled to an output of the second multiplexer, a second input of the third comparator is coupled to an output of the third multiplexer, and the third comparator selects a third maximum feature point from an output of the second multiplexer and an output of the third multiplexer; wherein a loop intermediate result memory access circuit is coupled to an output of the third comparator to receive the loop intermediate result of the maximum pooling operation of the current execution cycle, and the loop intermediate result memory access circuit is coupled to the second comparator to provide the loop intermediate result of the maximum pooling operation of the previous execution cycle; wherein the second comparator selects the second maximum feature point from the second portion of the current execution cycle and the loop intermediate result of the maximum pooling operation of the previous execution cycle.

9. A pooling method for an artificial intelligence chip, comprising: An instruction decoding module of the artificial intelligence chip decodes a pooling instruction to generate a decoding result, wherein the instruction decoding module is coupled to an instruction scheduling module of the artificial intelligence chip to receive the pooling instruction; a pooling control circuit of the artificial intelligence chip determines an execution cycle number of the pooling instruction based on the decoding result, wherein the pooling control circuit is coupled to the instruction decoding module, a register group of the artificial intelligence chip, and a first floating-point unit of the artificial intelligence chip; the pooling control circuit provides the execution cycle number to the first floating-point unit; the pooling control circuit reads a feature map value from the register group based on the decoding result; the pooling control circuit provides multiple feature points of a first receptive field of the feature map value to the first floating-point unit; and the first floating-point unit performs a pooling operation on the feature points of the first receptive field based on the execution cycle number to generate a pooling result of the first receptive field.

10. The pooling method as described in claim 9, further comprising: The pooling control circuit provides the number of execution cycles to a second floating-point unit of the artificial intelligence chip, wherein the second floating-point unit is coupled to the pooling control circuit; the pooling control circuit provides multiple feature points of a second receptive field of the feature map value to the second floating-point unit based on the decoding result; and the second floating-point unit performs a pooling operation on the feature points of the second receptive field based on the number of execution cycles to generate a pooling result of the second receptive field.

11. The pooling method as described in claim 9, further comprising: A pooling operation control module of the pooling control circuit determines the number of execution cycles for the pooling instruction based on the decoding result, wherein the pooling operation control module is coupled to the instruction decoding module to receive the decoding result; the pooling operation control module provides the number of execution cycles to the first floating-point arithmetic unit; an arithmetic element acquisition module of the pooling control circuit reads the feature map value from the register group based on the control of the pooling operation control module, wherein the arithmetic element acquisition module is coupled to the pooling operation control module and the register group; and a feature map input control module of the pooling control circuit provides the feature points of the first receptive field of the feature map value to the first floating-point arithmetic unit, wherein the feature map input control module is coupled to the arithmetic element acquisition module to receive the feature map value.

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