Display system

Abstract

The system of the present invention reduces the size and / or efficiency of a display system or device, integrating or including displays such as LED displays or LCoS displays, such as micro-LED displays and OLED displays, into such systems or devices. Embodiments of this disclosure include, but are not limited to, a display in which at least two pixels are four pixels comprising two green pixels, one blue pixel, and one red pixel, and wherein pixel logic circuitry keeps the red pixel in an on state while simultaneously driving the two green and blue pixels according to a field-sequential color (FSC) pixel driving process or method.

Description

[Technical Field]

[0001] This disclosure relates to displays, such as liquid crystal-on-silicon (LCoS) displays, light-emitting diode (LED) displays, including microLED displays and organic LED (OLED) displays, and microdisplays (e.g., liquid crystal-on-silicon displays or LED displays). More specifically, the present invention relates to displays operating according to field sequential driving technology. [Previous Technology]

[0002] A typical Augmented Reality (AR) head-mounted device includes a device mounted around the face or head. To generate augmented reality images, the head-mounted device needs to house multiple components, such as two displays, optical elements (e.g., an optical engine), and a power supply. Therefore, augmented reality head-mounted devices can be bulky and large in size. In mobile systems, such as augmented reality and head-mounted systems, displays of the liquid crystal-coated silicon (LCD) or micro-light-emitting diode (LED) types are typically used. The size, weight, and battery life of the displays used in such systems are important in manufacturing these systems to allow users to wear them comfortably for as long as possible before the system or device needs to be recharged.

[0003] Light-emitting diode (LED) displays, typically driven by thin-film transistor arrays, are used in augmented reality systems, such as head-mounted displays, and are relatively inexpensive. However, thin-film transistors have high resistance and therefore consume a large amount of power. Therefore, driving large currents with this type of thin-film transistor can also be challenging. Furthermore, miniaturizing thin-film transistors to an optimal size suitable for microdisplays is also challenging because they use a larger geometry than transistors fabricated on silicon wafers. While liquid crystal silicon-coated microdisplays made with silicon backplanes can place logic and memory under the pixels, such devices operate in a color-sequential manner, involving the continuous reuse of the same pixels and mirrors for red, green, and blue color fields. When driving LEDs, multiple panels (one for each color) may be required, thus tripling the size of the subsystem, or a spatial color arrangement involving multiple LEDs of different colors on a single panel could be used. However, these options often result in suboptimal display or display system sizes, for example, for augmented reality systems or devices. The displays according to the present invention, such as liquid crystal silicon-coated (LCoS) displays, light-emitting diode (LED) displays, including micro LED displays and OLED displays, and micro displays (e.g., LCoS or LED displays) can be used in applications or systems including but not limited to projectors, head-up displays, and augmented reality (AR), mixed reality (MR), and virtual reality (VR) systems or devices (e.g., head-mounted devices or other near-eye devices). [Summary of the Invention]

[0004] One aspect of this disclosure may involve, for example, driving a main pixel by driving sub-pixels in a field-sequential and / or hybrid mode, such that a single pixel driving circuit (including pixel logic circuitry, such as pixel control logic circuitry) is used to drive at least two sub-pixels or LED / LED pixels (e.g., microLEDs). Therefore, it is not necessary to provide a driving circuit or separate driving circuitry for each sub-pixel or LED / LED pixel (e.g., microLED). In an example of this disclosure, one or more pixels of the main pixel may be turned on at all times during a frame or color subframe, while simultaneously one or more other pixels (e.g., sub-pixels, LEDs, or microLEDs) are driven according to field-sequential operation. In an example aspect of this disclosure, the display is a multi-color display, for example, a multi-color microLED display including a main pixel, wherein the main pixel has multiple colored LEDs as sub-pixels (where the color of an LED may be different from the color of another LED among those LEDs). In an example aspect of this disclosure, the display is an LCoS display driven by field-sequential color operation.

[0005] Comparative examples of displays may require separate driving circuits for each sub-pixel within a main pixel (e.g., each of the red, green, and blue sub-pixel LED sets). The exemplary aspect of the present invention is directed to the reuse of driving circuitry (e.g., pixel circuitry, pixel control circuitry, pixel logic circuitry, or pixel control logic circuitry) over time and to reducing the number of copies of such circuitry required to drive the display according to the invention. Therefore, the display according to the invention has a reduced main pixel size, and thus a reduced overall size. The micro-LED display according to the invention is an alternative to other types of displays and provides a compact form factor and high optical engine efficiency because no external illumination source is required. Compared to displays such as LCoS displays, where the entire display emits light regardless of whether the image content requires it, in the example of the micro-LED display, according to the invention, only active pixels emit light.

[0006] According to the present invention, exemplary aspects of the present invention reduce the size of a display system or device and / or improve the efficiency of a display system or device that integrates or includes a display according to the present invention, wherein the display is, for example, an LED display, such as a micro-LED display and an OLED. According to the present invention, examples of circuitry allow the display to have a small size while providing sufficient resolution and brightness to the pixels of the display using reasonable power. According to the present invention, a display including circuitry has a low battery capacity to power the display and its associated circuitry. According to the present invention, a display including circuitry also allows the display and its associated circuitry to have a lighter weight. According to the present invention, the display provides advantages in applications including, but not limited to, projectors, head-up displays, and augmented reality (AR), mixed reality (MR), and virtual reality (VR) systems or devices, such as head-mounted devices or other near-eye devices or systems.

Implementation Method

[0008] Detailed embodiments are disclosed herein as needed. It must be understood that the disclosed embodiments are merely examples of various alternative forms. As used herein, the term "exemplary" is widely used to refer to embodiments as drawings, samples, models, or patterns. The drawings are not necessarily drawn to scale, and some features may be exaggerated or minimized to show details of particular components. In other instances, familiar components, systems, materials, or methods known to those skilled in the art have not been described in detail to avoid obscuring the content of this disclosure. Therefore, the specific structural and functional details disclosed herein should not be construed as a limitation, but only as a basis for the scope of the patent and a representative basis for teaching those skilled in the art.

[0009] Referring to FIG1, a block diagram of a display system 100 according to an example of the present disclosure is provided through an environmental context. As shown, the display system 100 may include a graphics processing device 102 electrically coupled to a digital driving device 104, and an optical engine 106 electrically and / or optically coupled to the digital driving device 104.

[0010] The graphics processing device 102 transmits image data and / or control data to the digital drive device 104. The graphics processing device 102 typically includes a processor or associated with a processor, and other conventional components well known to those skilled in the art. The processor may be internal to or external to the graphics processing device 102. In the exemplary aspect of this disclosure, the processor may execute software modules, programs, or instructions of the graphics processing device 102. Storage devices (e.g., memory devices or memory blocks) may also be internal to or external to the graphics processing device 102.

[0011] The digital drive unit 104 receives data from the graphics processing unit 102, analyzes the data in the analyzer 108, and arranges the received data before transmitting, for example, image data, to the optical engine 106. The analyzer 108 separates and / or identifies image and command data and routes the information (e.g., based on the received data) to the light source control 110, formatter 113, and bias control 112 modules. The light source control 110 is only used when the display is an LCoS display.

[0012] The light source control 110 converts the received instructions into timed control inputs. The bias control 112 converts the received instructions into voltages, while the formatter 113 converts the image data into binary format data (e.g., "bit plane"), which is used to drive the state of pixels in the display 120 after the bit plane has been stored in memory 114 (which serves as a temporary storage area and can additionally store control data). The digital driving device 104 may be, for example, a component of a computing system, head-mounted device, and / or other device using an LCoS or micro LED (uLED) display.

[0013] In an exemplary aspect of this disclosure, the optical engine 106 includes a spatial light modulator or display 120 component and all other means that may be necessary to complete the display system 100, as is known to those skilled in the art. In other exemplary aspects of this disclosure, the display 120 itself may be located outside the optical engine 106. If an LCoS display is used, the optical engine 106 may be used to include a light source 116, wherein the light source 116 is controlled such that it illuminates the spatial light modulator 120 using the intensity and on / off timing of electromagnetic radiation (e.g., light) provided by the light source control 110. The display 120 includes a pixel array 126 comprising a two-dimensional array of multiple columns and rows of primary pixels 128, indicated by dashed lines. In FIG. 1, only one primary pixel 128 is labeled, and only two columns and two rows are shown. However, in practical implementations, up to thousands or more columns and rows may be stored in the pixel array 126, allowing up to millions or more primary pixels 128 to exist in the display 120.

[0014] In an LCoS display, the spatial light modulator 120 includes a display front plane 122, such as a liquid crystal (LC) cell, which modulates reflected or transmitted light under the influence of or according to a power input from or based on a pixel circuit input to a pixel element (e.g., a pixel electrode or a conductive metal element, such as a reflective metal mirror). The pixel element is a pixel 128 of a two-dimensional pixel array 126, wherein the two-dimensional pixel array 126 is located within, coupled to, and / or integrated into a backplane integrated circuit 124, which also includes pixel circuitry, such as pixel array drive logic 125 that provides image data and / or control data and is connected to the pixel array. The pixel array is distributed as multiple columns or rows of multiple pixels, depending on a function of the data. In an LED display (e.g., a micro-LED display), a spatial light modulator 120 includes a front plane 122 of the display, such as an LED array (e.g., a micro-LED), which outputs light under the influence of or according to a power input from or based on a pixel circuit input under pixel elements (e.g., LEDs and micro-LEDs; see Figures 2A-2B), wherein the pixel elements are pixels 128 of a two-dimensional pixel array 126, wherein the two-dimensional pixel array 126 is located within, coupled to, and / or integrated into a backplane integrated circuit 124. Pixels 128 in the backplane are coupled to or electrically connected to the front plane and modulate reflected light according to a binary pattern supplied from memory 114. In one exemplary aspect of this disclosure, pixel 128 may include pixel elements (e.g., pixel electrodes or conductive and reflective metal elements, such as reflective metal mirrors or light-emitting structures, such as LEDs and microLEDs), pixel circuitry (e.g., pixel control or driving circuitry), and driving devices (e.g., current or voltage driving devices or systems). In one exemplary aspect of this disclosure, the pixel control or driving circuitry includes pixel logic or one or more logic functions. In a microLED display, the LED array emits light, and the backplane regulates the driving current supplied to each pixel's LEDs according to a binary pattern from memory 114 to make them emit light or not emit light.

[0015] As shown in the figure below, according to the present invention, a pixel or pixel unit 128 includes or integrates a memory element (e.g., a static random access memory (SRAM) element) and a pixel circuit / pixel driver circuit (e.g., the circuit of Figures 2-6) electrically coupled to the memory element in Figures 2-6. The memory element of the pixel is repeatedly loaded with a binary pattern provided by memory 114 to establish a time-dependent pixel state that generates the grayscale value (illuminance) of each pixel. In the case of an LCoS display, the pixel circuit / pixel driver circuit is used to translate the low potential voltage output from the memory element into a high potential voltage required to perform electro-optic modulation in the front plane 122. In the case of a micro LED display, the pixel driver (included in the pixel circuit / pixel driver circuit) is a current source that converts the binary output into a control current that changes over time to turn on or off.

[0016] The optical components 118 within the optical engine 106 may include a beam splitter, a polarizer (or polarizing beam splitter), a lens, and a waveguide, and are used to route light from the light source 116 to the spatial light modulator 120, and then through the modulated image to reach the user's eyes.

[0017] According to the present invention, Figures 2A and 2B illustrate examples of the configuration of the main pixel 200 and schematic diagrams thereof. The main pixel 200 may be the same as the pixel 128 shown in Figure 1. As shown in Figure 2A, the main pixel 200 includes four sub-pixels 201-204. In the example shown in Figure 2B, the sub-pixels 201-204 constituting the main pixel 200 each include light-emitting diodes (LEDs) 211-214; however, in another example, the sub-pixels 201-204 may be based on other light-emitting devices and / or on reflective materials or devices, such as digital micromirror devices (DMDs).

[0018] In one exemplary aspect of the present invention, the color of one or more LEDs 211-214 in the main pixel 200 may be different from that of another LED 211-214. LEDs according to the present invention include micro LEDs, OLEDs, quantum dots, etc. In an exemplary aspect of the present disclosure, as shown in FIG2A, there are two green LEDs 212 and 213, one blue LED 211, and one red LED 214. However, it will be understood by those skilled in the art that each LED of the main pixel 200 may be any color or combination of colors. In an exemplary aspect of the present disclosure, the light-emitting area (i.e., the light-emitting area corresponding to the physical size of the light-emitting region) of one or more LEDs 211-214 may be different from that of the other LEDs 211-214 in the main pixel 200. In an exemplary aspect of the present disclosure, LEDs may have different sizes to compensate for differences in photoelectric conversion efficiency between LEDs of different colors, perceptual differences in the human visual system (e.g., different sensitivities to different colors), etc. In an exemplary aspect according to this disclosure, as shown in FIG2A, green (G) subpixels 212 and 213 have the same size and shape, red (R) subpixels 204 and blue (B) subpixels 201 have the same shape, but the size of red subpixel 204 is larger than that of blue subpixel 201. It will be understood by those skilled in the art that the size, shape, number, and color of each subpixel 201-204 of the main pixel 200 may differ from one or more of the other subpixels 201-204. To implement a LCoS-based architecture for subpixels 201-204, LEDs 211-214 may alternatively be represented by metal mirrors (e.g., capacitor devices) driven by circuit components operating based on a voltage gap across electrodes.

[0019] As shown in FIG2A, sub-pixels 201-204 are arranged according to a Bayer type pattern. Since the eye reacts most strongly to green when distinguishing details, the number of green pixels or sub-pixels included in the main pixel 200 according to the invention determines the effective resolution of the display including the main pixel 200 according to the invention.

[0020] In another exemplary aspect of the present invention, a single green LED sub-pixel may be used. Figures 3A and 3B are schematic diagrams illustrating an example configuration of the main pixel 300 according to the present invention and its reproduction. The main pixel 300 may be the same as pixel 128 shown in Figure 1. As shown in Figure 3A, the main pixel 300 includes three sub-pixels 301-303. In the example shown in Figure 3B, the sub-pixels 301-303 constituting the main pixel 300 respectively include LEDs 311-313; however, in another example, the sub-pixels 301-303 may be based on other light-emitting devices and / or on reflective materials or devices, such as micromirrors. In an exemplary aspect of the present disclosure, the color of one or more of the LEDs 311-313 in the main pixel 300 may be different from that of another of the LEDs 311-313. The LEDs according to the present invention include micro LEDs, OLEDs, quantum dots, etc. As shown in Figure 3A, there is a green LED 312, a blue LED 311, and a red LED 313. However, it will be understood by those skilled in the art that each LED of the main pixel 300 can be any color or combination of colors. In one exemplary aspect of this disclosure, the light-emitting area (i.e., the light-emitting area corresponding to the physical size of the light-emitting region) of one or more LEDs 311-313 may differ from other LEDs 311-313 of the main pixel 300. In one exemplary aspect of this disclosure, LEDs may have different sizes to compensate for differences in photoelectric conversion efficiency between LEDs of different colors, perceptual differences in the human visual system, etc. In one exemplary aspect of this disclosure, as shown in FIG3A, the green (G) sub-pixel 302 and the blue (B) sub-pixel 301 have the same size and shape, while the red (R) sub-pixel 303 is larger than the green sub-pixel 302 and the blue sub-pixel 301 and has a different shape. As will be understood by those skilled in the art, the size, shape, number, and color of each sub-pixel 303-303 of the main pixel 300 may differ from one or more other sub-pixels 303-303. To realize that the sub-pixels 301-303 are based on an LCoS architecture, the LEDs 311-313 may alternatively be represented by circuit components (e.g., capacitor devices) operating based on a voltage gap across electrodes.

[0021] Compared to the main pixel 200, the main pixel 300 may have a lower effective resolution due to the reduced number of green sub-pixels. However, because the red LED may have reduced efficiency, the main pixel 300 can achieve a specific brightness more efficiently and / or more easily achieve white balance by using a larger red component. This disclosure is not limited to main pixels comprising only three or four sub-pixels, and in other exemplary aspects of this disclosure, the main pixel may include five or more sub-pixels.

[0022] In one example aspect of the present invention, a mapping software module is provided in software or display integrated circuit (IC) hardware, which maps an original image containing image information (e.g., R, G, B pixel color information) onto a physical arrangement of sub-pixels within a main pixel, such that the color information is distributed in sub-pixels 201-204 or 301-303, wherein the color information is distributed in sub-pixels 201-204 or 301-303 in such a way that the amount of color output from sub-pixels 201-204 or 301-303 corresponds to, is equal to, or is substantially equal to the amount of color represented by the color information of the software, software module, and / or hardware input to a display associated with a display (e.g., display driver software and / or hardware). The software may be stored in the memory of any component associated with the display device (e.g., in graphics processing device 102, digital driver device 104, and display device 120, etc., as shown in FIG. 1).

[0023] FIG4 illustrates a pixel circuit 400 according to an exemplary aspect of the present invention, which may correspond to an example of circuitry for driving the main pixel 200 shown in FIG2A and 2B. The pixel circuit 400 may be an example of at least a portion of the array driving logic 125 shown in FIG1. ​​In one exemplary aspect of the present disclosure, as shown in FIG4, all LEDs in the main pixel may share a common cathode terminal, while each anode terminal of the LED is driven by a separate LED driver. In another exemplary aspect of the invention, all LEDs in the pixel share a common anode, while each anode terminal of the LED is driven by a separate LED driver.

[0024] The pixel circuit 400 receives image data DATA, power supply voltage Vpix, column write input ROW indicating which column of the main pixel is selected, timing change values ​​GGB_TVV of G1 / G2 / B sub-pixels (e.g., sub-pixels 201-203 in FIG. 2A), timing change value R_TVV of red sub-pixels (e.g., sub-pixel 204 in FIG. 2A), and sub-pixel-specific enable inputs R_ena, B_ena, G1_ena, and G2_ena, which indicate the timing of the sub-pixel being driven; and outputs current waveforms at nodes PB, PG1, PG2, and PR to drive the corresponding sub-pixels (e.g., driving LEDs 211-214 through the corresponding nodes PB, PG1, PG2, and PR shown in FIG. 2B). Inputs may be received from the digital driving device 104 shown in FIG. 1 (e.g., received from bias control 112 and / or memory 114), and outputs may be sent to the sub-pixel LEDs (e.g., as shown in FIG. 2B).

[0025] FIG. 5 illustrates a pixel circuit 500 according to the present invention, and may correspond to an example of circuitry for driving the main pixel 200 shown in FIG. 2A and 2B. The pixel circuit 500 may be an example of at least a portion of the array driving logic 125 shown in FIG. 1. In one exemplary aspect of the present disclosure, as shown in FIG. 5, all LEDs in the main pixel may share a common cathode terminal, while each anode terminal of the LED is driven by a separate LED driver. In another exemplary aspect of the invention, all LEDs in the pixel share a common anode, while each anode terminal of the LED is driven by a separate LED driver.

[0026] The pixel circuit 500 receives image data DATA, power supply voltage Vpix, column write input ROW indicating which column of the main pixel is selected, timing change values ​​RGGB_TVV of R / G1 / G2 / B sub-pixels (e.g., sub-pixels 201-203 in FIG. 2A), and sub-pixel-specific enable inputs R_ena, B_ena, G1_ena, and G2_ena, which indicate the timing of the sub-pixel being driven; and outputs current waveforms at nodes PB, PG1, PG2, and PR to drive the corresponding sub-pixels (e.g., driving LEDs 211-214 through the corresponding nodes PB, PG1, PG2, and PR shown in FIG. 2B). Inputs may be received from the digital driving device 104 shown in FIG. 1 (e.g., received from bias control 112 and / or memory 114), and outputs may be sent to the sub-pixel LEDs (e.g., as shown in FIG. 2B).

[0027] In the pixel circuit according to the invention, as shown in Figures 4-5, each main pixel (i.e., a combination of one or more sub-pixels of the main pixel in Figure 2A, for example) includes or is associated with: current sources 421-424 (Figure 4) or 521-524 (Figure 5) of LEDs driven by the main pixel (e.g., each LED 211-214 in Figure 2B) (e.g., current source driving devices such as transistors or a combination of resistors and transistors), and at least one storage device (e.g., memory device) of pixel logic (e.g., pixel control logic) that stores the desired or predetermined brightness levels of one or more LEDs and starts and stops the current at desired or predetermined times, causing the LEDs to be driven according to a pulse-width modulation (PWM) mode of operation (i.e., where the driving waveform oscillates between zero and a set value, and the brightness is determined by the ratio of the time it takes for the driving waveform to reach the set value to the driving current), or other series of variable-width pulses or numbers in response to the stored brightness level values. In Figure 4, two pixel logic and storage devices 411, 412 are shown. Figure 5 illustrates a pixel logic and storage device 511. In the comparative example, four sets of pixel logic and storage devices are needed to drive four sub-pixels; therefore, pixel circuits 400 and 500 require less circuitry to drive the same number of sub-pixels. Although Figures 4 and 5 show pixel circuits corresponding to a main pixel with LEDs driven by current sources 421-424 or 521-524, in the implementation of the main pixel based on the LCoS architecture, current sources 421-424 or 521-524 can be replaced by voltage sources. Pixel circuit 500 occupies a smaller area compared to pixel circuit 400. Conversely, pixel circuit 400 provides a larger usable duty cycle and / or requires a lower peak current compared to pixel circuit 500.

[0028] FIG6 illustrates a pixel circuit 600 according to the present invention, and may correspond to a circuit for driving the main pixel 300 shown in FIG3A and 3B. The pixel circuit 600 may be an example of at least a portion of the array driving logic 125 shown in FIG1. ​​In one exemplary aspect of the present disclosure, as shown in FIG6, all LEDs in the main pixel may share a common cathode terminal, while each anode terminal of the LED is driven by a separate LED driver. In another exemplary aspect of the present invention, all LEDs in the pixel share a common anode, while each anode terminal of the LED is driven by a separate LED driver.

[0029] The pixel circuit 600 receives image data DATA, power supply voltage Vpix, column write input ROW indicating which column of the main pixel is selected, timing change values ​​GB_TVV of G / B sub-pixels (e.g., sub-pixels 301 and 302 in FIG. 3A), timing change values ​​R_TVV of red sub-pixels (e.g., sub-pixel 303 in FIG. 3A), and sub-pixel specific enable inputs R_ena, B_ena, and G_ena, which indicate the timing of the sub-pixel being driven; and outputs current waveforms at nodes PB, PG, and PR to drive the corresponding voltages (e.g., driving LEDs 301-303 through the corresponding nodes PB, PG, and PR shown in FIG. 3B). Inputs may be received from the digital driving device 104 shown in FIG. 1 (e.g., received from bias control 112 and / or memory 114), and outputs may be sent to the sub-pixel LEDs (e.g., as shown in FIG. 3B).

[0030] FIG7 illustrates the pixel circuit 700 of the present invention, and may correspond to the circuitry for driving the main pixel 300 shown in FIG3A and 3B. The pixel circuit 700 may be an example of at least a portion of the array driving logic 125 shown in FIG1. ​​In one exemplary aspect of the present disclosure, as shown in FIG7, all LEDs in the main pixel may share a common cathode terminal, while each anode terminal of the LED is driven by a separate LED driver. In another exemplary aspect of the present invention, all LEDs in the pixel share a common anode, while each anode terminal of the LED is driven by a separate LED driver.

[0031] The pixel circuit 700 receives image data DATA, power supply voltage Vpix, column write input ROW indicating which column of the main pixel is selected, timing change values ​​RGB_TVV of R / G / B sub-pixels (e.g., sub-pixels 301-303 in FIG. 3A), and sub-pixel-specific enable inputs R_ena, B_ena, and G_ena, which indicate the timing of the sub-pixel being driven; and outputs current waveforms at nodes PB, PG, and PR to drive the corresponding voltages (e.g., driving LEDs 301-303 through the corresponding nodes PB, PG, and PR shown in FIG. 3B). Inputs may be received from the digital driving device 104 shown in FIG. 1 (e.g., received from bias control 112 and / or memory 114), and outputs may be sent to the sub-pixel LEDs (e.g., as shown in FIG. 3B).

[0032] In an example of the pixel circuit according to the invention, as shown in Figures 6-7, each main pixel (i.e., one or more sub-pixels, such as a combination of main pixels 300 as shown in Figure 3A) includes or is associated with: current sources 621-623 (Figure 6) or 721-723 (Figure 7) for each LED driven by the main pixel (e.g., each LED 311-313 in Figure 3B) (e.g., current source driving devices such as transistors or combinations of resistors and transistors), and at least one storage device (e.g., memory device) of pixel logic (e.g., pixel control logic) that stores the desired or predetermined brightness levels of one or more LEDs and starts and stops the current at desired or predetermined times, causing the LEDs to respond to the stored brightness level values, according to the operating pulse width modulation (PWM) mode or other series of pulses with variable widths (where width refers to duration, corresponding to different brightness levels) or numbers. Two pixel logic and storage devices 611, 612 are shown in Figure 6. Only one pixel logic and storage device 711 is shown in Figure 7. In the comparative example, three sets of pixel logic and storage devices are required to drive three sub-pixels; therefore, pixel circuits 600 and 700 require fewer circuits to drive the same number of sub-pixels. While Figures 6 and 7 show pixel circuits corresponding to a main pixel with LEDs driven by current sources 621-623 or 721-723, in the implementation of the main pixel based on the LCoS architecture, current sources 621-623 or 721-723 can be replaced by voltage sources. Pixel circuit 700 occupies a smaller area compared to pixel circuit 600. Conversely, pixel circuit 600 offers a larger usable duty cycle and / or requires a lower peak current compared to pixel circuit 700.

[0033] In an exemplary aspect of this disclosure, although shown together in Figures 4-7, the storage device (e.g., memory device) and the pixel logic components and memory circuits 411 / 412, 511, 611 / 612 or 711 of the pixel logic may be electrically coupled separate components / devices / systems (e.g., as shown in Figures 8-10, the details of which will be described below).

[0034] In an exemplary aspect of this disclosure, the current sources 421-424, 521-524, 621-623, or 721-723 shown in Figures 4-7 serve as driving elements to drive the operation of LEDs 211-214 or 311-313 shown in Figures 2-3 when LEDs 211-214 or 311-313 convert current into light in a substantially linear manner. This contrasts with voltage driving sources that may produce undesirable variations in light output due to variations in, for example, the resistance of LEDs 211-214 or 311-314, their contact points, and the power supply network of the common cathode and driver power supply. In an exemplary aspect of this disclosure, when the display 120 is an LCoS display, voltage sources can be used to drive pixels / pixel elements / LEDs / LED pixels. The reference to "pixel" is a reference to pixels of any type of display, such as LCoS pixels or LED / LED pixels.

[0035] In one exemplary aspect of the present invention, the pixel memories shown in Figures 8-10 (e.g., pixel memories 811, 911, 913, 1011, and / or the memory components of the pixel logic and storage devices 411, 412, 511, 611, 612, or 711 shown in Figures 4-7) are loaded with data (e.g., image data, which may include video data), such as numerical values ​​(e.g., values ​​between 0 and 255, including 0-255, for pixels having an 8-bit color depth, or values ​​between 0 and 1023, including 0-1023, for pixels having a 10-bit color depth). In one exemplary aspect of the present invention, it will be understood by those skilled in the art that the bit depth can be changed, as can the numerical value representing the bit depth.

[0036] In one example aspect of the invention, as shown in Figures 8-10, data (e.g., image data) is loaded into pixel memories 811, 911, 913 and / or 1011 by placing data to be written (represented as "DATA" in the figures) on a data bus into the pixel memory of at least one sub-pixel, and by applying voltage or current pulses as ROW-WRITE inputs to pixel logic circuits 812, 912 and / or 1012, wherein "applying voltage or current pulses as ROW-WRITE inputs to pixel logic circuits 812, 912 and / or 1012" determines the timing of such data (e.g., DATA) being written into the pixel memory. In embodiments where the topmost and bottommost sub-pixels are driven separately (e.g., as shown in Figure 9), the pixel memory may carry image data DATA0 or DATA1 and be supplied with ROW-WRITE0 input or ROW-WRITE1 input in an appropriate manner. In an exemplary aspect according to this disclosure, the display (e.g., the display 120 of FIG1) includes an array of pixel elements (e.g., the main pixels 128 of FIG1), such as LEDs or mirrors, and the ROWWRITE input determines to write data to all the main pixels 128 in a column of the pixel array 126 simultaneously.

[0037] During the period when a particular color of the LED is in an active state (e.g., a frame or subframe), data (e.g., image data DATA[n:0, corresponding to a value, such as a color value) in pixel memory 811, 911, 913 and / or 10911 and represented by multiple bits of binary value is input to pixel logic circuits 812, 912 and / or 1012, wherein the period may be, for example, the entire duration of the video / image frame or a subset of the entire duration. In an exemplary aspect of this disclosure, one or more time-varying values ​​(e.g., time-varying digital values, such as multi-bit count values ​​or digital data patterns represented by voltage pulses) represented by reference numerals R_TVV and C_TVV data or R_TVV and C_TVV (where R represents a time-varying value of red and C represents a time-varying value of a combination of green (G) and blue (B)) are input to pixel logic circuits 812, 912 and / or 1012 (e.g., LED pixel control logic circuits), and logic functions (e.g., comparison, addition, OR, AND) combine the time-varying values ​​with image / video data (e.g., luminance data corresponding to color values) and generate outputs that control the LED / sub-pixel through drivers 820, 921, 922 and / or 1020 (e.g., current or voltage driving devices). For example, in an exemplary aspect according to this disclosure, a main clock is coupled to pixel logic circuitry, and during each cycle, for a period of time (e.g., a frame or subframe), the main clock increments a time-varying count value for a specific color (e.g., R_TVV and C_TVV data or R_TVV and C_TVV), and this count value is input to pixel logic circuitry 812, 912 and / or 1012, and is used to control when a current control device is activated by stored data (e.g., image / video data, such as brightness data) received by pixel logic circuitry 812, 912 and / or 1012 to achieve, for example, the desired or predetermined color, intensity or brightness of each LED / LED pixel. In one exemplary aspect of this disclosure, data in pixel memories 811, 911, 913, and / or 1011 is logically combined with input multi-bit count values ​​or digital data patterns, and logic functions (e.g., comparison, addition, OR, AND) determine, for each cycle of the main clock controlling the advancement or change of R_TVV and C_TVV input / data / values, that the current control driven by this logic is set high or low. For example, in one exemplary aspect of this disclosure, the main clock can advance the count from 0-256. The end result is a digital modulation of the LED output over time.In one embodiment of the present invention, as shown in FIG4, two pixel logic and storage devices 411 and 412 are used to control four LEDs of the main pixel. For example, one pixel logic and storage device 411 controls the green (G1 and G2) and blue LED / LED pixels, while the other pixel logic and storage device 412 controls the red LED / LED pixel. In addition to the count value, the enable inputs R_ena, G1_ena, G2_ena, and B_ena can be used to activate one of the LED drivers at a time, so that the control function is used only for one specific LED at a time. In another exemplary aspect of the present invention, as shown in FIG6, two pixel logic and storage devices 611 and 612 are used to control LEDs of three main pixels. For example, one pixel logic and storage device 611 controls the green and blue LED / LED pixels, while the other pixel logic and storage device 612 controls the red LED / LED pixel. In addition to the count value, the enable inputs R_ena, G_ena, and B_ena can be used to activate one of the LED drivers at a time, so that the control function is used only for one specific LED at a time.

[0038] In one example aspect of the invention, as shown in FIG5, all pixels / LEDs (e.g., three main pixels of different colors are represented by one or more LEDs or various colors) can be driven by a single pixel logic and storage device 511. The number of such pixel logic circuits / memory blocks required depends on the desired duty cycle.

[0039] Figures 8-10 illustrate exemplary pixel circuits of the present invention, including the logic operation of pixel logic circuits (i.e., the logic operation of pixels). In particular, Figure 8 illustrates an example where the pixel logic of Figure 4 is separate from the components of storage devices 411 and 412; Figure 9 illustrates an example where the pixel logic of Figure 5 is separate from the components of storage device 511; and Figure 10 illustrates an example where the pixel logic of Figure 6 is separate from the components of storage devices 611 and 612, or the pixel logic of Figure 7 is separate from the components of storage device 711.

[0040] In Figure 8, the pixel logic and storage device receives image data DATA[n:0] as input, a column write input ROW-WRITE indicating the timing of a selected column of the main pixel, a timing change value TVV[n:0], an operation input COMPUTE indicating the timing of the operation performed by the logic function 812 and the latch 813, and a sub-pixel-specific enable input (e.g., and an output voltage or current waveform to drive the pixel). The pixel driver 820 (e.g., the current source of Figures 4-7, or the voltage source in the LCoS implementation) is operablely connected to the pixel memory 811, the logic function 812, and the latch 813. The logic function 812 may store the desired or predetermined brightness levels of one or more sub-pixels and start and stop the current (or change the voltage) at desired or predetermined times, so that the sub-pixels are driven according to the operating pulse width modulation (PWM) mode or in response to other controls (e.g., stored in the pixel memory 811) of the stored brightness level value.

[0041] In Figure 9, different columns of sub-pixels within the main pixel can be driven separately. The pixel logic and storage device receives the top column image data DATA0[n:0] and bottom column image data DATA1[n:0] as input, the top column write input ROWWRITE0 and the bottom column write input ROWWRITE1 indicating the timing of the selection of the top and bottom columns of the sub-pixel, the timing change value TVV[n:0], the operation input COMPUTE indicating the timing of the operation performed by the logic function 912 and the latches 914 / 915, and the sub-pixel specific enable inputs R_ena, B_ena, G1_ena and G2_ena, which indicate the timing of the sub-pixel being driven; and outputs a voltage or current waveform to drive the pixel. Therefore, the first pixel driver 921 (e.g., a current source corresponding to the top column of sub-pixels within the main pixel of FIG4-7, or a voltage source in an LCoS implementation) is operatively connected to the first pixel memory 911, the logic function 912, and the first latch 914. The logic function 912 can output a voltage or current waveform representing the desired or predetermined brightness level of one or more sub-pixels in the top column, and start and stop the current (or change the voltage) at desired or predetermined times, so that the sub-pixels are driven according to the operating pulse width modulation (PWM) mode or in response to other controls (e.g., stored in the first pixel memory 911) of the stored brightness level value. The second pixel driver 922 (e.g., a current element corresponding to the bottom column of sub-pixels within the main pixel of FIG4-7, or a voltage source in an LCoS implementation) is operatively connected to the second pixel memory 913, the logic function 912, and the second latch 915. The logic function 912 can output voltage or current waveforms representing the desired or predetermined brightness level of one or more sub-pixels in the bottom column, and start and stop the current (or change the voltage) at desired or predetermined times, so that the sub-pixels are driven according to the PWM function or in response to other controls (e.g., stored in the second pixel memory 913) based on the value of the stored brightness level.

[0042] In one example aspect of the present invention, as shown in FIG9, the logic function elements / components / devices of the pixel logic circuit are shared between two adjacent main pixels and used in a time-division multiplexing manner, so that the operation of the logic function elements / components / devices of the pixel logic circuit alternates and cycles between each main pixel or LED pixel.

[0043] In Figure 10, the pixel logic and storage device receives image data DATA[n:0] as input, column write input ROW-WRITE indicating the timing of column selection of sub-pixels, timing change value TVV[n:0], operation input COMPUTE indicating the timing of logic function 1012 and latch 1013 performing operations, and sub-pixel specific enable inputs R_ena, B_ena and G_ena, which indicate the timing of sub-pixel driving; and outputs voltage or current waveforms to drive pixel driver 1020 (e.g., the current source of Figures 4-7, or the voltage source in LCoS implementation) which is operatively connected to pixel memory 1011, logic function 1012 and latch 1013. Logic function 1012 can store the desired or predetermined brightness levels of one or more sub-pixels and start and stop current (or change voltage) at desired or predetermined times, causing the sub-pixels to be driven according to the operating pulse width modulation (PWM) mode or in response to other controls (e.g., stored in pixel memory 1011) of the stored brightness level values. However, the example of Figure 10 is similar to that of Figure 8, but the main pixel includes only three sub-pixels (R, G, B) instead of four sub-pixels (R, G1, G2, B).

[0044] In one example aspect of the present invention, pixel memories 811, 911, 913 and / or 1011 are loaded by presenting data values ​​on an input data bus and by using ROW-WRITE (or ROW-WRITE0 / ROW-WRITE1) inputs (e.g., voltage inputs or voltage pulse inputs). The pixels / LEDs / LED pixels of the present invention emit or reflect light corresponding to the loaded data values ​​based on count values ​​(e.g., data or changing digital patterns such as linear count values) or one-hot encoded values ​​(e.g., data streams where only one value is always high), wherein the one-hot encoded values ​​are transmitted via a bus carrying time-varying voltage values ​​(e.g., the RGGB_TVV bus or TVV values) to the pixel logic circuit (e.g., the pixel logic circuit shown in Figures 4-7 and included in the pixel logic and memory blocks) logic function / pixel logic circuit / element / component / device (see Figures 8-10). The logic function / pixel logic circuit performs combinational logic (e.g., logic combinations such as AND, OR, XOR, or equivalent functions) on the stored data value and the input TTV value to produce a logical result, which is transmitted to a latch (which may be the last of a plurality of latches and is electrically coupled to the pixel driver). The latch outputs data to the pixel driver, and such data controls the pixel driver (e.g., which may be the last of a plurality of latches and is a current source or current source device in the case of an LED or micro-LED display, and a voltage source or voltage source device in the case of an LCoS or liquid crystal (LCD) display or micro-display). In an exemplary aspect according to this disclosure, the logic function / pixel logic circuit performs a comparison logic function. For example, in an exemplary aspect of the invention, when the display is a micro-LED display, the pixel driver may be a current source, or when the display is a micro-LCoS display, the pixel driver may be a voltage level offset. In one exemplary aspect of this disclosure, the latch of Figures 8-10 is periodically updated based on the activation of the COMPUTE input (e.g., whenever the value of TVV changes), wherein the activation of the COMPUTE input is established by logic in the backplane outside the pixel array. In another exemplary aspect of this disclosure, the COMPUTE input can also be used to control the flow / operation of the logic function elements / components / devices of the pixel control pixel logic circuit, and to reduce its power consumption by stopping and starting internal operations, so that energy is used only when needed.

[0045] Figures 11-14 illustrate the maximum duty cycle corresponding to the color of each LED of the main pixel (e.g., each color LED) compared to the frame length. For example, the maximum range of duty cycles, i.e., the length of a complete video frame, is shown in Figures 11-14. Figure 11 may correspond to the maximum duty cycle of a sub-pixel driven by the pixel driving circuits shown in Figures 4 and 8; Figure 12 may correspond to the maximum duty cycle of a sub-pixel driven by the pixel driving circuits shown in Figures 5 and 9; Figure 13 may correspond to the maximum duty cycle of a sub-pixel driven by the pixel driving circuits shown in Figures 6 and 10; and Figure 14 may correspond to the maximum duty cycle of a sub-pixel driven by the pixel driving circuits shown in Figures 7 and 10. However, it will be understood by those skilled in the art that the duty cycle / duration length can vary. Furthermore, the different frame lengths shown in Figures 11-14 are for illustrative purposes only, and in actual implementations, the length of each frame may be the same as or different from the length of another frame.

[0046] In the first example (shown in Figure 11), a larger duty cycle is used for the red LED due to its lower efficiency. For each possible maximum duty cycle, the on-time of each LED multiplied by its drive current determines the relative brightness of the LED / LED pixel. As shown in Figure 4, a memory (included in pixel logic and storage device 412) coupled to the circuitry driving the red LED (e.g., current source 424) is loaded with a value at the beginning of the full frame, while a memory (included in pixel logic and storage device 411) coupled to the circuitry driving the two green and one blue LEDs (e.g., current sources 422, 423, and 421, respectively) is loaded at the beginning of each color sub-frame, thus enabling circuit reuse (i.e., using pixel logic circuitry to drive color sub-frames individually, for example at different times, without needing to set separate pixel logic circuitry for each pixel or LED pixel). Therefore, as shown in Figure 11, the red LED is driven in parallel with the green and blue LEDs throughout the frame, with each green and blue LED driving one-third of the frame in a field-sequential manner. In other words, the sub-pixels are driven in a hybrid manner of full-time conduction and field-sequential operation.

[0047] In an example of the pixel circuit according to the invention, corresponding to the pixel circuit structure of FIG5, the image or video frame is divided into four cycles, as shown in FIG12, whereby each sub-pixel is independently activated, turned on, deactivated, or loaded according to the data (e.g., image or video data) during one of the cycles. Thus, as shown in FIG12, each LED is driven in a field-sequential manner for a quarter frame. This process involves four cycles and also reduces the number of circuits required to drive the pixels (e.g., micro-LED pixels or LCoS pixels) in exchange for operating at a faster clock rate and requiring higher current during the red cycle.

[0048] In the example of the pixel circuit according to the present invention, corresponding to the pixel circuit structure of FIG6, the red LED uses a longer duty cycle due to lower efficiency. For each possible maximum duty cycle, the amount of time each LED is on determines the relative brightness of the LED / LED pixel.

[0049] As shown in FIG. 6, a memory (included in pixel logic and storage device 612) coupled to the circuit driving the red LED (e.g., current source 623) is loaded with a value at the beginning of the entire frame, while a memory (included in pixel logic and storage device 611) coupled to the circuit for driving a green and a blue LED (e.g., current sources 622 and 621, respectively) is loaded at the beginning of each color sub-frame, thereby achieving circuit reuse (i.e., using pixel logic circuits to drive color sub-frames individually, for example at different times, without needing to set separate pixel logic circuits for each pixel or LED pixel). Therefore, as shown in FIG. 13, the red LED, green LED, and blue LED are driven in parallel throughout the frame, with the green LED and blue LED driving one-third of the frame in a field-sequential manner. In other words, the main pixels of the three sub-pixels are driven in a hybrid manner of full-time conduction and field-sequential operation.

[0050] In an example of the pixel circuit according to the invention, corresponding to the pixel circuit structure of FIG. 7, the image or video frame is divided into three cycles, as shown in FIG. 14, whereby each sub-pixel is independently activated, turned on, deactivated, or loaded according to the data (e.g., image or video data) during one of the cycles. Thus, as shown in FIG. 14, each LED is driven in a field-sequential manner for one-third of the frame. This process involves three cycles and also reduces the number of circuits required to drive the pixels (e.g., micro-LED pixels or LCoS pixels) in exchange for operating at a faster clock rate and requiring higher current during the red cycle.

[0051] Some examples of the pixel circuits according to the invention provide sub-pixel driving in a field-sequential manner or in a hybrid manner of full-time conduction and field-sequential operation. This allows for the reuse of pixel circuits (e.g., pixel driving or control circuits over time) and reduces the number of repetitions required for such circuits. As a result, the size of the main pixel is reduced, and therefore, the size of the entire display including such a main pixel is also reduced.

[0052] Although the above figures of Figures 11 and 13 illustrate an implementation in which the maximum duty cycle of the red subpixel is longer than that of other color subpixels, this disclosure is not limited thereto. In an exemplary aspect of this disclosure, one or other color subpixels may be driven for a longer time than the red subpixel. Furthermore, as mentioned above, this disclosure is not limited to using red, blue, and green for the main pixels, but may apply other colors or combinations of colors.

[0053] In each of Figures 11-14, the brightness of a subpixel is determined by its duty cycle relative to the maximum duty cycle within the frame. For example, a subpixel with a relative duty cycle of 50% will emit light for 50% of its assigned subframe and will be at medium brightness. To minimize power consumption signal transitions, single-pulse PWM can be implemented; that is, one pulse per color frame. This can be achieved by using a global N-bit counting bus and comparators, as described in more detail below with reference to Figure 15. Subpixels can be loaded with data values ​​(e.g., DAC codes or grayscale values), which trigger pulse transitions at points within the subframe when the DAC code equals the bus counter. For example, in a subpixel with an 8-bit color depth and a 50% duty cycle, the subpixel might be loaded with a DAC code of 128, which would cause the corresponding LED to turn on midway through the subframe (when the counter has a value of 128).

[0054] Silicon backplanes used in previous LCoS designs can be applied to micro LED displays. However, in some implementations, such backplanes may only be used to drive monochrome LEDs, and therefore multiple display panels are required to achieve full color. If such a backplane is applied to a multicolor LED process, either the resolution will be reduced or the size will have to be increased because three to four (3-4) pixel circuits are needed to drive three to four (3-4) LEDs that constitute the main pixel (i.e., the full-color pixel composed of sub-pixels of each color). In an exemplary aspect of the invention, by reducing the number of pixel circuits, complex pixel logic circuitry can be located below each pixel.

[0055] The pixel circuit according to the invention achieves a smaller display size without sacrificing power or speed. Unlike LCoS displays, the LED displays according to the invention, such as microLED displays, illuminate only the activated pixels, i.e., the "conductive" pixels (e.g., LEDs or microLEDs), instead of utilizing an external lighting source that emits light across the entire display (e.g., LCoS displays).

[0056] As described above, in one example of the logic function according to this disclosure, a comparator can be used to implement the PWM according to this disclosure. Digital comparator circuitry can occupy a significant area. The display size can be further reduced by time-division multiplexing the use of the digital comparator circuitry between adjacent pixels or groups of pixels (e.g., between multiple subpixels within a main pixel, between groups of subpixels within a main pixel, and / or between groups of main pixels). Timing can be synchronized with the global bus to evaluate each subpixel or pixel during a portion of the global counting cycle.

[0057] In one example aspect of the present invention, as shown in FIG15, the logic circuit includes a comparator shared among multiple sub-pixels and operating sequentially among sub-pixel rows within a main pixel. The logic circuit of FIG15 receives as input image data Data0 of the first row of sub-pixels within the main pixel, image data Data1 of the second row of sub-pixels within the main pixel, column selection input Row0 of the first column of sub-pixels within the main pixel, column selection input Row1 of the second column of sub-pixels within the main pixel, four sub-pixel memory selection inputs Pxl_selxy (where x represents the x position of the corresponding sub-pixel in the main pixel, y represents the y position of the corresponding sub-pixel in the main pixel, and both x and y are 0 at the top left sub-pixel), four sub-pixel latch selection outputs Pxl_gsetxy (where x represents the x position of the corresponding sub-pixel in the main pixel, y represents the y position of the corresponding sub-pixel in the main pixel, and both x and y are 0 at the top left sub-pixel), and a global timing counter G[7:0]. The logic circuit in Figure 15 outputs four pixel driving waveforms (e.g., time-varying voltage values) drvxy (where x represents the x position of the corresponding sub-pixel within the main pixel, y represents the y position of the corresponding sub-pixel within the main pixel, and both x and y are 0 at the top left sub-pixel).

[0058] The logic circuit in Figure 15 includes four sub-pixel memory circuits 1501-1504, two multiplexers 1511-1512, a logic function 1520 (which in some embodiments may be combinational logic circuits, such as a digital comparator circuit), and four sub-pixel latches 1531-1534. The logic circuit may also include a demultiplexer between the logic function 1520 and the four sub-pixel latches 1531-1534. In Figure 15, "subpixel (x,y)" refers to the (x,y) position of the subpixel within the main pixel, where (0,0) represents the subpixel at the top-left corner of the main pixel.

[0059] The components in FIG15 may correspond to the pixel driving and storage devices 411, 412, 511, 611, 612 and / or 711 shown in FIG4-7. For example, sub-pixel memory circuits 1501-1504 may correspond to pixel memories 811, 911, 913 and / or 1011 shown in FIG8-10; multiplexers 1511-1512 and logic function 1520 may correspond to logic functions 812, 912 and / or 1012 shown in FIG8-10; and sub-pixel latches 1531-1534 may correspond to latches 813, 914, 915 and / or 1013 shown in FIG8-10. Sub-pixel memory circuits 1501-1504 may each be implemented as an N-bit memory circuit, corresponding to the color depth of the sub-pixel. For example, the sub-pixel memory circuits 1501-1504 can be 8-bit SRAM circuits.

[0060] Figure 15 illustrates an example where four subpixels within a main pixel are arranged in a 2×2 array. Subpixel memories 1501 and 1502 (corresponding to the left row subpixels) are loaded by presenting the data value Data0 on the input data bus, and are loaded into memory according to Row0 or Row1 input, depending on the column of the input subpixel. Subpixel memories 1503 and 1504 (corresponding to the right row subpixels) are loaded by presenting the data value Data1 on the input data bus, and are loaded into memory according to Row0 or Row1 input, depending on the column of the input subpixel.

[0061] The outputs of subpixel memories 1501-1502 and 1503-1504 are multiplexed together by multiplexers 1511 and 1512, respectively, and output 8-bit data signals DATA[7:0] on a common bus based on pixel selection inputs Pxl_sel00, Pxl_sel10, Pxl_sel01, and Pxl_sel11. These signals are selected from the inputs of the corresponding subpixel memories 1501-1504. Logic function 1520 receives the data value DATA[7:0] and the 8-bit global count value G[7:0]. The output of logic function 1520 is toggled at the point when the data signal equals the global count value. This output is provided to subpixel latches 1531-1534. Next, subpixel latches 1531-1534 output the stored signal or value based on the operation of the corresponding output selection waveforms Pxl_gsel00, Pxl_gsel10, Pxl_gsel01, and Pxl_gsel11. The output of each subpixel latch is provided to the corresponding pixel driver drv00, drv10, drv01, or drv11 as appropriate.

[0062] The objects described herein can be implemented in digital electronic circuits, including the structural devices and equivalents thereof disclosed in this specification, or combinations thereof.

[0063] It should be understood that the disclosed subject matter is not limited in its application to the construction details and arrangement of components set forth in the following description or shown in the accompanying drawings. The disclosed subject matter can have other embodiments and can be implemented and performed in various ways. Furthermore, it should be understood that the wording and terminology used herein are for descriptive purposes and should not be considered limiting. Therefore, those skilled in the art will understand that the concepts on which this disclosure is based can readily serve as the basis for designing other structures, methods, and systems for achieving several purposes of the disclosed subject matter. Therefore, it is important that the patent scope be considered to include such equivalent constructions, provided they do not depart from the spirit and scope of the disclosed subject matter. Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it should be understood that this disclosure is made by way of example only, and many changes can be made to the implementation details of the disclosed subject matter without departing from the spirit and scope of the disclosed subject matter, which is limited only by the following patent scope. [Simplified Explanation of the Diagram]

[0007] The present disclosure is described herein with reference to various accompanying drawings, wherein similar reference numerals are suitably used to denote similar system components, and wherein: FIG1 illustrates examples of display systems according to various aspects of the present disclosure; FIGS. 2A to 3B respectively illustrate multicolor subpixels in main pixel systems according to various aspects of the present disclosure; FIGS. 4 to 6 respectively illustrate block diagrams of exemplary pixel circuits according to the present invention; FIGS. 7 to 10 respectively illustrate details of exemplary pixel circuits according to the present invention; FIGS. 11 to 14 respectively illustrate exemplary operating cycles of color elements according to the present invention; and FIG. 15 illustrates details of exemplary pixel circuits according to the present invention.

Claims

1. A display system comprising: a pixel logic circuit for controlling a plurality of pixels of a display by: receiving a main clock, including a time-varying waveform for each pixel of the pixels for each predetermined period of the main clock; and for each pixel of the pixels: applying combinational logic to a luminance data stored in a storage device and the time-varying waveform corresponding to the pixel; and outputting a result of the combinational logic as a start signal to a driving device corresponding to the pixel.

2. The display system of claim 1, wherein the combinational logic includes at least one of an AND function, an OR function, an XOR function, and an equivalent function applied to the luminance data and the time-varying waveform.

3. The display system as claimed in claim 1, wherein: The pixel logic circuit includes a combinational logic circuit that applies the combinational logic; and the combinational logic circuit is shared by a plurality of second pixels of the display.

4. The display system as claimed in claim 3, wherein the combinational logic circuit operates in a time-division multiplexing manner to alternately apply the combinational logic to the pixels and the second pixels.

5. The display system as claimed in claim 1, wherein the time-varying waveform contains a multi-bit count value incremented during each predetermined period of the main clock.

6. The display system as claimed in claim 5, wherein the combinational logic determines, based on a comparison between the brightness data and the multi-bit count value, that the activation signal is set high or low for each predetermined period.

7. The display system of claim 1, wherein the pixel logic circuitry comprises: a combinational logic circuitry for applying the combinational logic; the storage device comprising at least one pixel memory coupled to an input of the combinational logic circuitry to store the brightness data; and at least one pixel latch coupled to an output of the combinational logic circuitry to output the start signal.

8. The display system of claim 7, wherein the combinational logic circuitry includes a digital comparator circuitry that compares the brightness data from the at least one pixel memory with the time-varying waveform.

9. The display system as claimed in claim 1, wherein the activation signal controls the driving device to drive the corresponding pixel according to an operating pulse width modulation mode.

10. The display system according to any one of claims 1 to 9, wherein the driving device is a current driving device, and the display is a miniature light-emitting diode display, an organic light-emitting diode display, or a light-emitting diode display.

11. The display system according to any one of claims 1 to 9, wherein the driving device is a voltage driving device, and the display is a liquid crystal silicon-coated display or a liquid crystal display.

12. The display system as described in any one of claims 1 to 9, wherein: These pixels include four sub-pixels of a main pixel, the four sub-pixels including two green sub-pixels, one blue sub-pixel and one red sub-pixel; and the pixel logic circuit drives the red sub-pixel in the on state, while driving the two green sub-pixels and the blue sub-pixel according to a field sequence color sub-pixel driving process.

13. The display system as described in any one of claims 1 to 9, wherein: These pixels comprise four sub-pixels, including two green sub-pixels, one blue sub-pixel, and one red sub-pixel; and the pixel logic circuit drives the two green sub-pixels, the blue sub-pixel, and the red sub-pixel according to a field-sequence color sub-pixel driving process.

14. The display system as described in any one of claims 1 to 6, wherein: The pixel logic circuit includes a combinational logic circuit to apply the combinational logic; the storage device includes at least two pixel memories and at least two pixel latches, the at least two pixel memories being coupled to an input of the combinational logic circuit and the at least two pixel latches being coupled to an output of the combinational logic circuit. The combinational logic circuit applies the combinational logic to the output of a first pixel memory of the at least two pixel memories during a first portion of a frame period, and applies the combinational logic to the output of a second pixel memory of the at least two pixel memories during a second portion of the frame period, wherein the brightness data includes the output of the first pixel memory and the output of the second pixel memory.

Images