Method of making micro device tiled display and tiled display for optoelectronic system

Abstract

This invention discloses a structure and method for manufacturing a tile-based display for optoelectronic systems.

Description

Technical Field

[0001] This invention relates to a tile-based display device, and more specifically, to the seamless integration of tiles to a backplane for forming a tile-based display device. Prior Technology

[0002] Previously, the tile-based light-emitting diode (LED) method used mechanics to organize and hold the tiles together. These methods were adjustable, and therefore the tiles could be moved around and / or disassembled and put back together in various configurations. Summary of the Invention

[0003] This invention relates to a method for manufacturing a tile-based display. The method may include: providing a tile substrate having a plurality of tiles; providing a backplate layer; covering a first surface of either the backplate or the tile substrate with an adhesive; aligning and releasing the tiles onto the backplate; curing the adhesive; and filling areas or trenches between the plurality of tiles and areas or trenches between microdevices with a filler layer, wherein the filler layer extends to any side of the tiles depending on the viewing direction.

[0004] The present invention also relates to a tile-based display, which may include: one or more microdevices transferred to a substrate; and a passthrough pad formed on the top surface of the substrate to transfer a backplate to the top surface.

[0005] The present invention also relates to a tile-based display comprising: one or more microdevices transferred to a substrate; a patterned planarization layer for providing openings for connecting the microdevices; pad electrodes deposited and patterned on or above the microdevices; and a common pad formed on the top surface of the pad electrodes. Simple Explanation of the Diagram

[0006] The aforementioned advantages of the present invention will become apparent after reading the following embodiments and referring to the drawings.

[0007] Figure 1 shows an example of several transferred patterns aligned on a substrate.

[0008] Figure 2 illustrates an example of a tile array using optical illusion technology according to an embodiment of the present invention.

[0009] Figure 3A shows an embodiment in which the backplate contact pad is aligned with the contact pad on the substrate.

[0010] Figure 3B shows an electrode structure on a substrate that has signals for controlling an array of microdevices.

[0011] Figure 3C shows another structure in which signals are transmitted between blocks via some connectors on the substrate.

[0012] Figure 3D shows the structure formed after the blocks are transferred to the substrate and the connectors between the blocks are formed after the transfer.

[0013] Figure 3E shows a cross-sectional view of a block structure with a top metallization.

[0014] Figure 3F shows another illustrative example of a block structure with a top metallization.

[0015] Figure 3G shows another exemplary embodiment of the tile structure formed after a portion of the backplate is bonded to the substrate.

[0016] Figure 4 shows a flowchart illustrating the method of the present invention.

[0017] Figure 5A is a cross-sectional view of a microdevice array on a substrate according to an embodiment of the present invention.

[0018] Figure 5B is a cross-sectional view of a microdevice array on a substrate having a planarization layer according to an embodiment of the present invention.

[0019] Figure 5C is a cross-sectional view of a microdevice array including a separation layer and bonded to a backplane according to an embodiment of the present invention.

[0020] Figure 5D is a cross-sectional view of a microdevice array including an adhesive layer and bonded to a backplate according to one embodiment of the present invention.

[0021] Figure 5E is a cross-sectional view of an array of microdevices including a separation layer bonded to a backplane according to an embodiment of the present invention.

[0022] Figure 5F illustrates another bonding method for some of the pads facing the substrate in the structures of Figures 5B and 5C.

[0023] Figure 6A shows an alternative embodiment of a microdevice array on a substrate according to the present invention.

[0024] Figure 6B shows an alternative embodiment of a microdevice array on a substrate having electrodes present as appropriate, according to the present invention.

[0025] Figure 6C illustrates an alternative structure according to another embodiment of the present invention, including a separation layer, electrodes present as appropriate, and a microdevice array bonded to a backplane.

[0026] Figure 6D illustrates an alternative embodiment of an array of microdevices on a tile including a release layer and an adhesive layer.

[0027] Figure 6E shows another embodiment of a microdevice array on a tile having a separation layer and an adhesive layer.

[0028] Figure 7A illustrates an embodiment of a microdevice array processed in a front plate having metallization, pads, and electrodes.

[0029] Figure 7B illustrates an embodiment of a microdevice array processed in a pre-metallized plate.

[0030] Figure 7C shows a top view of an exemplary metallization and gasket used for bonding.

[0031] Figure 7D illustrates an embodiment of the front panel of the microdevice array integrated into the back panel.

[0032] Figure 8A illustrates an embodiment in which the planarization layer is etched back to expose the top of the pixel driving circuitry.

[0033] Figure 8B illustrates an embodiment with a bank layer deposited above the pixel driving circuitry.

[0034] While the invention allows for various modifications and alternatives, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the invention is not intended to be limited to the specific forms disclosed. Rather, the invention should cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the invention as defined by the appended claims. Implementation

[0035] In this embodiment, the terms "device" and "microdevice" are used interchangeably. However, it will be clear to those skilled in the art that the embodiments described herein are independent of device size.

[0036] This invention attempts to construct a more permanent and non-adjustable tile integration with a thinner form factor for consumer use. Similarly, while prior art was ideal for very large displays where tile seamlessness was less important (i.e., since the human eye does not view the screen at close range), this invention addresses a more seamless integration for smaller displays that are closer to the human eye and can therefore be more readily inferred to be imperfect.

[0037] In large displays, a single damaged or defective microdevice can render the entire display unusable. However, when tiled LEDs are integrated into a display, each tile can contain a controlled number of LEDs that can be tested to achieve satisfactory performance (i.e., to identify defective microdevices). Once its performance is deemed acceptable, it can then be transferred to the system substrate as a single tile, aligned with other similarly tested and acceptable tiles. If the LEDs on a tile are damaged, defective, or broken, the tile can be omitted from the transfer process or adjusted after the transfer process to the system substrate, thus reducing the likelihood of the entire display becoming unusable.

[0038] In one embodiment, the display tile may include one or more microdevices mounted on a surface of the display tile. The array of microdevices may include microLEDs, organic LEDs, sensors, solid-state devices, integrated circuits, microelectromechanical systems (MEMS), and / or other electronic components.

[0039] In another embodiment, a transfer substrate may be provided. The transfer substrate may be, but is not limited to, a printed circuit board (PCB), a thin-film transistor (TFT) backplane, an integrated circuit substrate, or, in one case, a component of a display such as an LED optical microdevice, such as a drive circuit system backplane.

[0040] In some embodiments, microdevices may be tested for defects and fixed, adjusted, or removed before being transferred to tiles to increase uniformity and limit defects in the display.

[0041] In an alternative embodiment, the microdevice may be tested for defects and fixed or adjusted after being transferred to the tile to increase uniformity and limit defects in the display.

[0042] In some embodiments, a buffer layer may be disposed on the top surface of the tile substrate. In one case, the buffer layer may be an adhesive layer. Alternatively, the buffer layer may be a release layer or a tile transferable substrate, which may be separable from the main substrate on which the buffer layer is formed.

[0043] In one embodiment, one or more microdevices may be formed or transferred onto the buffer layer.

[0044] In another embodiment, one or more planarization layers may be formed on or above the microdevice. The planarization layers may be made of an organic insulating material and patterned to expose the top of the microdevice.

[0045] In one embodiment, a separate backsheet can be fabricated. An adhesive layer can be deposited to cover the first surface of the backsheet.

[0046] In another embodiment, one or more tiles can be aligned to a backplate. Pressure can be applied to align the tiles. In one case, temperature, light, or microwave exposure can be used to cure the adhesive layer. In another case, additional residual adhesive can be cleaned after curing.

[0047] In another embodiment, a separation layer may be provided to optically isolate the microdevice from the backplane. The separation layer may be patterned and may be one of a reflective, opaque, or black matrix layer.

[0048] In one embodiment, the seamless microdevice tile array comprises aligned microdevice tiles filled with a black matrix to reduce external optical coupling.

[0049] In variations of the above embodiments, this seamless array may include trenches filled with a black matrix to reduce external optical coupling. In one case, these trenches may be filled with a reflective material. In another case, the reflective material may be patterned before or after array assembly. The trench filler may be opaque.

[0050] The following describes in detail various embodiments of the structure and method of the present invention.

[0051] Any area between pixels or tiles (i.e., when pixels or tiles are not perfectly aligned) may be noticeable to the observer. Therefore, the present invention further aims to present seamless tile arrays using additional structures such as reflective layers, fillers, black matrix and / or other layers to improve the external coupling of the generated LED light (e.g., covering any imperfections and open areas that are detectable by the human eye).

[0052] Figure 1 shows an example of several transferred patterns 102 seamlessly aligned on substrate 104.

[0053] Figure 2 shows two aligned patches 202 and 204, which may be referred to as patch 1 and patch 2, respectively. The area / space 206 between adjacent patches 202 and 204 may be filled with a filler layer. In one case, the space 206 between the patches may be filled with a black matrix. The black matrix may be made of a resin such as polyimide or polyacrylic acid, in which particles of a black pigment such as carbon black are dispersed. The thickness of the black matrix may be patterned or etched. In another case, the filler layer may be reflective or opaque and may be patterned.

[0054] In the case of a transparent display, area 206 may be filled with a transparent material. In this case, the material may be similar to the material used to create the tiles.

[0055] In one case, additional grooves 210 with the same width as the space between two tiles (202, 204) or the distance between microdevices at the edges of the two tiles can be created between a plurality of pixels (e.g., 208) (in one instance, this may include more than one pixel). These grooves 210 may also be slotted and filled with a filler layer. In one case, the filler layer may be a black matrix or another transparent material, such as a black matrix or transparent material used to fill the gaps between tiles to further reduce tile visibility. If this filler layer is reflective, it may be patterned. These grooves may have a set pattern, or the pattern may be extracted after the tiles are generated. If the microdevices are on the bottom side of the tiles, the grooves may be implemented closer to the surface of the microdevices.

[0056] In another case, a second layer may be deposited on top of the tile, similar to the material used to fill the tile space 206. In this case, especially if the material is opaque, openings may exist in the area 206 of the filler layer.

[0057] In one embodiment, a connector may be present between the pattern and the substrate (or backplate) 310.

[0058] Figure 3A illustrates an embodiment where the backplane contact pads are aligned with the contact pads on the tile substrate. Contact pads 304 for the microdevice array on the tile substrate 302 can be aligned with and attached to contact pads 308 on the surface of the backplane 310 to form a tile-based display. A filler layer may be present between the pads and in other spaces between the substrate 302 and the backplane 310. This filler may be an adhesive.

[0059] Figure 3B illustrates the electrode structure on a substrate 310 having signals for controlling an array of microdevices. These signals extend in a vertical and horizontal direction (or either both). Horizontal or vertical pads (320, 322) are present to connect to the signal lines (e.g., vertical signal line 324 and horizontal signal line 326). These pads are bonded to corresponding areas on block 302. The signal lines (324, 326) may carry data, addresses, operating voltages, and / or enable signals. In one case, the pads are not formed directly on the lines to avoid damage to the lines due to pressure applied during the bonding process. In another case, multiple pads may exist across the block for each signal to improve bonding yield.

[0060] Figure 3C illustrates another structure in which signals are transmitted between tiles 302 via connectors on substrate 310. Here, a signal from one pad (horizontal 320-2 or vertical 322-2) is transmitted through the tile, extends through the tile, and then reaches another pad on substrate 310. This signal is then transmitted to another tile via traces coupled to these pads and the pads themselves. This structure is more advantageous for transparent displays because there is less metallization on the substrate to block or reflect light.

[0061] Figure 3D illustrates the structure formed after the transfer of tiles to substrate 310 and the connection between tiles. Here, extended signal lines or bridging lines can be used to transmit signals between or through tiles 302. Similarly, traces or bridging elements are deposited, printed, or electroplated. Pads 342 are present on the top of the tiles (i.e., the surface away from substrate 310). A dielectric layer 344 may be present on the top surface of the tiles that need to be opened to expose the pads. The traces and bridging elements may be metals, conductive oxides, conductive polymers, etc.

[0062] Figure 3E shows a cross-sectional view of a tile structure with top metallization (i.e., forming traces and / or bridging elements). Here, the areas between the tiles are filled with filler 330 (i.e., tile filler). The same filler can also be used to cover the top surface of the tiles. The tiles are bonded to the substrate 320 via an adhesive layer 328. Multiple buffer layers 324 may be present. The buffer layer structure 324 may be reflective to the top emitting structure, or it may be transparent to the bottom emitting device. The buffer layer may be formed on the substrate 320 or the tile structure. Metallization 336 for traces and bridging elements is formed between the tiles above the tile filler layer 330. Matching filler structures 326 formed between a plurality of microdevices 334 may be present to reduce tile space effects. The matching filler 326 may extend to either side of the tile depending on the viewing orientation. In one case, dummy traces may be placed on top of the tiles to hide their appearance. In another case, the backplane 332 can be integrated with a plurality of microdevices 334.

[0063] Figure 3F illustrates another illustrative example of a tile structure with top metallization. Here, a planarization layer / dielectric layer 342 is deposited on top of the tile after or before bonding to the substrate 320. The dielectric layer may be the same material as the filler layer. Pads on the tile are exposed before traces or bridging are formed. Openings / vias 340 can be created through the dielectric layer 342 to provide metallization 336-2 for traces and bridging formed between tiles above the tile filler layer 330. A pattern 338 matching the filler structure 326 can be applied to the tile to further reduce any tile effects.

[0064] Figure 3G illustrates another exemplary embodiment of the tile structure formed after a portion of the backplane 340 is bonded to the substrate 320. Here, a planarization, dielectric, or protective layer 342 may be formed on top of the tiles, and the backplane 340 is formed on top of that layer 342. The backplane may be a thin-film transistor (TFT), a complementary metal-oxide-semiconductor (CMOS) wafer, or other type.

[0065] Figure 4 illustrates a process flow diagram 4000 for potential tile integration. In step 4001, an adhesive material is applied to the first surface of the backing plate. The adhesive may have specific properties such as optical transparency or thermal conductivity. A pad may be exposed after the adhesive layer is deposited on the surface of the backing plate. The adhesive material may also be applied to the surface of the tiles. Next, in step 4002, the tiles are aligned with the first surface of the backing plate. In step 4003, pressure is applied to release the tiles from the first surface of the backing plate. Next, the adhesive may be cured in step 4004 (curing the adhesive). Before taking step 4004, residual adhesive may be cleaned in step 4003a, and a black matrix may be applied between the tiles in step 4003b. Steps 4003a and 4003b may be repeated or skipped entirely after step 4004. These steps may also be repeated multiple times as needed after step 4004 (repeat cycle 4008). Applying a black matrix in step 4003b limits the chance of light escaping between tiles and also masks any imperfections from tile cutting. Post-processing can be applied to the tiles or substrate during the final step.

[0066] Referring to FIG. 5A, one embodiment of the present invention includes a substrate 502. The substrate may be glass, sapphire, or some other material. A buffer layer 504 may be disposed on the substrate. In one case, the buffer layer may be a release layer or a pattern transferable substrate, which may be separable from the main substrate, and the buffer layer is formed on top of the main substrate. One or more microdevices 506 may be formed or transferred on the buffer layer 504. In one case, a pass-through pad 550 may be formed on the surface of the substrate 502 or the buffer layer 504 to transmit backplane or other layer signals to the top. In one case, the structure in FIG. 5A may be bonded to another substrate from the substrate 502 side, and the active surface of the device may be away from the substrate 502. In this case, a separation film closer to the microdevice layer 506 may be formed to create the illusion of a depth hidden from the substrate 502. Here, the area between the pattern substrates 506 may be filled with a material similar to the isolation layer, or the top surface may be the same material as the isolation layer. Therefore, the active depth of the structure will be from the isolation layer toward the surface. In this case, the isolation layer may be formed on the surface of the substrate 502 before the microdevice 506 is formed on the surface of the substrate 502. Here, the space between the microdevices and the space between the substrates after the isolation layer may be filled with a filler layer.

[0067] Referring to Figure 5B, one or more planarization layers 508 may be formed on or above the microdevice 506. The planarization layer 508 may be made of an organic insulating material and patterned to expose the top 508-2 of the microdevice. The planarization layer 508 may also be etched back to reduce its thickness or expose the surface of the microdevice. Additionally, the top of the backplane feed pad 550 may be exposed 552. A backplane 510 may be formed on the planarization layer 508. A passivation, planarization, or protective layer 508-3 may be formed on layer 508. A metal layer may be a portion of layer 508-3. The backplane is coupled to the microdevice and feed pad via exposed areas 508-2 and 552. The planarization layer rests on top of the microdevice 506, which is formed on a buffer layer 504 and rests on the substrate 502.

[0068] Figure 5C is a cross-sectional view of a microdevice array including a separation layer according to an embodiment of the present invention, wherein a backplate is formed on the top surface of the microdevice layer (the surface away from the substrate 502). A separation layer 510 may be formed between the microdevice 506 and the backplate 512. The separation layer 510 optically isolates the microdevice 506 from the backplate layer 512. This separation layer 510 may be, but is not limited to, a reflective, opaque, black matrix, or patterned layer. This separation layer 510 helps reduce the effect of the backplate on the microdevice 506. The layer 510 may be added after the microdevice 506 (i.e., on top), as shown in Figure 5C, or the layer 510 may be added to the structure before the microdevice 506.

[0069] The structures in Figures 5C and 5B can be transferred to another substrate or backplane 514 to form larger structures or provide other functionalities such as mechanical flexibility, as shown in Figures 5D and 5E. Here, the top surface of the structure in Figure 5C or 5B is bonded to the top surface of substrate 514. An adhesive can be applied to the top surface of the substrate or structure in Figures 5B and 5C. Substrate 514 may have pixel circuitry or metallization to further control the microdevices in the structures of Figures 5B and 5C.

[0070] Figure 5F illustrates another method of bonding some pads 512-2 from the structures of Figures 5B and 5C to pads 516-2 on the substrate 514. Here, these pads transmit signals from the substrate to the structure. These signals can control blocks (i.e., if a tiled structure is used) or control components in the structure. Here, pads 512-2 and 516-2 can be formed on dielectric or buffer layers 512 or 516.

[0071] Figure 6A shows an alternative embodiment of the invention including substrate 602. The substrate may be glass, sapphire, or some other material. Substrate layer 610 may be disposed on the substrate. The backplane layer may include a buffer layer, a microdevice circuitry for controlling or driving the microdevice, and a metallization layer. One or more microdevices 606 may be formed or transferred onto the backplane 604. In one example, the microdevice driver circuitry is formed on the substrate layer / microdevice pattern 610 before being attached to the backplane layer.

[0072] Referring to Figure 6B, one or more planarization layers 608 are formed on or above the microdevice 606. The planarization layer 608 may be made of an organic insulating material and patterned to expose the top of the microdevice. In another example, the planarization layer may be etched to expose the top of the microdevice. A common electrode 616, if present, may be disposed on top of the planarization layers(s) 608. The common electrode 616 may be patterned. Multiple other layers may be formed on top of the planarization layers, such as color converters, color filters, etc.

[0073] Figure 6C shows another embodiment of the invention in which a separation layer 612 is added between the microdevice layer and the backplane layer 610. A buffer layer 612-2 may be formed on top of the separation layer 612. The separation layer 612 may optically or electrically isolate the microdevice 606 from the backplane layer 610. This layer may be, but is not limited to, a reflective, opaque, black matrix, or patterned layer.

[0074] The structures in Figures 6B and 6C can be transferred to another substrate or backplane 614, as shown in Figures 6D and 6E. An adhesive layer 620 can be applied to the top surface of the substrate 614 and the structures in Figures 6B or 6C.

[0075] Figure 7A illustrates another embodiment of microdevice transfer onto substrate 702. A buffer layer 716 may be formed on the substrate 702 prior to the transfer of the microdevice. Microdevice 704 is planarized, and planarization layer 706 is patterned to open to the connectors of microdevice 704. In another embodiment, planarization layer 706 is etched back to expose the top of microdevice 704. Here, electrodes are deposited and patterned to form pad electrodes 708-1 for the microdevice. Pads may be formed on top of the electrodes. Another electrode 710-1 (i.e., a metallization electrode) may be formed to generate a common signal connected to more than one microdevice. Dielectric layer 712 may be formed to cover the common electrode and may cover portions of the pads (or pad electrodes 708-1). The portions of the common signal may be open to generate a common pad electrode. A common pad 714 may be formed on top of the common pad electrode 708-1. In one case, the buffer layer 716 may be a release layer or a pattern transferable substrate that can be separated from the main substrate, with the buffer layer formed on top of the main substrate.

[0076] Figure 7B illustrates another embodiment where the common signal is formed on a different layer compared to the pad electrode. Here, a dielectric layer 712 may be formed after microdevice transfer, having an opening providing proximity to the microdevice contacts. A common signal 710-2 is formed to connect to a pair of microdevices 704. A planarization layer 706 is formed, with openings formed in the planarization layer to expose the microdevice connectors and the common pad electrode 708-2. The microdevice pad electrode 708-2 is formed on top of the planarization layer, and a microdevice pad 714 may be formed on top of the microdevice pad electrode. The dielectric layer 712 may be formed to cover portions of the microdevice pad electrode 708 or the microdevice pad.

[0077] In another case, common signals can be formed in columns (or rows). A planarization or dielectric layer is formed, and a second common signal is formed to connect to other microdevice contacts arranged in rows (or columns). In this case, there will be column common pads and row common pads.

[0078] Figure 7C shows an exemplary top view of a microdevice with microdevice pads 726 and common pads 728 formed on the top of substrate 702. Common signal / connectors 724 may be formed in columns (or rows). A planarization or dielectric layer is formed, and a second common signal 720 is formed to connect other microdevice contacts arranged in rows (or columns). In this case, there will be column common pads and row common pads.

[0079] Figure 7D illustrates an embodiment of the front panel before the microdevice array is integrated with the backplane. Microdevices are transferred onto substrate 702. A buffer layer 716 may be formed on the substrate 702 before the microdevices are transferred to it. Microdevice 704 is planarized, and a planarization layer 706 is patterned to open to the connectors of microdevice 704. In another embodiment, the planarization layer 706 is etched back to expose the top of microdevice 704. A common pad 714 may be formed on top of common pad electrodes 708. Backplane 742 may be integrated into a backplane substrate 740 having pads 744. The backplane and microdevice substrate may be bonded together via the backplane pads 744 and the common pads 714 of the substrate.

[0080] Figure 8A illustrates an embodiment where the planarization layer is etched back or patterned to expose the top of the pixel driving circuitry. Here, a substrate 802 is provided. A buffer layer 804 may be formed on the substrate 802. A pixel driving circuitry 808 may be disposed on top of the buffer layer 804 to control or drive a microdevice. The pixel driving circuitry is planarized, and the planarization layer 806 is patterned to open to connections to the pixel driving circuitry. In another embodiment, the planarization layer 806 is etched back to expose the top of the pixel driving circuitry 808. A plurality of pads 812 may be formed on top of the planarization layer 806. A dielectric layer 810 may be formed to cover a portion of the pads (or pad electrodes 708). In another embodiment, the planarization layer may be simply a dielectric layer.

[0081] Figure 8B illustrates an embodiment with a row of layers, which is a dielectric layer deposited above the pixel driving circuitry. Here, a substrate 802 is provided. A buffer layer 804 may be formed on the substrate 802. A pixel driving circuitry 808 may be disposed on top of the buffer layer 804 to control or drive microdevices. The row of layers may be configured and patterned to open to connections to the pixel driving circuitry. A plurality of pads 812 may be formed on top of the row of layers through openings. The pads 812 may be formed on the dielectric or buffer layer 814.

[0082] In the above embodiments, the buffer layer 804 may be a release layer or a pattern transferable substrate, which can be separated from the main substrate on which the buffer layer is formed.

[0083] According to one embodiment, a method for manufacturing a tile-based display may be provided. The method may include: providing a tile substrate having a plurality of tiles; providing a backplate layer; covering a first surface of either the backplate or the tile substrate with an adhesive; aligning and releasing the tiles onto the backplate; and curing the adhesive.

[0084] According to another embodiment, the method may further include providing a buffer layer on the top surface of the tile substrate or the backing layer. The buffer layer may be reflective or transparent. The area between the plurality of tiles and the microdevice is filled with a filler layer, wherein the filler layer extends to either side of the tile depending on the viewing direction.

[0085] According to some embodiments, metallization for traces and bridging components is formed between these blocks above the filler layer. The filler layer is a black matrix or a transparent material.

[0086] According to another embodiment, the method may further include: depositing a dielectric layer on the top surface of the tiles; providing openings through the dielectric layer to provide the metallization or traces and bridging elements formed between the tiles; aligning the tiles to the backplane, including aligning contact pads of the tile substrate to contact pads on the surface of the backplane. The contact pads of the tile substrate are connected to signal lines to transmit signals between or via the tiles.

[0087] According to some embodiments, releasing the tiles onto the backplate includes applying pressure to the tiles to release them onto the surface of the backplate.

[0088] According to one embodiment, the microdevice driver circuitry is formed on the microdevice tile before being attached to the backplane substrate.

[0089] According to another embodiment, a tile-based display may be provided. The tile-based display may include: one or more microdevices transferred to a substrate; and a delivery pad formed on a top surface of the substrate to deliver a backplate to the top surface.

[0090] According to another embodiment, the tile-based display may further include: a planarization layer formed and patterned to expose the top surface of the one or more microdevices; a protective layer formed on the planarization layer; and a separation layer formed between the microdevices and the backplate. The separation layer is one of a reflective, opaque, black matrix, or patterned layer.

[0091] According to another embodiment, a tile-based display may be provided. The tile-based display includes: one or more microdevices transferred to a substrate; a patterned planarization layer for providing openings for connecting the microdevices; pad electrodes deposited and patterned on or above the microdevices; and a common pad formed on the top surface of the pad electrodes.

[0092] According to some embodiments, the tile display may further include: a metallization electrode formed to generate a common signal; and a dielectric layer covering a portion of the pad electrode and the common pad.

[0093] The present invention provides the following implementation schemes: [Solution 1] A method for manufacturing a microdevice tile display, comprising: Provide a tile substrate having a plurality of tiles; Provide a backsheet layer; The first surface of either the backing layer or the pattern substrate is covered with an adhesive; Align and release these blocks onto the backplate; Curing the adhesive; and The areas or grooves between the plurality of blocks and the areas or grooves between microdevices are filled with a filler layer, wherein the filler layer extends to either side of the block depending on the view orientation. [Solution 2] As in Solution 1, it further includes providing a buffer layer on the top surface of the pattern substrate or the backing layer. [Solution 3] The method of Solution 1, wherein the buffer layer is reflective or transparent. [Solution 4] The method of Solution 1, wherein the regions or grooves between the blocks and the regions or grooves between the microdevices have the same width. [Solution 5] The method of Solution 4, wherein the regions or grooves between the blocks and the regions or grooves between the microdevices are slotted. [Solution 6] The method of Solution 5, wherein the filler layer is reflective and is patterned before or after the tile display is assembled. [Solution 7] The method of Solution 6, wherein the grooves have a set pattern, or the pattern can be extracted after the block is generated. [Solution 8] As in Solution 4, wherein when the microdevices are on the bottom side of the blocks, the grooves are applied closer to the surface of the microdevices. [Solution 9] The method of Solution 4, wherein the grooves are filled with an opaque filler. [Solution 10] As in Solution 1, the metallization for the traces and bridging elements is formed between the blocks above the filler layer. [Solution 11] The method of Solution 1, wherein the filler layer is a black matrix or transparent material used to reduce external light coupling. [Solution 12] The method of Solution 1, wherein the filler layer is a black matrix or transparent material used to reduce the visibility of the tile. [Solution 13] As in Solution 1, it further includes depositing a dielectric layer on the top surface of the tiles. [Solution 14] The method of Solution 1 further includes providing an opening through the dielectric layer to provide the metallization or the traces and the bridging formed between the tiles. [Solution 15] The method of Solution 1, wherein aligning the tiles to the back plate includes aligning the contact pads of the tile substrate to the surface of the back plate. [Solution 16] The method of Solution 15, wherein the contact pads of the tile substrate are connected to signal lines to transmit signals between or through the tiles. [Solution 17] The method of Solution 1, wherein releasing the blocks to the backplate comprises applying pressure to the blocks to release them onto the surface of the backplate. [Solution 18] As in Solution 1, wherein the microdevice driver circuitry is formed on the microdevice block before being attached to the backplane substrate. [Solution 19] A tile-based display, comprising: One or more microdevices, which are transferred to a substrate; and A pass-through pad is formed on the top surface of the substrate to pass the backsheet to the top surface. [Solution 20] A tile-based display as described in Solution 19 further includes a planarization layer that is formed and patterned to expose the top surface of the one or more microdevices. [Solution 21] As in Solution 19, the tile-type display further includes a protective layer formed on the planarization layer. [Solution 22] As in Solution 19, the tile-type display further includes a separation layer formed between the microdevices and the backplate. [Solution 23] A tile-based display as in Solution 19, wherein the separation layer is one of a reflective, opaque, black matrix, or patterned layer. [Solution 24] A tile-based display, comprising: One or more microdevices are transferred to a substrate; A patterned planarization layer is used to provide openings for connecting these microdevices; Pad electrodes, which are deposited and patterned on or above the microdevices; and A common liner is formed on the top surface of the liner electrode. [Solution 25] A tile-type display as in Solution 24, which further includes metallization electrodes formed to generate a common signal. [Solution 26] As in Solution 24, the tile-type display further includes a dielectric layer that covers the pad electrode and a portion of the common pad.

[0094] The foregoing description of one or more embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. In view of the foregoing teachings, many modifications and variations are possible. It is intended that the scope of the invention not be limited to these embodiments, but rather to the claims appended herein.

[0095] 102: Piece 104:Substrate 202: Plot 204: Piece 206: Area / Space 208 pixels 210: Trench 302:Tile substrate 304: Contact gasket 308: Contact gasket 310:Substrate / Backplane 320: Horizontal pad / substrate 320-2: Horizontal gasket 322: Vertical padding 322-2: Vertical padding 324: Vertical signal line / buffer layer 326: Horizontal signal line / matching filler structure 328: Adhesive layer 330: Filler / Block Filler Layer 332: Backplate 334: Microdevices 336: Metallic compounds 336-2: Metallide 338: Pattern 340: Opening / Through Hole / Backplate 342: Pad / Planarization Layer / Dielectric Layer / Protective Layer 344: Dielectric layer 502:Substrate 504: Buffer layer 506: Microdevice 508: Planarization layer 508-2: Top / Exposed Area 508-3: Protective layer 510: Backplate 512: Backplate / Dielectric Layer 512-2: Padding 514:Substrate 516: Buffer layer 516-2: Padding 550: Passing Pad 552: Exposed Area 602:Substrate 606: Microdevice 608: Planarization layer 610: Backplane Layer / Substrate Layer / Microdevice Diagram 612: Separation layer 612-2: Buffer layer 614:Substrate / Backplane 616: Common Electrode 620: Adhesive layer 702:Substrate 704: Microdevice 706: Planarization layer 708: Pad Electrode 708-1: Pad Electrode 708-2: Pad Electrode 710-1: Another electrode 710-2: Common Signal 712: Dielectric layer 714: Padding 716: Buffer layer 720: Second Common Signal 724: Common Signal / Connector 726: Microdevice Pad 728: Common Pad 740:Backplane substrate 742: Backplate 744: Backplate Pad 802:Substrate 804: Buffer layer 806: Planarization layer 808: Pixel driver circuit 810: Dielectric layer 812: Padding 814: Buffer layer 4000: Process Flow Chart 4001: Steps 4002: Steps 4003: Steps 4003a: Steps 4003b: Steps 4004: Steps 4008: Repeated loop

Claims

1. A method of manufacturing a microdevice tile display, comprising: providing a tile substrate having a plurality of tiles, wherein each of the plurality of tiles includes one or more microdevices on its surface; providing a backplate, wherein a portion of the backplate is formed after the plurality of tiles are bonded to the tile substrate; covering a first surface of the backplate or the tile substrate with an adhesive; aligning and releasing the tiles to the backplate; curing the adhesive; and filling areas or trenches between the plurality of tiles and areas or trenches between microdevices with a filler layer, wherein the filler layer extends to either side of the tiles depending on a viewing direction.

2. The method of claim 1, further comprising providing a buffer layer on the top surface of the tile substrate or the backplate.

3. The method of claim 2, wherein the buffer layer is reflective or transparent.

4. The method of claim 1, wherein the regions or trenches between the blocks and the regions or trenches between the microdevices have the same width.

5. The method of claim 4, wherein the regions or trenches between the blocks and the regions or trenches between the microdevices are slotted.

6. The method of claim 5, wherein the filler layer is reflective and is patterned before or after the tile display is assembled.

7. The method of claim 6, wherein the grooves have a set pattern, or the pattern can be extracted after the block is generated.

8. The method of claim 4, wherein when the microdevices are on the bottom side of the blocks, the grooves are applied closer to the surface of the microdevices.

9. The method of claim 4, wherein the trenches are filled with an opaque filler.

10. The method of claim 1, wherein the metallization for traces and bridging elements is formed between the blocks above the filler layer.

11. The method of claim 1, wherein the filler layer comprises a black matrix or transparent material for reducing external light coupling.

12. The method of claim 1, wherein the filler layer comprises a black matrix or transparent material for reducing tile visibility.

13. The method of claim 1, further comprising depositing a dielectric layer on the top surface of the tiles.

14. The method of claim 13, further comprising providing an opening through the dielectric layer to provide metallization for traces and bridging formed above the filler layer between the tiles.

15. The method of claim 1, wherein aligning the tiles to the backplate includes aligning the contact pads of the tile substrate to the contact pads on the surface of the backplate.

16. The method of claim 15, wherein the contact pads of the tile substrate are connected to signal lines to transmit signals between or through the tiles.

17. The method of claim 1, wherein releasing the blocks to the backplate comprises applying pressure to the blocks to release them onto the surface of the backplate.

18. The method of claim 1, wherein the microdevice driver circuitry is formed on the tiles prior to being attached to the backplane.

19. A tile-based display comprising: a plurality of tiles on a substrate, wherein each of the plurality of tiles includes one or more microdevices on its surface; and a pass-through pad formed on a top surface of the substrate to pass a backplate to the top surface, wherein a portion of the backplate is formed after the plurality of tiles are bonded to the substrate.

20. The tile-based display of claim 19, further comprising a planarization layer formed and patterned to expose the top surface of the one or more microdevices.

21. The tile-based display of claim 20 further includes a protective layer formed on the planarization layer.

22. The tile-based display of claim 19 further includes a separation layer formed between the microdevices and the backplane.

23. The tile-based display of claim 22, wherein the separation layer is one of a reflective, opaque, black matrix, or patterned layer.

24. A tile-based display comprising: a plurality of tiles on a substrate, wherein each of the plurality of tiles includes one or more microdevices on its surface; a backplate formed after the plurality of tiles are bonded to the substrate; a patterned planarization layer for providing openings for connecting the microdevices; pad electrodes deposited and patterned on or above the microdevices; and a common pad formed on the top surface of the pad electrodes.

25. The tile display of claim 24, further comprising metallization electrodes formed to generate a common signal.

26. The tile display of claim 24 further includes a dielectric layer covering the pad electrode and a portion of the common pad.

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