Encoder and flash memory controller

Abstract

An encoder includes: a barrel shifter module, a circular convolution calculation circuit, and a compensation circuit. The barrel shifter module processes multiple data blocks to sequentially generate multiple local verification data blocks. The circular convolution calculation circuit is coupled to the barrel shifter module and performs a circular convolution operation on the multiple local verification data blocks to generate multiple convolution results. The compensation circuit is coupled to the circular convolution calculation circuit and performs a compensation operation on the multiple convolution results to generate multiple verification data blocks, wherein the compensation operation is causal. The multiple data blocks and the multiple verification data blocks are written into a flash memory.

Claims

1. An encoder comprising: a first barrel shifter module for processing a plurality of data blocks to sequentially generate a plurality of partial parity data blocks, wherein the plurality of partial parity data blocks include a first portion and a second portion, the first portion being generated earlier than the second portion, and the number of partial parity data blocks included in the first portion being less than the number of partial parity data blocks included in the second portion; a first calculation circuit coupled to the first barrel shifter module for generating a first calculation result based on the first portion; an adjustment circuit for adjusting the second portion of the plurality of partial parity data blocks based on the first calculation result to generate an adjusted second portion; and a first circulant convolution calculation circuit coupled to the adjustment circuit for performing a circulant convolution operation on the adjusted first portion to generate a parity data block of the second portion. A compensation circuit, coupled to the first circular convolution calculation circuit, is used to perform a compensation operation on the second part of the verification data block to generate a compensated second part of the verification data block, wherein the compensation operation is causal; a second calculation circuit, coupled to the compensation circuit, is used to generate a first part of the verification data block based at least on the compensated second part of the verification data block; wherein the first part of the verification data block and the compensated second part of the verification data block are multiple verification data blocks generated by the encoder for the multiple data blocks, and the multiple data blocks and the multiple verification data blocks are written into a flash memory.

2. The encoder as claimed in claim 1, wherein the compensation circuit is configured to perform the compensation operation on a convolution result corresponding to each of the second portions of the plurality of local verification data blocks; the compensation circuit compensates the convolution result corresponding to the target local verification data block based on the convolution results corresponding to one or more other local verification data blocks that are generated earlier than the target local verification data block.

3. The encoder as described in claim 1, wherein the first portion of the plurality of local check data blocks includes C1 local check data blocks, the second portion of the plurality of local check data blocks includes C2 local check data blocks, and C1 is less than C2; the first calculation circuit includes: a second circular convolution calculation circuit for performing a circular convolution operation on the C1 local check data blocks to generate C1 intermediate blocks; and a second barrel shifter module coupled to the second circular convolution calculation circuit for processing the C1 intermediate blocks to generate C2 calculation result blocks as the first calculation result; wherein, The adjustment circuit adds the C2 calculation result blocks to the C2 local verification data blocks respectively to generate the adjusted second part.

4. The encoder as described in claim 3, wherein the compensated second part of the verification data block includes C2 compensated verification data blocks, and the second calculation circuit includes: a third barrel shifter module for processing the C2 compensated verification data blocks to generate C1 processed blocks; a third circular convolution calculation circuit coupled to the third barrel shifter module for performing a circular convolution operation on the C1 processed blocks to generate C1 output blocks; and an output circuit coupled to the third circular convolution calculation circuit for adjusting the C1 output blocks based on the C1 intermediate blocks to generate C1 verification data blocks as the verification data blocks of the first part.

5. The encoder as described in claim 3, wherein C1 equals 2 and C2 equals 3.

6. The encoder as claimed in claim 5, wherein each of the first computing circuit and the second computing circuit includes a compensation circuit that performs a compensation operation in a causal manner.

7. The encoder as described in claim 1 is a low-density parity check (LDPC) code encoding circuit in a flash memory controller.

8. The encoder as described in claim 1, wherein, The encoder is used to perform LDPC encoding on multiple data blocks based on a tesseract-like parity check matrix that is isomorphic to a quasi-cyclic (QC)-LDPC parity check matrix.

9. A flash memory controller comprising an encoder as described in claim 1.

10. An encoder comprising: a barrel shifter module for processing a plurality of data blocks to generate a plurality of partial parity data blocks, wherein the plurality of partial parity data blocks include a first portion and a second portion, the first portion being generated earlier than the second portion, and the number of partial parity data blocks included in the first portion being less than the number of partial parity data blocks included in the second portion; an adjustment circuit for adjusting the second portion of the plurality of partial parity data blocks according to the first portion, to generate an adjusted second portion; and a circulant convolution calculation circuit coupled to the adjustment circuit for performing a circulant convolution operation on the adjusted second portion to generate a parity data block of the second portion. A compensation circuit, coupled to the circular convolution calculation circuit, is used to perform a compensation operation on the second part of the verification data block to generate a compensated second part of the verification data block, wherein the compensation operation is causal; and a calculation circuit, coupled to the circular convolution calculation circuit, is used to generate a second part of the verification data block based at least on the compensated second part of the verification data block; wherein the first part of the verification data block and the compensated second part of the verification data block are multiple verification data blocks generated by the encoder for the multiple data blocks, and the multiple data blocks and the multiple verification data blocks are written into a flash memory.

11. The encoder of claim 10, wherein the compensation circuit is configured to perform the compensation operation on a convolution result corresponding to each of the second portions of the plurality of local check data blocks; the compensation circuit compensates the convolution result corresponding to the target local check data block based on the convolution results corresponding to one or more other local check data blocks that are generated earlier than the target local check data block.

12. The encoder as described in claim 9, wherein the first portion of the plurality of local check data blocks contains only one local check data block.

13. The encoder as described in claim 10 is a low-density parity check (LDPC) code encoding circuit in a flash memory controller.

14. The encoder as described in claim 10, wherein, The encoder is used to perform LDPC encoding on multiple data blocks based on a tesseract-like parity check matrix that is isomorphic to a quasi-cyclic (QC)-LDPC parity check matrix.

15. The encoder of claim 10, wherein the encoder is used to perform LDPC encoding on the plurality of data blocks based on a parity check matrix, and each submatrix in the first column and the first row of the parity check matrix is ​​an identity matrix.

16. A flash memory controller comprising an encoder as described in claim 10.

17. An encoder comprising: a barrel shifter module for processing multiple data blocks to sequentially generate multiple partial parity data blocks; a circular convolution calculation circuit coupled to the barrel shifter module for performing a circular convolution operation on the multiple partial parity data blocks to generate multiple convolution results; and a compensation circuit coupled to the circular convolution calculation circuit for performing a compensation operation on the multiple convolution results to generate multiple parity data blocks, wherein the compensation operation is causal; wherein... The multiple data blocks and the multiple check data blocks are written into a flash memory.

18. The encoder of claim 17, wherein the compensation circuit is configured to perform the compensation operation on a convolution result corresponding to each of the plurality of local checks; the compensation circuit compensates the convolution result corresponding to the target local check data block based on the convolution result corresponding to one or more other local check data blocks that are generated earlier than the target local check data block.

19. The encoder as described in claim 17, wherein, The encoder is used to perform LDPC encoding on multiple data blocks based on a tesseract-like parity check matrix that is isomorphic to a quasi-cyclic (QC)-LDPC parity check matrix.

20. A flash memory controller comprising an encoder as described in claim 17.

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