Memory system and method performed thereby, controller and memory device

Abstract

A system includes a memory device and a controller. The controller is configured to: when performing data transfer to the memory device in response to a first operation corresponding to a first command, check whether a second command has been received, wherein performing data transfer to the memory device includes performing data transfer according to an allocation unit (AU). In response to determining that a second command has been received and that data transfer in the current AU is complete, the controller sends a pause command to the memory device. The memory device is configured to: in response to receiving the pause command from the controller, pause data reception for the first operation; allocate buffer space for the second operation corresponding to the second command; perform the second operation using the buffer space allocated for the second operation; and return the execution result of the second operation to the controller.

Description

[Technical Field]

[0001] In general, the present invention relates to memory systems, and more specifically, to the management of pause and resume operations of memory systems. [Previous Technology]

[0002] The memory system may include one or more memory elements for storing data. Memory elements may be, for example, non-volatile memory elements and volatile memory elements. Generally, a host system can use the memory system to store data in memory elements and retrieve data from memory elements. [Summary of the Invention]

[0003] This invention describes the management of pause and resume operations in a memory system.

[0004] For example, in one aspect, the present invention describes a system including a memory device and a controller. The controller is configured to: when performing data transfer to the memory device in response to a first operation corresponding to a first command, check whether a second command has been received, wherein performing the data transfer to the memory device includes performing the data transfer according to an allocation unit (AU); and in response to determining that the second command has been received and data transfer in the current AU is complete, send a pause command to the memory device. The memory device is configured to: in response to receiving the pause command from the controller, pause data reception for the first operation; allocate buffer space for the second operation corresponding to the second command; perform the second operation using the buffer space allocated for the second operation; and return the execution result of the second operation to the controller.

[0005] In another aspect, the present invention describes a method performed by a system including a memory device and a controller. The method includes: when performing data transfer to the memory device for a first operation corresponding to a first command, checking by the controller whether a second command has been received, wherein performing the data transfer to the memory device includes performing the data transfer according to an AU; in response to determining that the second command has been received and that data transfer in the current AU is complete, sending a pause command to the memory device by the controller; in response to receiving the pause command from the controller, pausing data reception for the first operation by the memory device; allocating buffer space by the memory device for the second operation corresponding to the second command; performing the second operation by the memory device using the buffer space allocated for the second operation; and returning the execution result of the second operation to the controller by the memory device.

[0006] In another aspect, the present invention describes a controller for controlling a memory device. The controller includes at least one processor coupled to a memory containing at least one stored programming instruction, which, when executed by the at least one processor, causes the controller to perform operations including: checking whether a second command has been received while performing data transfer to the memory device in response to a first operation corresponding to a first command, wherein performing the data transfer to the memory device includes performing the data transfer according to an AU; and sending a pause command to the memory device in response to determining that the second command has been received and that data transfer in the current AU is complete.

[0007] In another aspect, the present invention describes a memory device. The memory device includes: at least one processor coupled to at least one memory containing at least one stored programming instruction; at least one internal memory; at least one buffer space; and an array of memory cells, wherein, when executed by the at least one processor, the programming instructions cause the memory device to perform operations including: receiving a pause command from the controller to pause the data reception while performing data reception from the controller for a first operation corresponding to a first command; pausing the data reception for the first operation in response to receiving the pause command from the controller; allocating a buffer space in the at least one buffer space for a second operation corresponding to a second command; performing the second operation using the buffer space allocated for the second operation; and returning the result of the execution of the second operation to the controller.

[0008] Details of one or more embodiments of the inventive subject matter of the present invention are set forth in the drawings and the description below. Other features, aspects, and advantages of the inventive subject matter will become apparent from the description, drawings, and claims.

Implementation Method

[0010] A memory system can be a memory device, a memory module, or a hybrid of a memory device and a memory module. Examples of memory devices and memory modules are described below with reference to Figures 1, 2A, and 2B. Typically, a host system can utilize a memory system that includes one or more memory elements, such as a memory device for storing data. The host system can provide data to be stored in the memory device and can request data to be retrieved from the memory device.

[0011] The memory device may include multiple memory cells. Each memory cell may be configured with different storage modes or states, such as single-level cell (SLC) or multi-level cell (MLC). Each SLC memory element can only store one bit, while an MLC can store more than one bit of information. For example, a three-level cell (TLC) can store three bits of data, a four-level cell (QLC) can store four bits of data, and a five-level cell (PLC) can store five bits of data. TLC, QLC, PLC, and other cells capable of storing more than one bit of information are collectively referred to as MLC in this specification. The state of the memory cell can be programmed, and the state of the memory cell can be determined by comparing the read voltage of the memory cell with one or more read level thresholds.

[0012] QoS (Quality of Service) is a key evaluation factor for memory systems. QoS metrics can include, for example, latency / response time, system throughput, and other measurements. Different QoS latency metrics or numbers can be established for various applications. For example, a mixed write and read (or mixed input and output (I / O)) workload environment can include, for example, random write / read workloads and sequential write / read workloads. In one example, for a mixed workload with a 70% write / 30% write / read ratio, a 4K page size, and a drive capacity with a queue depth of 1, the memory system can have a QoS target of 99.9%. In another example, for a mixed workload with a 70% write / 30% write / read ratio, a 4K page size, and a drive capacity with a queue depth of 32, the memory system can have a QoS target of 99.999%.

[0013] Each programming pass executed on the memory system requires a certain amount of time to complete (e.g., programming time). The long programming time associated with the memory system, especially with MLC memory systems where each memory element stores more than 2 bits of information, can negatively impact the achievement of relevant QoS objectives.

[0014] In a memory system operating with a mixed workload, if a read operation request is received while a previous programming operation is in progress, the read operation will be forced to wait until the programming operation is complete. Since the programming time associated with MLC memory systems is long, and each memory element stores more than 2 bits of information, the read operation is delayed during this long programming time, negatively impacting QoS latency and throughput targets.

[0015] Specific embodiments of the inventive subject matter described in this summary can be implemented and illustrate achieving one or more of the following potential advantages. In some embodiments, the QoS of the memory system and the user experience (e.g., in terms of system response time) for read operations (or other operations with higher execution priority) can be improved because ongoing lower execution priority operations (e.g., programming or write operations) can be preempted by higher execution priority operations. For example, a data transfer interruption mechanism can be introduced on the memory controller and memory device of the memory system, such that lower execution priority operations (e.g., programming operations) can be paused earlier to perform higher execution priority operations (e.g., read operations) compared to other memory systems that do not implement the disclosed features. Furthermore, in some cases, unlike write pause commands that can only pause ongoing programming operations after data transfer from the controller to the memory device is complete (e.g., but before the data is actually stored in the memory device), the techniques described in this summary can pause ongoing programming operations while data is still being transferred from the memory controller, without having to wait for the memory device to finish receiving the complete data from the controller.

[0016] In some embodiments, the described technique allows for a pre-checking method to be implemented on the memory controller side to ensure that the processing of read operations preempts the programming data transfer process of programming operations. In some embodiments, the firmware does not need to involve any additional control actions on the memory controller side, and the hardware can handle the pre-checking or determination. Read processing can automatically pause data transfer to reduce latency.

[0017] On the memory device, a dynamic page buffer switching method can be implemented to ensure that read and write operations can be mixed and processed correctly. In some embodiments, a command-based preemptive interaction mechanism is designed in the described technique to avoid confusion in the internal processing logic on the memory device side. For example, using this feature, the memory device can automatically identify the operation type and switch the read / program design context without disrupting the internal state machine of the memory device.

[0018] In some embodiments, the described techniques can reduce pauses in other storage operations, improve the efficiency of processing read commands, and / or increase the throughput of the memory system because waiting until data transfer for an ongoing programming operation is completed can be avoided.

[0019] FIG1 shows a block diagram of an example system 100 having memory devices according to some aspects of the present invention. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory devices. As shown in FIG1, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 may be, for example, a processor (e.g., central processing unit (CPU)) or system-on-a-chip (SoC) (e.g., application processor (AP)) of an electronic device. Host 108 may be configured to send data to or receive data from memory device 104. In order to send data to or receive data from memory device 104, in addition to data, host 108 may also send instructions to memory system 102.

[0020] The memory device 104 may be any memory device disclosed in the present invention. As detailed below, the memory device 104 (e.g., a NAND flash memory device) may support interrupt-triggered program operation pauses.

[0021] In some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash Memory (CF) card, Universal Serial Bus (USB) flash memory drive, or other media for electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment in an SSD or embedded multimedia card (eMMC) for use as data storage and enterprise memory arrays in mobile devices such as smartphones, tablets, and laptops.

[0022] The memory controller 106 can be configured to control the operation of the memory device 104 (e.g., read, clear, and programming operations). For example, based on instructions received from the host 108, the memory controller 106 can send various commands (e.g., programming commands, read commands, clear commands, etc.) to the memory device 104 to control the operation of the memory device 104. Consistent with the scope of this invention, in some embodiments, the memory controller 106 sends a programming command to the memory device 104 to initiate a programming operation to be performed by the memory device 104. During the ongoing programming operation, an interruption (e.g., a read operation to another page), for example, from the host 108, may occur. The memory controller 106 can be configured to send an interrupt command to the memory device 104 to suspend the programming operation. In some embodiments, upon completion of other operations triggered by the interrupt, the memory controller 106 can also be configured to send a resume command to the memory device 104 to resume and complete the suspended programming operation.

[0023] The memory controller 106 may also be configured to manage various functions relating to data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices via at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Connection (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Small Interface (SCSI) protocol, Enhanced Small Magnetic Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0024] The memory controller 106 and one or more memory devices 104 can be integrated into various types of memory devices and can be included in, for example, the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In one example shown in FIG2A, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a memory card connector 204 configured to couple the memory card 202 to a host (e.g., host 108 in FIG1). In another example shown in FIG2B, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. SSD 206 may also include an SSD connector 208 configured to couple SSD 206 to a host (e.g., host 108 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of SSD 206 is greater than the corresponding storage capacity and / or operating speed of memory card 202.

[0025] FIG3 shows a block diagram of an example memory system 302 according to some aspects of the present invention. As shown, the memory system 302 includes a memory controller 306 and a memory device 304. The memory controller 306 and the memory device 304 may be exemplary embodiments of the memory controller 106 and the memory device 104 discussed in conjunction with FIG1, FIG2A and FIG2B.

[0026] The memory controller 306 can exchange data with the memory device 304, for example, in response to a request from a host (e.g., host 108 in FIG. 1). As an example, the memory controller 306 can read data from the memory device 304 in response to a request from the host and can provide the read data to the host. As another example, the memory controller 306 can write data to the memory device 304 or program data in response to a program request from the host.

[0027] In some embodiments, in order to perform the above operations, the memory controller 306 may provide signals such as address (ADDR), command (CMD), and control signal (CTRL) to the memory device 304, and may exchange data with the memory device 304. The memory device 304 may respond to the signals received from the memory controller 306 by outputting data or may program the received data.

[0028] The memory controller 306 can provide read commands, programming commands, clear commands, etc., to the memory device 304 as commands. For example, the memory controller 306 can request programming operations on the word line units of the memory device 304 via a programming command. The memory controller 306 can send one or more addresses representing one or more word lines, to which the programming operation is executed, such that programming is performed on the memory units on one or more word lines of the memory block of the memory device 304 indicated by one or more addresses ADDR. As another example, the memory controller 306 can request a read operation to read data stored in the memory units on one or more word lines of the memory device 304 via a read command. As another example, the memory controller 306 can request a clear operation to clear the programmed data in the memory units of one or more memory blocks or sub-blocks of the memory device 304 via a clear command.

[0029] FIG4 shows a block diagram of an example memory controller 406 according to some aspects of the present invention. The memory controller 406 may include one or more processors 422 and one or more memories, including cache memory 424 and / or one or more of another type of data storage. FIG4 shows dynamic random access memory (DRAM) 426 as independent of the memory controller 406; however, in some other embodiments, DRAM 426 may be included as part of the memories included in the memory controller 406. In some embodiments, the memory controller 406 may include a DRAM controller 425 for DRAM 426. The memory controller 406 may also include an interface (I / F) 428 (also referred to as a “front-end interface”) to a host 408 and an interface (I / F) 430 (also referred to as a “back-end interface”) to a memory device 404. In some embodiments, interface 428 may receive instructions and data from the host 408 and forward instructions and data to the processor 422 and DRAM 426, respectively. In some implementations, interface 430 can transmit control signals and data from processor 422 and DRAM 426 to memory device 404, respectively.

[0030] In some embodiments, processor 422 may include an arithmetic logic unit (ALU) configured to perform arithmetic and / or logical operations. One or more memories of memory device 404, memory controller 406, such as cache memory 424, or a combination thereof, may store programming instructions that, when loaded into processor 422, can be executed by processor 422 to perform various functions of memory controller 406, such as those described in this invention. As an example, memory controller 406 is configured to perform functions such as: repeatedly checking whether a second command has been received from host 408 when performing data transfer to memory device 404 in response to a first operation corresponding to a first command; and sending a pause command to memory device 404 whenever a second command is received, provided that data transfer in the current allocation unit has been completed.

[0031] FIG5 illustrates a schematic diagram of an example memory device 502 according to some aspects of the present invention. The memory device 502 may be an example embodiment of the memory device 104 or 304 discussed in conjunction with FIG1, FIG2A and 2B and FIG3. As shown, in some embodiments, the memory device 502 includes a microcontroller unit (MCU) 510, internal memory 520, a page pool 530, and a memory cell array 540.

[0032] Typically, the memory cell array 540 includes one or more storage planes, each storage plane including multiple memory blocks. In some embodiments, a memory block is the basic or smallest unit for performing a erase operation. In some embodiments, each memory block includes multiple pages, each storage plane including multiple memory cells. In some embodiments, a page is the basic or smallest unit for performing programming operations. In some embodiments, the memory cells of a page may share a word line.

[0033] In some embodiments, the memory cell array 540 is a flash memory array and is implemented using three-dimensional (3D) NAND flash memory technology. In these embodiments, each block in the memory block includes a plurality of memory cell strings arranged vertically (e.g., perpendicular to the main surface of the die). Each memory cell string includes a plurality of memory cells connected in series.

[0034] In some embodiments, the MCU 510, internal memory 520, and page pool 530 operate as peripheral circuitry driving the memory cell array 540. That is, the MCU 510, internal memory 520, and page pool 530 can be used to perform read, write, and clear operations on the memory cell array 540. These components perform read, write, and clear operations on the memory cell array 540 based on the control of the MCU 510.

[0035] MCU 510 may include one or more processing cores that can execute corresponding control software, firmware, or both of the MCU to perform the functions of the MCU. MCU 510 may receive commands CMD and / or control signals CTRL, for example, through the input / output buffer of memory device 502. MCU 510 is configured to control the overall operation of memory device 502 in response to commands CMD and / or control signals CTRL. In one example, in response to a read command, MCU 510 may generate control parameters to generate control signals to read data from memory cell array 540. In another example, in response to a write or programming command, MCU 510 may generate control parameters to generate control signals to write data or program to memory cell array 540. In another example, in response to a clear command, MCU 510 may generate control parameters to generate control signals to clear one or more blocks of memory cell array 540.

[0036] Internal memory 520 operates as cache memory or buffer memory of memory device 502. Internal memory 520 can be implemented as, for example, cache buffer memory, page cache memory, or otherwise for fast data access. For example, internal memory 520 can temporarily store data received from memory controller or host, or can temporarily store relay data (e.g., mapping table) of memory cell array 540. Alternatively or additionally, internal memory 520 can temporarily store various information required for the operation of MCU 510. For example, MCU 510 can search for open memory blocks by using data stored in internal memory 520.

[0037] Page pool 530 includes multiple page buffers (or page registers). Page pool 530 operates under the control of MCU 510. In some embodiments, page pool 530 is connected to memory cell array 540 via bit lines. In some embodiments, page pool 530 is connected to internal memory 520 via multiple data lines. Page pool 530 can store data to be programmed into memory cells of memory cell array 540 or data read from memory cells. During programming operations, page pool 530 receives data to be programmed into memory cells from internal memory 520 of memory device 502 and stores the received data. During read operations, page pool 530 temporarily stores data read from memory cells and outputs the read data to internal memory 520 of memory device 502. In some embodiments, in addition to page buffers, page pool 530 may also include column select circuitry, etc.

[0038] Figure 6 illustrates a schematic diagram of managing pause and resume operations associated with a memory system, according to some aspects of the present invention. From left to right, Figure 6 shows a timeline of operations including those performed by the memory controller of the memory system (e.g., memory controller 106 of memory system 102). For example, the memory controller may perform these operations in a mixed write and read workload environment.

[0039] Figure 6 uses CMD1-CMD5 to refer to the various commands used for different operations. CMD1 refers to the data transfer pause command, CMD2 refers to the read command, CMD3 refers to the programming command, CMD4 refers to the resume previous programming data transfer command, and CMD5 refers to the abort last programming operation command.

[0040] As shown in FIG. 6, programming commands for programming the memory device are issued by the memory controller, for example, based on programming commands from the host. Furthermore, for example, based on commands from the same host that also provides programming commands, one or more addresses are issued, representing one or more word lines of a memory block of the memory device to which programming operations should be performed. In response to receiving the programming commands and addresses, programming operations on the programming commands are performed.

[0041] In some embodiments, the programming operations of the programming commands on the memory device include the memory controller sending or transmitting data to be programmed into the memory device. In some embodiments, the memory controller performs the data transfer to the memory device according to allocation units. That is, in order to transfer the data to be programmed into the memory device, the memory controller divides the data into a sequence of multiple allocation units (AUs) and sends the AUs one by one in sequence according to the sequence of AUs. For example, as shown in FIG6, the memory controller sends data to the memory device in the sequence of AU0, AU1, AU2, AU3.

[0042] An AU is a basic unit or minimum amount of data that can be retrieved from or written to a memory system independently. In some implementations, the size of an AU is the same throughout the memory system. In other implementations, the size of an AU can vary within the memory system or differ from one memory system to another. In some implementations, each AU has a size smaller than the page size. As a non-limiting example, each AU can have a size equal to half, a quarter, or an eighth of the page size.

[0043] Programming operations (including data transfers from the memory controller to the memory device) require a certain amount of time to complete. Generally, different operations may have different characteristics, such as execution priority, and may take different durations or be associated with different durations to complete. In order to improve the overall execution efficiency or response time of the memory system, a programming operation with a higher execution priority than another programming operation may preempt or interrupt the execution of the other programming operation, even if the other programming operation may already be executing, or if it receives a command from a programming operation with a higher execution priority after a command from another programming operation with a lower execution priority.

[0044] During the execution of a programming operation, the memory controller, for example, repeatedly checks whether another command related to the memory system has been received, while simultaneously performing data transfer to the memory device for the programming operation corresponding to the programming command. This other command may request another command with a higher execution priority than the current programming operation.

[0045] In some cases, no other command is received, and the memory controller continues to transfer the current AU, or continues to transfer the next AU in the sequence to the memory device. In other cases, another command related to the memory system is received, for example, a command from the same or a different host.

[0046] Although Figure 6 illustrates other commands as read commands, more generally, other commands can be any command that requests an operation with a higher execution priority than the current programming operation of the programming command. In some embodiments, the execution priority of different operations can be determined based on the duration of completing different operations. For example, an operation that requires a shorter duration to complete can have a higher execution priority. In the example shown in Figure 6, other commands can be operations that take less time to complete than the programming operation of the programming command. For example, other commands can be read operations that take less time to complete than the programming operation. As another example, another command can be another programming operation for writing a smaller amount of data to the memory device, which will take less time to complete than the current programming operation for writing a larger amount of data to the memory device. In some other embodiments, the execution priority of different operations can be determined, or otherwise based on the importance of the operations or other factors or preferences.

[0047] In the example shown in FIG. 6, in response to receiving or detecting a read command, the memory controller issues a data transfer pause command to suspend the ongoing data transfer process for programming operations. In some cases, the data transfer pause command is sent once a read command is detected to limit the delay in servicing the read command. Therefore, in some implementations, the memory controller may send a data transfer pause immediately after the current AU's transfer is completed and before the transfer of subsequent AUs in the AU sequence begins. In some implementations, if the transfer of the current AU (e.g., AU0 shown in FIG. 6) has not yet been completed, the memory controller may wait for the current AU's transfer to complete and then continue processing the switch to perform operations related to the received read command.

[0048] After the data transfer pause command, the memory controller issues a read command corresponding to the received read command (e.g., from the host) to execute the read operation of the read command. As shown in FIG6, during the program pause phase, the read operation is executed. The read operation of the read command on the memory device includes: the memory device sending the read data to the memory controller. In some embodiments, such as in the case of transferring program data for program operation, the memory device similarly performs the read data transfer to the memory controller according to AU.

[0049] In some cases, after a read operation is completed, the memory controller issues a command to resume the previous programming data transfer. This command resumes the previously suspended programming operation on the memory device, and more specifically, resumes the data transfer process so that the data transfer of the previously suspended programming operation can continue. In some embodiments, the data transfer process can be resumed from the next AU in the AU sequence (e.g., AU1, where the data transfer process is suspended), so that the transfer of the data to be programmed from the memory controller to the memory device can be completed.

[0050] In other cases, upon completion of the read operation, the memory controller additionally or alternatively issues a command to abort the final programming operation. The command to abort the final programming operation instructs the memory device to abort the previously suspended programming operation. Upon receiving the command to abort the final programming operation, the memory device may discard the AU of the data to be programmed that was received during the final programming operation.

[0051] Figure 7 illustrates another schematic diagram of pause and resume operations associated with a memory system, according to some aspects of the present invention. Figure 7 illustrates multiple operations, including those performed, for example, by memory devices of the memory system (e.g., memory device 104 or memory device 502 of memory system 102) in a mixed write and read workload environment. The operations in Figure 7 may correspond to operations performed by the memory controller of the memory system discussed in Figure 6. The memory device may include an MCU, internal memory, a page pool, and a memory cell array, respectively similar to the MCU 510, internal memory 520, page pool 530, and memory cell array 540 of memory device 502.

[0052] As shown in FIG7, the AU (or simply AU) of the data is received by the memory device, for example, from the memory controller. In some embodiments, the AU may be an intermediate AU in an AU sequence being transferred for programming operations. The AU is called an "intermediate" AU because it is not the last AU in the AU sequence, and the transfer of the data to be programmed to the memory cell of the memory device has not yet been completed, wherein the AU is received by the memory device. In some embodiments, during the execution of programming operations, the AU may be temporarily stored in the internal memory of the memory device (e.g., internal memory 520) and then transferred to be stored in the buffer space allocated for programming operations in the page pool of the memory device.

[0053] After receiving the AU, the memory device receives a command, such as a command from the memory controller. In some embodiments, the memory device may include a command arbitrator. In some embodiments, the command arbitrator may be implemented as an integral part or a separate component of the memory device's MCU. In some embodiments, the command arbitrator may receive and process commands from the memory controller, for example, to determine the type of command. In some embodiments, the type of command may include, for example, a data transfer pause command, a read command, a resume previous programming data transfer command, etc. Corresponding operations can be configured for each command. The MCU may perform corresponding operations based on the type of command, for example, based on MCU control signals. In some embodiments, by using a command arbitrator, the memory device can automatically identify commands and switch read / programming contexts without disrupting the memory device's internal state machine. In some embodiments, command-based preemptive interaction between the memory controller and the memory device can prevent confusion or malfunction of the memory device's internal processing logic.

[0054] Generally, a command arbitrator can be implemented by hardware, firmware, software, or a combination of these elements in the memory device. In some embodiments, the command arbitrator can be implemented using hardware to handle arbitration or determination without imposing any additional control actions on the firmware of the memory device. In some embodiments, such implementation can further reduce latency and improve the response speed of the memory device.

[0055] In some cases where the command is a data transmission pause command, the memory device pauses data reception for the programming operation and stores the data (including AUs already received in the AU sequence for the programming operation) and stores the context of the execution state of the programming command in the internal memory of the memory device. For example, the context of the programming command may include functions, variables, and other object data and / or relay data describing the current execution state of the programming command, so that the programming command can be resumed after the pause. As an example, the context of the programming command may include information such as programming pages, programming passes, and programming / verification cycles for which the programming operation is paused, which can be used to resume the paused programming operation.

[0056] In some of these cases, a read command may follow a data transfer pause command. Therefore, the memory device also allocates buffer space in the page pool for read operations of read commands. In some embodiments, the memory device may dynamically allocate corresponding buffer spaces in the page pool for read operations and programming operations. In some embodiments, the buffer space allocated for read operations may differ from the buffer space allocated for programming operations. For example, the individual buffer spaces may correspond to different page buffers (or page registers) in the page pool, different spaces within the same page buffer, or different spaces within different page buffers. In some embodiments, the memory device may dynamically switch between the various buffer spaces in the page pool for read operations and programming operations without unintentionally overwriting data or causing other malfunctions. In some embodiments, this dynamic page buffer switching method at the memory device end can ensure that read and write operations are handled correctly, for example, in mixed I / O applications. The execution of a read operation performed while the programming operation is paused can use the allocated buffer space to temporarily store data read from the memory cells of the memory device. When a read operation is completed, the memory device returns the result of the read operation to the memory controller, including providing the memory controller with the allocated buffer space for storing the read data.

[0057] In some cases where the command is to resume the previous programming data transfer command, the memory device resumes the previously suspended programming operation of the memory device. In some embodiments, the memory device restores the context from internal memory and continues to receive data from the memory controller for programming operations. Specifically, the memory device can resume the data reception process at an AU in the AU sequence where the data reception process has been suspended, thereby enabling the memory device to complete the reception of data to be programmed.

[0058] In some embodiments, such as when programming operations are performed before a pause, these subsequently received AUs can be temporarily stored in the internal memory of the memory device and then transferred to the buffer space allocated for the programming operation in the page pool of the memory device. Once the memory device has received the entire sequence of AUs, the memory device can map the buffer space allocated for the programming operation to the memory cells of the memory device. That is, the memory device programs the AUs stored in the buffer space into the memory cells. AUs can be mapped or unmapped. AUs can switch between mapped and unmapped. For example, a mapped AU can refer to an AU that has been allocated to a logical address space (e.g., used by the host), while an unmapped AU can refer to an AU that is not currently allocated to a logical address space used by the host, while the mapped AU can currently be used to store and retrieve data for the host.

[0059] In some cases where the command is to abort the last programming operation, the memory device aborts the programming operation (suspends its data receiving process to enable read operations). The memory device may reset the internal memory and release the buffer space allocated in the page pool for the programming operation, thereby discarding all data (including AUs already received in the AU sequence) that was saved for the programming operation now aborted by the memory controller.

[0060] FIG8 is a swimlane diagram of an example process 800 for managing pause and resume operations according to some aspects of the present invention. Example process 800 may be executed by a memory system (e.g., memory system 102). Example process 800 will be described as being executed by a memory system having a memory controller and memory devices suitably programmed according to the present invention. In some embodiments, some or all of the operations in example process 800 may be implemented based on the techniques described in conjunction with FIGS. 3-7. The operations shown in process 800 may not be exhaustive, and other operations may be performed before, after, or between any illustrated operations. Furthermore, some of these operations may be performed simultaneously or in a different order than shown in FIG8.

[0061] The memory controller sends a first command to perform a first operation on the memory device (802). For example, the first operation may be a programming operation, a clearing operation, or another operation to be performed by the memory device. For example, a programming operation may be used to store data from the host computer to the memory system.

[0062] In response to the first command, the memory device begins to execute the first operation (804) on the memory device side. In example process 800, if the first operation is a programming operation, the execution of the programming operation begins by receiving data to be programmed into the memory device from the memory controller. The memory device may receive data AU one AU at a time in the AU sequence. In order to execute the programming command, the memory device may allocate buffer space for the programming operation, which is used to temporarily store the data to be programmed into the memory device.

[0063] When performing data transfer to a memory device for a programming operation corresponding to a programming command, the memory controller monitors and determines whether a second command has been received from the host and whether the data transfer in the current AU has been completed (806). For example, the second command may be associated with a second operation having a higher execution priority than the first operation, so that the first operation can be paused and preempted by the second operation. For example, the second command may be a read command that includes an identifier of the memory device, is affected by the first operation in process or in progress, and requests the memory device to read data from the memory device. As another example, the second command may be another programming command that requests the memory device to write some data (e.g., a smaller amount of data or data with a higher priority) before the first programming operation is completed.

[0064] In some embodiments, the memory controller may check whether a second command is received from the host once, periodically, or intermittently. For example, the memory controller may perform the check repeatedly at a predetermined frequency, such as every 1 µs, 10 µs, or 50 µs. As another example, the memory controller may perform the check before or during the transfer of each AU in the AU sequence from the memory controller to the memory device.

[0065] In response to the determination that no second command has been received from the host (or no command with a higher execution priority than the current first operation has been received), data transmission will continue, and the next AU in the AU sequence will be transferred from the memory controller to the memory device.

[0066] In response to the determination that the second command has been received and that the data transfer in the current AU (i.e., the AU currently being transferred at the time the second command was received) has not been completed, the memory controller may wait for the data transfer in the current AU to be completed.

[0067] In response to confirming that the second command has been received and that the data transfer in the current AU has been completed, the memory controller sends a pause command to the memory device to pause the first operation (808).

[0068] In response to receiving a pause command from the controller, the memory device performs a data transmission pause operation. The execution of the pause operation interrupts or suspends the programming of the memory device (810). In some embodiments, the memory device pauses the reception of data from the memory controller. In conjunction with the pause of data reception, the memory device stores the received data (including received AU) for the first operation and the context of the execution state of the first operation in the internal memory of the memory device.

[0069] By pausing or interrupting the ongoing first operation even before the data transfer from the memory controller to the memory device is complete, the memory system can respond more quickly to a second command (e.g., a read command) that has a higher execution priority. Advantageously, in some embodiments, the first operation can be paused substantially simultaneously with the recognition of the second command to reduce or limit latency such as the operation of the second operation, for example, taking into account applicable QoS metrics in a mixed write and read workload environment.

[0070] The memory controller sends a second command (812) to the memory device for performing a second operation. Using the above example, the second command may be a read command and the second operation may be a read operation for reading data from the memory device. In some embodiments, the second command sent by the memory controller to the memory device may have a different format than the second command received by the memory controller from the host. For example, the second command sent by the memory controller to the memory device may be generated by the memory controller based on information included in the second command received by the memory controller from the host, such as a read operation instructing the reading of data from the memory device. The second command sent by the memory controller to the memory device may include, for example, additional or different data fields, control information, or have a different format than the second command received by the memory controller from the host.

[0071] In response to receiving a second command from the memory controller, the memory device immediately resumes execution of the second operation after the first operation (e.g., programming operation) is paused, resulting in little or no delay in servicing the second command. Advantageously, in memory systems operating with mixed workloads, pausing data transmission for the first operation allows the second operation to be serviced without waiting for the transmission of the remaining AUs in the AU sequence for the ongoing first operation to complete. Therefore, in some cases, the latency of the memory system can be significantly reduced.

[0072] In some embodiments, the memory device allocates buffer space (814) in the page pool for a read operation corresponding to the second command. The memory device uses the buffer space allocated for the second operation in the page pool to perform the second operation (816). For example, the memory device can use the buffer space to temporarily store data read from a memory cell and output the data to the internal memory of the memory device. The memory device returns the execution result of the second operation to the controller (818). For example, if the second operation is a read operation, the memory device can provide the read data stored in the internal memory to the memory controller. Furthermore, in some cases, the memory device can release the buffer space allocated for the second operation after the second operation is completed.

[0073] The memory controller receives the execution result of the second operation from the memory device (820). For example, as a result of executing the second operation, the memory controller may receive data obtained from the memory cell of the memory device.

[0074] In some embodiments, the memory controller sends a recovery command to the memory device to resume the first operation (822) that was performed in step 802 and suspended in step 808.

[0075] In response to receiving a recovery command from the controller, the memory device recovers the context of the first operation from its internal memory and continues to execute the first operation. For example, if the first operation is a programming operation, the recovery command can resume the data transfer process so that data transfer of a previously suspended programming operation can be resumed (824). Specifically, the data transfer process can be resumed from the AU where the data transfer process was suspended in the AU sequence, thereby completing the data transfer from the memory controller to the memory device.

[0076] Just as the memory device performs programming operations before pausing, the memory device can store the AU received later in the buffer space allocated for the programming operation. When the data transfer is complete, the memory device maps the buffer space allocated for the programming operation to the memory cell of the memory device (826). That is, the memory device can program the AU stored in the buffer space into the memory cell.

[0077] In some embodiments, the memory controller sends an abort command to abort the first operation (828). When the abort command is sent, the first operation may or may not have been completed. In some embodiments, the memory controller may continue execution of step 828 directly after step 820 (skipping step 822). In some other embodiments, the memory controller may execute step 822 first, and then execute step 828.

[0078] In response to receiving an abort command from the memory controller, the memory device aborts the first operation, which may still be in progress. In some implementations, aborting the first operation may include releasing buffer space in the page pool or any other resources previously allocated for the first operation (830).

[0079] FIG9 is a flowchart of an example process 900 for managing pause and resume operations according to some aspects of the present invention. Example process 900 can be performed by any suitable memory device disclosed herein, such as memory controller 106 in FIG1 and FIG2A and FIG2B, memory controller 306 in FIG3, or memory controller 406 in FIG4. Example process 900 will be described as being performed by a memory controller of a memory system having a memory controller and a memory device suitably programmed according to the present invention. In some embodiments, some or all of the operations in example process 900 can be implemented based on the techniques described in conjunction with FIGS. 3-7. The operations shown in method 900 may not be exhaustive, and other operations may be performed before, after, or between any illustrated operations. Furthermore, some of these operations may be performed simultaneously or in a different order than shown in FIG9.

[0080] When performing data transfer to the memory device in response to the first operation corresponding to the first command, the memory controller monitors and checks whether a second command has been received (902). In some cases, the first command may be a programming command that performs a programming operation. The programming operation can be used to store data from the host to the memory system. In some cases, the second command may be a read command that performs a read operation. The read operation can be used by the host to read data from the memory system. In some other cases, the second command may be another command that performs another read operation to store (e.g., a smaller amount) of data from the host to the memory system.

[0081] Data transfer to the memory device can be performed at AU. That is, in order to transfer data for the first operation (e.g., data to be programmed is transferred to the memory device), the memory controller divides the data into a sequence of multiple AUs and sends the AUs one by one in sequence according to the sequence of AUs.

[0082] The memory controller may, while performing data transfer to the memory device in response to the first operation, repeatedly, i.e., at each of a plurality of time points, check whether a second command has been received. For example, the memory controller may perform the check at a predetermined frequency, such as every 1 µs, 10 µs, or 50 µs. As another example, the memory controller may perform the check before or during the transfer of each AU in the AU sequence from the memory controller to the memory device.

[0083] In response to the determination that the second command has been received and that the data transfer in the current AU has not been completed, the memory controller waits for the data transfer in the current AU to be completed.

[0084] In response to confirming that the second command has been received and that data transfer in the current AU is complete, the memory controller sends a pause command (904) to the memory device. The pause command can interrupt or pause the ongoing data transfer for the first operation immediately after the current AU has been transferred.

[0085] FIG10 is a flowchart of an example process 1000 for managing pause and resume operations according to some aspects of the present invention. Example process 1000 can be performed by any suitable memory device disclosed herein, such as memory device 104 in FIG1 and FIG2A and FIG2B, memory device 304 in FIG3, or memory device 502 in FIG5. Example process 1000 will be described as being performed by a memory device of a memory system having a memory controller and a memory device suitably programmed according to the present invention. In some embodiments, some or all of the operations in example process 1000 can be implemented based on the techniques described in conjunction with FIGS. 3-7. The operations shown in method 1000 may not be exhaustive, and other operations may be performed before, after, or between any illustrated operations. Furthermore, some of these operations may be performed simultaneously or in a different order than shown in FIG10.

[0086] When performing data reception from the memory controller in response to the first operation corresponding to the first command, the memory device receives a pause command from the controller to pause data reception (1002). Performing data reception may include storing the received AU into a first buffer space allocated for the first operation in the page pool of the memory device. For example, the first buffer space may be one or more page buffers in the page pool 530 of the memory device 502 of FIG. 5.

[0087] In response to receiving a pause command from the controller, the memory device pauses data reception for the first operation (1004). Data reception can be paused once the current AU in the AU sequence is received. In some cases, pausing data reception from the controller includes saving the context of the execution state of the first operation to the internal memory of the memory device.

[0088] The memory device allocates a second buffer space (1006) in the page pool of the memory device for the second operation corresponding to the second command. For example, the second buffer space may be one or more page buffers in the page pool 530 of the memory device 502 of FIG. 5. In some cases, the second buffer space may be a buffer space different from the first buffer space allocated in the page pool for the first operation. For example, the first and second buffer spaces may correspond to different page buffers in the page pool (e.g., different page buffers in the page pool 530 of the memory device 502 of FIG. 5), different spaces in the same page buffer (e.g., different spaces in the page buffers in the top row of the page pool 530 of the memory device 502 of FIG. 5), or different spaces in different page buffers.

[0089] The memory device uses the second buffer space allocated for the second operation to perform the second operation (1008). Specifically, the memory device can perform the second operation immediately after the first operation is paused. In the case that the second operation is a read operation, the memory device can store the data read from the memory cell of the memory device in the second buffer space.

[0090] The memory device returns the execution result of the second operation to the memory controller (1010). If the second operation is a read operation, the memory device can provide the read data to the memory controller.

[0091] According to one aspect of the present invention, a system including a memory device and a controller is disclosed. The controller is configured to: when performing data transfer to the memory device in response to a first operation corresponding to a first command, check whether a second command has been received, wherein performing data transfer to the memory device includes performing data transfer according to an AU; and in response to determining that a second command has been received and data transfer in the current AU is complete, send a pause command to the memory device. The memory device is configured to: in response to receiving the pause command from the controller, pause data reception for the first operation; allocate buffer space for the second operation corresponding to the second command; perform the second operation using the buffer space allocated for the second operation; and return the execution result of the second operation to the controller.

[0092] In some embodiments, the controller is configured to: wait for the data transmission in the current AU to complete in response to determining that a second command has been received and that data transmission in the current AU has not been completed.

[0093] In some embodiments, the controller is configured to repeatedly check whether a second command has been received while performing data transfer to the memory device in response to the first operation.

[0094] In some embodiments, performing the first operation includes transferring a plurality of AUs of data from the controller to the memory device, and the current AU is not the last AU among the plurality of AUs of data.

[0095] In some implementations, each AU has a size smaller than the page size.

[0096] In some implementations, each AU has a size equal to one-quarter of the page size.

[0097] In some embodiments, the controller is configured to: in response to receiving the execution result of the second operation from the memory device, send a recovery command to the memory device to restore the first operation; and the memory device is configured to: in response to receiving the recovery command from the controller, continue to receive data for the first operation.

[0098] In some embodiments, the memory device is further configured to: in response to receiving a recovery command from the controller, restore the context of the first operation from the first buffer space.

[0099] In some embodiments, the controller is configured to: in response to receiving the execution result of the second operation from the memory device, send an abort command to the memory device to abort the first operation; and wherein the memory device is configured to: in response to receiving the abort command from the controller, release the first buffer space previously allocated for the first operation, wherein the first buffer space is different from the buffer space allocated for the second operation.

[0100] In some embodiments, the memory device is configured to release buffer space allocated for the second operation in response to the completion of the second operation.

[0101] According to another aspect of the present invention, a method performed by a system including a memory device and a controller is disclosed. The method includes: when performing data transfer to the memory device for a first operation corresponding to a first command, checking by the controller whether a second command has been received, wherein performing data transfer to the memory device includes performing data transfer according to an AU; in response to determining that a second command has been received and data transfer in the current AU is completed, sending a pause command to the memory device by the controller; in response to receiving the pause command from the controller, pausing data reception for the first operation by the memory device; allocating buffer space by the memory device for the second operation corresponding to the second command; performing the second operation by the memory device using the buffer space allocated for the second operation; and returning the execution result of the second operation to the controller by the memory device.

[0102] In some embodiments, the method further includes: responding to determining that a second command has been received and that data transmission in the current AU has not been completed, waiting for data transmission in the current AU to be completed.

[0103] In some embodiments, the method further includes: while performing data transfer to the memory device for the first operation, repeatedly checking whether a second command has been received.

[0104] In some embodiments, the method further includes: in response to receiving the execution result of the second command from the memory device, sending a recovery command to the memory device via the controller to restore the first operation; and in response to receiving the recovery command from the controller, continuing data reception for the first operation via the memory device.

[0105] In some embodiments, the method further includes: in response to receiving a recovery command from the controller, restoring the context of the first operation from internal memory.

[0106] In some embodiments, the method further includes: in response to receiving the execution result of the second operation from the memory device, sending an abort command to the memory device via the controller to abort the first operation; and in response to receiving the abort command from the controller, releasing the first buffer space previously allocated for the first operation via the memory device, wherein the first buffer space is different from the buffer space allocated for the second operation.

[0107] In some embodiments, the method further includes: in response to completing the second operation, releasing the buffer space allocated for the second operation via the memory device.

[0108] According to another aspect of the present invention, a controller for controlling a memory device is disclosed. The controller includes at least one processor coupled to a memory containing at least one stored programming instruction, which, when executed by the at least one processor, causes the controller to perform operations including: checking whether a second command has been received when performing data transfer to the memory device in response to a first operation corresponding to a first command, wherein performing data transfer to the memory device includes performing data transfer according to an AU; and sending a pause command to the memory device in response to determining that a second command has been received and that data transfer in the current AU is complete.

[0109] In some embodiments, the operation includes: responding to the determination that a second command has been received and that data transmission in the current AU has not been completed, waiting for data transmission in the current AU to be completed.

[0110] In some embodiments, the operation includes: while performing data transfer to the memory device for the first operation, repeatedly checking whether a second command has been received.

[0111] In some embodiments, the operation includes: in response to receiving the execution result of the second operation from the memory device, sending a recovery command to the memory device to restore the first operation.

[0112] In some embodiments, the operation includes: in response to receiving the execution result of the second operation from the memory device, sending a stop command to the memory device to stop the first operation.

[0113] According to another aspect of the present invention, a memory device is disclosed. The memory device includes: at least one processor coupled to at least one memory of stored programming instructions; at least one internal memory; at least one buffer space; and an array of memory cells, wherein, when executed by the at least one processor, the programming instructions cause the memory device to perform operations including: receiving a pause command from a controller to pause data reception when performing data reception from a controller for a first operation corresponding to a first command; pausing data reception for the first operation in response to receiving the pause command from the controller; allocating buffer space in at least one buffer space for a second operation corresponding to a second command; performing the second operation using the buffer space allocated for the second operation; and returning the execution result of the second operation to the controller.

[0114] In some embodiments, suspending data reception from the controller for the first operation includes saving the context of the execution state of the first operation to at least one internal memory.

[0115] In some embodiments, performing data reception from the controller for the first operation includes: allocating a first buffer space in at least one buffer space for the first operation, wherein the first buffer space is different from the buffer space allocated for the second operation.

[0116] In some embodiments, the operation includes: in response to receiving a recovery command from the controller for resuming the first operation, recovering the context of the first operation from at least one internal memory; continuing to receive data from the controller for the first operation; saving data to a first buffer space allocated for the first operation; and mapping the first buffer space allocated for the first operation to a memory cell array.

[0117] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance given herein, such adaptations and modifications are intended to fall within the meaning and scope of the equivalents of the disclosed embodiments.

[0118] The breadth and scope of this invention should not be limited by any of the embodiments described in the above example embodiments, but should be defined solely by the appended claims and their equivalents. Therefore, other embodiments are also within the scope of the claims. [Simplified Explanation of the Diagram]

[0009] Figure 1 shows a block diagram of an example system having a memory device according to some aspects of the present invention. Figure 2A shows a schematic diagram of an example memory card having a memory device according to some aspects of the present invention. Figure 2B shows a schematic diagram of an example solid-state drive (SSD) having a memory device according to some aspects of the present invention. Figure 3 shows a block diagram of an example memory system according to some aspects of the present invention. Figure 4 shows a block diagram of an example memory controller according to some aspects of the present invention. Figure 5 shows a schematic diagram of an example memory device according to some aspects of the present invention. Figure 6 shows a schematic diagram of managing pause and resume operations associated with a memory system according to some aspects of the present invention. Figure 7 shows another schematic diagram of managing pause and resume operations associated with a memory system according to some aspects of the present invention. Figure 8 shows a swimlane diagram of an example process performed by a memory controller and a memory device according to some aspects of the present invention. Figure 9 is a flowchart of an example process performed by a memory controller according to some aspects of the present invention. Figure 10 is a flowchart of an example process performed by a memory device according to some aspects of the present invention. The same symbols and labels in the various figures indicate the same elements.

Claims

1. A memory system, comprising: Memory devices; The controller is configured to: perform a data transfer to the memory device for a first operation corresponding to a first command, wherein performing the data transfer to the memory device includes performing the data transfer according to an allocation unit; and after performing the data transfer and the data transfer in the current allocation unit is completed, send a second command to the memory device; and the memory device is configured to: store the received data in the current allocation unit in a first buffer space; allocate a second buffer space for a second operation corresponding to the second command; perform the second operation using the second buffer space allocated for the second operation; and return the execution result of the second operation to the controller; wherein the first buffer space is different from the second buffer space allocated for the second operation.

2. The system as described in claim 1, wherein, The controller is configured to: upon determining that the second command has been received and that the data transmission in the current allocation unit is not yet complete, wait for the data transmission in the current allocation unit to complete.

3. The system as described in claim 1, wherein, The controller is configured to: after data transmission in the current allocation unit is completed, and before sending the second command, send a third command to the memory device to pause the data transmission.

4. The system as described in any one of claims 1 to 3, wherein, Performing the first operation includes transferring a plurality of data allocation units from the controller to the memory device, wherein the current allocation unit is not the last allocation unit among the plurality of data allocation units.

5. The system as described in any one of claims 1 to 3, wherein, Each allocation unit has a size smaller than the page size.

6. The system as described in any one of claims 1 to 3, wherein, Each allocation unit has a size equal to one-quarter of the page size.

7. The system as described in claim 3, wherein, The controller is configured to: in response to receiving the execution result of the second operation from the memory device, send a recovery command to the memory device to restore the first operation; and wherein the memory device is configured to: in response to receiving the recovery command from the controller, continue receiving data for the first operation.

8. The system as described in claim 7, wherein, The memory device is also configured to: in response to receiving the recovery command from the controller, restore the context of the first operation from the first buffer space.

9. The system as described in claim 3, wherein, The controller is configured to: in response to receiving the execution result of the second operation from the memory device, send an abort command to the memory device to abort the first operation; and wherein the memory device is configured to: in response to receiving the abort command from the controller, release the first buffer space previously allocated for the first operation.

10. The system as described in any one of claims 1 to 3, wherein, The memory device is configured to: in response to completing the second operation, release the second buffer space allocated for the second operation.

11. A method performed by a system including a memory device and a controller, wherein, The method includes: performing a data transfer to the memory device for a first operation corresponding to a first command, wherein performing the data transfer to the memory device includes performing the data transfer according to an allocation unit; the memory device storing received data in the current allocation unit in a first buffer space; after performing the data transfer and the data transfer in the current allocation unit is completed, sending a second command to the memory device; allocating a second buffer space through the memory device for a second operation corresponding to the second command; performing the second operation through the memory device using the second buffer space allocated for the second operation; and returning the execution result of the second operation to the controller through the memory device; wherein the first buffer space is different from the second buffer space allocated for the second operation.

12. The method as described in claim 11, further comprising: In response to the determination that the second command has been received and that the data transmission in the current allocation unit is not yet complete, wait for the data transmission in the current allocation unit to complete.

13. The method as described in claim 11, further comprising: After the data transfer in the current allocation unit is completed, and before sending the second command, a third command is sent to the memory device to pause the data transfer.

14. The method as described in claim 13, further comprising: In response to receiving the execution result of the second operation from the memory device, the controller sends a recovery command to the memory device to restore the first operation; And in response to receiving the recovery command from the controller, continue receiving the data for the first operation via the memory device.

15. The method as described in claim 14, further comprising: In response to receiving the recovery command from the controller, the context of the first operation is restored from internal memory.

16. The method as described in claim 13, further comprising: In response to receiving the execution result of the second operation from the memory device, the controller sends a stop command to the memory device to stop the first operation; And in response to receiving the abort command from the controller, the first buffer space previously allocated for the first operation is released through the memory device.

17. The method of any one of claims 11 to 13, further comprising: In response to the completion of the second operation, the second buffer space allocated for the second operation is released through the memory device.

18. A memory device, comprising: At least one buffer space; A memory cell array, and a microcontroller unit coupled to the at least one buffer space and the memory cell array, wherein the microcontroller unit is configured to: receive a second command while performing data reception for a first operation corresponding to a first command, wherein a first buffer space in the at least one buffer space is allocated for the first operation; allocate a second buffer space in the at least one buffer space for a second operation corresponding to the second command; perform the second operation using the second buffer space allocated for the second operation; and return the execution result of the second operation to the controller; wherein the first buffer space is different from the second buffer space allocated for the second operation.

19. The memory device as claimed in claim 18, wherein, The microcontroller unit is further configured to release the second buffer space allocated for the second operation in response to the completion of the second operation.

20. The memory device as claimed in any one of claims 18 or 19, wherein, The microcontroller unit is further configured to: respond to a received abort command by releasing the first buffer space previously allocated for the first operation.

21. The memory device as claimed in any one of claims 18 or 19, wherein, After returning the execution result, the microcontroller unit is further configured to: continue receiving data for the first operation; and save the data to the first buffer space allocated for the first operation.

Images