Metallic layer for dimming light-emitting diode chips

Abstract

This invention discloses a solid-state light-emitting device comprising a light-emitting diode and a semi-transparent metal layer deposited on an LED chip, the semi-transparent metal layer being capable of dimming the light output of the LED chip. The thickness of the semi-transparent metal layer can be adjusted based on the desired dimming level. In one embodiment, the metal layer can be deposited on top of a passivation layer above the LED structure, such that the metal layer is not electrically coupled to the LED. The metal layer can additionally cover the mesa sidewalls of the LED structure. In other embodiments, the metal layer can be titanium or platinum, or other suitable metals. In another embodiment, the metal layer can be deposited on the passivation layer, wherein the deposition time of the metal layer can be based on the desired dimming amount.

Description

[Technical Field]

[0001] The present invention relates to a solid-state light-emitting device comprising a light-emitting diode (LED), and more particularly to a metal layer for dimming light emitted by an LED chip. [Previous Technology]

[0002] Solid-state light-emitting devices, such as light-emitting diodes (LEDs), are increasingly used in both consumer and commercial applications. Advances in LED technology have resulted in efficient and mechanically robust light sources with long lifespans. As a result, modern LEDs have enabled a variety of new display applications and are increasingly used in general lighting applications, often replacing incandescent and fluorescent light sources.

[0003] A light-emitting diode (LED) is a solid-state device that converts electrical energy into light, and typically comprises one or more active layers (or active regions) of semiconductor material disposed between oppositely doped n-type and p-type layers. When a bias voltage is applied across the doped layers, holes and electrons are injected into one or more active layers, where the holes and electrons recombine to produce emission, such as visible light or ultraviolet light emission. The active regions can be made of, for example, silicon carbide, gallium nitride, gallium phosphide, aluminum nitride, and / or gallium arsenide-based materials and / or organic semiconductor materials. Photons generated by the active regions are excited in all directions.

[0004] With the advancement of modern light-emitting diode technology, this technology continues to seek improved light-emitting diodes and solid-state light-emitting devices with the required lighting characteristics that can overcome the challenges associated with conventional light-emitting devices. [Summary of the Invention]

[0005] This invention relates to a solid-state light-emitting device comprising a light-emitting diode (LED), and more particularly to a translucent metal layer deposited on an LED chip capable of dimming the light output of the LED chip. The thickness of the translucent metal layer can be adjusted based on the desired dimming level. In an embodiment, the metal layer can be deposited on top of a passivation layer above the LED structure, such that the metal layer is not electrically coupled to the LED. The metal layer can additionally cover the mesa sidewalls of the LED structure. In other embodiments, the metal layer can be titanium or platinum, or other suitable metal. In an embodiment, the metal layer can be deposited on the passivation layer by sputtering, wherein the sputtering deposition time of the metal layer can be based on the desired dimming level.

[0006] In one embodiment, the LED chip includes: an active LED structure including an n-type layer, a p-type layer and an active layer between the n-type layer and the p-type layer, the active LED structure forming a mesa having mesa sidewalls defining the periphery of the active LED structure; a metal layer that is partially transparent to the wavelength of light generated by the active LED structure; and a passivation layer between the metal layer and the active LED structure, such that the metal layer is electrically insulated from the active LED structure.

[0007] In another embodiment, the LED chip may include a carrier sub-substrate. The LED chip may also include an active LED structure bonded to the carrier sub-substrate, the active LED structure including an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer, the active LED structure forming a mesa having mesa sidewalls defining the periphery of the active LED structure. The LED chip may also include a metal layer that is partially transparent to the wavelength of light generated by the active LED structure. The LED chip may also include a dielectric layer between the metal layer and the active LED structure, such that the metal layer is electrically insulated from the active LED structure.

[0008] In another embodiment, a method for manufacturing an LED chip is disclosed. The method includes forming an active LED structure over a carrier substrate, the active LED structure including an n-type layer, a p-type layer, and an active layer between the n-type and p-type layers, the active LED structure forming a mesa having mesa sidewalls defining the periphery of the active LED structure. The method may also include depositing a passivation layer over the active LED structure. The method may also include depositing a metal layer over the passivation layer, the metal layer being partially transparent to the wavelength of light emitted by the active LED structure, wherein the metal layer is electrically insulated from the active LED structure, and wherein the metal layer dims the light emitted by the active LED structure.

[0009] In another configuration, any of the aforementioned configurations and / or various individual configurations and features described herein may be combined individually or together to obtain additional advantages. Any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise indicated herein.

[0010] Those skilled in the art should understand the scope of the invention and its additional features after reading the following detailed description of preferred embodiments in relation to the accompanying drawings.

Implementation Method

[0019] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments, and show the best mode of practice. Upon reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the invention and recognize the application of such concepts not specifically set forth herein. It should be understood that such concepts and applications fall within the scope of the invention and the appended claims.

[0020] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, the elements should not be limited by the terms. The terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of the invention, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] It should be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another component, it can be directly on or directly extending to the other component, or an intervening component may also be present. In contrast, when a component is referred to as "directly located on" or "directly extending to" another component, no intervening component is present. Similarly, it should be understood that when a component, such as a layer, region, or substrate, is referred to as "located above" or "extending above" another component, it can be directly located above or directly extending above the other component, or an intervening component may also be present. In contrast, when a component is referred to as "directly located above" or "directly extending above" another component, no intervening component is present. It should also be understood that when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or an intervening component may be present. In contrast, when a component is referred to as "directly connected" or "directly coupled" to another component, no intervening component is present.

[0022] Relative terms such as “below” or “above”, or “upper” or “lower”, or “horizontal” or “vertical” may be used herein to describe the relationship between one element, layer or region and another element, layer or region as illustrated in the figures. It should be understood that the terms mentioned above, as well as the terms discussed above, are intended to cover different device orientations other than those depicted in the figures.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "the" are intended to include the plural forms as well. It should be further understood that the terms "comprising" and / or "including" as used herein specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should be further understood that the terms used herein should be interpreted as having the meaning appropriate to their context in this specification and in the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0025] Embodiments are described herein with reference to illustrative drawings of embodiments of the invention. Therefore, the actual dimensions of layers and elements may differ, and variations in the shape of the drawings are anticipated due to, for example, manufacturing techniques and / or tolerances. For instance, areas illustrated or described as squares or rectangles may have circular or curved features, and areas shown as straight lines may have some irregularity. Therefore, the areas illustrated in the figures are illustrative, and their shapes are not intended to depict the precise shape of the areas of the device, nor are they intended to limit the scope of the invention. Furthermore, for illustrative purposes, the dimensions of structures or areas may be enlarged relative to other structures or areas, and thus, a general structure provided to illustrate the subject matter of the invention may or may not be drawn to scale. Common elements between the figures may be shown herein with common element symbols and may not be described again subsequently.

[0026] This invention relates to a solid-state light-emitting device comprising a light-emitting diode (LED), and more particularly to a translucent metal layer deposited on an LED chip capable of dimming the light output of the LED chip. The thickness of the translucent metal layer can be adjusted based on the desired dimming level. In an embodiment, the metal layer can be deposited on top of a passivation layer above the LED structure, such that the metal layer is not electrically coupled to the LED. The metal layer can additionally cover the mesa sidewalls of the LED structure. In other embodiments, the metal layer can be titanium or platinum, or other suitable metal. In an embodiment, the metal layer can be deposited on the passivation layer by sputtering, wherein the sputtering deposition time of the metal layer can be based on the desired dimming level.

[0027] A typical light-emitting diode (LED) wafer includes an active light-emitting diode (ALD) structure or region having a number of different semiconductor layers configured in different ways. The fabrication and operation of LEDs and their active structures are generally known in the art and are only briefly discussed herein. The layers of the ALD structure can be fabricated using known processes with suitable processing techniques using metal-organic chemical vapor deposition (MOCVD). The layers of the ALD structure can include a number of different layers and typically include an active layer sandwiched between n-type and p-type oppositely doped epitaxial layers, all sequentially formed on a growth substrate. It should be understood that additional layers and elements can also be included in the ALD structure, including (but not limited to) buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, contact layers, current-dispersing layers, and light extraction layers and elements. The active layer can include single-quantum-well, multi-quantum-well, dual-heterogeneous, or superlattice extraction layers.

[0028] Active light-emitting diode (ALD) structures can be fabricated from various material systems, some of which are based on group III nitrides. Group III nitrides refer to semiconductor compounds formed between nitrogen (N) and elements in group III of the periodic table, typically aluminum (Al), gallium (Ga), and indium (In). Gallium nitride (GaN) is a common binary compound. Group III nitrides also refer to ternary and quaternary compounds, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). For group III nitrides, silicon (Si) is a common n-type dopant, and magnesium (Mg) is a common p-type dopant. Therefore, for III-nitride-based material systems, the active layer, n-type layer, and p-type layer may comprise one or more layers of GaN, AlGaN, InGaN, and AlInGaN, which may be undoped or doped with Si or Mg. Other material systems include silicon carbide (SiC), organic semiconductor materials, and other III-V systems and related compounds such as gallium phosphide (GaP) and gallium arsenide (GaAs).

[0029] Active LED structures can be grown on a growth substrate, which can contain many materials such as sapphire, SiC, aluminum nitride (AlN), and GaN. The 4H polytype SiC is a suitable substrate, but other SiC polytypes, including 3C, 6H, and 15R polytypes, can also be used. SiC has certain advantages, such as closer lattice matching to group III nitrides compared to other substrates, resulting in high-quality group III nitride films. SiC also has extremely high thermal conductivity, so the total output power of group III nitride devices on SiC is not limited by the heat dissipation of the substrate. Sapphire is another common substrate for group III nitrides and also has certain advantages, including lower cost, availability of existing manufacturing processes, and good light transmission optical properties.

[0030] Different embodiments of the active light-emitting diode (ALD) structure can emit light of different wavelengths depending on the composition of the active layer and the n-type and p-type layers. In some embodiments, the ALD structure can emit blue light with a peak wavelength range of approximately 430 nm to 480 nm. In other embodiments, the ALD structure can emit green light with a peak wavelength range of 500 nm to 570 nm. In other embodiments, the ALD structure can emit red light with a peak wavelength range of 600 nm to 650 nm. In some embodiments, the ALD structure can emit light with a peak wavelength in any visible spectrum region, for example, with a peak wavelength primarily in the range of 400 nm to 700 nm.

[0031] In some embodiments, the active light-emitting diode (ALD) structure may be arranged to emit light beyond the visible spectrum, including one or more portions of the ultraviolet (UV) spectrum, infrared (IR) spectrum, or near-IR spectrum. The UV spectrum is typically divided into three wavelength range categories denoted by the letters A, B, and C. In this manner, UV-A light is typically defined as having a peak wavelength in the range of 315 nm to 400 nm, UV-B is typically defined as having a peak wavelength in the range of 280 nm to 315 nm, and UV-C is typically defined as having a peak wavelength in the range of 100 nm to 280 nm. UV EADs are particularly suitable for applications related to the disinfection of microorganisms in air, water, and surfaces, as well as other applications. In other applications, UV EADs may also incorporate one or more phosphorescent materials to provide the EAD package with dense emission having a broad spectrum and improved color quality for visible light applications. The near-IR and / or IR wavelengths of the light-emitting diode structure used in this invention may have wavelengths higher than 700 nm (such as in the range of 750 nm to 1100 nm or more than 1100 nm).

[0032] The light-emitting diode (LED) chip may also be coated with one or more phosphorescent or other conversion materials (such as phosphors), such that at least some of the light from the LED chip is absorbed by one or more phosphors and converted into one or more different wavelength spectra according to the characteristics of the one or more phosphors. In some embodiments, the combination of the LED chip and one or more phosphors emits a combination of generally white light. The one or more phosphors may include phosphors emitting yellow (e.g., YAG:Ce), green (e.g., LuAg:Ce), and red (e.g., Cai-x-ySrxEuyAlSiN3) phosphors and combinations thereof. The phosphorescent materials described herein may be or may include one or more of phosphors, scintillators, phosphorescent inks, quantum dot materials, solar bands, and the like. The phosphorescent material can be provided by any suitable means, such as direct coating on one or more surfaces of an LED, dispersion in an encapsulation material arranged to cover one or more LEDs, and / or coating on one or more optical or support elements (e.g., by powder coating, inkjet printing, or similar methods). In some embodiments, the phosphorescent material can be down-converted or up-converted, and combinations of both down-converting and up-converting materials can be provided. In some embodiments, multiple different (e.g., different compositions) phosphorescent materials arranged to produce different peak wavelengths can be arranged to receive emission from one or more LED wafers. In some embodiments, one or more phosphors can include yellow phosphors (e.g., YAG:Ce), green phosphors (e.g., LuAg:Ce), and red phosphors (e.g., Cai-x-ySrxEuyAlSiN3), and combinations thereof. One or more phosphorescent materials can be provided in various arrangements on one or more portions of an LED wafer and / or sub-mount. In some embodiments, one or more surfaces of an LED chip may be conformally coated with one or more luminescent materials, while other surfaces of such an LED chip and / or associated sub-base may be free of luminescent materials. In some embodiments, the top surface of an LED chip may contain luminescent materials, while one or more side surfaces of the LED chip may be free of luminescent materials. In some embodiments, all or substantially all of the outer surfaces of an LED chip (e.g., except for contact defining or mounting surfaces) may be coated or otherwise covered with one or more luminescent materials. In some embodiments, one or more luminescent phosphorescent materials may be arranged in a substantially uniform manner on or above one or more surfaces of an LED chip. In other embodiments, one or more luminescent materials may be arranged in a non-uniform manner on or above one or more surfaces of an LED chip in terms of material composition, concentration, and thickness. In some embodiments, the loading percentage of one or more luminescent materials may vary on or between one or more outer surfaces of an LED chip. In some embodiments, one or more luminescent materials may be patterned on portions of one or more surfaces of an LED chip to include one or more stripes, dots, curves, or polygonal shapes.In some embodiments, multiple light-emitting materials may be arranged in different discrete regions or discrete layers on or above the LED chip.

[0033] Light emitted by the active layer or region of a light-emitting diode (LED) chip typically travels in multiple directions. For directional applications, internal mirrors or external reflective surfaces can be used to redirect as much light as possible toward the desired emission direction. Internal mirrors may comprise single or multiple layers. Some multilayer mirrors include a metallic reflective layer and a dielectric reflective layer, wherein the dielectric reflective layer is disposed between the metallic reflective layer and a plurality of semiconductor layers. A passivation layer is disposed between the metallic reflective layer and first and second electrical contacts, wherein the first electrical contact is electrically connected to a first semiconductor layer, and the second electrical contact is electrically connected to a second semiconductor layer. For single or multilayer mirrors containing surfaces exhibiting less than 100% reflectivity, light may be absorbed by the mirror. Additionally, light redirected through the active LED structure can be absorbed and redirected by other layers or elements within the LED chip.

[0034] As used herein, a layer or region illuminating a light-emitting device may be considered "transparent" when at least 80% of the emitted radiation illuminating that layer or region passes through it. Furthermore, as used herein, a layer or region illuminating a light-emitting diode may be considered "reflective" or embodied as a "mirror" or "reflector" when at least 80% of the emitted radiation illuminating that layer or region is reflected. In some embodiments, the emitted radiation includes visible light, such as in blue and / or green light-emitting diodes with or without phosphorescent materials. In other embodiments, the emitted radiation may include non-visible light. For example, in the context of GaN-based blue and / or green light-emitting diodes, silver (Ag) may be considered a reflective material (e.g., at least 80% reflectivity). In the case of UV light-emitting diodes, appropriate materials may be selected to provide the desired reflectivity (and in some embodiments, high reflectivity) and / or the desired absorptivity (and in some embodiments, low absorptivity). In some embodiments, the "light-transmitting" material may be arranged to transmit at least 50% of the emitted radiation of the desired wavelength.

[0035] This invention is applicable to LED chips having various geometries (such as vertical geometries). Vertical geometry LED chips typically include anode and cathode connectors on opposite sides or faces of the LED chip. In some embodiments, vertical geometry LED chips may also include a growth substrate disposed between the anode and cathode connectors. In some embodiments, the LED chip structure may include a carrier sub-base in which the growth substrate is removed. In other embodiments, any of the principles described can also be applied to flip-chip structures in which anode and cathode connectors are obtained from the same side of the LED chip for flip-chip mounting to another surface.

[0036] This invention relates to a solid-state light-emitting device comprising a light-emitting diode (LED), and more particularly to a semi-transparent metal layer deposited on an LED chip capable of dimming the light output of the LED chip. The metal layer is semi-transparent to the wavelength of light emitted by the LED chip. Because the brightness is often too high, standard sapphire alternatives are difficult to meet binning requirements. This invention provides a solution because existing chip platforms can incorporate titanium or other metal layers instead of etching passivation and texturing, so as to provide chips with a certain range of brightness using the same chip platform. The thickness of the metal layer can be modified to provide different dimming levels, thus allowing a single LED chip platform to meet multiple brightness requirements. Titanium or platinum metal layers can be used because these metal layers adhere well to the passivation layer and are resistant to gold etchants while still having light-blocking capabilities.

[0037] FIG1 is a general cross-section of an LED chip 10 embodying a vertical chip structure according to the principles of the present invention. The LED chip 10 includes an active LED structure 12 formed on a carrier sub-substrate 14. The active LED structure 12 generally refers to a portion of the LED chip 10 that includes a semiconductor layer (such as an epitaxial semiconductor layer) forming a structure that generates light when electrically activated. The active LED structure 12 is formed on and supported by the carrier sub-substrate 14, which can be made of many different materials (among which silicon or doped silicon is suitable). In some embodiments, the carrier sub-substrate 14 includes a conductive material such that the carrier sub-substrate 14 is a portion of the conductive connection leading to the active LED structure 12. The active LED structure 12 may generally include a p-type layer 16, an n-type layer 18, and an active layer 20 disposed between the p-type layer 16 and the n-type layer 18. The active LED structure 12 can include many additional layers, such as (but not limited to) buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, contact layers, current dispersing layers, and light extraction layers and elements. Additionally, the active layer 20 can include single quantum wells, multiple quantum wells, dual heterostructures, or superlattice structures. In FIG. 1, a p-type layer 16 is disposed between the active layer 20 and the carrier sub-substrate 14, such that the p-type layer 16 is closer to the carrier sub-substrate 14 than the n-type layer 18. The active LED structure 12 can initially be formed by sequentially epitaxially growing or depositing the n-type layer 18, the active layer 20, and the p-type layer 16 on a growth substrate. The active LED structure 12 can then be flip-chip bonded to the carrier sub-substrate 14 by means of one or more bonding metals 22, and the growth substrate is removed. In this manner, the top surface 18' of the n-type layer 18 forms the primary light extraction surface of the LED chip 10. In some embodiments, the top surface 18' may include a textured or patterned surface for improving photoextraction. In other embodiments, the doping order may be reversed such that the n-type layer 18 is disposed between the active layer 20 and the carrier sub-substrate 14. In one embodiment, an outer layer 50 is coated over the top surface 18' of the n-type layer 18 to cover and protect the top surface 18'. In another embodiment, the outer layer 50 may be a neutral dielectric material, such as silicon nitride (SiN), silicon dioxide (SiO2), or aluminum oxide (Al2O3) or other suitable passivation materials.

[0038] The LED chip 10 may include a first reflective layer 24 provided on the p-type layer 16. In some embodiments, a current-dispersing layer 26 may be provided between the p-type layer 16 and the first reflective layer 24. Although other materials may be used, the current-dispersing layer 26 may comprise a thin layer of a transparent conductive oxide such as indium tin oxide (ITO) or a thin metal layer such as platinum (Pt). The first reflective layer 24 may comprise a variety of different materials and preferably includes a material exhibiting a stepped refractive index, wherein the material of the active LED structure 12 promotes total internal reflection (TIR) ​​of the light generated by the active LED structure 12. Light undergoing TIR is redirected without absorption or loss, thereby facilitating suitable or desired LED chip emission. In some embodiments, the first reflective layer 24 comprises a material having a refractive index lower than that of the material of the active LED structure 12. The first reflective layer 24 may comprise a variety of different materials, some of which have a refractive index less than 2.3, while others may have refractive indices less than 2.15, less than 2.0, and less than 1.5. In some embodiments, the first reflective layer 24 comprises a dielectric material, such as silicon dioxide (SiO2) and / or silicon nitride (SiN). It will be understood that a variety of dielectric materials can be used, such as SiN, SiNx, Si3N4, silicon (Si), germanium (Ge), SiO2, SiOx, titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), ITO, magnesium oxide (MgOx), zinc oxide (ZnO), and combinations thereof. In some embodiments, the first reflective layer 24 may comprise multiple alternating layers of different dielectric materials, such as alternating layers of symmetrically repeated or asymmetrically arranged SiO2 and SiN. Some group III nitride materials, such as GaN, can have a refractive index of about 2.4, while SiO2 can have a refractive index of about 1.48, and SiN can have a refractive index of about 1.9. Embodiments having an active LED structure 12 including GaN and a first reflective layer 24 including SiO2 can form a sufficient stepped refractive index between the two to allow for efficient TIR of light. The first reflective layer 24 can have different thicknesses depending on the type of material used, and in some embodiments has a thickness of at least 0.2 micrometers (μm). In some embodiments, the first reflective layer 24 can have a thickness in the range of 0.2 μm to 0.7 μm, while in some embodiments, the thickness can be about 0.5 μm.

[0039] The LED chip 10 may further include a second reflective layer 28 on the first reflective layer 24, such that the first reflective layer 24 is disposed between the active LED structure 12 and the second reflective layer 28. The second reflective layer 28 may include a metal layer configured to reflect light from the active LED structure 12 that can be transmitted through the first reflective layer 24. The second reflective layer 28 may include many different materials, such as silver (Ag), gold (Au), aluminum (Al), nickel (Ni), titanium (Ti), or combinations thereof. The second reflective layer 28 may have different thicknesses depending on the type of material used, having a thickness of at least 0.1 μm in some embodiments, or in the range of 0.1 μm to 0.7 μm, or in the range of 0.1 μm to 0.5 μm, or in the range of 0.1 μm to 0.3 μm. As illustrated, the second reflective layer 28 may include or form one or more reflective layer interconnects 30, which provide conductive paths through the first reflective layer 24. In this manner, one or more reflective layer interconnects 30 can extend through the entire thickness of the first reflective layer 24. In some embodiments, the second reflective layer 28 is a metallic reflective layer and the reflective layer interconnects 30 include reflective layer metallic vias. Thus, the first reflective layer 24, the second reflective layer 28, and the reflective layer interconnects 30 form a reflective structure of the LED chip 10 on the p-type layer 16. Thus, the reflective structure may include dielectric and metallic reflective layers as disclosed herein. In some embodiments, the reflective layer interconnects 30 comprise the same material as the second reflective layer 28 and are formed simultaneously with the second reflective layer 28. In other embodiments, the reflective layer interconnects 30 may comprise a different material than the second reflective layer 28. Some embodiments may also include one or more interface and / or adhesive layers 32 located between the first reflective layer 24 and the second reflective layer 28, at the interface between the first reflective layer 24 and the current dispersing layer 26 to facilitate improved adhesion therebetween. Many different materials can be used for the adhesive layer 32, such as titanium oxide (TiO, TiO2), titanium oxynitride (TiON, TixOyN), tantalum oxide (TaO, Ta2O5), tantalum oxynitride (TaON), aluminum oxide (AlO, AlxOy), or combinations thereof, with TiON, AlO, or AlxOy being preferred materials. In some embodiments, the adhesive layer includes AlxOy, where 1 ≤ x ≤ 4 and 1 ≤ y ≤ 6. In some embodiments, the adhesive layer includes AlxOy (where x = 2 and y = 3) or Al2O3. The adhesive layer 32 can be deposited by electron beam deposition, which provides a smooth, dense, and continuous layer without significant changes in surface morphology. The adhesive layer 32 can also be deposited by sputtering, chemical vapor deposition, or plasma-enhanced chemical vapor deposition.

[0040] The LED chip 10 may also include a barrier layer 34 on the second reflective layer 28 to prevent material (such as Ag) of the second reflective layer 28 from migrating to other layers. Preventing this migration helps the LED chip 10 maintain effective operation throughout its lifespan. The barrier layer 34 may include a conductive material, wherein suitable materials include, but are not limited to, Ti, Pt, Ni, Au, tungsten (W), and combinations thereof, or alloys thereof. In some embodiments, the barrier layer 34 is configured to extend laterally beyond a portion of the active LED structure 12, or the peripheral boundary of the active LED structure 12, to provide an electrical connection to the p-contact 36. In this regard, the electrical path between the p-contact 36 and the p-type layer 16 may include the barrier layer 34, the second reflective layer 28, and the reflective layer interconnect 30. In other embodiments, the polarity may be reversed such that the p-contact 36 is replaced by an n-contact electrically coupled to the n-type layer 18, and an electrical connection to the p-type layer 16 is formed through the carrier sub-base 14. Passivation layer 38 is included on any portion of the barrier layer 34 and the second reflective layer 28 that may not be covered by barrier layer 34. Passivation layer 38 protects LED chip 10 and provides electrical insulation for the LED chip and may include many different materials, such as dielectric materials including, but not limited to, silicon nitride. In some embodiments, passivation layer 38 is a single layer, and in other embodiments, passivation layer 38 includes multiple layers. In some embodiments, passivation layer 38 may include one or more metal-containing interlayers disposed or embedded therein, which may act as a breakage stop layer for any breakage that may propagate through passivation layer 38 and additional light reflective layers.

[0041] In FIG. 1, the active LED structure 12 forms a first opening 40 or recess extending through a portion of the p-type layer 16, the active layer 20, and the n-type layer 18. The first opening 40 may be formed by a subtractive process (such as etching) applied to the active LED structure 12 prior to bonding with the carrier sub-substrate 14. As used herein, the first opening 40 may also be referred to as an active LED structure opening. As illustrated, a portion of the first reflective layer 24 and the adhesive layer 32 are configured to cover the sidewall surfaces of the p-type layer 16, the active layer 20, and the n-type layer 18 within the first opening 40. A passivation layer 38 extends along the first reflective layer 24 in the first opening 40 and is disposed on the surface of the n-type layer 18. The LED chip 10 further includes an n-contact metal layer 42 disposed on the passivation layer 38 and throughout the LED chip 10. At the first opening 40, the n-contact metal layer 42 extends into the first opening 40 to form an n-contact interconnect 44, which may be referred to as an n-contact via. In this manner, a first opening 40 can be defined, wherein portions of the n-contact metal layer 42, the n-contact interconnect 44, the passivation layer 38, and the first reflective layer 24 extend into the active LED structure 12. Therefore, the n-contact metal layer 42 and the n-contact interconnect 44 can be integrally formed to provide electrical connections through the first opening 40 to the n-type layer 18. In other embodiments, the n-contact metal layer 42 and the n-contact interconnect 44 can be formed separately and may comprise the same or different materials. In some embodiments, the n-contact metal layer 42 and the n-contact interconnect 44 comprise a single layer or multiple layers containing a conductive metal, such as one or more alloys of Al, Ti, and the above.

[0042] As illustrated, p-contact 36 may be formed on barrier layer 34, and one or more top passivation layers 46-1 and 46-2 may be provided on one or more top or side surfaces of n-type layer 18 for additional electrical insulation. In FIG. 1, top passivation layer 46-2 is configured to cover mesa sidewall 12' of active LED structure 12. Top passivation layers 46-1 and 46-2 may comprise separate layers of a continuous layer of dielectric material (such as silicon nitride). During the fabrication of the mesa of active LED structure 12, an etching step is applied from n-type layer 18 to active LED structure 12. The etching step effectively forms mesa sidewall 12' with an inclined surface along the periphery of active LED structure 12.

[0043] FIG2 is a cross-section of an LED chip 11 similar to the LED chip 10 of FIG1 and further comprising a metal layer 48 according to one or more embodiments of the present invention, the metal layer dimming the light emitted by the LED chip 11.

[0044] In FIG. 1, LED chip 10 has a top passivation layer 46-1 and a top passivation layer 46-2 etched away to expose the n-type layer 18. The n-type layer is then textured so that the top surface 18' has improved light extraction. However, in the embodiment of FIG. 2, LED chip 11 does not have the etched passivation layers 46-1 and 46-2, and instead has an additional metal layer 48 deposited on top of the passivation layer 46-2. Without texture, the light emitted by LED chip 11 is reduced to a first degree, and then the metal layer 48 (which can be translucent or partially opaque) can further reduce the light emitted by LED chip 11, and more specifically the light emitted by active LED structure 12. The metal layer 48 can be configured to reduce the amount of light escaping from LED chip 11 generated by active LED structure 12 by absorbing and / or internally reflecting a portion of the light from active LED structure 12. The metal layer 48 can also cover the mesa sidewall 12'. In some embodiments, the metal layer 48 may have different thicknesses, having a first thickness above the top of the active LED structure 12 and a second thickness above the mesa sidewall 12'. The thickness of the metal layer 48 above the active LED structure 12 and the mesa sidewall 12' can be selected based on the desired emission pattern or selected to adjust the overall dimming level of the metal layer 48. In other embodiments, the metal layer 48 may have a uniform thickness.

[0045] In this embodiment, the metal layer 48 is at least one of titanium and platinum, wherein titanium or platinum is a metal that adheres well to the passivation layer 46-2 and is resistant to gold etchants. The thickness of the metal layer 48 can be adjusted based on the desired light emission from the LED chip 11. A thicker metal layer 48 will reduce the light emitted by the LED chip 11 more or dim the light emitted by the LED chip 11 than a thinner metal layer 48.

[0046] In an embodiment, the metal layer 48 can be deposited on top of the passivation layer 46-2 via sputtering deposition or other forms of physical vapor deposition (such as cathodic arc deposition, electron beam physical vapor deposition, evaporation deposition, closed-space sublimation, pulsed laser deposition, or pulsed electron deposition). Given a known deposition rate, the length of the deposition process can determine the thickness of the metal layer 48.

[0047] In the embodiment, due to the passivation layers 46-1 and 46-2, which are dielectric materials (e.g., silicon nitride, etc.), the metal layer 48 is electrically insulated from or not electrically coupled to the active LED structure 12.

[0048] In an embodiment, the metal layer 48 can be patterned via a photomask to ensure that the metal layer 48 is not present in the dicing and pad areas of the LED chip 11. By ensuring that the metal layer 48 is not present in the dicing and pad areas of the LED chip 11, the metal layer 48 can be electrically insulated from the active LED structure 12 and other components of the LED chip 11. The metal layer 48 can also be patterned and have a variable thickness covering the top of the LED chip 11 to have adjustable brightness, adjustable emission pattern, and / or adjustable emitter shape. In an embodiment, the metal layer 48 can be deposited over a photoresist layer, which produces the patterned metal layer 48 after the photomask is applied.

[0049] In an embodiment, the metal layer 48 may have an outer layer 50 applied over the metal layer to cover and protect the metal layer 48. In an embodiment, the outer layer 50 may be a neutral dielectric material, such as SiN, SiO2, or Al2O3, or other suitable passivation materials.

[0050] As illustrated, the outer layer 50 may cover the metal layer 48 along the sidewall 12' and extend laterally through the metal layer 48 to electrically insulate the p-contact 36 from the metal layer 48. Therefore, the metal layer 48 can be effectively embedded or surrounded by passivation layers 46-1 and 46-2, and the dielectric material of the outer layer 50, so that the metal layer 48 is electrically insulated from the active LED structure 12. By covering the metal layer 48 with the outer layer 50, the metal layer 48 is electrically insulated from and environmentally isolated from additional layers that can be added to the LED chip 11 and / or the environment surrounding the LED chip 11.

[0051] Referring now to FIG. 3, another embodiment of the LED chip 11 is shown, wherein the metal layer 48 above the mesa sidewall 12' can have a different thickness compared to the metal layer 48 above the top surface of the active LED structure 12. For example, as shown in FIG. 3, the metal layer 48 above the top surface of the LED chip 11 is thicker than the metal layer 48 above the mesa sidewall 12'. Additionally, in the embodiment shown in FIG. 3, the metal layer 48 can have an opening 49 in which a photomask is applied to create a pattern. The top layer 50 can fill the opening 49, where the metal layer 48 is not present.

[0052] Referring now to Figures 4A and 4B, top views are shown of an LED chip (e.g., LED chip 11) without a metal layer (Figure 4A) and with a metal layer 48 (Figure 4B) according to one or more embodiments of the present invention. In an embodiment, as shown in Figure 4B, the metal layer 48 can be patterned to include openings 52 to prevent the metal layer 48 from covering the solder pads or scribe lines on the top of the LED chip 11.

[0053] Referring now to FIG5, a flowchart is shown depicting a method 500 for manufacturing an LED chip 11 having a metal layer 48 according to one or more embodiments of the present invention.

[0054] Method 500 can begin at step 502, wherein the method includes forming an active LED structure 12 above the carrier subbase 14, the active LED structure 12 including an n-type layer 18, a p-type layer 16 and an active layer 20 between the n-type layer 18 and the p-type layer 16, the active LED structure 12 forming a platform having a platform sidewall 12' defining the periphery of the active LED structure 12.

[0055] At step 504, the method may include depositing a passivation layer 46 over the active LED structure 12. In an embodiment, the passivation layer 46 may be a dielectric, such as silicon nitride.

[0056] At step 506, the method may include depositing a metal layer 48 over the passivation layer 46-2, the metal layer being partially transparent to the wavelength of light generated by the active LED structure 12, wherein the metal layer 48 is electrically insulated from the active LED structure 12, and wherein the metal layer 48 dims the light emitted by the active LED structure 12. In an embodiment, the metal layer 48 may be deposited via sputtering deposition, wherein the duration of deposition of the metal layer 48 controls the thickness of the metal layer 48, which in turn controls the amount of dimming provided by the metal layer 48. In other embodiments, other deposition techniques such as chemical vapor deposition or plasma-enhanced chemical vapor deposition are also possible. The metal layer 48 may also be deposited in a predetermined pattern, or deposited over a photoresist layer that produces a patterned metal layer 48 after the application of a photomask.

[0057] Referring now to FIG6, a graph is shown depicting experimental results illustrating how the display transmittance varies with the thickness of the metal layer according to one or more embodiments of the present invention.

[0058] Figure 600 depicts experimental results 602 showing the transmission percentage as a function of the thickness of the metal layer 48. In this example, the metal layer 48 is titanium, and the emitted light is at 451 nm. The thickness is in angstroms. The table on which Figure 600 is based is provided in Table 1 below: Thickness (A) Transmittance % 40 71.261 80 50.782 120 36.188 160 25.788 200 18.377

[0059] It is anticipated that any of the aforementioned states and / or various individual states and features as described herein can be combined to achieve additional advantages. Unless otherwise indicated herein, any of the various embodiments disclosed herein can be combined with one or more other disclosed embodiments.

[0060] Those skilled in the art will understand improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims. [Simplified Explanation of the Diagram]

[0011] Several aspects of the invention are illustrated in the accompanying drawings, which are incorporated in and form part of the specification, and are used together with the embodiments to explain the principles of the invention.

[0012] [Figure 1] is a general cross-section of a light-emitting diode (LED) wafer embodying a vertical wafer structure according to one or more embodiments of the present invention.

[0013] [Figure 2] is a cross-section of an LED chip similar to that of Figure 1 and further comprising a metal layer according to one or more embodiments of the present invention, the metal layer dimming the light emitted by the LED chip.

[0014] [Figure 3] is a cross-section of an LED chip according to one or more embodiments of the present invention, which is a different embodiment of the LED chip depicted in Figure 2.

[0015] [Figure 4A] is a top view of an LED chip without a metal layer according to one or more embodiments of the present invention.

[0016] [Figure 4B] is a top view of an LED chip with a metal layer according to one or more embodiments of the present invention.

[0017] [Figure 5] is a flowchart depicting a method for manufacturing an LED chip having a metal layer according to one or more embodiments of the present invention.

[0018] [Figure 6] is a graph depicting experimental results showing how the display transmittance varies with the thickness of the metal layer according to one or more embodiments of the present invention.

Claims

1. A light-emitting diode chip, comprising: An active light-emitting diode structure includes an n-type layer, a p-type layer, and an active layer between the n-type layer and the p-type layer; A metal layer covering at least a portion of the top surface of the active light-emitting diode structure, wherein the metal layer is partially transparent to the wavelength of light generated by the active light-emitting diode structure, and wherein the metal layer is patterned without covering the dicing or pad areas of the light-emitting diode wafer; a passivation layer between the metal layer and the active light-emitting diode structure, such that the metal layer is electrically insulated from the active light-emitting diode structure; and an outer layer above the metal layer, wherein the outer layer is a neutral dielectric material.

2. The light-emitting diode chip of claim 1, wherein the active light-emitting diode structure forms a mesa having mesa sidewalls defining the periphery of the active light-emitting diode structure, and wherein the mesa sidewalls are covered by the passivation layer and the metal layer.

3. The light-emitting diode chip of claim 1, wherein the metal layer is configured to absorb light emitted by the active light-emitting diode structure.

4. The light-emitting diode chip of claim 3, wherein the amount of light absorbed by the metal layer corresponds to the thickness of the metal layer.

5. The light-emitting diode chip of claim 1, wherein the metal layer is at least one of titanium and platinum.

6. The light-emitting diode wafer of claim 1, wherein the metal layer is deposited onto the passivation layer by sputtering.

7. The light-emitting diode chip of claim 2, wherein the first thickness of the metal layer above the top of the active light-emitting diode structure is different from the second thickness of the metal layer above the mesa sidewall of the active light-emitting diode structure.

8. The light-emitting diode chip of claim 1, wherein the metal layer is patterned in a predetermined pattern.

9. A light-emitting diode chip, comprising: Carrier sub-base; An active light-emitting diode (ALD) structure bonded to the carrier sub-substrate includes an n-type layer, a p-type layer, and an active layer disposed between the n-type layer and the p-type layer; a metal layer covering at least a portion of the top surface of the ALD structure, wherein the metal layer is partially transparent to the wavelength of light generated by the ALD structure, and wherein the metal layer is patterned without covering the dicing or pad areas of the ALD wafer; a dielectric layer between the metal layer and the ALD structure, such that the metal layer is electrically insulated from the ALD structure; and an outer layer above the metal layer, wherein the outer layer is a neutral dielectric material.

10. The light-emitting diode chip of claim 9, wherein the active light-emitting diode structure forms a mesa having mesa sidewalls defining the periphery of the active light-emitting diode structure, and wherein the mesa sidewalls are covered by the dielectric layer and the metal layer.

11. The light-emitting diode chip of claim 9, wherein the metal layer is configured to absorb light emitted by the active light-emitting diode structure.

12. The light-emitting diode wafer of claim 11, wherein the amount of light absorbed by the metal layer corresponds to the thickness of the metal layer.

13. The light-emitting diode chip of claim 9, wherein the metal layer is at least one of titanium and platinum.

14. The light-emitting diode wafer of claim 9, wherein the metal layer is deposited onto the dielectric layer by sputtering.

15. The light-emitting diode chip of claim 10, wherein the first thickness of the metal layer above the top of the active light-emitting diode structure is different from the second thickness of the metal layer above the mesa sidewall of the active light-emitting diode structure.

16. The light-emitting diode chip of claim 9, wherein the metal layer is patterned in a predetermined pattern.

17. The light-emitting diode chip of claim 9, wherein the dielectric layer is silicon nitride.

18. A method for manufacturing a light-emitting diode (LED) chip, comprising: An active light-emitting diode (ALD) structure is formed above a carrier substrate. The ALD structure includes an n-type layer, a p-type layer, and an active layer between the n-type layer and the p-type layer. A passivation layer is deposited above the ALD structure. A metal layer is deposited above the passivation layer. The metal layer is partially transparent to the wavelength of light emitted by the ALD structure. The metal layer is electrically insulated from the ALD structure. The metal layer is configured to dim the light emitted by the ALD structure. An outer layer is deposited above the metal layer. The outer layer is a neutral dielectric material.

19. The method of claim 18, further comprising: The metal layer is deposited to a predetermined thickness based on a predetermined dimming level.

20. The method of claim 18, further comprising: The metal layer is deposited according to a predetermined pattern corresponding to the emission pattern.

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