Sense amplifier reducing capacitive coupling effect and a sense circuit and a memory device comprising the same

Abstract

This disclosure provides a sense amplifier. The sense amplifier includes first to third transistors, a bias circuit, and a voltage coupling circuit. The first transistor is coupled between a first power supply terminal and a first node. A second transistor is coupled between the first node and a second node, and its gate receives a reference voltage. A third transistor is coupled between the first node and the third node, and its gate receives a data voltage. The bias circuit couples the second node and the third node to a second power supply terminal. The voltage coupling circuit is coupled between the first node and the gates of the second transistor, and provides a first voltage to the gate of the second transistor. The first voltage is negatively correlated with the voltage at the first node. The resistive-capacitive load of the gate of the second transistor is less than the resistive-capacitive load of the gate of the third transistor.

Description

Technical Field

[0001] This disclosure relates to non-volatile memory, and more specifically, to a sense amplifier, a sense circuit, and a memory device including the sense circuit for reducing capacitive coupling effects. Prior Technology

[0002] In non-volatile memory (NVM) technology, stored information is encoded as changes in resistance, threshold voltage, or charge state. A sense amplifier is designed to accurately and quickly convert these subtle physical changes into reliable digital signals for subsequent processing. The input from the memory cell is fed into one input of the sense amplifier, while a reference signal is input to the other. Upon startup, the sense amplifier amplifies the difference between the two inputs and drives the output to a specific logic level representing the memory cell's stored state (e.g., bit 0 or bit 1). This differential sensing method enhances noise immunity and improves read accuracy, which is particularly important in scaled memory technologies with small signal margins. Summary of the Invention

[0003] One embodiment of this disclosure provides a sense amplifier suitable for non-volatile memory (NVM) devices. The sense amplifier includes a first transistor, a second transistor, a third transistor, a bias circuit, and a voltage coupling circuit. The first transistor is coupled between a first power supply and a first node. A gate of the first transistor receives a common enable signal, and the first transistor is turned on by the enable signal to generate a common voltage at the first node. The second transistor is coupled between the first node and a second node. A gate of the second transistor receives a reference voltage. The third transistor is coupled between the first node and a third node. A gate of the third transistor receives a data voltage. The bias circuit couples the second and third nodes to a second power supply and generates sense output data based on the reference voltage and the data voltage. The voltage coupling circuit is coupled between the gates of the first node and the second transistor and provides a first voltage to the gate of the second transistor. During a sensing period in a non-volatile memory device, the resistive-capacitive load of the second transistor as seen from its gate is less than the resistive-capacitive load of the third transistor as seen from its gate. The first voltage is negatively correlated with the common voltage.

[0004] One embodiment of this disclosure provides a sensing circuit suitable for an NVM device. The sensing circuit includes multiple sense amplifiers, multiple data lines, and a reference voltage line. The multiple data lines are respectively coupled to the multiple sense amplifiers; the reference voltage line provides a reference voltage. Each sense amplifier includes a first transistor, a second transistor, a third transistor, a bias circuit, and a voltage coupling circuit. The first transistor is coupled between a first power supply and a first node. A gate of the first transistor receives a common enable signal, and the first transistor is turned on by the enable signal to generate a common voltage at the first node. The second transistor is coupled between the first node and a second node. A gate of the second transistor is coupled to the reference voltage line; the third transistor is coupled between the first node and a third node. A gate of the third transistor is coupled to a corresponding data line among the multiple data lines. The bias circuit couples the second and third nodes to a second power supply and generates sense output data based on the reference voltage and the data voltage. A voltage coupling circuit is coupled between the first node and the gate of the second transistor, and is used to provide a first voltage to the gate of the second transistor. The first voltage is negatively correlated with the common voltage.

[0005] One embodiment of this disclosure provides an NVM device. The NVM device includes a memory array, the aforementioned sensing circuitry (i.e., sensing circuitry having multiple sense amplifiers, multiple data lines, and a reference voltage line), and a bit line selector. The memory array includes multiple bit lines. The bit line selector is used to select a set of bit lines from the multiple bit lines for coupling to the multiple data lines respectively.

[0006] The proposed sensing amplifier, sensing circuit, and NVM device can stabilize the voltage on the reference voltage line, thereby preventing erroneous judgments about the storage state of the memory cell. Furthermore, the proposed sensing amplifier, sensing circuit, and NVM device have a small overall area. Simple Explanation of the Diagram

[0007] The following detailed description, when read in conjunction with the accompanying drawings, provides the best understanding of the format of this disclosure. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for ease of discussion, the dimensions of various features can be increased or decreased arbitrarily.

[0008] Figure 1 is a functional block diagram of a non-volatile memory (NVM) device according to some embodiments of this disclosure.

[0009] Figure 2 is a circuit diagram of a sensing circuit according to some comparative embodiments.

[0010] Figure 3 is a circuit diagram of a sense amplifier according to some embodiments of this disclosure.

[0011] Figure 4 is a circuit diagram of a sense amplifier according to some embodiments of this disclosure.

[0012] Figure 5 is a circuit diagram of a sense amplifier according to some embodiments of this disclosure. Implementation

[0013] [Priority Claims and Cross-Referencing] This application claims priority to U.S. Provisional Patent Application No. 63 / 734,217, filed December 16, 2024, the entire contents of which are incorporated herein by reference.

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided patent subject matter. Specific examples of components and arrangements described below are intended to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For instance, reference numerals and / or letters may be repeated in various examples. This repetition is for simplification and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, it should be understood that when a component is described as being "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or there may be an intermediate component.

[0016] In addition, for ease of description, this document uses spatially related terms such as "below," "above," "left," and "right" to describe the relationship between one element or feature and another shown in the accompanying drawings. These spatially related terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the drawings. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially related descriptors used herein will be interpreted accordingly.

[0017] Figure 1 is a functional block diagram of a non-volatile memory (NVM) device 100 according to some embodiments of this disclosure. Figure 2 is a circuit diagram of a sensing circuit 130 according to some comparative embodiments. The NVM device 100 includes a memory array 110, a bit line selector 120, and sensing circuit 130. The memory array includes word lines WL1 to WLm, bit lines BL1 to BLn, and a number of memory cells C11 to Cnm of "m×n", where m and n are positive integers. Word lines WL1 are coupled to the first column of memory cells C11 to Cn1; and word lines WL2 are coupled to the second column of memory cells C12 to Cn2, and so on. Bit lines BL1 are coupled to the first row of memory cells C11 to C1m; and bit lines BL2 are coupled to the second row of memory cells C21 to C2m, and so on. Bit line selector 120 is coupled to bit lines BL1 to BLn. The sensing circuit 130 includes data lines DL1 to DLk, a reference voltage line 20, and k-stage sensing amplifiers 22_1 to 22_k, where k is a positive integer less than n. The sensing circuit 130 is coupled to the bit line selector 120 via the data lines DL1 to DLk.

[0018] The read operation of the NVM device 100 may include a charging period and a sensing period, which alternate. During each charging period of the NVM device 100, the bit line selector 120 is able to select a set of bit lines (e.g., k bit lines) from bit lines BL1 to BLn to connect to data lines DL1 to DLk of the sensing circuit 130. Then, a selected set of memory cells (e.g., k memory cells) in the selected column can charge the set of bit lines.

[0019] During each sensing period of the NVM device 100, the enable signal EN enables sense amplifiers 22_1 to 22_k. The sense amplifiers 22_1 to 22_k determine the storage state of a selected memory cell (e.g., bit 0 or bit 1), thereby generating output data D1 to Dk. The sensing circuit 130 can combine the output data D1 to Dk to form k-bit output data Dout. In some embodiments, the transition of the enable signal EN can indicate the start or end of a sensing period.

[0020] For example, during a first charging period, k selected memory cells in the selected column charge bit lines BL1 to BLk connected to data lines DL1 to DLk; then, during a first sensing period, the sensing circuit 130 can generate output data Dout based on the data voltage on data lines DL1 to DLk. As another example, during a second charging period, another k selected memory cells in the selected column charge bit lines BL(k+1) to BL2k connected to data lines DL1 to DLk; then, the sensing circuit 130 can generate another k-bit output data Dout based on the data voltage on data lines DL1 to DLk. In an example where n is 120 and k is 40, the sensing circuit 130 can read out a column of memory cells during three sensing periods.

[0021] During sensing, the transistor Mp of each sensing amplifier 22_1 to 22_k is turned on by the enable signal EN. The turned-on transistor Mp provides a high voltage VDD to the sensing amplifiers 22_1 to 22_k, enabling the sensing amplifiers 22_1 to 22_k to compare the data voltages on data lines DL1 to DLk with the reference voltage Vref on the reference voltage line 20, thereby generating output data D1 to Dk. For example, if the data voltage on data line DL1 has a first level (e.g., a high level) higher than the reference voltage Vref, the output data D1 will be a low voltage VSS representing bit 1; if the data voltage on data line DL1 has a second level (e.g., a low level) lower than the reference voltage Vref, the output data D1 will be a high voltage VDD representing bit 0.

[0022] However, when transistor Mp is turned on, a rapid voltage rise occurs at the drain of each transistor Mp, leading to an increase in the reference voltage Vref and the data voltages on data lines DL1 to DLk. This capacitive coupling effect is caused by parasitic capacitance between the drain of transistor Mp and the reference voltage line 20, as well as parasitic capacitance between the drain of transistor Mp and each data line DL1 to DLk. Furthermore, during sensing, the resistive-capacitive (RC) load on the reference voltage line 20 is lower than the RC load on each data line DL1 to DLk because data lines DL1 to DLk are connected to bit lines, and each bit line may connect to more than one hundred memory cells. Therefore, the reference voltage line 20 may be more susceptible to capacitive coupling effects. For example, the reference voltage Vref may couple to a higher level than the data voltage (e.g., a high level), causing the corresponding output data to remain at a low voltage VSS representing bit 1. Therefore, compensation measures are needed to mitigate the capacitive coupling effect caused by transistor Mp in order to prevent the sensing amplifiers 22_1 to 22_k from misjudging the storage state of these memory cells.

[0023] Figure 3 is a circuit diagram of a sense amplifier 300A according to some embodiments of this disclosure. The sense circuit 130 may include multiple stages of sense amplifiers 300A. For example, one implementation of the sense circuit 130 is to replace the sense amplifiers 22_1 to 22_k in Figure 2 with sense amplifiers 300A respectively. The sense amplifier 300A includes transistors M1 to M3, a voltage coupling circuit 310A, and a bias circuit 320.

[0024] Each transistor M1 to M3 includes a source, a drain, and a gate. The source of transistor M1 is coupled to a first power supply terminal P1 providing a high voltage VDD; the drain of transistor M1 is coupled to a first node N1; and the gate of transistor M1 is used to receive an enable signal EN. The source of transistor M2 is coupled to the first node N1; the drain of transistor M2 is coupled to a second node N2; and the gate of transistor M2 is coupled to a reference voltage line 20 providing a reference voltage Vref. The source of transistor M3 is coupled to the first node N1; the drain of transistor M3 is coupled to a third node N3; and a gate of transistor M3 is coupled to a data line DL (e.g., one of data lines DL1 to DLk in FIG. 2) to receive a data voltage Vda. In some embodiments, transistors M1, M2, and M3 are P-type transistors, but this disclosure is not limited thereto.

[0025] One of the second node N2 and the third node N3 can be the output terminal of the sense amplifier 300A used to generate output data (e.g., one of the output data D1 to Dk in Figure 2). The gates of transistors M2 and M3 can be regarded as the input terminals of the sense amplifier 300A.

[0026] A voltage coupling circuit 310A is coupled between the first node N1 and the gate of transistor M2. The voltage coupling circuit 310A provides a first voltage V1 to the gate of transistor M2 to adjust the reference voltage Vref received by transistor M2. The first voltage V1 is negatively correlated with a common voltage Vcom at the first node N1. For example, when the common voltage Vcom increases, the first voltage V1 decreases; and when the common voltage Vcom decreases, the first voltage V1 increases.

[0027] Voltage coupling circuit 310A includes a capacitor 312 and an inverter 314. An input terminal of the inverter is coupled to a first node N1. Capacitor 312 is coupled between an output terminal of inverter 314 and the gate of transistor M2. In some embodiments, capacitor 312 comprises a metal-oxide-semiconductor (MOS) capacitor. The MOS capacitor may be implemented by transistor M4, which includes a source, a drain, and a gate. The source and drain of transistor M4 are coupled to the gate of transistor M2, and the gate of transistor M4 is coupled to the output terminal of inverter 314. Alternatively, the source and drain of transistor M4 are coupled to the output terminal of inverter 314, and the gate of transistor M4 is coupled to the gate of transistor M2. In some embodiments, transistor M4 is a P-type transistor, but this disclosure is not limited thereto.

[0028] The bias circuit 320 couples the second node N2 and the third node N3 to a second power supply terminal P2 that provides a low voltage VSS. In some embodiments, the bias circuit 320 includes a latching circuit for latching the voltages of the second node N2 and the third node N3, wherein the latching circuit includes transistors MA1, MA2, MA3, and MA4. Each transistor MA1, MA2, MA3, and MA4 includes a source, a drain, and a gate. Transistors MA1 and MA2 are coupled in series between the second node N2 and the second power supply terminal P2. Transistors MA3 and MA4 are coupled in series between the third node N3 and the second power supply terminal P2. The gates of transistors MA3 and MA4 are coupled to a fourth node N4 located between transistors MA1 and MA2. The gates of transistors MA1 and MA2 are coupled to a fifth node N5 located between transistors MA3 and MA4. In some embodiments, transistors MA1 and MA3 are P-type transistors, and transistors MA2 and MA4 are N-type transistors, but this disclosure is not limited thereto.

[0029] At the start of the sensing period, when the enable signal EN turns on transistor M1, the common voltage Vcom may rise rapidly. Due to the capacitive coupling effect caused by parasitic capacitors, this will pull up the reference voltage Vref and the data voltage Vda. It is important to note that during the sensing period, the RC load of the reference voltage line 20 may be less than the RC load of the data line DL, because the data line DL is connected to a single bit line, which may connect to more than one hundred memory cells. Therefore, the magnitude of the reference voltage Vref may be more easily affected by the common voltage Vcom. In other words, during the sensing period, the RC load of transistor M2 as seen from the gate of transistor M2 may be less than the RC load of transistor M3 as seen from the gate of transistor M3. Inverter 314 outputs a reversed common voltage Vcom, which is then coupled to the gate of transistor M2 through the capacitive coupling effect generated by capacitor 312, serving as the first voltage V1. The first voltage V1 is negatively correlated with the common voltage Vcom, which can suppress the rise of the reference voltage Vref, thus making the rise of the reference voltage Vref and the rise of the data voltage Vda substantially equal. Therefore, it can be ensured that the storage state of the memory cell will not be misjudged.

[0030] This MOS capacitor is used to compensate for the capacitive coupling effect caused by parasitic capacitors. To generate a coupling effect equivalent to that caused by parasitic capacitors, the MOS capacitor can be implemented by transistor M4, and the size of transistor M4 can be the same as that of transistor M2. Furthermore, for effective compensation, the capacitance value of the MOS capacitor is positively correlated with the voltage difference between its gate and source / drain. The reverse common voltage Vcom output by inverter 314 can be a low voltage VSS (e.g., ground voltage), which may be much lower than the reference voltage Vref. Therefore, even the small-area transistor M4 can generate sufficient capacitance to produce the first voltage V1.

[0031] Figure 4 is a circuit diagram of a sensing amplifier 300B according to some embodiments of this disclosure. Sensing circuit 130 may include multiple stages of sensing amplifiers 300B. For example, one implementation of sensing circuit 130 is to replace sensing amplifiers 22_1 to 22_k in Figure 2 with sensing amplifiers 300B respectively. Sensing amplifier 300B in Figure 4 is similar to sensing amplifier 300A in Figure 3; therefore, only the differences between them will be described below.

[0032] The sensing amplifier 300B includes a voltage coupling circuit 310B. The voltage coupling circuit 310B includes a capacitor 312, an inverter 314, and a capacitor 316. The voltage coupling circuit 310B provides a first voltage V1 to the gate of transistor M2 and a second voltage V2 to the gate of transistor M3. The first and second voltages are used to adjust the reference voltage Vref received by transistor M2 and the data voltage Vda received by transistor M3, respectively. The first voltage V1 and the second voltage V2 are negatively correlated with the common voltage Vcom at the first node N1. For example, when the common voltage Vcom increases, the first voltage V1 and the second voltage V2 decrease; and when the common voltage Vcom decreases, the first voltage V1 and the second voltage V2 increase.

[0033] The capacitor 312 and inverter 314 in Figure 4 are similar to those described in Figure 3; therefore, detailed descriptions of them are omitted. Capacitor 316 is coupled between the output of inverter 314 and the gate of transistor M3. In some embodiments, capacitor 316 comprises a metal-oxide-semiconductor (MOS) capacitor. This MOS capacitor may be implemented by a transistor M5, which includes a source, a drain, and a gate. The source and drain of transistor M5 are coupled to the gate of transistor M3, and the gate of transistor M5 is coupled to the output of inverter 314. Alternatively, the source and drain of transistor M5 are coupled to the output of inverter 314, and the gate of transistor M5 is coupled to the gate of transistor M3. In some embodiments, transistor M5 is a P-type transistor, but this disclosure is not limited thereto. In some embodiments, the size of transistor M5 may be the same as the size of transistor M3.

[0034] Inverter 314 outputs an inverted common voltage Vcom. This inverted common voltage Vcom is then coupled to the gate of transistor M2 as a first voltage V1, and to the gate of transistor M3 as a second voltage V2. The first voltage V1 and the second voltage V2 are used to suppress the rise of the reference voltage Vref and the data voltage Vda. Since the RC load of the reference voltage line 20 may be less than the RC load of the data line DL, the capacitance value of capacitor 312 can be less than or equal to the capacitance value of capacitor 316. In other words, the aspect ratio of transistor M4 can be less than or equal to the aspect ratio of transistor M5. Therefore, when the common voltage Vcom rises rapidly, the rise in the reference voltage Vref and the data voltage Vda is adjusted to be substantially equal, ensuring that the storage state of the memory cell is not misjudged.

[0035] Because of the RC load on the reference voltage line 20 and the signal line carrying the enable signal EN, subsequent sense amplifier stages will receive a reference voltage Vref and / or a data voltage Vda coupled to a higher level. Therefore, when sense amplifiers 300A / 300B are applied to the sense circuit 130, the capacitance value of capacitor 312 in the i-th stage sense amplifier 300A / 300B may be smaller than the capacitance value of capacitor 312 in the j-th stage sense amplifier 300A / 300B, where i and j are positive integers and i < j < k. Similarly, the capacitance value of capacitor 316 in the i-th stage sense amplifier 300A / 300B may also be smaller than the capacitance value of capacitor 316 in the j-th stage sense amplifier 300A / 300B.

[0036] The bias circuit 320 can be implemented by various types of latching circuits, and the number of transistors in such latching circuits may be more or less than those shown in Figures 3 and 4. For example, transistors MA1 and MA3 can be omitted. Furthermore, the bias circuit 320 is not limited to being implemented by latching circuits.

[0037] Figure 5 is a circuit diagram of a sensing amplifier 300C according to some embodiments of this disclosure. The sensing circuit 130 may include multiple stages of sensing amplifiers 300C. For example, one implementation of the sensing circuit 130 is to replace the sensing amplifiers 22_1 to 22_k in Figure 2 with sensing amplifiers 300C, respectively. The sensing amplifier 300C in Figure 5 is similar to the sensing amplifier 300A in Figure 3; therefore, only the differences between them will be described below.

[0038] The sensing amplifier 300C includes a bias circuit 330. The bias circuit 330 couples the second node N2 and the third node N3 to the second power supply terminal P2. The bias circuit 330 includes a current source. A first terminal of the current source is coupled to the second node N2 and the third node N3. A second terminal of the current source is coupled to the second power supply terminal P2. The circuit structure of this current source can be simpler than the latch-up circuit shown in Figures 3 and 4, thereby reducing the overall circuit area of ​​the sensing amplifier 300C. It should be noted that, without departing from the scope of this disclosure, the voltage coupling circuit 310A of the sensing amplifier 300C can be replaced by the voltage coupling circuit 310B in Figure 4.

[0039] Accordingly, the sensing amplifier provided in this disclosure can mitigate the capacitive coupling effect of the reference voltage line 20, thereby stabilizing the reference voltage Vref and preventing misjudgment of the storage state of the memory cell. Furthermore, due to the small overall area of ​​the voltage coupling circuit, the sensing amplifier provided in this disclosure also has a compact circuit structure.

[0040] In this document, the term "substantially" is used to describe and explain minute differences. When used in conjunction with an event or situation, the term can refer to either the exact occurrence of the event or situation or a situation that is very close to it. With respect to a given value or range, the term "substantially" as used herein generally refers to a range within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise stated, all ranges disclosed herein include endpoints. Furthermore, when numerical values ​​or characteristics are described as "substantially" identical, the term may refer to values ​​within ±10%, ±5%, ±1%, or ±0.5% of the average of these values.

[0041] The foregoing outlines several features of embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications to them without departing from the spirit and scope of this disclosure.

[0042] 20: Reference voltage line 22_1 to 22_k: Sensing amplifier 100: Non-volatile memory (NVM) devices 110: Memory Array 120: Bit line selector 130: Sensing Circuit 300A: Sensing Amplifier 300B: Sensing Amplifier 300C: Sensing Amplifier 310A: Voltage Coupling Circuit 310B: Voltage Coupling Circuit 312: Capacitor 314: Inverter 316: Capacitor 320: Bias circuit 330: Bias circuit BL1 to BLn: Bit Line C11 to Cnm: Memory Cells D1 to Dk: Output data DL: Data Line DL1 to DLk: Data Line Dout: Output data EN: Enable signal M1: Transistor M2: Transistor M3: Transistor M4: Transistor M5: Transistor MA1: Transistor MA2: Transistor MA3: Transistor MA4: Transistor Mp: Transistor N1: First node N2: Second node N3: Third node N4: Fourth Node N5: Fifth Node P1: First power supply terminal P2: Second power supply terminal V1: First voltage V2: Second voltage Vcom: Common Voltage Vda: Data voltage VDD: High Voltage Vref: Reference voltage VSS: Low Voltage WL1 to WLm: Character Lines

Claims

1. A sensing amplifier suitable for non-volatile memory devices, comprising: A first transistor is coupled between a first power supply terminal and a first node, wherein a gate of the first transistor is used to receive a common enable signal, and the first transistor is turned on by the enable signal to generate a common voltage at the first node; a second transistor is coupled between the first node and a second node, wherein a gate of the second transistor is used to receive a reference voltage; a third transistor is coupled between the first node and a third node, wherein a gate of the third transistor is used to receive a data voltage; a bias circuit is used to couple the second node and the third node to a second power supply terminal, and generate sensing output data based on the reference voltage and the data voltage; And a voltage coupling circuit coupled between the first node and the gate of the second transistor, for providing a first voltage to the gate of the second transistor, wherein the first voltage is negatively correlated with the common voltage, wherein during a sensing period of the non-volatile memory device, a resistive-capacitive load of the second transistor seen from the gate of the second transistor is less than a resistive-capacitive load of the third transistor seen from the gate of the third transistor.

2. The sensing amplifier of claim 1, wherein the voltage coupling circuit includes: An inverter, including an input terminal coupled to the first node; And a first capacitor, coupled between an output terminal of the inverter and the gate of the second transistor.

3. The sensing amplifier of claim 2, wherein the first capacitor includes a first MOS capacitor, the first MOS capacitor includes a fourth transistor, wherein a source and a drain of the fourth transistor are coupled to the gate of the second transistor, and a gate of the fourth transistor is coupled to the output of the inverter, and the size of the fourth transistor is equal to the size of the second transistor.

4. The sensing amplifier of claim 3, wherein the voltage coupling circuit is further coupled between the first node and the gate of the third transistor, and is further configured to provide a second voltage to the gate of the third transistor, wherein the second voltage is negatively correlated with the common voltage at the first node.

5. The sensing amplifier of claim 4, wherein the voltage coupling circuit further comprises: A second capacitor is coupled between the output of the inverter and the gate of the third transistor.

6. The sensing amplifier of claim 5, wherein the second capacitor includes a second MOS capacitor, the second MOS capacitor includes a fifth transistor, wherein a source and a drain of the fifth transistor are coupled to the gate of the third transistor, and a gate of the fifth transistor is coupled to the output of the inverter, and the size of the fifth transistor is equal to the size of the third transistor.

7. The sensing amplifier of claim 6, wherein the aspect ratio of the fourth transistor is greater than or equal to the aspect ratio of the fifth transistor.

8. The sensing amplifier of claim 1, wherein the bias circuit includes a latching circuit for latching the voltages of the second node and the third node.

9. The sensing amplifier of claim 1 further includes a parasitic capacitor coupled between the drain of the first transistor and the gate of the second transistor, and the parasitic capacitor generates a capacitive coupling effect when the first transistor is turned on.

10. A sensing circuit suitable for non-volatile memory devices, comprising: Multi-stage sensing amplifier; Multiple data lines are respectively coupled to these sensing amplifiers; And a reference voltage line for providing a reference voltage, wherein each sense amplifier includes: a first transistor coupled between a first power supply terminal and a first node, wherein a gate of the first transistor is used to receive a common enable signal, and the first transistor is turned on by the enable signal to generate a common voltage at the first node; a second transistor coupled between the first node and a second node, wherein a gate of the second transistor is coupled to the reference voltage line; a third transistor coupled between the first node and a third node, wherein a gate of the third transistor is coupled to a corresponding data line among the plurality of data lines; a bias circuit for coupling the second node and the third node to a second power supply terminal, and generating sense output data according to the reference voltage and the data voltage; And a voltage coupling circuit, coupled between the first node and the gate of the second transistor, for providing a first voltage to the gate of the second transistor, wherein the first voltage is negatively correlated with the common voltage.

11. The sensing circuit of claim 10, wherein during a sensing period of the non-volatile memory device, a resistive-capacitive load of the reference voltage line is less than a resistive-capacitive load of the corresponding data line among the plurality of data lines.

12. The sensing circuit of claim 10, wherein the voltage coupling circuit includes: An inverter, including an input terminal coupled to the first node; And a first capacitor, coupled between an output terminal of the inverter and the gate of the second transistor.

13. The sensing circuit of claim 12, wherein the capacitance of the first capacitor of an i-th stage sensing amplifier is less than the capacitance of the first capacitor of a j-th stage sensing amplifier, wherein i and j are positive integers and i is less than j.

14. The sensing circuit of claim 12, wherein the first capacitor includes a MOS capacitor, the MOS capacitor includes a fourth transistor, wherein a source and a drain of the fourth transistor are coupled to the gate of the second transistor, and a gate of the fourth transistor is coupled to the output of the inverter, and the size of the fourth transistor is equal to the size of the second transistor.

15. The sensing circuit of claim 14, wherein the voltage coupling circuit is further coupled between the first node and the gate of the third transistor, and is further configured to provide a second voltage to the gate of the third transistor, wherein the second voltage is negatively correlated with the common voltage at the first node.

16. The sensing circuit of claim 15, wherein the voltage coupling circuit further comprises: A second capacitor is coupled between the output of the inverter and the gate of the third transistor.

17. The sensing circuit of claim 16, wherein the second capacitor includes a MOS capacitor, the MOS capacitor includes a fifth transistor, wherein a source and a drain of the fifth transistor are coupled to the gate of the third transistor, and a gate of the fifth transistor is coupled to the output of the inverter, and the size of the fifth transistor is equal to the size of the third transistor.

18. The sensing circuit of claim 17, wherein the aspect ratio of the fourth transistor is greater than or equal to the aspect ratio of the fifth transistor.

19. The sensing circuit of claim 10, wherein the bias circuit includes a latching circuit for latching the voltages of the second node and the third node.

20. A non-volatile memory device, comprising: A memory array, including multiple bit lines; such as the sensing circuitry in request item 10; And a bit line selector for selecting a set of bit lines from the plurality of bit lines to be coupled to the plurality of data lines respectively.

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