Semiconductor device with heat dissipation isolation structure, method for manufacturing heat dissipation isolation structure, and die

Abstract

This disclosure provides a semiconductor device with a heat dissipation isolation structure, comprising a silicon substrate, a plurality of semiconductor structures, and at least one heat dissipation isolation structure. The semiconductor structures are spaced apart on the silicon substrate; at least one heat dissipation isolation structure is disposed on the silicon substrate and located between the semiconductor structures. The heat dissipation isolation structure includes an insulator and a heat dissipation channel disposed within the insulator. Thus, the heat dissipation isolation structure disclosed herein is located between the semiconductor structures, enabling direct conduction of internal heat energy of the semiconductor device to the outside of the semiconductor device. Combined with the formation of a packaged heat dissipation structure and an external heat dissipation system architecture, this significantly improves the heat dissipation capability of the semiconductor device and enhances its overall operating performance.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device with a heat dissipation isolation structure, a method for manufacturing the heat dissipation isolation structure, and a die. Prior Technology

[0002] In semiconductor devices, heat dissipation technology has always been a crucial factor affecting component reliability and performance. In traditional integrated circuit packaging and assembly architectures, semiconductor devices typically improve heat dissipation efficiency by incorporating additional heat dissipation structures, such as thermal paste, heat sinks, or heat sink fins.

[0003] However, the heat generated by semiconductor devices during operation is mostly concentrated in the internal structure, while the aforementioned heat dissipation structures are usually located on the exterior or surface of the semiconductor device, lacking direct thermal contact with the internal heat-generating structures. Therefore, heat must first be transferred to the external heat dissipation structure via internal materials or structures with relatively low thermal conductivity before it can be further dissipated. This indirect heat dissipation method easily leads to problems such as limited heat dissipation paths and high overall thermal resistance, thus limiting the performance improvement and reliability of integrated circuits in high-performance applications. After packaging and system assembly, the heat dissipation efficiency of the semiconductor device further decreases, affecting the overall system performance improvement and reliability. Summary of the Invention

[0004] The main purpose of this disclosure is to solve the problems of poor heat dissipation in existing semiconductor devices and poor heat dissipation in the overall system.

[0005] To achieve the above objectives, this disclosure provides an embodiment of a semiconductor device with a heat dissipation isolation structure, comprising a silicon substrate, a plurality of semiconductor structures, and at least one heat dissipation isolation structure. The semiconductor structures are spaced apart on the silicon substrate; at least one heat dissipation isolation structure is disposed on the silicon substrate and located between the semiconductor structures, and the heat dissipation isolation structure includes an insulator and a heat dissipation channel disposed in the insulator.

[0006] Furthermore, this disclosure also provides a method for manufacturing a heat dissipation isolation structure, which includes a groove forming step, a filling structure forming step, and a second insulating layer forming step. The groove forming step involves forming at least one groove on a silicon substrate, and forming a first insulating layer on the surface of the groove. The filling structure forming step involves forming a filling structure on the first insulating layer in the groove, the thickness of which is between 10 nanometers and 500 nanometers. The second insulating layer forming step involves forming a second insulating layer on the first insulating layer and the filling structure, such that the filling structure is disposed between the first insulating layer and the second insulating layer, wherein the first insulating layer and the second insulating layer together constitute an insulator, and the filling structure defines a heat dissipation channel.

[0007] Furthermore, this disclosure provides a die comprising the aforementioned semiconductor device and a first sealing ring. The first sealing ring is disposed on a silicon substrate and surrounds the semiconductor device having a heat dissipation isolation structure in a top view; wherein, at least one heat dissipation isolation structure extends from inside the first sealing ring to outside the first sealing ring in the top view.

[0008] Therefore, the heat dissipation isolation structure disclosed herein is disposed between semiconductor structures. This heat dissipation isolation structure can directly conduct the internal heat energy of the semiconductor device to the outside of the semiconductor device, significantly improving the heat dissipation capacity of the semiconductor device and improving the overall working performance of the semiconductor device. Simple Explanation of the Diagram

[0009] [Figure 1A] is a partial three-dimensional schematic diagram of a semiconductor device with a heat dissipation and isolation structure according to an embodiment of the present disclosure. [Figure 1B] is a partial structural cross-sectional view of a semiconductor device with a heat dissipation and isolation structure according to an embodiment of the present disclosure. [Figure 2A] is a partial three-dimensional schematic diagram of a semiconductor device with a heat dissipation isolation structure according to other embodiments disclosed herein. [Figure 2B] is a partial structural cross-sectional view of a semiconductor device with a heat dissipation isolation structure according to other embodiments disclosed herein. [Figure 3] is a top view and a partially enlarged view of a wafer according to an embodiment disclosed herein. [Figure 4] is a top-view magnified schematic diagram of a grain of an embodiment disclosed herein. [Figure 5] is a schematic diagram of the cross section taken from section line AA in Figure 4. [Figure 6] is a cross-sectional schematic diagram of a 2.5D packaging structure of another embodiment disclosed herein. [Figure 7] is a cross-sectional schematic diagram of the three-dimensional packaging structure of other embodiments disclosed herein. [Figure 8] is a schematic flowchart of a method for manufacturing a heat dissipation isolation structure according to an embodiment of the present disclosure. Figures 9A to 9C are schematic diagrams of the manufacturing process corresponding to the structure in Figure 8. [Figure 10] is a schematic flowchart of the manufacturing method of the heat dissipation isolation structure of other embodiments disclosed herein. Figures 11A to 11F are schematic diagrams of the manufacturing process corresponding to the structure in Figure 10. [Figure 12] is a schematic flowchart of the manufacturing method of the heat dissipation isolation structure of other embodiments disclosed herein. Figures 13A to 13G are schematic diagrams of the manufacturing process corresponding to the structure in Figure 12. [Figure 14] is a schematic flowchart of the manufacturing method of the heat dissipation isolation structure of other embodiments disclosed herein. Figures 15A to 15H are schematic diagrams of the manufacturing process corresponding to the structure in Figure 14. Implementation

[0010] To facilitate the explanation of the central ideas disclosed in the above-mentioned creative content section, specific embodiments are provided below. The various objects in the embodiments are drawn to scale suitable for illustration, rather than to scale with actual components, as will be stated prior.

[0011] Please refer to Figures 1A to 5, which illustrate a semiconductor device 100 with a heat dissipation isolation structure according to an embodiment of the present disclosure. The device includes a silicon substrate 10, a plurality of semiconductor structures 20, and at least one heat dissipation isolation structure 30.

[0012] The silicon substrate 10 is capable of having at least one groove 11, which can be disposed around each semiconductor structure 20.

[0013] A plurality of semiconductor structures 20 are spaced apart on the silicon substrate 10. Each semiconductor structure 20 may include passive components (e.g., resistors, capacitors, and inductors), active components (e.g., FinFETs, GAAFETs, MOSFETs, ForkFETs, CFETs), and logic circuits, etc., which can be formed on the silicon substrate 10 to operate various circuit operations, including backside power delivery technology.

[0014] A heat dissipation isolation structure 30 is disposed on a silicon substrate 10 and located between multiple semiconductor structures 20. The heat dissipation isolation structure 30 includes an insulator 31 and a heat dissipation channel 32 disposed in the insulator 31. The heat dissipation isolation structure 30 can be disposed in a groove 11 and can surround each semiconductor structure 20. The heat dissipation isolation structure 30 can be used to isolate adjacent semiconductor structures 20, prevent leakage current from semiconductor structures 20 and reduce parasitic effects. The heat dissipation isolation structure 30 can also improve the heat dissipation efficiency of the overall structure through the heat dissipation channel 32. In one embodiment of this disclosure, the material of the insulator 31 may include insulating materials such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and silicon germanium oxide (SiGeOx).

[0015] Please refer to Figures 1A and 1B. In one embodiment of this disclosure, a high thermal conductivity material is provided in the heat dissipation channel 32. The high thermal conductivity material can guide the heat generated by each semiconductor structure 20 from the semiconductor device 100, thereby improving the overall heat dissipation efficiency of the structure and reducing the impact of heat on the semiconductor structure 20. The high thermal conductivity material can be, for example, tungsten (W), germanium (Ge), aluminum nitride (AlN), or silicon carbide (SiC), etc. Any material that can be applied in semiconductor manufacturing processes such as epitaxy and deposition, and possesses good thermal conductivity, meets the requirements of this disclosure.

[0016] Referring to Figures 2A and 2B, in one embodiment of this disclosure, the heat dissipation channel 32 may be a hollow structure. The heat dissipation channel 32 may be connected to a fluid device (not shown) to transport a heat-conducting fluid, and the heat generated by each semiconductor structure 20 may be guided out of the semiconductor device 100 by the heat-conducting fluid. The heat-conducting fluid may be ordinary air, nitrogen, or a heat dissipation liquid, etc.

[0017] Please refer to Figures 3 to 5, which illustrate one embodiment of the present disclosure of a die 1000, which includes the semiconductor device 100 as described above and a first sealing ring 200. The semiconductor device 100 may be, for example, a graphics processing unit (GPU), a central processing unit (CPU), high bandwidth memory (HBM), or memory. Referring to Figure 3, multiple dies 1000 are formed on a wafer W, and the wafer W can be diced along multiple dicing paths C to separate the dies 1000 from each other.

[0018] Please refer to Figures 3 to 5. The first sealing ring 200 is disposed on the silicon substrate 10 and surrounds the semiconductor device 100 in the top view (as shown in Figure 4). In this way, the first sealing ring 200 can protect the semiconductor structure 20 inside the semiconductor device 100 from being damaged.

[0019] Please refer to Figures 3 to 5. In one embodiment of this disclosure, the heat dissipation isolation structure 30 extends from inside the first sealing ring 200 to outside the first sealing ring 200 in the top view (as shown in Figure 4). In this way, the heat dissipation isolation structure 30 can conduct the heat energy inside the semiconductor device 100 to outside the first sealing ring 200 through the extended portion.

[0020] Referring to Figures 4 and 5, in other embodiments disclosed herein, the die 1000 further includes a second sealing ring 300 disposed on the silicon substrate 10 and surrounding the first sealing ring 200 in the top view (as shown in Figure 4). When the wafer W undergoes the die 1000 dicing process, the second sealing ring 300 can preferentially withstand and absorb mechanical stress, cracks, or destructive energy, thereby being damaged or destroyed first, effectively preventing cracks from propagating into the semiconductor device 100, and thus protecting the integrity and reliability of the internal structure of the semiconductor device 100. As shown in Figures 4 and 5, the heat dissipation isolation structure 30 can extend between the first sealing ring 200 and the second sealing ring 300 and surround the second sealing ring 300 to guide heat energy from inside the semiconductor device 100 out of the semiconductor device 100.

[0021] Referring to Figure 6, in other embodiments disclosed herein, multiple chips 1000 can be packaged into a 2.5D package structure 2000 using a 2.5D packaging method. The 2.5D package structure 2000 includes a packaging substrate 2100, an interposer 2200, multiple chips 1000, multiple connectors 2300, and a packaging layer 2400. The interposer 2200 is formed on the packaging substrate 2100; the multiple chips 1000 are arranged side-by-side on the interposer 2200; each connector 2300 connects between the packaging substrate 2100 and the interposer 2200, and between the interposer 2200 and each chip 1000; the packaging layer 2400 covers the surrounding area of ​​the chips 1000. The packaging layer 2400 has a vertical channel 2410 arranged in a vertical direction and a horizontal channel 2420 arranged in a horizontal direction. The vertical channel 2410 and the horizontal channel 2420 surround each grain 1000 in a top-down view, and are interconnected with the heat dissipation channel 32 of each grain 1000 and the aforementioned fluid device. Herein, the aforementioned fluid device can input the heat-conducting fluid into the vertical channel 2410 and the horizontal channel 2420, allowing the heat-conducting fluid to enter the heat dissipation channel 32 through the vertical channel 2410 or the horizontal channel 2420, so that the heat-conducting fluid can guide the heat energy within the grain 1000 out of the grain 1000, achieving rapid heat dissipation (as shown by the arrow in Figure 6).

[0022] In other embodiments disclosed herein, the aforementioned fluid device may include an output channel and a recovery channel. The output channel and the recovery channel are connected to the vertical channel 2410 and the horizontal channel 2420. The heat-conducting fluid can be introduced into the vertical channel 2410 and the horizontal channel 2420 through the output channel, and then converged into the recovery channel through the vertical channel 2410 and the horizontal channel 2420 to form a three-dimensional circulating heat-conducting path, so that the heat energy inside the grain 1000 can be smoothly discharged, and the heat-conducting fluid is prevented from bringing the heat energy back to the grain 1000 during the circulation process.

[0023] In addition, in other embodiments disclosed herein, each die 1000 may have the same or different heights depending on the type or configuration of the semiconductor device 100 it is mounted on. The vertical channel 2410 and the horizontal channel 2420 may also be adjusted in size or position to accommodate the aforementioned height differences, so that the heat generated inside the die 1000 can still be effectively guided to the outside of the die 1000 through the vertical channel 2410 and the horizontal channel 2420, thereby maintaining stable heat dissipation performance.

[0024] Referring to Figure 7, in other embodiments disclosed herein, multiple chips 1000 can be stacked vertically to form a three-dimensional packaging structure 3000 through a three-dimensional (3D) packaging method. The three-dimensional packaging structure 3000 includes a packaging substrate 3100, multiple chips 1000, multiple connectors 3200, and a packaging layer 3300. The multiple chips 1000 are vertically stacked on the packaging substrate 3100; each connector 3200 connects the packaging substrate 3100 and the chips 1000, as well as between adjacent chips 1000; the packaging layer 3300 has a vertical channel 3310 and a horizontal channel 3320. The vertical channel 3310 and the horizontal channel 3320 are arranged around each chip 1000 in a top view, and the vertical channel 3310 and the horizontal channel 3320 are interconnected with the heat dissipation channel 32 of each chip 1000 and the aforementioned fluid device. In this way, the aforementioned fluid device can input the heat-conducting fluid into the vertical channel 3310 and the horizontal channel 3320, allowing the heat-conducting fluid to enter the heat dissipation channel 32 through the vertical channel 3310 or the horizontal channel 3320, so that the heat-conducting fluid can guide the heat energy in the grain 1000 out of the grain 1000, thereby achieving the purpose of rapid heat dissipation.

[0025] Please refer to Figures 8 to 15H, which illustrate a method S100 for manufacturing a heat dissipation isolation structure according to an embodiment of this disclosure. This method includes a groove forming step S110, a filling structure forming step S120, and a second insulating layer forming step S130. The method S100 for manufacturing the heat dissipation isolation structure can be performed before or after the semiconductor structure 20 has been fully formed. The following description assumes the semiconductor structure 20 has not yet been formed.

[0026] Groove forming step S110: At least one groove 11 is formed on the silicon substrate 10, and a first insulating layer L1 is formed on the surface of the groove 11 (as shown in FIG9A). The first insulating layer L1 can be formed by processes such as deposition, etching, annealing, and oxidation.

[0027] Filling structure forming step S120: A filling structure A2 is formed on the first insulating layer L1 in the groove 11. The thickness of the filling structure A2 is between 10 nanometers and 500 nanometers (as shown in Figure 9B).

[0028] Step S130: A second insulating layer L2 is formed on the first insulating layer L1 and the filling structure A2, such that the filling structure A2 is disposed between the first insulating layer L1 and the second insulating layer L2 (as shown in Figure 9C). The first insulating layer L1 and the second insulating layer L2 together constitute an insulator 31, and the filling structure A2 defines a heat dissipation channel 32.

[0029] Please refer to Figures 8 to 9C. In the groove forming step S110 of one embodiment of this disclosure, the first insulating layer L1 can be formed directly in accordance with the surface of the groove 11.

[0030] In addition to the aforementioned process method, please refer to Figures 10 to 11F. In the manufacturing method S100 of the heat dissipation isolation structure in other embodiments of this disclosure, the groove forming step S110 further includes a first insulating structure forming step S110a, a photoresist layer forming step S110b, a first insulating layer forming step S110c, and a photoresist removal step S110d.

[0031] First insulating structure forming step S110a: At least one groove 11 and a first insulating structure A1 (as shown in FIG11A) are formed on silicon substrate 10.

[0032] Photoresist layer formation step S110b: A first insulating layer predetermined formation area D is defined on the surface of the first insulating structure A1 located in the groove 11, and a photoresist layer P is formed in the area of ​​the first insulating structure A1 that is not in the first insulating layer predetermined formation area D (as shown in Figure 11B).

[0033] First insulating layer formation step S110c: The first insulating structure A1 not covered by the photoresist layer P is etched so that the first insulating structure A1 in the groove 11 can conform to the surface of the groove 11 to form the first insulating layer L1 (as shown in Figure 11C).

[0034] Photoresist removal step S110d: Remove photoresist layer P (as shown in Figure 11D).

[0035] Please refer to Figures 11A to 11F. After the photoresist removal step S110d, the filling structure formation step S120 (as shown in Figure 11E) and the second insulating layer formation step S130 (as shown in Figure 11F) can be performed.

[0036] Referring to Figures 8 to 9C, in the filling structure formation step S120 of one embodiment of this disclosure, a filling structure A2 with a thickness between 10 nanometers and 500 nanometers can be directly formed on the first insulating layer L1 in the groove 11. The filling structure A2 can be formed by deposition.

[0037] In addition to the aforementioned process method, please refer to Figures 12 to 13G. In the manufacturing method S100 of the heat dissipation isolation structure in other embodiments of this disclosure, the filling structure forming step S120 further includes a filling structure filling step S120a and a filling structure etching step S120b. The filling structure filling step S120a follows the groove forming step S110 (as shown in Figures 9A or 13A to 13D), and after the filling structure etching step S120b, the second insulating layer forming step S130 (as shown in Figure 13G) can be performed.

[0038] Filling structure filling step S120a: Fill the first insulating layer L1 in the groove 11 with filling structure A2 (as shown in Figure 13E).

[0039] Etching step S120b for the filling structure: Etching the filling structure A2 to make the thickness of the filling structure A2 between 10 nanometers and 500 nanometers (as shown in Figure 13F).

[0040] Referring to Figures 1A, 1B, and 8 to 13G, in one embodiment of this disclosure, the filling structure A2 can be a high thermal conductivity material. Referring to Figures 2A, 2B, and 14 to 15H, in other embodiments of this disclosure, when the filling structure A2 is a removable filling material, a channel etching step S140 is further included after the second insulating layer formation step S130: the filling structure A2 is etched to remove it, thereby forming a hollow heat dissipation channel 32 in the insulator 31 (as shown in Figure 15H). The coefficient of thermal expansion of the removable filling material and the first insulating layer L1 is between 1 ppm / °C and 20 ppm / °C; the temperature resistance range of the removable filling material is between 1000°C and 1200°C.

[0041] Please refer to Figures 2A, 2B, 4, 14 to 15H. In other embodiments disclosed herein, since the filling structure A2 can extend beyond the first sealing ring 200 or the second sealing ring 300, the etching process can start from the extended filling structure A2 in the channel etching step S140, thereby reducing the difficulty of etching the filling structure A2.

[0042] Therefore, this disclosure has the following advantages:

[0043] 1. The heat dissipation isolation structure 30 disclosed herein is disposed between the semiconductor structures 20. This heat dissipation isolation structure 30 can directly conduct the internal heat energy of the semiconductor device 100 to the outside of the semiconductor device 100, significantly improving the heat dissipation capacity of the semiconductor device 100 and improving the overall working performance of the semiconductor device 100.

[0044] 2. The heat dissipation isolation structure 30 can be used to isolate adjacent semiconductor structures 20, prevent leakage current in semiconductor structures 20 and reduce parasitic effects.

[0045] 3. In the die 1000 type, the heat dissipation isolation structure 30 can further conduct the internal heat energy of the semiconductor device 100 away from the semiconductor device 100 by means of the portion extending from the first sealing ring 200 or the second sealing ring 300, thereby reducing the adverse effects of heat energy on the semiconductor device 100.

[0046] The embodiments described in this disclosure are for illustrative purposes only. Those skilled in the art will understand that the various features, elements, or steps of this disclosure are not mutually exclusive, but can be combined, modified, or replaced in various ways as needed without departing from the spirit and scope of this disclosure. In particular, unless otherwise expressly stated, one or more features in any embodiment can be freely combined with features in other embodiments to produce new embodiments. All such implementations derived from feature combinations or modifications should be considered within the scope of this disclosure and should not be regarded as limiting the scope of this disclosure.

[0047] 1000: Grain size 2000: 2.5D package structure 2100: Packaging substrate 2200: Intermediary Layer 2300: Connector 2400: Encapsulation layer 2410: Vertical Channel 2420: Horizontal Channel 3000: Three-dimensional packaging structure 3100: Packaging substrate 3200: Connector 3300: Encapsulation layer 3310: Vertical Channel 3320: Horizontal Channel 100: Semiconductor devices 10: Silicon substrate 11: Groove 20: Semiconductor Structure 30: Heat dissipation and isolation structure 31: Insulator 32: Heat dissipation channel 200: First sealing ring 300: Second sealing ring W: Wafer C: Cutting track A1: First insulation structure A2: Filling Structure D: Pre-formed area of ​​the first insulating layer P: Photoresist layer L1: First insulating layer L2: Second insulating layer S100: Manufacturing method of heat dissipation and isolation structure S110: Groove Forming Steps S110a: First insulating structure formation step S110b: Photoresist layer formation steps S110c: Steps for forming the first insulating layer S110d: Photoresist Removal Procedure S120: Steps for forming the filling structure S120a: Filling steps for the filling structure S120b: Filling Structure Etching Step S130: Second insulating layer formation step S140: Channel Etching Step

Claims

1. A semiconductor device having a heat dissipation isolation structure, comprising: a silicon substrate; a plurality of semiconductor structures spaced apart on the silicon substrate; and at least one heat dissipation isolation structure disposed on the silicon substrate and located between the semiconductor structures, the heat dissipation isolation structure including an insulator and a heat dissipation channel disposed in the insulator.

2. The semiconductor device with a heat dissipation isolation structure as described in claim 1, wherein, The heat dissipation channel contains a material with high thermal conductivity.

3. The semiconductor device with a heat dissipation isolation structure as described in claim 2, wherein, The high thermal conductivity material is selected from the group consisting of tungsten (W), germanium (Ge), aluminum nitride (AlN) and silicon carbide (SiC).

4. A method for manufacturing a heat dissipation isolation structure as described in claim 1, comprising: a groove forming step: forming at least one groove on a silicon substrate, and forming a first insulating layer on the surface of the groove; a filling structure forming step: forming a filling structure on the first insulating layer in the groove, the thickness of the filling structure being between 10 nanometers and 500 nanometers; and a second insulating layer forming step: forming a second insulating layer on the first insulating layer and the filling structure, such that the filling structure is disposed between the first insulating layer and the second insulating layer, wherein... The first insulating layer and the second insulating layer together constitute the insulator, and the heat dissipation channel is defined by the filling structure.

5. The manufacturing method as described in claim 4, wherein, The groove forming step further includes the following steps: a first insulating structure forming step: forming the at least one groove and a first insulating structure on the silicon substrate; a photoresist layer forming step: defining a predetermined forming area of ​​the first insulating layer on the surface of the first insulating structure located in the groove, and forming a photoresist layer in the area of ​​the first insulating structure that is not in the predetermined forming area of ​​the first insulating layer; a first insulating layer forming step: etching the first insulating structure not covered by the photoresist layer so that the first insulating structure in the groove can form the first insulating layer in accordance with the surface of the groove; and a photoresist removal step: removing the photoresist layer.

6. The manufacturing method as described in claim 4, wherein, The filling structure forming step further includes the following steps: a filling structure filling step: filling the filling structure on the first insulating layer in the groove; and a filling structure etching step: etching the filling structure so that the thickness of the filling structure is between 10 nanometers and 500 nanometers.

7. The manufacturing method as described in claim 4, wherein, The filling structure is made of a high thermal conductivity material.

8. The manufacturing method as described in claim 7, wherein, The high thermal conductivity material is selected from the group consisting of tungsten (W), germanium (Ge), aluminum nitride (AlN) and silicon carbide (SiC).

9. The manufacturing method as described in claim 4, wherein, When the filling structure is a removable filling material, a channel etching step is further included after the second insulating layer formation step: the filling structure is etched to remove the filling structure, so as to form a hollow heat dissipation channel in the insulator.

10. The manufacturing method as described in claim 9, wherein, The coefficient of thermal expansion of the removable filler material matches that of the first insulating layer between 1 ppm / °C and 20 ppm / °C; the temperature resistance of the removable filler material is between 1000°C and 1200°C.

11. A die comprising: a semiconductor device with a heat-dissipating isolation structure as described in any one of claims 1 to 3; and a first sealing ring disposed on the silicon substrate and surrounding the semiconductor device with the heat-dissipating isolation structure in a top view; wherein, In the top view, the at least one heat dissipation isolation structure extends from inside the first sealing ring to outside the first sealing ring.

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