Integrated circuit interposer, optoelectronic computing system, integrated circuit apparatus, method for modulating optical signal, method of fabricating integrated circuit interposer, and method and system for transmitting information from nodes to destination interposer

Abstract

An integrated circuit interposer includes: a semiconductor substrate layer; a first metal contact layer including a first metal contact segment and a second metal contact segment, the first metal contact segment including metal contacts arranged for electrically coupled to a first semiconductor die via controlled-collapse wafer connection, and the second metal contact segment including metal contacts arranged for electrically coupled to a second semiconductor die via controlled-collapse wafer connection. A first patterning layer includes individually photomask-patterned metal path segments. A second patterning layer includes individually photomask-patterned waveguide segments, including a first waveguide spanning at least one boundary between the individually photomask-patterned waveguide segments. A first modulator is coupled to the first waveguide for modulating an optical wave in the first waveguide based on a first electrical signal, and a second modulator is coupled to the first waveguide for modulating an optical wave based on a second electrical signal.

Description

[Technical Field]

[0001] This disclosure relates to an optoelectronic computing platform. [Previous Technology]

[0002] Computations performed on electronic data encoded in analog or digital form as electrical signals (e.g., voltage or current) are typically implemented using electronic computing hardware, such as analog or digital electronic devices implemented in integrated circuits (e.g., processors, application-specific integrated circuits (ASICs) or system-on-a-chip (SoCs)), electronic circuit boards, or other electronic circuits. Optical signals have been used for transmitting data over both long and short distances (e.g., within data centers). Operations performed on such optical signals often occur in the context of optical data transmission, such as within devices used to exchange or filter optical signals in networks. The use of optical signals in computing platforms is more restricted. [Summary of the Invention]

[0003] Generally, in a first aspect, an integrated circuit interposer includes: a semiconductor substrate layer; a first metal contact layer, the first metal contact layer including a plurality of metal contact segments at a first surface of the integrated circuit interposer, the metal contact segments including a first metal contact segment and a second metal contact segment, the first metal contact segment including a plurality of metal contacts arranged for electrically coupled to a first semiconductor die via controlled-collapse wafer connection, the second metal contact segment including a plurality of metal contacts arranged for electrically coupled to a second semiconductor die via controlled-collapse wafer connection. The interposer includes: a first patterning layer, the first patterning layer including a plurality of individually photomask-patterned metal path segments at a first distance from the semiconductor substrate layer; and a second patterning layer, the second patterning layer including a plurality of individually photomask-patterned waveguide segments at a second distance from the semiconductor substrate layer different from the first distance. The second patterning layer includes: a first waveguide spanning at least one boundary between waveguide segments patterned by individual photomasks; a first modulator coupled to the first waveguide at a first location along the first waveguide for modulating an optical wave in the first waveguide based on an electrical signal received at a first metal contact in a first metal contact segment; and a second modulator coupled to the first waveguide at a second location along the first waveguide for modulating an optical wave in the first waveguide based on an electrical signal received at a second metal contact in either the first or second metal contact segment.

[0004] Each aspect may include one or more of the following features. The waveguide segment may include a first waveguide segment and a second waveguide segment, the first waveguide segment including a first portion of a first waveguide that couples the pilot mode to the edge of the first waveguide segment, and the second waveguide segment including a second portion of a first waveguide that couples the pilot mode to the edge of the second waveguide segment.

[0005] The metal path segment may include a first metal path segment that overlaps with at least a portion of a first metal contact segment and at least a portion of a second metal contact segment, and provides at least one metal path between at least one metal contact of the first metal contact segment and at least one metal contact of the second metal contact segment.

[0006] The metal path segment may include a second metal path segment that overlaps with at least a portion of the first metal contact segment and does not overlap with any portion of the second metal contact segment, and provides at least one metal path connected to at least one metal contact of the first metal contact segment.

[0007] The integrated circuit interposer may further include a second metal contact layer, which includes a plurality of metal contact segments on the second surface of the integrated circuit interposer.

[0008] The integrated circuit interposer may also include at least one capacitor or inductor electrically coupled to at least one of the first semiconductor die or the second semiconductor die.

[0009] The first modulator and the second modulator may be amplitude modulators configured to modulate the light wave in the first waveguide with the same predetermined amplitude scaling factor.

[0010] Generally, in another aspect, a system includes an integrated circuit interposer and a plurality of semiconductor dies. The integrated circuit interposer includes a first substrate having a plurality of metal contact sets on its surface, the plurality of metal contact sets including a first metal contact set and a second metal contact set. The integrated circuit interposer also includes one or more patterned waveguide layers forming one or more optical waveguides. The plurality of semiconductor dies are electrically coupled to the plurality of metal contact sets on the first substrate, wherein each semiconductor die includes a semiconductor substrate and circuitry formed on the semiconductor substrate. The plurality of semiconductor dies include a first semiconductor die and a second semiconductor die, the first semiconductor die including a first circuit, the second semiconductor die including a second circuit, the first semiconductor die being electrically coupled to the first metal contact set, and the second semiconductor die being electrically coupled to the second metal contact set. The first circuit is configured to optically communicate with the second circuit via one or more optical waveguides.

[0011] Embodiments may include one or more of the following features. The integrated circuit interposer may include a plurality of modulators and a plurality of photodetectors associated with a plurality of semiconductor dies, wherein the plurality of modulators includes a first modulator and the plurality of photodetectors includes a first photodetector. The first modulator of the integrated circuit interposer may be electrically coupled to one or more metal contacts in a first set of metal contacts and configured to receive a first transmitted electrical signal from a first circuit of the first semiconductor die and modulate light traveling in a first optical waveguide of the integrated circuit interposer based on the first transmitted electrical signal. The first photodetector of the integrated circuit interposer may be electrically coupled to one or more metal contacts in a second set of metal contacts and configured to convert the modulated light traveling in the first optical waveguide of the integrated circuit interposer into a first received electrical signal and transmit the first received electrical signal to a second circuit of the second semiconductor die through one or more metal contacts in the second set of metal contacts.

[0012] The plurality of modulators may include a second modulator, and the plurality of photodetectors may include a second photodetector. The second modulator of the integrated circuit interposer may be electrically coupled to one or more metal contacts in the second set of metal contacts and configured to receive a second transmitted electrical signal from a second circuit of the second semiconductor die, and modulate light traveling in a first or second optical waveguide of the integrated circuit interposer based on the second transmitted electrical signal. The second photodetector of the integrated circuit interposer may be electrically coupled to one or more metal contacts in the first set of metal contacts and configured to convert the modulated light traveling in the first or second optical waveguide of the integrated circuit interposer into a second received electrical signal, and transmit the second received electrical signal to a first circuit of the first semiconductor die through one or more metal contacts in the first set of metal contacts.

[0013] The system may include laser dies deployed on or in a first substrate and configured to provide laser beams directed to one or more optical waveguides.

[0014] Generally, in another aspect, an integrated circuit interposer includes: a semiconductor substrate and a first metal contact layer, the first metal contact layer including: a first metal contact segment and a second metal contact segment, the first metal contact segment including metal contacts configured to be electrically coupled to a first circuit, and the second metal contact segment including metal contacts configured to be electrically coupled to a second circuit. The integrated circuit interposer includes: a first patterning layer including a plurality of individually photomask-patterned metal path segments; and a second patterning layer including a plurality of individually photomask-patterned waveguide segments. The second patterning layer includes: a first waveguide spanning at least one boundary between waveguide segments patterned by individual photomasks; a first modulator coupled to the first waveguide at a first location along the first waveguide for modulating an optical wave in the first waveguide based on a first electrical signal transmitted from a first circuit and received at a first metal contact in a first metal contact segment; and a second modulator coupled to the first waveguide at a second location along the first waveguide for modulating an optical wave in the first waveguide based on a second electrical signal transmitted from a second circuit and received at a second metal contact in either the first or second metal contact segment.

[0015] The implementation may include one or more of the following features. The first modulator and the second modulator may be amplitude modulators configured to use distributed pulse-amplitude modulation to modulate the optical waves in the first waveguide.

[0016] The integrated circuit interposer may include digital logic at the destination of the modulated light wave, which is used to map the analog sum result to the digital sum result.

[0017] Generally, in another aspect, a method of manufacturing an integrated circuit interposer includes: forming a first metal contact layer on a semiconductor wafer, the first metal contact layer including a plurality of metal contact segments at a first surface of the integrated circuit interposer. The metal contact segments include a first metal contact segment and a second metal contact segment, the first metal contact segment including a plurality of metal contacts arranged for electrically coupled to a first semiconductor die via controlled-collapse wafer connection, and the second metal contact segment including a plurality of metal contacts arranged for electrically coupled to a second semiconductor die via controlled-collapse wafer connection. The method includes: forming a first patterned layer on the semiconductor wafer at a first distance from a semiconductor substrate layer, including individually patterning a plurality of metal path segments; and forming a second patterned layer on the semiconductor wafer at a second distance from the semiconductor substrate layer different from the first distance, including individually patterning a plurality of waveguide segments. The second patterned layer includes: a first waveguide spanning at least one boundary between waveguide segments patterned by individual photomasks; a first modulator coupled to the first waveguide at a first location along the first waveguide for modulating an optical wave in the first waveguide based on an electrical signal received at a first metal contact in a first metal contact segment; and a second modulator coupled to the first waveguide at a second location along the first waveguide for modulating an optical wave in the first waveguide based on an electrical signal received at a second metal contact in either the first or second metal contact segment.

[0018] Generally, in another aspect, a method of manufacturing an integrated circuit interposer includes: forming a first metal contact layer on a semiconductor wafer, wherein the first metal contact layer includes a plurality of metal contact segments, the plurality of metal contact segments including: a first metal contact segment and a second metal contact segment, the first metal contact segment including a plurality of metal contacts configured to be electrically coupled to a first circuit, and the second metal contact segment including a plurality of metal contacts configured to be electrically coupled to a second circuit. The method includes forming a first patterning layer on the semiconductor wafer, including individually patterning a plurality of metal path segments; and forming a second patterning layer on the semiconductor wafer, including individually patterning a plurality of waveguide segments. The second patterning layer includes: a first waveguide spanning at least one boundary between waveguide segments patterned by individual photomasks; a first modulator coupled to the first waveguide at a first location along the first waveguide and configured to modulate an optical wave in the first waveguide based on an electrical signal received at a first metal contact in a first metal contact segment; and a second modulator coupled to the first waveguide at a second location along the first waveguide and configured to modulate an optical wave in the first waveguide based on an electrical signal received at a second metal contact in either the first or second metal contact segment.

[0019] Generally, in another aspect, an apparatus includes an interconnect module. The interconnect module includes: a first substrate; a first metal contact layer formed on the first substrate, wherein the first metal contact layer includes a first metal contact configured to be electrically coupled to a first die including circuitry; and a patterned waveguide layer including a plurality of individually photomask-patterned waveguide segments disposed on the substrate, wherein the patterned waveguide layer includes a first waveguide spanning at least one boundary between the individually photomask-patterned waveguide segments. The interconnect module includes: a first modulator coupled to the first waveguide at a first location along the first waveguide and configured to modulate an optical signal traveling in the first waveguide based on a first electrical signal received from the first die at the first metal contact; and a second modulator coupled to the first waveguide at a second location along the first waveguide and configured to modulate the optical signal in the first waveguide based on a second electrical signal received at a second metal contact, the second metal contact being electrically coupled to the first die or a second die including circuitry. The first waveguide enables the optical signal to travel from the source location to the target location across at least one boundary between waveguide segments patterned by individual photomasks, and modulates the optical signal by the first and second modulators as it travels from the source location to the target location.

[0020] Each aspect may include one or more of the following features. The first metal contact layer may include a second metal contact configured to be electrically coupled to a second die including circuitry.

[0021] The first metal contact can be electrically coupled to the first die via controlled collapse wafer connection, and the second metal contact can be electrically coupled to the second die via controlled collapse wafer connection.

[0022] The first metal contact may be located in a first region corresponding to a waveguide segment patterned by a first individual photomask; and the second metal contact may be located in a second region corresponding to a waveguide segment patterned by a second individual photomask, the second waveguide segment patterned by a second individual photomask being different from the first waveguide segment patterned by a first individual photomask.

[0023] The optical signal is then detected to generate the detected signal; and the circuit is configured to map the detected amplitude of the detected signal using a predetermined amplitude scale that indicates the number of modulators through which the modulated signal passes.

[0024] The device may include: a detector configured to detect an optical signal after the optical signal has passed through the first and second modulators to generate a detected signal; and circuitry configured to map the detected phase of the detected signal using a predetermined phase scale that indicates the number of modulators through which the modulated signal passes.

[0025] The device may include: a detector configured to detect an optical signal after the optical signal has passed through the first and second modulators to generate a detected signal; and circuitry configured to map the detected polarization of the detected signal using a predetermined polarization scale that indicates the number of modulators through which the modulated signal passes.

[0026] Each individually patterned waveguide segment can be manufactured by exposing the corresponding mask using a photolithography system. Different individually patterned waveguide segments can be manufactured by different exposures of the same mask or different masks.

[0027] The first metal contact can be electrically coupled to the first die via controlled collapse wafer connection.

[0028] The device may include a first grain.

[0029] The device may include first and second granules.

[0030] In some examples, the first modulator can be configured to modulate the amplitude of the optical signal.

[0031] In some examples, the first modulator can be configured to modulate the phase or polarization of the optical signal.

[0032] The patterned waveguide layer may include: a first individually photomask-patterned waveguide segment, which includes a first portion of a first waveguide that couples a guiding mode to the edge of the first waveguide segment; and a second individually photomask-patterned waveguide segment, which includes a second portion of a first waveguide that couples a guiding mode to the edge of the second waveguide segment.

[0033] The device may include a second metal contact layer, which includes a second metal contact, wherein the first metal contact is disposed on a first side of the substrate and the second metal contact is disposed on a second side of the substrate.

[0034] The interconnect module may include an optoelectronic interposer, wherein the substrate, the first metal contact layer, the patterned waveguide layer, the first modulator and the second modulator are part of the optoelectronic interposer.

[0035] The first substrate may include a semiconductor substrate.

[0036] The interconnect module may include a filter capacitor or a decoupling capacitor electrically coupled to at least one of the first die or the second die.

[0037] Generally speaking, in another aspect, a method includes: modulating an optical signal in a first waveguide at a first location along a first waveguide formed on a first substrate based on a first electrical signal received at a first metal contact electrically coupled to a first die including a circuit; modulating an optical signal in a first waveguide at a second location along the first waveguide based on a second electrical signal received at a second metal contact electrically coupled to a first die or a second die including a circuit; and transmitting the modulated optical signal from a first individually photomask-patterned waveguide segment deployed on the first substrate to a second individually photomask-patterned waveguide segment deployed on the first substrate, wherein the first individually photomask-patterned waveguide segment is fabricated by performing a first exposure on the first photomask using a photolithography system, and the second individually photomask-patterned waveguide segment is fabricated by performing a second exposure on the second photomask using a photolithography system, the first exposure being different from the second exposure, and the first photomask being the same as or different from the second photomask.

[0038] Each aspect may include one or more of the following features. The first metal contact may be located in a first region corresponding to a waveguide segment patterned by a first individual photomask, and the second metal contact may be located in a second region corresponding to a waveguide segment patterned by a second individual photomask.

[0039] The method may include detecting a modulated optical signal at a destination location downstream of the intermediate location, where the optical signal is modulated to generate a detected signal; and mapping the detected amplitude of the detected signal using a predetermined amplitude scale that indicates the number of intermediate locations where the modulated signal is located.

[0040] A first individually patterned waveguide segment can be manufactured by performing a first exposure of a first photomask using a photolithography system, and a second individually patterned waveguide segment can be manufactured by performing a second exposure of a second photomask using a photolithography system. The first exposure may be different from the second exposure, and the first photomask may be the same as or different from the second photomask.

[0041] The first metal contact can be electrically coupled to the first die via controlled collapse wafer connection.

[0042] The first grain may include a semiconductor grain.

[0043] The first substrate may include a semiconductor substrate.

[0044] The second metal contact can be electrically coupled to the second die, and the method can include transmitting a modulated optical signal along a first waveguide along at least one boundary between waveguide segments patterned across individual photomasks.

[0045] The first and second positions along the first waveguide can be located on the same individually patterned waveguide segment.

[0046] The first and second positions along the first waveguide can be located on different individually patterned waveguide segments.

[0047] The method may include filtering a signal on a first die or a second die using a filter capacitor deployed on a first substrate, wherein the first die or the second die includes a second substrate different from the first substrate.

[0048] The method may include decoupling a first circuit portion from a second circuit portion using a decoupling capacitor deployed on a first substrate, wherein the first circuit portion is on a first or second die, and the second circuit portion is on a first or second die.

[0049] Generally, in another aspect, an apparatus includes an interposer. The interposer includes: an interposer substrate; and a first metal contact layer formed on the interposer substrate, wherein the first metal contact layer includes a first metal contact, a second metal contact, and a third metal contact, the first metal contact being configured to be electrically coupled to a first die including a circuit, the second metal contact being configured to be electrically coupled to either the first die or a second die including a circuit, the first die including a first substrate different from the interposer substrate, and the second die including a second substrate different from the interposer substrate. The interposer includes a patterned waveguide layer formed on the interposer substrate, wherein the patterned waveguide layer includes a first waveguide. The interposer layer includes: a first modulator coupled to the first waveguide at a first location along the first waveguide and configured to modulate an optical signal traveling in the first waveguide based on a first electrical signal received at a first metal contact to generate a first modulated optical signal; and a second modulator coupled to the first waveguide at a second location along the first waveguide and configured to modulate the first modulated light wave in the first waveguide based on a second electrical signal received at a second metal contact to generate a second modulated optical signal. The interposer layer also includes: a detector configured to detect the second modulated optical signal to generate a detected signal; and a detection circuit configured to map detected characteristics of the detected signal to an output signal using a predetermined scale indicating the number of modulators that modulate the signal in a predetermined manner, wherein the output signal is electrically coupled to a third contact, and the third contact is electrically coupled to at least one of a first die, a second die, or a third die.

[0050] Each aspect may include one or more of the following features. The first metal contact may be electrically coupled to the first die via a controlled collapse wafer connection.

[0051] The second metal contact can be electrically coupled to the second die via controlled collapse wafer connection.

[0052] The third metal contact can be electrically coupled to the third die via controlled collapse wafer connection.

[0053] The first metal contact layer may include a first metal contact section and a second metal contact section. The first metal contact section may include a plurality of metal contacts arranged for electrical coupling to the first die, and the second metal contact section may include a plurality of metal contacts arranged for electrical coupling to the second die.

[0054] Multiple metal contacts in the first metal contact section can be electrically coupled to the first die via controlled collapse wafer connection.

[0055] Multiple metal contacts in the second metal contact section can be electrically coupled to the second die via controlled collapse wafer connection.

[0056] The device may include a first patterned metal layer formed on an interposer substrate, the first patterned metal layer may include a plurality of individually photomask-patterned metal path segments.

[0057] The patterned waveguide layer may include multiple individually patterned waveguide segments, and the first waveguide may span at least one boundary between the individually patterned waveguide segments.

[0058] The first metal contact may be located in a first region corresponding to a waveguide segment patterned by a first individual photomask; and the second metal contact may be located in a second region corresponding to a waveguide segment patterned by a second individual photomask, the second waveguide segment patterned by a second individual photomask being different from the first waveguide segment patterned by a first individual photomask.

[0059] Generally speaking, in another aspect, an apparatus includes: an interposer configured to perform distributed pulse-amplitude modulation on an optical signal in a first optical waveguide based on a first electrical signal and a second electrical signal, wherein a first die electrically coupled to the interposer receives the first electrical signal, and a second electrical signal is received from either the first die or a second die electrically coupled to the interposer.

[0060] Each aspect may include one or more of the following features. The interposer may include an interposer substrate, and the first die may include a first substrate different from the interposer substrate.

[0061] The second grain may include a second substrate that is different from the interposer substrate.

[0062] The first die can be electrically coupled to the interposer using controlled collapse wafer interconnect.

[0063] The second die can be electrically coupled to the interposer using controlled collapse wafer interconnect.

[0064] The interposer may include: an interposer substrate; and a first metal contact layer formed on the interposer substrate, wherein the first metal contact layer includes a first metal contact, a second metal contact and a third metal contact, the first metal contact being configured to be electrically coupled to a first die, and the second metal contact being configured to be electrically coupled to a first die or a second die.

[0065] The interposer may include a first optical waveguide, a first modulator, and a second modulator. The first modulator may be configured to modulate an optical signal in the first optical waveguide based on a first electrical signal received at a first metal contact. The second modulator may be configured to modulate an optical signal in the first optical waveguide based on a second electrical signal received at a second metal contact.

[0066] The device may include: a detector configured to detect an optical signal after the optical signal has passed through the first and second modulators to generate a detected signal; and a detection circuit configured to map the detected amplitude of the detected signal to an output signal using a predetermined amplitude scale that indicates the number of modulators through which the modulated signal passes.

[0067] The output signal can be electrically coupled to a third contact, which is electrically coupled to at least one of the first, second, or third dies.

[0068] Generally, in another aspect, a method for transmitting information from multiple nodes to at least one destination is provided. The method includes: transmitting a signal having a predetermined initial amplitude from a source onto a transmission medium; modulating the amplitude of the signal at each of a plurality of intermediate locations between the source and the destination using a modulation value selected from a binary set of two possible modulation values, wherein for each intermediate location, the binary set consists of a modulation value of 1 and a predetermined amplitude scaling factor S greater than 0 and less than 1. The method includes: detecting a signal at the destination after the signal transmission has passed through all intermediate locations; and mapping the detected amplitude of the detected signal using a predetermined amplitude scale indicating the number of intermediate locations at which the signal has been modulated by the predetermined amplitude scaling factor.

[0069] Each aspect may include one or more of the following features. The predetermined amplitude scale may include a maximum detected amplitude that is substantially equal to the predetermined initial amplitude, and a minimum detected amplitude that is substantially equal to SN, where N is the number of intermediate positions.

[0070] For each intermediate position, the predetermined amplitude scaling factor S can be different.

[0071] For each intermediate position, the predetermined amplitude scaling factor S can be equal.

[0072] The predetermined scaling factor S can be approximately equal to, where k is the number of intermediate positions.

[0073] The signal transmitted from the source may have a predetermined initial amplitude in each of the plurality of time slots including the first time slot.

[0074] The modulation of the signal amplitude at each of the plurality of intermediate positions can occur within a first time slot after the propagation delay based on the propagation distance between each intermediate position and the source.

[0075] The method may also include maintaining time synchronization among multiple nodes, sources and destinations.

[0076] The transmission medium may include an optical waveguide.

[0077] An optical waveguide may be formed in an integrated circuit interposer including metal contacts arranged for electrically coupling to at least one semiconductor die in a controlled collapse wafer connection.

[0078] Selected modulation values ​​at one or more of the intermediate positions can be provided based on electrical signals from the semiconductor die.

[0079] Generally, in another aspect, a system for transmitting information from multiple nodes to at least one destination is provided. The system includes: a transmission medium; a source configured to transmit a signal having a predetermined initial amplitude onto the transmission medium; and a plurality of amplitude modulators coupled to the transmission medium at respective intermediate locations between the source and the destination, each amplitude modulator being configured to modulate the amplitude of the signal by a selected modulation value from a binary set of two possible modulation values. For each amplitude modulator, the binary set consists of a modulation value of 1 and a predetermined amplitude scaling factor S greater than 0 and less than 1. The system includes: a detector at the destination configured to detect the signal after the signal transmission has passed through all intermediate locations; and circuitry configured to map the detected amplitude of the detected signal using a predetermined amplitude scale indicating the number of intermediate locations at which the signal is modulated by a shared amplitude scaling factor.

[0080] Generally speaking, in another aspect, a method includes: transmitting a signal having predetermined preliminary optical characteristics from a source to a transmission medium; modulating the optical characteristics of the signal at each of a plurality of intermediate locations between the source and the destination by means of a selected modulation value; detecting the signal at the destination after the signal transmission has passed through the intermediate locations; and mapping the detected optical characteristics of the detected signal using a predetermined scale indicating the number of intermediate locations where the signal is modulated.

[0081] Each aspect may include one or more of the following characteristics. Optical properties may include amplitude.

[0082] The modulation optical characteristics may include modulating the amplitude of the signal at each of a plurality of intermediate positions by selecting a modulation value from a binary set of two possible modulation values. For each intermediate position, the binary set consists of a modulation value of 1 and a predetermined amplitude scaling factor S that is greater than 0 and less than 1.

[0083] The detected optical characteristics of the detected signal may include mapping the detected amplitude of the detected signal using a predetermined amplitude scale that indicates the number of intermediate positions of the signal modulated by a predetermined amplitude scaling factor at that location.

[0084] The predetermined amplitude scale may include a maximum detected amplitude that is substantially equal to the predetermined initial amplitude and a minimum detected amplitude that is substantially equal to SN, where N is the number of intermediate positions.

[0085] For each intermediate position, the predetermined amplitude scaling factor S can be different.

[0086] For each intermediate position, the predetermined amplitude scaling factor S can be equal.

[0087] The predetermined scaling factor S can be substantially equal to, and k is the number of intermediate positions.

[0088] The signal transmitted from the source may have a predetermined initial amplitude in each of a plurality of time slots including the first time slot.

[0089] The modulation of the signal amplitude at each of the plurality of intermediate positions can occur within a first time slot after the propagation delay based on the propagation distance between each intermediate position and the source.

[0090] This method may also include maintaining time synchronization among multiple nodes, sources and destinations.

[0091] The transmission medium may include an optical waveguide.

[0092] An optical waveguide may be formed in an integrated circuit interposer including metal contacts arranged for electrically coupling to at least one semiconductor die in a controlled collapse wafer connection.

[0093] The modulation value at one or more intermediate positions can be provided based on the electrical signal from the semiconductor die.

[0094] The modulation optical characteristics may include modulating the amplitude of the signal at each of a plurality of intermediate positions by selecting a modulation value from a binary set of two possible modulation values. For each intermediate position, the binary set consists of a modulation value of 1 and a predetermined amplitude scaling factor S greater than 1.

[0095] Optical properties may include phase or polarization.

[0096] Generally speaking, in another aspect, a method includes: transmitting a signal having predetermined preliminary first optical characteristics and predetermined preliminary second optical characteristics from a source to a transmission medium; modulating the first or second optical characteristics of the signal at each of a plurality of intermediate locations between the source and the destination by means of a selected modulation value; detecting the signal at the destination after the signal transmission has passed through the intermediate locations; and mapping the detected first and second optical characteristics of the detected signal using a predetermined scale indicating the number of intermediate locations where the signal is modulated.

[0097] Each aspect may include one or more of the following features. The first optical characteristic may include amplitude and the second optical characteristic may include phase.

[0098] The first optical characteristic may include amplitude and the second optical characteristic may include polarization.

[0099] The first optical characteristic may include phase and the second optical characteristic may include polarization.

[0100] The signal may have a predetermined preliminary third optical characteristic. The method may include modulating a first, second, or third optical characteristic of the signal at each of a plurality of intermediate locations between the source and the destination by means of a selected modulation value; and mapping the detected first, second, and third optical characteristics of the detected signal using a predetermined scale indicating the number of intermediate locations at which the signal is modulated.

[0101] The first optical characteristic may include amplitude, the second optical characteristic may include phase, and the third optical characteristic may include polarization.

[0102] Generally speaking, in another aspect, a system includes: a transmission medium; a source configured to transmit a signal having predetermined preliminary optical characteristics onto the transmission medium; a plurality of optical characteristic modulators coupled to the transmission medium at respective intermediate positions between the source and the destination; a detector at the destination configured to detect the signal after the signal transmission has passed through the intermediate positions; and circuitry configured to map the detected optical characteristics of the detected signal using a predetermined scale indicating the number of intermediate positions at which the signal is modulated.

[0103] Each aspect may include one or more of the following features. Each optical characteristic modulator may include an amplitude modulator configured to modulate the amplitude of the signal by a selected modulation value from a binary set of two possible modulation values.

[0104] For each amplitude modulator, the binary set may consist of a modulation value of 1 and a predetermined amplitude scaling factor S that is greater than 0 and less than 1.

[0105] For each amplitude modulator, the binary set may consist of a modulation value of 1 and a predetermined amplitude scaling factor S greater than 1.

[0106] Each optical property modulator may include a phase or polarization modulator configured to modulate the phase or polarization of a signal by a selected modulation value from a binary set of two possible modulation values.

[0107] Each aspect may have one or more of the following advantages.

[0108] Data can be modulated onto any of various types of signals. Certain types of signals offer advantages in transmission or processing compared to other types. Examples of different signal types include optical signals corresponding to light waves modulated by signal data, and electrical signals (e.g., voltage or current) corresponding to electrical waveforms modulated by signal data. Various modulations, such as amplitude modulation, phase modulation, or combinations of amplitude and phase modulation, can be used according to a predetermined constellation diagram. Light waves, used as the underlying signal carrier for optical signals, offer certain advantages compared to electrical waveforms used as the underlying signal carrier for electrical signals. For example, light waves typically have a higher bandwidth capacity than electrical waveforms. There are also generally lower power requirements and shorter time delays (or "delays") associated with transmitting data for optical signals over a given distance.

[0109] Optical signals can be used to transmit data between different electronic nodes in a system or device (e.g., computing nodes in a data center or integrated circuits within a device package). However, the complexity associated with using such optical communication links typically includes overhead, including the conversion between optical signals and electrical signals used as inputs and / or outputs of electronic modules. Delays associated with timing synchronization used for signal conversion are also added.

[0110] Some embodiments of the optoelectronic computing platform described herein can reduce the complexity required to integrate communication via optical signals into the platform. As described in more detail below, sets of integrated circuits can be combined in an efficient manner by using large (e.g., wafer-level) optoelectronic interposers. As described in more detail below, techniques for distributed pulse-amplitude modulation (PAM) aggregation can also be used in such optoelectronic computing platforms or other platforms or computing systems to combine communication and computation in an efficient manner.

[0111] Details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the invention will become apparent from the specification, the drawings, and the claims.

[0112] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. In the event of any conflict with a patent application or patent application disclosure incorporated herein by reference, the definition herein shall prevail.

Implementation Method

[0114] Figure 1 illustrates an example of an optoelectronic computing platform 100. The platform 100 includes an array of computing nodes 102, each coupled to an optoelectronic interposer integrated circuit (OIIC) 104. In addition to metal paths providing electrical signal connections between the computing nodes 102 within one or more metal layers, as in a typical electronic interposer IC, the OIIC 104 in this example also includes optical waveguides providing optical signal connections between the computing nodes 102. Manufacturing challenges have been overcome to enable the OIIC 104 to be fabricated on large substrates (e.g., entire semiconductor wafers, such as silicon-on-insulator (SOI) wafers) to support a relatively large number of computing nodes 102 and relatively long waveguides in at least one photonic layer of the OIIC 104. Each computing node 102 is implemented on a semiconductor die, which is connected to OIIC 104 via a controlled collapsed chip connection (or "flip-chip" connection) using conductive bumps (e.g., solder bumps) on an arrangement of metal contacts on the surface of the OIIC. Near the opposite edge of the array of computing nodes 102, there are also input / output (I / O) modules 106 connected to OIIC 104, which enable signals to be coupled into and out of the computing platform 100. The I / O modules 106 enable the computing platform 100 to couple to various devices, including, for example, dynamic random access memory (DRAM) chips or other types of memory devices. To support interfaces to such devices, the I / O modules 106 may include circuitry configured according to any of various device protocols, including DDR SDRAM, PCI(e), USB, Ethernet, etc. In this example, each of the twelve compute nodes 102 in the 3×4 array includes a compute unit 108 (e.g., a CPU or GPU) and a multiplexer (MUX) 110, and each I / O module 106 includes I / O circuitry and a MUX (not shown). When the MUX 110 is coupled to or from the OIIC 104, it enables the selection and routing of electrical signals. On the other side of the OIIC 104 is a package substrate 112, which, for example, provides electrical connections for signals and / or power. This example also shows a row of interface ports 114 near another edge of the array, providing another method for directly coupling signals to or from the OIIC 104. The various features of the OIIC 104 described herein enable power-efficient integration of a variety of functional chips on the wafer-level optoelectronic computing platform 100.

[0115] Figure 2A illustrates an example of a channel interface 200 providing data paths in an OIIC. For compute nodes 202A and 202B that are relatively close to each other, metal paths within the OIIC allow electrical signals to propagate directly on electrical data paths 204 between nodes 202A and 202B (or between the dies formed on which compute nodes 202A and 202B are located). For example, advanced interface bus (AIB) technology for connecting different wafers (or “chiplets”) in a multi-wafer platform can be used to implement electrical data paths 204 on metal paths. In some embodiments, the pattern of the metal path is defined by the pattern of a corresponding photomask, wherein a photolithography system is used to transfer the pattern on the photomask onto the substrate of the optoelectronic interposer integrated circuit. Short distances between nearby compute nodes are defined by a distance less than the length of the longest straight metal path, which can be generated using a single photomask (or “reticle”) used to pattern a single segment of the metal path. For computing nodes that are relatively far apart from each other, or for computing nodes that are relatively far from I / O modules, the optical waveguides within the OIIC enable optical signals, which convert / revert electrical signals from nodes, to propagate between nodes. In Figure 2A, node 202A and I / O module 206, which is far from node 202A, are connected via optical data channels 208. In this example, optical data channels 208 include independent optical paths 209A and 209B (e.g., waveguides) carrying optical signals in opposite directions; however, other examples may include optical paths carrying bidirectional optical signals.

[0116] In some embodiments, the long distance is defined by a distance greater than the longest dimension of a segment patterned by a single photomask. This long optical path provides a low-latency and power-efficient optical data path, avoiding the need for long wires in large (e.g., wafer-level) platforms, which would present insurmountable manufacturing and performance challenges. Platform 100 selects the appropriate type of data path (i.e., electrical or optical) based on the propagation distance between the source and destination. Adjacent computing nodes can utilize the short electrical signal paths provided by OIIC 104. Meanwhile, as shown in this example, computing nodes at any location in the array (on the computing die) can have direct optical connections to I / O modules 206 (on the I / O die) and their connected devices (e.g., DRAM 210 or PCI(e) devices 212), with similar bandwidth and low latency as the short electrical connections between adjacent computing nodes. This breaks the access limitations that the central die might otherwise encounter in large multi-wafer platforms.

[0117] In some embodiments, the conversion between electrical signals and optical signals for the optical channel occurs at a bidirectional transceiver within the photonic layer of OIIC 104. For example, for electro-optical conversion, the bidirectional transceiver may include an optical modulator (e.g., a Mach-Zehnder interferometer) that receives electrical signals (e.g., voltage signals) to control the amplitude modulation of light waves provided by a light source to generate modulated light waves. The light source may be, for example, a laser integrated into platform 100, or a port of an edge coupler or surface grating coupler that receives light waves, for example, from an optical fiber coupled to an external laser. For opto-electrical conversion, the bidirectional transceiver may include a photodetector that converts the optical power of the light waves into a resulting current signal. This current signal can then be converted into a voltage signal within a computing node (e.g., using a transimpedance amplifier). For example, the electrical signal can be transmitted through a through-silicon via (TSV) to or from metal contacts on the surface of OIIC 104.

[0118] Figure 2B illustrates examples of other types of components that may be included in OIIC 230. OIIC 230 includes a metal layer and a waveguide layer 220 formed on a substrate 234. In this example, along with metal interconnects 222 (e.g., some for carrying signals and some for carrying power) and optical waveguide interconnects 224, there is a region 226 including metal capacitors (e.g., 238) and planar inductors. The metal interconnects 222 are capable of interconnecting different electronic integrated circuits (EICs), such as electronic integrated circuits 221A and electronic integrated circuits 221B. For example, electronic integrated circuit 221A may be similar to the arithmetic unit 108 of Figure 1, and electronic integrated circuit 221B may be similar to the multiplexer 110. Electronic integrated circuit 221A performs calculations and transmits data to other arithmetic nodes via electronic integrated circuit 221B and optical waveguide interconnects 224. For example, passive electronic components such as capacitors and inductors can be useful for better utilizing the limited area within each compute die coupled to the OIIC 230. For instance, capacitors can be used for power decoupling in electronic circuits, where it is useful to have the power decoupling capacitors relatively close to the electronic circuitry. These capacitors can be charged and discharged as needed using metal TSVs (not shown) from one of the metal contacts connected to the compute die. These passive components can occupy a relatively large amount of space, and the available space in the OIIC 230 can be more than the available space in the compute die. Because one or more passive components can be placed directly beneath a compute die (such as the EIC 221A) that includes circuitry using one or more passive components, the distance of the metal conductive paths used for electrical connections is relatively short.

[0119] In the example of Figure 2B, EIC 221B modulates the refractive index of a portion of the optical waveguide 224 by applying electrical signals to electrodes 232a and 232b respectively through electrical paths 228a and 228b. This enables EIC 221B to generate modulated optical signals that can be transmitted to another EIC or I / O module 206. Similarly, a photodetector can be coupled to the waveguide, and the electrical output of the photodetector can be electrically coupled to EIC 221B through electrical paths similar to electrical paths 228a or 228b. Electrical paths 228a and 228b include metal contacts electrically coupled to EIC 221B.

[0120] Figure 3 illustrates an example of an arrangement 300 of paths within a layer of OIIC 310. Because the size of arrangement 300 is larger than a typical pattern produced by a single scaled-down mask during semiconductor manufacturing, arrangement 300 can be fabricated using multiple individually mask-patterned segments formed using one or more masks. In some embodiments, wafer-level OIIC 310 is formed over a large portion of the entire semiconductor wafer. A grid of metal paths 302 provides a power distribution grid within the layer of OIIC 310. The power distribution grid can be connected to one or more power sources, for example, at the edges of arrangement 300 and / or via TSVs distributed across arrangement 300. At regular intervals, each set of metal contacts 304 provides a dense array of connections for individual compute dies in controlled-collapse wafer connections. Short metal paths 306 between arrays of corresponding edge rows of contacts for different compute dies are used for electrical channels (e.g., advanced interface bus channels). While it may be difficult to fabricate the metal path 306 for data crossing the boundaries between segments patterned across multiple individual photomasks due to pattern misalignment, a metal path 302 for power can be fabricated to cross those boundaries because the metal path is much thicker. In some embodiments, the metal path 302 and the metal path 306 may be fabricated in different metal layers or in a single metal layer.

[0121] In at least one photonic layer separated from one or more metal layers, a long waveguide 308 spanning the boundary between multiple individually patterned photomask segments is used as the optical channel. Techniques can be used to reduce losses that might otherwise be associated with misalignment between adjacent patterned photomask segments, such as by gradually increasing the waveguide width near the crossing (up to approximately 10 micrometers, with a loss of only about 0.004 dB), as described in the article “Wafer-scale silicon photonic switches beyond die size limit” by Seok et al., which is incorporated herein by reference. Transmitter and receiver devices, or transceiver devices that include both transmitter and receiver devices, are placed at regular intervals to enable optical signals to be transmitted and received from different computing dies. In some embodiments, multiple photonic layers exist, having waveguides in one direction in one layer and waveguides in a vertical direction in another layer. Alternatively, in some embodiments, a photonic device, such as a directional switch, may be present at the intersection between two waveguides. The switch can be controlled by an electrical signal provided through the computing node, or by an electrical signal provided by a controller outside the computing node.

[0122] As described herein, some implementations of OIICs can offer a number of advantages. One potential advantage is the ability to support a large number of optical channels due to the density of optical waveguides that can be fabricated in one or more photonic layers of the OIIC. The achieved density may be limited by the spacing achievable in the fabrication of an array of parallel waveguides, but can be on the order of hundreds or even thousands of waveguides. This results in a number of optical signal paths that can be much larger than those provided by fiber arrays, which can be limited to a much smaller number (e.g., about 16 or 32). The size of the OIIC also has advantages. Computational nodes that are more sensitive to manufacturing yield (e.g., 102) remain small (the size of a single photomask-patterned die). OIICs with better manufacturing yields (e.g., 104) can be larger (e.g., most of a 30cm × 30cm complete wafer). Thus, the OIIC is large enough to accommodate a large number of die-wafer computational nodes, but also small enough to be much more compact than platforms using external photonic couplers, modulators, and switches. The number of slots required within the platform for photonic devices can also be reduced, leaving more available space for small-chip computing nodes. Optoelectronic computing platforms using OIICs can be highly flexible by combining any of various types of computing nodes, provided the die size and contact / bump arrangement remain the same. Such platforms can be used in a variety of applications, such as neuromorphic computing or high-performance computing, or in custom applications that can benefit from dense and flexible optical network substrates to reduce power requirements, manage heat dissipation, increase signal bandwidth, and / or reduce communication latency.

[0123] In addition to supporting communication between different computing nodes or between computing nodes and I / O modules, the optical channels provided by OIIC can also be used for efficient forms of distributed computing that can be performed using components within OIIC. An example of such distributed computing is distributed pulse-amplitude modulation (PAM) aggregation, which can be used with optical signals transmitted via optical transmission media (such as optical waveguides in OIIC), or with various other types of signals transmitted via other suitable transmission media. As an example of distributed PAM aggregation, consider a system comprising multiple nodes that produce partial results (e.g., different addends or different partial sums), which need to be added together to produce an aggregated sum at a specific destination in the system.

[0124] Figure 4A illustrates an example movement of partial results 400 in a distributed summation computation. Each box represents a different computation node in the system, and the arrows indicate the direction of movement of partial results in the system. The example computation performed is the following dot product of two vectors, which can be part of a larger computation, such as the multiplication of a vector and a matrix or the multiplication of two matrices. For example, vector x can be an input vector, and vector w can be a row element of a matrix of weight values. Each of the initial set of computation nodes 402a, 402b, 402c, 402d (collectively referred to as 402) represented in the top row computes a different product of the individual elements of the vectors in the dot product. The partial results from these computations then move to the other computation nodes 404a, 404b (collectively referred to as 404) represented in the middle row, each of the other computation nodes computes the sum of those partial results. The partial results from these computations then move to another computation node 406, which computes the final sum to produce the total result, which may then need to be moved to different parts of the system. This is merely an example layout where the cumulative path sinks the results to the center in the physical implementation. In general, non-shrinkable architectures may require the bus to have a length that cannot be scaled efficiently.

[0125] Figure 4B shows an alternative example of the movement of partial result 400, where the summation of the final result stage is performed using a transmission medium 408 (e.g., an optical waveguide). As the signal propagates down the waveguide, the amplitudes of different pulses within the signal are modulated, such that the final result is represented by the final amplitude. This example leverages the inflow symmetry of the computation and utilizes the distributed PAM aggregation technique described in more detail below to rapidly provide results (e.g., near the speed of light) by performing addition through multiple binary modulation operations to produce multi-level PAM modulation results.

[0126] Figures 5A, 5B, and 5C illustrate different stages of an example data flow in a distributed vector matrix multiplication (VMM) system with multiple multiplication modules, labeled according to the weight values ​​of the matrices used in the VMM computation, where the weights correspond to the rows of the matrix and the weights correspond to the columns of the matrix. The distributed vector matrix multiplication (VMM) system is configured to perform the following matrix operations:

[0127] In Figure 5A, the four elements of vector x are distributed and multiplied with different weight values ​​of the matrix. For example, operation node 500a performs multiplication w1, 1·x1, operation node 500b performs multiplication w2, 1·x1, operation node 500c performs multiplication w3, 1·x1, and operation node 500d performs multiplication w4, 1·x1. Operation node 502a performs multiplication w1, 2·x2, operation node 502b performs multiplication w2, 2·x2, operation node 502c performs multiplication w3, 2·x2, and operation node 502d performs multiplication w4, 2·x2. Operation node 504a performs multiplication w1, 3·x3, operation node 504b performs multiplication w2, 3·x3, operation node 504c performs multiplication w3, 3·x3, and operation node 504d performs multiplication w4, 3·x3. Operator node 506a performs multiplication w1, 4·x4, operator node 506b performs multiplication w2, 4·x4, operator node 506c performs multiplication w3, 4·x4, and operator node 504d performs multiplication w4, 4·x4.

[0128] In Figure 5B, after multiplying the vector element values ​​with their corresponding weight values, the adder tree works inward toward the center of the multiplication module to produce multiple distinct partial sum results. Adders 510a, 510b, 510c, 510d (collectively referred to as 510) and adders 512a, 512b, 512c, 512d (collectively referred to as 512) are provided to produce partial sum results. For example, adder 510a adds the outputs of operation nodes 500a and 502a to produce a sum w1,1·x1 + w1,2·x2; adder 510b adds the outputs of operation nodes 500b and 502b to produce a sum w2,1·x1 + w2,2·x2; adder 510c adds the outputs of operation nodes 500c and 502c to produce a sum w3,1·x1 + w3,2·x2; and adder 510d adds the outputs of operation nodes 500d and 502d to produce a sum w4,1·x1 + w4,2·x2. Adder 512a sums the outputs of operands 504a and 506a to produce a sum w1,3·x3 + w1,4·x4; adder 512b sums the outputs of operands 504b and 506b to produce a sum w2,3·x3 + w2,4·x4; adder 512c sums the outputs of operands 504c and 506c to produce a sum w3,3·x3 + w3,4·x4; adder 512d sums the outputs of operands 504d and 506d to produce a sum w4,3·x3 + w4,4·x4. In this example, adders 510 and 512 perform addition in the electrical domain. Adder 510 is electrically coupled to operands 500 and 502. Adder 512 is electrically coupled to operands 504 and 506.

[0129] In Figure 5C, for each element of the output vector, the partial sums within each row are added together to accumulate the sum through distributed PAM aggregation performed on the corresponding transmission media 514A, 514B, 514C, and 514D (e.g., the corresponding optical waveguides). Figure 5C shows a top view of an example of computational nodes (e.g., 500, 502, 504, 506) and adders (e.g., 510, 512) overlaid on top of the transmission media 514A, 514B, 514C, and 514D. In this example, adders 510a and 512a modulate the light traveling in the transmission medium 514A according to, for example, a distributed PAM aggregation technique described in more detail below. Similarly, adders 510b and 512b modulate the light traveling in transmission medium 514B, adders 510c and 512c modulate the light traveling in transmission medium 514C, and adders 510d and 512d modulate the light traveling in transmission medium 514D, all according to, for example, a distributed PAM aggregation technique. In this example, computing nodes 500, 502, 504, and 506 are not optically coupled to transmission media 514A, 514B, 514C, and 514D. By synchronously driving the optical channels (e.g., within OIIC), results can be accumulated simultaneously and transmitted to the appropriate destination computing node within the optoelectronic computing platform.

[0130] A simplified example of distributed PAM aggregation technology is described with reference to Figure 6. In this example, there are two nodes 600 and 602, each with a 1-bit value, and those values ​​are added to the summation result transmitted along the transmission medium 606 to the destination D604. Node 600 has 1 bit, and node 602 has 1 bit. Table 608 in Figure 6 shows different possible combinations of the 1-bit value with the corresponding values ​​of the result bit 610 and carry bit 612, which together represent the sum of the two 1-bit values. There is also an amplitude value 614, which corresponds to the amplitude of the modulated signal that has been transmitted from the source to the transmission medium 606 and passed through the corresponding modulator at each node in the node. The signal begins with a predetermined initial amplitude, which in this example is represented as amplitude 1. As the signal passes through each node, if a 1-bit value is "0", the node allows the signal to pass without changing its amplitude (corresponding to modulation value 1), or if a 1-bit value is "1", the node modulates the signal by a predetermined amplitude scaling factor (or "modulation depth") m, where . Therefore, distributed summation is performed using distributed multiplication.

[0131] In this example, the predetermined modulation depth is 0.5. Ignoring any tiny propagation losses that may be associated with transmission through the modulator at each node, if both nodes have a 1-bit value of 0, the amplitude of the signal at destination D604 will still be 1. If one node has a 1-bit value of 1 and the other node has a 1-bit value of 0, the amplitude of the signal at destination D604 will be 0.5. If both nodes have a 1-bit value of 1, the amplitude of the signal at destination D604 will be 0.25. In other examples, the predetermined modulation depth may be different, but if the predetermined modulation depth is the same at each node, the amplitude value will represent a count of the number of nodes with a value of "1". This technique can be scaled to any number of nodes at corresponding intermediate positions along the transmission medium 600. Any number of 1-bit values ​​can also be transmitted in the sequential time slot to add multi-bit values.

[0132] Figure 7 illustrates an example of a digital logic circuit 700, which, for the example of Figure 6, can be used to map the detected analog amplitude summation result 710 to a digital summation result 712. At the input, the analog amplitude summation result 710 can be provided, for example, as the voltage of a transimpedance amplifier driven by the photocurrent of a photodetector that detects light waves in an optical waveguide used as the transmission medium 606. Only two comparators 702A and 702B with different comparison thresholds (0.75 and 0.375, respectively) are needed to distinguish the three different possible amplitude values. The circuit then uses XOR gates 704a, 704b and AND gate 706, along with synchronous digital circuit elements (e.g., flip-flops) 708, to provide the result 712 and an indication of each new frame 714. The timing for each bit corresponds to the timing of the individual time slots of the light wave, which can be controlled by a high-speed clock signal 716.

[0133] In this example, the output of XOR gate 704a is the result bit (similar to result bit 610 in Figure 6), and the output of AND gate 706 is the carry bit (similar to carry bit 612). XOR gate 704b and synchronous digital circuit element 708 are used to add the previous carry bit (if any) to the result bit of a string of 1-bit values ​​being added. For example, using digital logic circuit 700, two nodes can add arbitrarily long multi-bit values ​​one bit at a time. A similar principle can be used to implement logic circuits with additional logic gates that map the detected analog magnitude sum to a digital sum when more than two nodes are adding values ​​together.

[0134] For example, any of various analog-to-digital converter (ADC) circuits can be used to convert the detected analog amplitude sum result into a digital sum, such as circuits that implement a nonlinear fast ADC using a combination of comparators and encoding. Figure 18A shows an example of circuit 1800 for calculating the result of adding four addends from four corresponding nodes, where multiple bit addends are provided one bit at a time in consecutive time slots. In this example, a scaling factor of 0.8 is used. If all four bits of the four addends are 0, the amplitude of the light traveling in the transmission medium (e.g., similar to 606 in Figure 6) is 1. If one bit of the four bits of the four addends is 1, the amplitude of the light traveling in the transmission medium is 0.8. If two bits of the four bits of the four addends are 1, the amplitude of the light traveling in the transmission medium is 0.64. If three bits of the four bits of the four addends are 1, the amplitude of the light traveling in the transmission medium is 0.512. If all four bits of the four addends are 1, the amplitude of the light traveling in the transmission medium is 0.41. A threshold of 0.9 can be used to distinguish between values ​​1 and 0.8. A threshold of 0.72 can be used to distinguish between values ​​0.8 and 0.64. A threshold of 0.58 can be used to distinguish between values ​​0.64 and 0.512. A threshold of 0.46 can be used to distinguish between values ​​0.512 and 0.41.

[0135] The photodetector 1802 receives light from the transmission medium and provides a photocurrent to the transimpedance amplifier 1804, which generates a voltage signal proportional to the photocurrent. In this example, there are four comparators 1806A-1806D that compare the voltage signal (at the negative terminal) with four corresponding voltage thresholds (at the positive terminal) of 0.46, 0.58, 0.72, and 0.9. If the voltage signal is less than the threshold, a binary output corresponding to 1 is provided; if the voltage signal is greater than the threshold, a binary output corresponding to 0 is provided. The circuit 1800 also includes an encoder circuit 1808 that stores values ​​in a result register 1810 (e.g., a set of flip-flops) and performs a binary summation on a string of 1-bit values ​​provided by the comparators 1806A-1806D until a final result is produced.

[0136] For example, encoder circuit 1808 could be a thermometer-to-binary encoder (e.g., a fat-tree encoder, which can be implemented using a reference sheet). Additional information on fat-tree encoders can be found in the article "FAT TREE ENCODER DESIGN FOR ULTRA-HIGH SPEED FLASH A / D CONVERTERS" by Daegyu Lee et al., presented at the 45th Midwest Symposium on Circuits and Systems, 2002, the entire contents of which are incorporated herein by reference. In general, thermometer-to-binary conversion has a logarithmic circuit depth (as a function of the number N of the addend), and the binary output has a bit width equal to ceiling(log_2(N+1)) (rounded up (log_2(N+1))) (e.g., 4 bits in this example). Therefore, in this example, there are 3 bits to represent the possible summation results. This example of thermometer-to-binary encoding implicitly illustrates the output result bit and the carry bit, as the next most significant bit after the result bit is shifted.

[0137] Circuit 1800 includes a register interface 1812, which is used by encoder circuit 1808 when partial results are added to and written back to the appropriate portion of result register 1810. In this addition step, the operands are the existing value in register 1810 and the output of encoder circuit 1808. Register interface 1812 may have a sliding window, which can be implemented, for example, by using a shift register as result register 1810.

[0138] Figures 18B to 18F show an example of a digital logic circuit 1800 used to add four addends 31, 7, 27, and 3 (encoded as binary values ​​11111, 00111, 11011, and 00011, respectively), producing a final result 68 (encoded as binary value 01000100). Figure 18B shows the state of circuit 1800, where the four 1-bit values ​​of the least significant bit of each addend are 1,1,1,1. The comparator output corresponding to this least significant analog value (from the highest threshold to the lowest threshold) is 1,1,1,1. The bits written to the result register 1810 (for bit positions 2,1,0) are 1,0,0 (representing 1+1+1+1=4).

[0139] Figure 18C shows the state of circuit 1800, where the four 1-bit values ​​of the least significant bit of each addend are 1,1,1,1. The comparator output corresponding to this least significant analog value (from the highest threshold to the lowest threshold) is 1,1,1,1. The bits written to the result register 1810 (for bit positions 3,2,1) are 1,1,0 (representing 1+1+1+1+2 (carry) = 6).

[0140] Figure 18D shows the state of circuit 1800, where the four 1-bit values ​​of the least significant bit of each addend are 1,1,0,0. The comparator output corresponding to this intermediate level analog value (from the highest threshold to the lowest threshold) is 1,1,0,0. The bits written to result register 1810 (for bit positions 4,3,2) are 1,0,1 (representing 1+1+0+0+3 (carry) = 5).

[0141] Figure 18E shows the state of circuit 1800, where the four 1-bit values ​​of the least significant bit of each addend are 1,0,1,0. The comparator output corresponding to this intermediate level analog value (from the highest threshold to the lowest threshold) is 1,1,0,0. The bits written to result register 1810 (for bit positions 5,4,3) are 1,0,0 (representing 1+0+1+0+2 (carry) = 4).

[0142] Figure 18F shows the state of circuit 1800, where the four 1-bit values ​​of the least significant bit of each addend are 1,0,1,0. The comparator output corresponding to this intermediate level analog value (from the highest threshold to the lowest threshold) is 1,1,0,0. The bits written to result register 1810 (for bits 6,5,4) are 1,0,0 (representing 1+0+1+0+2 (carry) = 4). The final result of the sum stored in result register 1810 is the binary value 01000100.

[0143] Figure 8A is a diagram 800 of an example of a distributed PAM aggregation technique for adding three 1-bit values ​​b0, b1, and b2 held by nodes N0, N1, and N2, respectively. The sum of the three 1-bit values ​​b0, b1, and b2 is transmitted along the transmission medium 606 to the destination D604.

[0144] Figure 8B shows Table 802 for aggregating 1-bit values ​​(e.g., b0, b1, b2) from three nodes (e.g., N0, N1, N2) at an intermediate position along the transmission medium (e.g., 606). As in the previous example, since only the sum is needed at the destination, the fact that different possible combinations of 1-bit values ​​can result in the same received signal amplitude is irrelevant. In this example, there are only four different possible amplitude values, so the number of comparisons required in this case is three instead of two. In general, the number of comparisons required will scale with the number of nodes. There will also be additional results and / or carry bits required by additional nodes. The figure shows amplitude value 804, where a predetermined modulation depth of 0.5 is used for each node, as in the previous example, but also shows optimized amplitude value 806, where a predetermined modulation value of 0.66 (rounded to two decimal places) is used for each node. Using an amplitude based on a modulation depth of 0.5, the step size between the two minimum values ​​0.125 and 0.25 is 0.125. In contrast, with an optimized amplitude of 806 based on a modulation depth of 0.66, the larger step size between the two minimum values ​​of 0.29 and 0.44 is 0.15.

[0145] The following is an example of the calculation used to determine the optimal value of the predetermined modulation depth m, where k is the number of addends (and the number of modulators at the midpoint of the transmission medium). The step size (also called the minimum step size) between the different amplitudes that are closest to each other and therefore most difficult to resolve for a given signal-to-noise ratio is the step size between all k modulators applying the predetermined modulation depth and k-1 modulators applying the predetermined modulation depth. Therefore, the optimal modulation depth is determined by maximizing this minimum step size, as described below. Thus, the optimization technique is characterized by the optimal modulation depth increasing as more nodes are added, which makes the modulation more power efficient. The minimum step size can be increased when the predetermined amplitude scaling factor S is substantially equal to a certain value, compared to when the amplitude scaling factor S is some other value. Here, the term "substantially equal to" a certain value means within ±10% of that value.

[0146] Figure 9 shows examples of different graphs showing how the minimum step size varies with the modulation depth of each modulator for a given value of k. Curve 901 is used, curve 902 is used, curve 903 is used, and curve 904 is used. Here, k is the number of addends being summed, and also the number of modulators at the midpoint along the transmission medium. For each value of k, the optimal predetermined modulation depth occurs at the maximum value of the minimum step size. By maximizing the minimum step size that needs to be resolved between the two closest amplitude values, the sensitivity to noise is reduced, which optimizes performance by reducing the error rate for a given signal-to-noise ratio.

[0147] The following is an example of calculation, which shows that as k increases, the optimal modulation depth applied by the nodes approaches 1 / e (relatively quickly).

[0148] Figure 10 illustrates an example configuration 1000 for using distributed PAM aggregation in a system 1014 that performs matrix multiplication using 8-bit multiplication. Data elements in the input vector and coefficients in the weight matrix are electrically multiplied to a digital value. Spatially distributed partial sums exist, which are added in summing modules 1002 to produce a 17-bit intermediate result. There are eight summing modules 1002a to 1002h. Summing modules 1002a, 1002b, 1002c, and 1002d can be similar to, for example, adders 510a, 510b, 510c, and 510d of Figure 5C, respectively. Summing modules 1002e, 1002f, 1002g, and 1002h can be similar to, for example, adders 512a, 512b, 512c, and 512d, respectively. Using a modulator 1006 (such as a high-speed underdriven binary segmented carrier injection modulator (SCIM)), the bits of the sum of each segment are serialized in a serializer 1004 and aggregated onto an optical transmission medium 1005 to provide a sequence of optical intensities that is received at a light-to-electric receiver module 1008, which includes circuitry for generating amplified analog electrical signals (e.g., continuous-time linear equalizer (CTLE) circuitry and / or transimpedance amplifier (TIA) circuitry). The transmission medium 1005 may be similar to the transmission medium 514 of Figure 5C.

[0149] For example, the partial sums generated by summing module 1002a and the partial sums generated by summing module 1002e are aggregated onto optical transmission medium 1005a using modulators 1006a and 1006e. This is similar to the example in FIG5, where the partial sums generated by adder 510a and the partial sums generated by adder 512a are aggregated onto transmission medium 514A. Similarly, the partial sums generated by summing module 1002b and the partial sums generated by summing module 1002f are aggregated onto optical transmission medium 1005b using modulators 1006b and 1006f. The partial sums generated by summing module 1002c and the partial sums generated by summing module 1002g are aggregated onto optical transmission medium 1005c using modulators 1006c and 1006g. The partial sums generated by summing module 1002d and the partial sums generated by summing module 1002h are aggregated onto optical transmission medium 1005d using modulators 1006d and 1006h.

[0150] In some embodiments, different bits of the 17-bit intermediate result are aggregated onto the transmission medium 1005 in different time slots. The serializer 1004 serializes the 17-bit intermediate result into 17 1-bit values. The 17 1-bit values ​​of the intermediate result generated by the summing module 1002a and the 17 1-bit values ​​of the intermediate result generated by the summing module 1002e are aggregated onto the transmission medium 1005 in 17 consecutive time slots. For example, in time slot 0, bits 0 of summing module 1002a and bits 0 of summing module 1002e are aggregated onto the transmission medium 1005a. In time slot 1, bits 1 of summing module 1002a and bits 1 of summing module 1002e are aggregated onto the transmission medium 1005a. In time slot 16, bits 16 of summing module 1002a and bits 16 of summing module 1002e are aggregated onto transmission medium 1005a. The optical signals on optical transmission medium 1005 in time slots 0 to 16 represent bits 0 to 16 of the sum of the 17-bit intermediate results generated by summing module 1002a and the 17-bit intermediate results generated by summing module 1002e.

[0151] The analog digital module 1010 provides a digital sum carry value, which is provided to the deserializer 1012 to be deserialized into an 18-bit sum 1016. Carrier injection absorptive amplitude modulators are useful in some embodiments, for example, due to thermal stability, which helps to reproduce a predetermined modulation depth at multiple modulators. In some embodiments, no single binary segmented carrier injection modulator (SCIM) is driven at full scale (hence the term "underdriven"), thus significantly reducing the power / area of ​​the modulator driver. A variety of alternative configurations can be used. For example, different types of modulators, including Mach-Zehnder interferometers or ring modulators, can be used. Some configurations can use multiple optical wavelengths, enabling the use of lower serializer-deserializer (SERDES) frequencies.

[0152] Figures 11A and 11B respectively show various example layouts 1100A and 1100B of a system using distributed PAM aggregation technology to distribute and aggregate partial results. In Figure 11A, input light 1006 is distributed to branches of four waveguides 1108a, 1108b, 1108c, and 1108d. Along the branch of waveguide 1108a, there are two data modulators 1102a and 1102e, with a photodiode 1104a at the end of waveguide 1108a. The data modulators 1102a and 1102e can be similar to the modulators 1006a and 1006e of Figure 10. Along the branch of waveguide 1108b, there are two data modulators 1102b and 1102f, with a photodiode 1104b at the end of waveguide 1108b. Data modulators 1102b and 1102f can be similar to modulators 1006b and 1006f in Figure 10. Two data modulators 1102c and 1102g exist along a branch of waveguide 1108c, with a photodiode 1104c at the end of waveguide 1108c. Data modulators 1102c and 1102g can be similar to modulators 1006c and 1006g in Figure 10. Two data modulators 1102d and 1102h exist along a branch of waveguide 1108d, with a photodiode 1104d at the end of waveguide 1108d. Data modulators 1102d and 1102h can be similar to modulators 1006d and 1006h in Figure 10.

[0153] In Figure 11B, two data modulators 1102 are present along each of the four waveguide branches, with photodiodes 1104 at the ends of the waveguides, and additional photodiodes 1104 at the ends of the waveguides. These photodiodes are separated from the four waveguides, thus providing multiple destinations for each branch (e.g., to locally store the results of aggregation). For example, the optical signal in waveguide 1108a is separated and sent to photodiodes 1104a and 1104e, the optical signal in waveguide 1108b is separated and sent to photodiodes 1104b and 1104f, the optical signal in waveguide 1108c is separated and sent to photodiodes 1104c and 1104g, and the optical signal in waveguide 1108d is separated and sent to photodiodes 1104d and 1104h. Therefore, the destination where the results are provided is not necessarily at the ends of the waveguides.

[0154] Various other systems can use distributed PAM aggregation technology to perform the summation of binary values ​​in different time slots along the transmission medium. For example, in addition to wafer-level systems that use an interposer to provide optical waveguides as the transmission medium, systems can also use optical fibers as the transmission medium to connect different nodes in a data center (e.g., server racks). Moreover, some systems can use electrical modulators to aggregate binary values ​​encoded on electrical signals transmitted along electrical transmission lines.

[0155] In some embodiments, as in the example of FIG. 1, two or more computing nodes 102 may be fabricated on the same substrate and then connected to OIIC 104 via controlled collapse wafer interconnect. Different computing nodes 102 do not necessarily reside on separate dies; a single semiconductor die can support multiple computing nodes 102. In some embodiments, each of the computing nodes 102 includes circuitry formed on a substrate, and this circuitry is electrically and optically coupled to OIIC 104 via the substrate of the computing node 102, for example, through vertical electrical contacts such as vias and vertical coupling elements. The computing nodes 102 do not necessarily need to be "flipped" to be connected to OIIC 104.

[0156] In some embodiments, distributed computation can use distributed phase modulation aggregation techniques, in which two or more nodes of phase modulators are positioned along the path of an optical signal. The optical signal begins with a predetermined initial phase, such as phase 0. As the signal passes through each node, if a 1-bit value is “0”, the node allows the signal to pass without changing the phase of the signal (corresponding to a modulation value of 1); if a 1-bit value is “1”, the node modulates the signal with a predetermined phase delay. Thus, distributed phase delay operation is used to perform distributed summation operation. At the destination, decoding circuitry is configured to map the detected phase of the detected signal using a predetermined phase scale, which indicates the number of modulators that modulate the signal through which it modulates.

[0157] In some embodiments, distributed computation can use distributed polarization modulation aggregation techniques, in which two or more nodes of polarization modulators are positioned along the path of an optical signal. The optical signal begins with a predetermined initial polarization. As the signal passes through each node, if a 1-bit value is “0”, the node allows the signal to pass without changing the polarization of the signal (corresponding to a modulation value of 1); if a 1-bit value is “1”, the node modulates the signal by a predetermined polarization change. Thus, a distributed polarization correction operation is used to perform a distributed summation operation. At the destination, the decoding circuit is configured to map the detected polarization of the detected signal using a predetermined polarization scale, which indicates the number of modulators that modulate the signal through which it modulates.

[0158] In some embodiments, distributed computing can use the aggregation of two or more optical characteristics, such as amplitude and phase, amplitude and polarization, or phase and polarization. For example, a process for distributed computing may include transmitting a signal having predetermined preliminary first optical characteristics and predetermined preliminary second optical characteristics from a source to a transmission medium; modulating the first or second optical characteristics of the signal with a selected modulation value at each of a plurality of intermediate locations between the source and the destination; detecting the signal at the destination after the signal transmission has passed through the intermediate locations; and mapping the detected first and second optical characteristics of the detected signal using a predetermined scale indicating the number of intermediate locations where the signal was modulated. For example, the first optical characteristic may be amplitude, and the second optical characteristic may be phase. For example, the first optical characteristic may be amplitude, and the second optical characteristic may be polarization. For example, the first optical characteristic may be phase, and the second optical characteristic may be polarization.

[0159] Figure 12 is a flowchart of an example of a process 1200 for modulating an optical signal. Process 1200 includes the following steps:

[0160] Step 1202: At a first location along a first waveguide formed on a first substrate, an optical signal in the first waveguide is modulated based on a first electrical signal received at a first metal contact electrically coupled to a first die including a circuit. For example, the first waveguide may be similar to waveguide 514 of FIG. 5C or transmission medium 606 of FIG. 6, the first substrate may be similar to packaging substrate 112 (FIG. 1) or substrate 234 (FIG. 5C), the first metal contact may be similar to metal contact 236a or 236b, the first die may be similar to EIC 221B or node N0, and the first location may be similar to the location of node N0600.

[0161] Step 1204: At a second location along the first waveguide, an optical signal in the first waveguide is modulated based on a second electrical signal received at a second metal contact electrically coupled to the first die or a second die including circuitry. The second die may resemble node N1602, and the second location may resemble the location of node N1602.

[0162] Step 1206: Transmit the modulated optical signal from a first individually patterned waveguide segment deployed on the first substrate to a second individually patterned waveguide segment deployed on the first substrate. The first individually patterned waveguide segment is fabricated by performing a first exposure of the first photomask using a photolithography system, and the second individually patterned waveguide segment is fabricated by performing a second exposure of the second photomask using a photolithography system. The first exposure is different from the second exposure, and the first photomask may be the same as or different from the second photomask.

[0163] Process 1200 may include one or more of the following features. For example, a first metal contact may be located in a first region corresponding to a waveguide segment patterned by a first individual photomask, and a second metal contact may be located in a second region corresponding to a waveguide segment patterned by a second individual photomask.

[0164] Process 1200 may include: detecting a modulated optical signal at a destination location downstream of an intermediate location, wherein the optical signal is modulated to generate a detection signal at the intermediate location; and mapping the detected amplitude of the detected signal using a predetermined amplitude scale indicating the number of intermediate locations where the modulated signal is located. For example, a photodiode 1104 (FIGs 11A, 11B) may be used to detect the modulated optical signal. Digital logic circuitry similar to circuit 700 in FIG. 7 may be used to map the detected amplitude of the detected signal using a predetermined amplitude scale.

[0165] The first individually patterned waveguide segment can be fabricated by performing a first exposure of the first photomask using a photolithography system, and the second individually patterned waveguide segment can be fabricated by performing a second exposure of the second photomask using a photolithography system, wherein the first exposure is different from the second exposure. The first photomask may be the same as or different from the second photomask.

[0166] The first metal contact can be electrically coupled to the first die via a controlled-collapse wafer connection. For example, this can be similar to the example of FIG1, where each computing node 102 is implemented on a semiconductor die connected to OIIC 104 via a controlled-collapse wafer connection.

[0167] The first die may include a semiconductor die. The first substrate may include a semiconductor substrate. The second metal contact may be electrically coupled to the second die, and the method may include transmitting a modulated optical signal along the first waveguide across at least one boundary between waveguide segments patterned by individual photomasks.

[0168] The first position and the second position along the first waveguide can be located on the same individually patterned waveguide segment. The first position and the second position along the first waveguide can be located on different individually patterned waveguide segments.

[0169] Process 1200 may include filtering a signal on a first die or a second die using a filter capacitor deployed on a first substrate, wherein the first die or the second die includes a second substrate different from the first substrate. For example, the first substrate may be similar to substrate 234 of FIG. 2B, the filter capacitor may be similar to capacitor 238, and the first die may be similar to EIC 221A.

[0170] Process 1200 may include decoupling a first circuit portion from a second circuit portion using a decoupling capacitor deployed on a first substrate, wherein the first circuit portion is on a first or second die, and the second circuit portion is on a first or second die. For example, the first substrate may be similar to substrate 234 of FIG. 2B, the decoupling capacitor may be similar to capacitor 238, the first die may be similar to EIC 221A, and the second die may be similar to EIC 221B.

[0171] Figure 13 is a flowchart of an example of a process 1300 for manufacturing an interposer layer for an integrated circuit. Process 1300 includes the following steps.

[0172] Step 1302: A first metal contact layer is formed on the semiconductor wafer. The first metal contact layer includes a plurality of metal contact segments at a first surface of the integrated circuit interposer. The metal contact segments include a first metal contact segment and a second metal contact segment. The first metal contact segment includes a plurality of metal contacts arranged for electrically coupling to a first semiconductor die via controlled-collapse wafer connection. The second metal contact segment includes a plurality of metal contacts arranged for electrically coupling to a second semiconductor die via controlled-collapse wafer connection.

[0173] Step 1304: Form a first patterned layer on the semiconductor wafer at a first distance from the semiconductor substrate layer, including patterning multiple metal path segments individually.

[0174] Step 1306: Forming a second patterned layer on a semiconductor wafer at a second distance from the semiconductor substrate layer that is different from the first distance, including individually patterning a plurality of waveguide segments. The second patterned layer includes: a first waveguide spanning at least one boundary between individually patterned waveguide segments; a first modulator coupled to the first waveguide at a first location along the first waveguide for modulating an optical wave in the first waveguide based on an electrical signal received at a first metal contact in a first metal contact segment; and a second modulator coupled to the first waveguide at a second location along the first waveguide for modulating an optical wave in the first waveguide based on an electrical signal received at a second metal contact in either the first metal contact segment or a second metal contact in the second metal contact segment.

[0175] Figure 14 is a flowchart of another example of a process 1400 for manufacturing an interposer layer for an integrated circuit. Process 1400 includes the following steps.

[0176] Step 1402: Form a first metal contact layer on a semiconductor wafer, wherein the first metal contact layer includes a plurality of metal contact segments. The metal contact segments include a first metal contact segment and a second metal contact segment, the first metal contact segment including a plurality of metal contacts configured to be electrically coupled to a first circuit, and the second metal contact segment including a plurality of metal contacts configured to be electrically coupled to a second circuit.

[0177] Step 1404: Form a first patterning layer on a semiconductor wafer, including patterning multiple metal path segments individually.

[0178] Step 1406: Forming a second patterned layer on a semiconductor wafer, including individually patterning a plurality of waveguide segments. The second patterned layer includes: a first waveguide spanning at least one boundary between individually patterned waveguide segments; a first modulator coupled to the first waveguide at a first location along the first waveguide and configured to modulate an optical wave in the first waveguide based on an electrical signal received at a first metal contact in a first metal contact segment; and a second modulator coupled to the first waveguide at a second location along the first waveguide and configured to modulate an optical wave in the first waveguide based on an electrical signal received at a second metal contact in either the first or second metal contact segment.

[0179] Figure 15 is a flowchart of an example of a process 1500 for transmitting information from multiple nodes to at least one destination. Process 1500 includes the following steps:

[0180] Step 1502: Transmit a signal with a predetermined initial amplitude from the source to the transmission medium. The transmission medium may be similar to transmission medium 408 (Fig. 4B), 514 (Fig. 5C), 606 (Fig. 6, 8A), 514 (Fig. 5C), 1005 (Fig. 10) or 1108 (Fig. 11).

[0181] Step 1504: Modulate the amplitude of the signal at each of a plurality of intermediate locations between the source and the destination by selecting a modulation value from a binary set of two possible modulation values, wherein for each intermediate location, the binary set includes: modulation value 1 and a predetermined amplitude scaling factor S greater than 0 and less than 1.

[0182] Step 1506: After the signal transmission has passed through all intermediate locations, detect the signal at the destination. For example, photodiode 1104 (Figures 11A, 11B) can be used to detect the signal at the destination.

[0183] Step 1508: Map the detected amplitude of the detected signal using a predetermined amplitude scale, which indicates the number of intermediate positions of the signal modulated by a predetermined amplitude scaling factor at that location. For example, digital logic circuitry similar to circuit 700 in FIG7 can be used to map the detected amplitude of the detected signal using a predetermined amplitude scale.

[0184] Process 1500 may include one or more of the following features. The predetermined amplitude scale may include a maximum detected amplitude that is substantially equal to the predetermined initial amplitude, and a minimum detected amplitude that is substantially equal to SN, where N is the number of intermediate positions.

[0185] In some examples, the predetermined amplitude scaling factor S may be different for each intermediate position. In some examples, the predetermined amplitude scaling factor S may be equal for each intermediate position. The predetermined amplitude scaling factor may be substantially equal to , where is the number of intermediate positions.

[0186] The signal transmitted from the source can have a predetermined initial amplitude in each of the plurality of time slots, including the first time slot. Based on the propagation distance between each intermediate position and the source, after a propagation delay, the amplitude of the signal at each of the plurality of intermediate positions can be modulated in the first time slot.

[0187] Process 1500 may include maintaining time synchronization among multiple nodes, sources, and destinations. The transmission medium may include an optical waveguide. The optical waveguide may be formed in an integrated circuit interposer including metal contacts arranged for electrically coupling to at least one semiconductor die via controlled-collapse wafer connections. Selected modulation values ​​at one or more intermediate locations may be provided based on electrical signals from the semiconductor die.

[0188] Figure 16 is a flowchart of an example of a process 1600 for transmitting information from multiple locations to at least one destination. Process 1600 includes the following steps:

[0189] Step 1602: Transmit a signal with predetermined preliminary optical characteristics from the source to the transmission medium.

[0190] Step 1604: Modulate the optical properties of the signal at each of a plurality of intermediate locations between the source and the destination by selecting a modulation value.

[0191] Step 1606: After the signal transmission passes through the intermediate position, detect the signal at the destination.

[0192] Step 1608: Use a predetermined scale to map the detected optical characteristics of the detected signal, the predetermined scale indicating the number of intermediate positions of the modulated signal therein.

[0193] Process 1600 may include one or more of the following features. Optical characteristics may include amplitude. Modulation optical characteristics may include modulating the amplitude of the signal at each of a plurality of intermediate positions by selecting a modulation value from a binary set of two possible modulation values, wherein for each intermediate position, the binary set includes: modulation value 1, and a predetermined amplitude scaling factor S greater than 0 and less than 1.

[0194] The detected optical characteristics of the detected signal may include mapping the detected amplitude of the detected signal using a predetermined amplitude scale, which indicates the number of intermediate positions at which the signal is modulated by a predetermined amplitude scaling factor. The predetermined amplitude scale may include a maximum detected amplitude substantially equal to a predetermined initial amplitude, and a minimum detected amplitude substantially equal to SN, where N is the number of intermediate positions.

[0195] In some examples, the predetermined amplitude scaling factor may be different for each intermediate position. In some examples, the predetermined amplitude scaling factor S may be equal for each intermediate position. The predetermined amplitude scaling factor S may be substantially equal to the number of intermediate positions.

[0196] The signal transmitted from the source can have a predetermined initial amplitude in each of the plurality of time slots, including the first time slot. Based on the propagation distance between each intermediate position and the source, after a propagation delay, the amplitude of the signal at each of the plurality of intermediate positions can be modulated in the first time slot.

[0197] Process 1600 may include maintaining time synchronization among multiple nodes, sources, and destinations. The transmission medium may include an optical waveguide. The optical waveguide may be formed in an integrated circuit interposer including metal contacts arranged for electrically coupling to at least one semiconductor die via controlled-collapse wafer interconnects.

[0198] Selected modulation values ​​at one or more intermediate locations can be provided based on electrical signals from the semiconductor die. Modulation optics can include modulating the amplitude of the signal at each of the plurality of intermediate locations by selecting a modulation value from a binary set of two possible modulation values, wherein for each intermediate location, the binary set includes: a modulation value of 1 and a predetermined amplitude scaling factor S greater than 1. For example, an optical amplifier providing optical gain (e.g., a semiconductor optical amplifier or a doped fiber amplifier) ​​can be used to achieve an amplitude scaling factor S > 1.

[0199] Optical properties may include phase or polarization.

[0200] Figure 17 is a flowchart of an example of a process 1700 for transmitting information from multiple locations to at least one destination. Process 1700 includes the following steps:

[0201] Step 1702: Transmit the signal having predetermined preliminary first optical characteristics and predetermined preliminary second optical characteristics from the source to the transmission medium.

[0202] Step 1704: Modulate the first or second optical properties of the signal at each of a plurality of intermediate locations between the source and the destination by selecting a modulation value.

[0203] Step 1706: After the signal transmission passes through the intermediate position, detect the signal at the destination.

[0204] Step 1708: Use a predetermined scale to map the detected first and second optical characteristics of the detected signal, the predetermined scale indicating the number of intermediate positions of the modulated signal therein.

[0205] Process 1700 may include one or more of the following features. In some examples, the first optical characteristic may include amplitude, and the second optical characteristic may include phase. In some examples, the first optical characteristic may include amplitude, and the second optical characteristic may include polarization. In some examples, the first optical characteristic may include phase, and the second optical characteristic may include polarization.

[0206] The signal may have a predetermined preliminary third optical characteristic. Process 1600 may include modulating a first, second, or third optical characteristic of the signal at each of a plurality of intermediate locations between the source and the destination by a selected modulation value; and mapping the detected first, second, and third optical characteristics of the detected signal using a predetermined scale, the predetermined scale indicating the number of intermediate locations at which the signal is modulated. The first optical characteristic may include amplitude, the second optical characteristic may include phase, and the third optical characteristic may include polarization.

[0207] The systems and operations described in this specification can be implemented in digital electronic circuits or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations thereof. Embodiments of the subject matter described in this specification can be implemented using one or more modules of computer program instructions encoded on a computer-readable medium that are executed by or control the operation of a data processing device. The computer-readable medium can be a manufactured product, such as a hard disk drive in a computer system or an optical disc sold through retail channels, or an embedded system. The computer-readable medium can be acquired separately and subsequently encoded with one or more modules of computer program instructions, for example, by transmitting one or more modules of computer program instructions over a wired or wireless network. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination thereof.

[0208] A computer program (also known as a program, software, software application, script, or code) may be written in any programming language (including compiled or interpreted languages, declarative or procedural languages) and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored as part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., a file that stores portions of one or more modules, subroutines, or code). A computer program may be deployed to execute on a single computer, or on multiple computers located on a website or distributed across multiple websites and interconnected by a communications network.

[0209] The processes and logic flows described in this specification can be executed by one or more programmable processors that execute one or more computer programs to perform functions by manipulating input data and producing output. The processes and logic flows can also be executed by dedicated logic circuits, and the device can also be implemented as dedicated logic circuits, such as FPGAs (Field Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits).

[0210] Some of the systems described in this specification can provide photoelectric platforms and / or distributed PAM aggregation capabilities for the systems disclosed in U.S. Patent Application 16 / 431,167, filed June 4, 2019 and published as US20190370652, and U.S. Patent Application 17 / 204,320, filed March 17, 2021 and published as US20210201126. The entire contents of the above patent applications and published applications are incorporated herein by reference. For example, each of one or more computing units 108 in Figure 1 may include the artificial neural network computing system 100 of Figure 1A in US20210201126, the system 104 of Figure 1F, the system 300 of Figure 3A, the system 302 of Figure 3B, the system 400 of Figure 4A, the system 500 of Figure 5, the system 700 of Figure 7, the system 900 of Figure 9, the optoelectronic computing system 1800 of Figure 18, the system 1900 of Figure 19A, the system 1920 of Figure 19B, the system 2110 of Figure 21B, the system 2300A of Figure 23A, the system 2300B of Figure 23B, and the system 2300C of Figure 23C. The system 2400A of Figure 24A, the system 2400B of Figure 24B, the system 2400C of Figure 24C, the system 2400D of Figure 24D, the system 2400E of Figure 24E, the system 2600 of Figure 26, the system 2700 of Figure 27, the system 2800 of Figure 28, the system 2900 of Figure 29, the system 3000 of Figure 30, the system 3100 of Figure 31, the system 3200 of Figure 32A, the system 3500 of Figure 35A, the system 3600 of Figure 36, the system 3700 of Figure 37, the system 3800 of Figure 38, or the system 4000 of Figure 41, or some of the elements of the systems mentioned above. Each of one or more operational nodes 102 may also include optoelectronic elements in addition to electronic circuitry. Each of one or more operational nodes 102 may be coupled to the optoelectronic interposer integrated circuit 104 in a manner similar to how integrated circuit 4604 is coupled to integrated circuit 4602 as shown in FIG. 46 of US20210201126, or in a manner similar to how integrated circuit 4702 is coupled to integrated circuit 4602 as shown in FIG. 47. Each of one or more operational nodes 102 may include two or more integrated circuits stacked together, as shown in FIGS. 48 and 49 of US20210201126.

[0211] In some embodiments, the optoelectronic interposer integrated circuit 104 may be similar to the interposer 208 of Figures 2A, 2B, 2C, 2D, 2F, 2G, 3, 5C, 11A, and 11B, the interposer 702 of Figure 7, the integrated circuit 802 used as the interposer shown in Figures 8A and 8B, and the integrated circuit 902 used as the interposer shown in Figures 9A, 9B, and 9C in U.S. Provisional Patent Application No. 63 / 123,338, filed December 9, 2020 (the entire contents of which are incorporated herein by reference), the interposer 702 of Figure 7, the integrated circuit 802 used as the interposer shown in Figures 8A and 8B, and the integrated circuit 902 used as the interposer shown in Figures 9A, 9B, and 9C.

[0212] Various types of components can be mounted on the nic interposer integrated circuit 104, such as laser 212, thermoelectric cooler 216, lens 220, photonic circuit 224, digital chip 232 or digital storage module 234 (e.g., a stack of multiple dynamic random access memory (DRAM) chips, as in a high bandwidth memory (HBM) chip), as shown in Figure 2A of US 63 / 123,338.

[0213] Although this disclosure has been described in conjunction with certain embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which should be given the broadest interpretation to cover all such modifications and equivalent structures permitted by law. [Simplified Explanation of the Diagram]

[0113] This disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, by convention, the various features in the drawings are not drawn to scale. Instead, for clarity, the dimensions of the various features are arbitrarily enlarged or reduced. Figure 1 is a schematic diagram of an example of an optoelectronic computing platform. Figure 2A is a schematic diagram of an example of a data channel provided by an optoelectronic interposer IC. Figure 2B is a schematic diagram of an example optoelectronic interposer IC including passive electronic components. Figure 3 is a schematic diagram of an example of an optoelectronic interposer IC. Figures 4A and 4B are schematic diagrams of examples of the movement of partial results in distributed summation calculations. Figures 5A, 5B, and 5C are schematic diagrams of examples of data flow in a distributed computing architecture. Figure 6 is a schematic diagram of an example of distributed PAM aggregation technology. Figure 7 is a circuit diagram of an example digital logic used to map analog summation results to digital summation results. Figure 8 is a table of examples of bits being summed to produce analog amplitude. Figure 9 is a collection of graphs showing the minimum step size as a function of modulation depth. Figure 10 is a schematic diagram of an example system configuration. Figures 11A and 11B are schematic diagrams of the example system layout. Figures 12 through 17 are flowcharts. Figure 18A is a diagram illustrating an example of the general architecture of a digital logic circuit used to map an analog sum result to a data sum result. Figures 18B through 18F are diagrams illustrating examples of the state of the digital logic circuit when used to add four addends and map the analog sum result to a data sum result. Similar reference numerals and designations in the various figures indicate similar elements.

Claims

1. An integrated circuit interposer, comprising: A semiconductor substrate layer; A first metal contact layer, located on a first surface of the integrated circuit interposer, includes a plurality of metal contact segments, the plurality of metal contact segments including: a first metal contact segment including a plurality of metal contacts arranged for electrically coupling to a first semiconductor die via a controlled-collapse wafer connection; and a second metal contact segment including a plurality of metal contacts arranged for electrically coupling to a second semiconductor die via a controlled-collapse wafer connection; a first patterning layer, located at a first distance from the semiconductor substrate layer, including a plurality of individually photomask-patterned metal path segments; and a second patterning layer, located at a second distance from the semiconductor substrate layer different from the first distance, including a plurality of individually photomask-patterned waveguide segments, the second patterning layer including: a first waveguide spanning at least one boundary between the plurality of individually photomask-patterned waveguide segments. A first modulator coupled to the first waveguide at a first location along the first waveguide for modulating an optical wave in the first waveguide based on an electrical signal received at a first metal contact in the first metal contact segment; and a second modulator coupled to the first waveguide at a second location along the first waveguide for modulating the optical wave in the first waveguide based on an electrical signal received at a second metal contact in either the first or second metal contact segment.

2. The integrated circuit interposer as described in claim 1, wherein, The plurality of individually patterned waveguide segments include: a first waveguide segment comprising a first portion of the first waveguide coupled to an edge of the first waveguide segment; and a second waveguide segment comprising a second portion of the first waveguide coupled to an edge of the second waveguide segment.

3. The integrated circuit interposer as requested in item 1 or 2, wherein, The plurality of individually patterned metal path segments include a first metal path segment that overlaps with at least a portion of the first metal contact segment and at least a portion of the second metal contact segment, and provides at least one metal path between at least one metal contact of the first metal contact segment and at least one metal contact of the second metal contact segment.

4. The integrated circuit interposer as described in claim 3, wherein, The plurality of individually patterned metal path segments include a second metal path segment that overlaps with at least a portion of the first metal contact segment but does not overlap with any portion of the second metal contact segment, and provides at least one metal path connected to at least one metal contact of the first metal contact segment.

5. The integrated circuit interposer of claim 1 or 2 further includes a second metal contact layer located on a second surface of the integrated circuit interposer, including a plurality of metal contact segments.

6. The integrated circuit interlayer of claim 1 or 2 further includes at least one capacitor or inductor electrically coupled to at least one of the first semiconductor die or the second semiconductor die.

7. The integrated circuit interposer as requested in item 1 or 2, wherein, The first modulator and the second modulator are amplitude modulators configured to modulate the light wave in the first waveguide with the same predetermined amplitude scaling factor.

8. An integrated circuit interposer, comprising: A semiconductor substrate; A first metal contact layer comprising: a first metal contact segment including a plurality of metal contacts configured to be electrically coupled to a first circuit; and a second metal contact segment including a plurality of metal contacts configured to be electrically coupled to a second circuit; a first patterning layer including a plurality of individually photomask-patterned metal path segments; and a second patterning layer including a plurality of individually photomask-patterned waveguide segments, the second patterning layer comprising: a first waveguide spanning at least one boundary between the plurality of individually photomask-patterned waveguide segments; a first modulator coupled to the first waveguide at a first location along the first waveguide for modulating an optical wave in the first waveguide based on a first electrical signal transmitted from the first circuit and received at a first metal contact in the first metal contact segment; and a second modulator coupled to the first waveguide at a second location along the first waveguide for modulating the optical wave in the first waveguide based on a second electrical signal transmitted from the second circuit and received at a second metal contact in either the first metal contact segment or the second metal contact segment.

9. The integrated circuit interposer as described in claim 8, wherein, The first modulator and the second modulator are amplitude modulators configured to use distributed pulse-amplitude modulation to modulate the light wave in the first waveguide.

10. The integrated circuit interposer of claim 9, comprising a digital logic at a destination of the modulated light wave for mapping an analog sum result to a digital sum result.

11. A photoelectric computing system, comprising: An integrated circuit interposer includes: a first substrate having a plurality of metal contact sets on a surface of the first substrate, the plurality of metal contact sets including a first metal contact set and a second metal contact set; and one or more patterned waveguide layers forming one or more optical waveguides, the one or more optical waveguides including a first optical waveguide; a plurality of semiconductor dies electrically coupled to the plurality of metal contact sets on the first substrate, each semiconductor die including a semiconductor substrate and a circuit formed on the semiconductor substrate; wherein the plurality of semiconductor dies include a first semiconductor die and a second semiconductor die, the first semiconductor die including a first circuit, the second semiconductor die including a second circuit, the first semiconductor die being electrically coupled to the first metal contact set, and the second semiconductor die being electrically coupled to the second metal contact set; wherein the integrated circuit interposer receives a first transmission electrical signal from the first circuit of the first semiconductor die, and modulates light in the first optical waveguide of the integrated circuit interposer based on the first transmission electrical signal, and wherein the first circuit is configured to optically communicate with the second circuit through the one or more optical waveguides.

12. The optoelectronic computing system as described in request item 11, wherein, The integrated circuit interposer includes a plurality of modulators and a plurality of photodetectors associated with the plurality of semiconductor dies. The plurality of modulators includes a first modulator, and the plurality of photodetectors includes a first photodetector. The first modulator of the integrated circuit interposer is electrically coupled to one or more metal contacts in a first set of metal contacts. The first photodetector of the integrated circuit interposer is electrically coupled to one or more metal contacts in a second set of metal contacts and is configured to convert modulated light traveling in the first optical waveguide of the integrated circuit interposer into a first received electrical signal, and to transmit the first received electrical signal to the second circuit of the second semiconductor die through one or more metal contacts in the second set of metal contacts.

13. The optoelectronic computing system as described in request item 12, wherein, The plurality of modulators includes a second modulator, and the plurality of photodetectors includes a second photodetector; wherein the second modulator of the integrated circuit interposer is electrically coupled to one or more metal contacts in the second set of metal contacts and is configured to receive a second transmitted electrical signal from the second circuit of the second semiconductor die, and modulate light traveling in the first optical waveguide of the integrated circuit interposer based on the second transmitted electrical signal; and wherein the second photodetector of the integrated circuit interposer is electrically coupled to one or more metal contacts in the first set of metal contacts and is configured to convert the modulated light traveling in the first optical waveguide of the integrated circuit interposer into a second received electrical signal, and transmit the second received electrical signal to the first circuit of the first semiconductor die through one or more metal contacts in the first set of metal contacts.

14. The optoelectronic computing system of any one of claims 11 to 13, comprising a laser die deployed on or in the first substrate, and configured to provide a laser beam directed to the one or more optical waveguides.

15. A method for manufacturing an interposer layer of an integrated circuit, comprising: A first metal contact layer is formed on a semiconductor wafer. The first metal contact layer, located on a first surface of the integrated circuit interposer, includes a plurality of metal contact segments, each including: a first metal contact segment comprising a plurality of metal contacts arranged for electrically coupling to a first semiconductor die via a controlled-collapse wafer connection; and a second metal contact segment comprising a plurality of metal contacts arranged for electrically coupling to a second semiconductor die via a controlled-collapse wafer connection. A first patterned layer is formed on the semiconductor wafer at a first distance from a semiconductor substrate layer, including individually patterning a plurality of metal path segments; and a second patterned layer is formed on the semiconductor wafer at a second distance from the semiconductor substrate layer, different from the first distance, including individually patterning a plurality of waveguide segments. The second patterned layer includes: a first waveguide spanning at least one boundary between the plurality of individually patterned waveguide segments. A first modulator coupled to the first waveguide at a first location along the first waveguide for modulating an optical wave in the first waveguide based on an electrical signal received at a first metal contact in the first metal contact segment; and a second modulator coupled to the first waveguide at a second location along the first waveguide for modulating the optical wave in the first waveguide based on an electrical signal received at a second metal contact in either the first or second metal contact segment.

16. A method for manufacturing an integrated circuit interposer, comprising: A first metal contact layer is formed on a semiconductor wafer, wherein the first metal contact layer includes a plurality of metal contact segments, the plurality of metal contact segments including: a first metal contact segment including a plurality of metal contacts configured to be electrically coupled to a first circuit; a second metal contact segment including a plurality of metal contacts configured to be electrically coupled to a second circuit; a first patterning layer is formed on the semiconductor wafer, including individually patterning a plurality of metal path segments; and a second patterning layer is formed on the semiconductor wafer, including individually patterning a plurality of waveguide segments, the second patterning layer including: a first waveguide spanning at least one boundary between the plurality of waveguide segments patterned by individual photomasks; A first modulator coupled to the first waveguide at a first location along the first waveguide and configured to modulate an optical wave in the first waveguide based on an electrical signal received at a first metal contact in the first metal contact segment; and a second modulator coupled to the first waveguide at a second location along the first waveguide and configured to modulate the optical wave in the first waveguide based on an electrical signal received at a second metal contact in either the first or second metal contact segment.

17. An integrated circuit device, comprising: An interconnect module includes: a first substrate; a first metal contact layer formed on the first substrate, wherein the first metal contact layer includes a first metal contact configured to be electrically coupled to a first die including a circuit; a patterned waveguide layer including a plurality of individually photomask-patterned waveguide segments disposed on the substrate, wherein the patterned waveguide layer includes a first waveguide spanning at least one boundary between the plurality of individually photomask-patterned waveguide segments; a first modulator coupled to the first waveguide at a first location along the first waveguide and configured to modulate an optical signal traveling in the first waveguide based on a first electrical signal received from the first die at the first metal contact; and a second modulator coupled to the first waveguide at a second location along the first waveguide and configured to modulate the optical signal in the first waveguide based on a second electrical signal received at a second metal contact, the second metal contact being electrically coupled to the first die or a second die including a circuit. The first waveguide enables the optical signal to travel from a source location to a target location across at least one boundary between the plurality of individually patterned waveguide segments, and when the optical signal travels from the source location to the target location, the optical signal is modulated by the first modulator and the second modulator.

18. An integrated circuit arrangement as claimed in claim 17, wherein, The first metal contact layer includes a second metal contact configured to be electrically coupled to the second die including the circuit.

19. An integrated circuit arrangement as claimed in claim 18, wherein, The first metal contact is electrically coupled to the first die via a controlled collapse wafer connection, and the second metal contact is electrically coupled to the second die via a controlled collapse wafer connection.

20. An integrated circuit arrangement as claimed in any of claims 17 to 19, wherein, The first metal contact is located in a first region corresponding to a first individually patterned waveguide segment, and the second metal contact is located in a second region corresponding to a second individually patterned waveguide segment, the second individually patterned waveguide segment being different from the first individually patterned waveguide segment.

21. An integrated circuit arrangement as claimed in any one of claims 17 to 19, comprising: A detector is configured to detect the optical signal after the optical signal transmission has passed through the first modulator and the second modulator to generate a detected signal; And a circuit configured to map a detected amplitude of the detected signal using a predetermined amplitude scale, wherein the predetermined amplitude scale indicates the number of modulators through which the optical signal is modulated.

22. An integrated circuit arrangement as claimed in any one of claims 17 to 19, comprising: A detector is configured to detect the optical signal after the optical signal transmission has passed through the first modulator and the second modulator to generate a detected signal; And a circuit configured to map a detected phase of the detected signal using a predetermined phase scale, wherein the predetermined phase scale indicates the number of modulators through which the optical signal is modulated.

23. An integrated circuit arrangement as claimed in any one of claims 17 to 19, comprising: A detector is configured to detect the optical signal after the optical signal has been transmitted through the first modulator and the second modulator to generate a detected signal; and a circuit is configured to map a detected polarization of the detected signal using a predetermined polarization scale, wherein the predetermined polarization scale indicates the number of modulators through which the optical signal is modulated.

24. An integrated circuit arrangement as claimed in any of claims 17 to 19, wherein, Each individually patterned waveguide segment is fabricated by exposing a corresponding mask using a photolithography system. Different individually patterned waveguide segments are fabricated by exposing the same mask or different masks.

25. An integrated circuit arrangement as claimed in any of claims 17 to 19, wherein, The first metal contact is electrically coupled to the first die via a controlled collapse wafer connection.

26. An integrated circuit device as claimed in any one of claims 17 to 19, comprising the first die.

27. An integrated circuit arrangement as claimed in claim 18 or 19, comprising the first die and the second die.

28. An integrated circuit arrangement as claimed in any one of claims 17 to 19, wherein the first modulator is configured to modulate the amplitude of the optical signal.

29. An integrated circuit arrangement as claimed in any one of claims 17 to 19, wherein the first modulator is configured to modulate the phase or polarization of the optical signal.

30. An integrated circuit arrangement as claimed in any of claims 17 to 19, wherein, The patterned waveguide layer includes: a first individually photomask-patterned waveguide segment including a first portion of the first waveguide coupled to an edge of the first waveguide segment; and a second individually photomask-patterned waveguide segment including a second portion of the first waveguide coupled to an edge of the second waveguide segment.

31. The integrated circuit arrangement of claim 17, including a second metal contact layer comprising second metal contacts, wherein the first metal contacts are disposed on a first side of the substrate and the second metal contacts are disposed on a second side of the substrate.

32. An integrated circuit arrangement as claimed in any of claims 17 to 19, wherein, The interconnect module includes an optoelectronic interposer layer, wherein the substrate, the first metal contact layer, the patterned waveguide layer, the first modulator, and the second modulator are parts of the optoelectronic interposer layer.

33. An integrated circuit arrangement as claimed in any of claims 17 to 19, wherein, The first substrate includes a semiconductor substrate.

34. An integrated circuit arrangement as claimed in any of claims 17 to 19, wherein, The interconnect module includes a filter capacitor or a decoupling capacitor electrically coupled to at least one of the first die or the second die.

35. A method for modulating an optical signal, comprising: An optical signal is modulated in the first waveguide at a first location along a first waveguide formed on a first substrate based on a first electrical signal received at a first metal contact electrically coupled to a first die including a circuit; the optical signal is modulated in the first waveguide at a second location along the first waveguide based on a second electrical signal received at a second metal contact electrically coupled to the first die or a second die including a circuit; and the modulated optical signal is transmitted from a first individually photomask-patterned waveguide segment deployed on the first substrate to a second individually photomask-patterned waveguide segment deployed on the first substrate, wherein the first individually photomask-patterned waveguide segment is fabricated by performing a first exposure on a first photomask using a photolithography system, and the second individually photomask-patterned waveguide segment is fabricated by performing a second exposure on a second photomask using the same photolithography system, the first exposure being different from the second exposure, and the first photomask being the same as or different from the second photomask.

36. The method for modulating optical signals as claimed in claim 35, wherein, The first metal contact is located in a first region corresponding to the waveguide segment patterned by the first individual photomask, and the second metal contact is located in a second region corresponding to the waveguide segment patterned by the second individual photomask.

37. The method of modulating an optical signal as described in claim 35 or 36, comprising: The modulated optical signal is detected at a destination location downstream of a plurality of intermediate locations, the optical signal being modulated at the plurality of intermediate locations to generate a detected signal; and a detected amplitude of the detected signal is mapped using a predetermined amplitude scale, wherein the predetermined amplitude scale indicates the number of intermediate locations at which the optical signal is modulated.

38. The method for modulating optical signals as claimed in claim 35 or 36, wherein, A waveguide segment patterned by a first photomask is fabricated by performing a first exposure on a first photomask using a photolithography system, and a waveguide segment patterned by a second photomask is fabricated by performing a second exposure on a second photomask using the same photolithography system. The first exposure is different from the second exposure, and the first photomask may be the same as or different from the second photomask.

39. The method for modulating optical signals as claimed in claim 35 or 36, wherein, The first metal contact is electrically coupled to the first die via a controlled collapse wafer connection.

40. The method for modulating optical signals as claimed in claim 35 or 36, wherein, The first grain comprises a semiconductor grain.

41. The method of modulating an optical signal as claimed in claim 35 or 36, wherein one of the first substrates comprises a semiconductor substrate.

42. The method for modulating optical signals as claimed in claim 35 or 36, wherein, The second metal contact is electrically coupled to the second die, and the method includes transmitting the modulated optical signal along the first waveguide along at least one boundary between multiple individually patterned waveguide segments.

43. The method for modulating an optical signal as described in claim 42, wherein, The first and second positions along the first waveguide are located on the same individually patterned waveguide segment.

44. The method for modulating an optical signal as claimed in claim 42, wherein, The first and second positions along the first waveguide are located on waveguide segments patterned by different individual photomasks.

45. The method of modulating an optical signal as claimed in claim 35 or 36, comprising filtering a signal on the first die or the second die using a filter capacitor disposed on the first substrate, wherein, The first or second grain includes a second substrate that is different from the first substrate.

46. ​​The method of modulating an optical signal as claimed in claim 35 or 36, comprising decoupling a first circuit portion from a second circuit portion using a decoupling capacitor disposed on the first substrate, wherein, The first circuit portion is on the first die or the second die, and the second circuit portion is on the first die or the second die.

47. An integrated circuit device, comprising: An interposer layer includes: an interposer substrate; a first metal contact layer formed on the interposer substrate, wherein the first metal contact layer includes a first metal contact, a second metal contact, and a third metal contact, the first metal contact being configured to be electrically coupled to a first die including a circuit, the second metal contact being configured to be electrically coupled to the first die or a second die including a circuit, the first die including a first substrate different from the interposer substrate, and the second die including a second substrate different from the interposer substrate; a patterned waveguide layer formed on the interposer substrate, wherein the patterned waveguide layer includes a first waveguide; and a first modulator coupled to the first waveguide at a first location along the first waveguide and configured to modulate an optical signal traveling in the first waveguide based on a first electrical signal received at the first metal contact to generate a first modulated optical signal. A second modulator coupled to the first waveguide at a second location along the first waveguide and configured to modulate the first modulated optical signal in the first waveguide based on a second electrical signal received at the second metal contact to generate a second modulated optical signal; a detector configured to detect the second modulated optical signal to generate a detected signal; and a detection circuit configured to map a detected characteristic of the detected signal to an output signal using a predetermined scale, wherein the predetermined scale indicates the number of modulators that modulate the optical signal in a predetermined manner, and wherein the output signal is electrically coupled to the third metal contact, and the third metal contact is electrically coupled to at least one of the first die, the second die, or a third die.

48. An integrated circuit arrangement as claimed in claim 47, wherein, The first metal contact is electrically coupled to the first die via a controlled collapse wafer connection.

49. An integrated circuit arrangement as claimed in claim 48, wherein, The second metal contact is electrically coupled to the second die via a controlled collapse wafer connection.

50. An integrated circuit arrangement as claimed in claim 49, wherein, The third metal contact is electrically coupled to the third die via a controlled collapse wafer connection.

51. An integrated circuit arrangement as claimed in any of claims 47 to 50, wherein, The first metal contact layer includes a first metal contact segment and a second metal contact segment. The first metal contact segment includes a plurality of metal contacts arranged for electrical coupling to the first die, and the second metal contact segment includes a plurality of metal contacts arranged for electrical coupling to the second die.

52. The integrated circuit arrangement as claimed in claim 51, wherein, The plurality of metal contacts in the first metal contact section are electrically coupled to the first die via a controlled collapse wafer connection.

53. An integrated circuit arrangement as claimed in claim 52, wherein, The plurality of metal contacts in the second metal contact section are electrically coupled to the second die via a controlled collapse wafer connection.

54. The integrated circuit arrangement of claim 51 includes a first patterned metal layer formed on the interposer substrate, the first patterned metal layer including a plurality of individually photomask-patterned metal path segments.

55. An integrated circuit arrangement as claimed in claim 54, wherein, The patterned waveguide layer includes multiple individually patterned waveguide segments, and the first waveguide spans at least one boundary between the multiple individually patterned waveguide segments.

56. An integrated circuit arrangement as claimed in claim 54, wherein, The first metal contact is located in a first region corresponding to a first individually patterned waveguide segment, and the second metal contact is located in a second region corresponding to a second individually patterned waveguide segment, which is different from the first individually patterned waveguide segment.

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