Low resistivity dram buried word line stack

Abstract

A method for a DRAM device having buried word lines is described. This method includes forming a metal capping layer and a molybdenum conductor layer in features on a substrate. The method includes depositing the metal capping layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer on the metal capping layer by atomic layer deposition (ALD).

Description

[Technical Field]

[0001] [Cross-reference to related applications] This application claims priority to U.S. Provisional Application No. 63 / 154,589, filed on February 26, 2021, the entire disclosure of which is incorporated herein by reference.

[0002] The embodiments of this disclosure pertain to the field of semiconductor devices and semiconductor device manufacturing. More specifically, the embodiments of this disclosure relate to a method including depositing a metal capping layer on a substrate and depositing a molybdenum conductor layer on the metal capping layer. [Previous Technology]

[0003] Electronic devices, such as personal computers, workstations, computer servers, mainframes, and other computer-related equipment, such as printers, scanners, and hard disk drives, use memory devices that provide large data storage capacity while consuming low power. There are two main types of random access memory (RAM): dynamic and static, which are well-suited for use in electronic devices. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but requires periodic reprogramming or "updating" to maintain this voltage for very short periods. Static random access memory (SRAM) is so named because it does not require periodic updates.

[0004] DRAM memory circuits are manufactured by replicating millions of identical circuit elements (called DRAM cells) on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary) of data. In its most common form, a DRAM cell consists of two circuit components: a field-effect transistor (FET) and a capacitor.

[0005] The manufacture of a DRAM cell includes the manufacture of transistors, capacitors, and three contacts: one contact for each bit line, word line, and reference voltage. DRAM manufacturing is a highly competitive business. The pressure to reduce the size of individual cells and increase memory cell density to allow more memory to be compressed onto a single memory chip remains, especially for densities greater than 256 megapixels. Limitations on cell size reduction include the path length of both active and passive word lines through the cell, the size of the cell capacitors, and compatibility between array and non-array devices.

[0006] In manufacturing, DRAM word lines are formed by atomic layer deposition of titanium nitride (TiN) and tungsten (W) stacks. Due to the further miniaturization of buried word line dimensions, these stacks present scaling issues. Therefore, there is a need in the art to demonstrate low resistivity metal stacks in buried word line manufacturing. [Summary of the Invention]

[0007] One or more embodiments of this disclosure relate to a method for forming embedded character lines. In some embodiments, the method includes depositing a metal capping layer on a substrate by physical vapor deposition (PVD), the substrate including at least one feature and the feature having one or more of a gate oxide layer and a work function metal layer deposited thereon; and depositing a molybdenum conductor layer on the metal capping layer by atomic layer deposition (ALD).

[0008] Another aspect of this disclosure relates to a method for forming DRAM embedded word lines having a resistance in the range of 10 µΩ-cm to 20 µΩ-cm. In one or more embodiments, this method includes depositing a metal capping layer on a substrate by DC physical vapor deposition (PVD), wherein the substrate is exposed to a metal precursor including tungsten at a DC current of 35 kW and a bias voltage of 1160 W, and depositing a molybdenum conductor layer on the metal capping layer by thermal atomic layer deposition, wherein the metal capping layer is exposed to the molybdenum precursor. In one or more embodiments, this method includes depositing a metal capping layer on a substrate by RF physical vapor deposition (PVD), wherein the substrate is exposed to a metal precursor including tungsten at a RF current of 3 kW, a bias voltage of 50 W, and a pressure of 230 mTorr, and depositing a molybdenum conductor layer on the metal capping layer by thermal atomic layer deposition, wherein the metal capping layer is exposed to the molybdenum precursor. In one or more embodiments, the method includes depositing a metal capping layer on a substrate by RF physical vapor deposition (PVD), wherein the substrate is exposed to a metal precursor including molybdenum under a 3 kW radio frequency, a 50 W bias, and a 100 mTorr pressure, and depositing a molybdenum conductor layer on the metal capping layer by thermal atomic layer deposition, wherein the metal capping layer is exposed to the molybdenum precursor.

Implementation Method

[0019] Before describing several exemplary embodiments of the present invention, it should be understood that the present invention is not limited to the details of the construction or process steps described below. The present invention can have other embodiments and can be practiced or performed in various ways.

[0020] As used in this specification and the appended claims, the term "substrate" refers to a surface or a portion thereof on which a process is performed. Those skilled in the art will also understand that reference to a substrate may also refer to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, reference to the step of deposition on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0021] As used herein, "substrate" refers to any substrate on which a film treatment is performed during the manufacturing process, or a material surface formed on the substrate. For example, substrate surfaces on which treatments can be performed may include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any film treatment steps disclosed in this disclosure may also be performed on an underlayer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include this underlayer as indicated by the context.

[0022] According to one or more embodiments, the term "on" relating to a film or layer of a film includes a film or layer directly on a surface (for example, a substrate surface), and having one or more underlying layers between the film or layer and the surface (for example, a substrate surface). Therefore, in one or more embodiments, the phrase "on a substrate surface" is intended to include one or more underlying layers. In other embodiments, the phrase "directly on" refers to a layer or film in contact with a surface (for example, a substrate surface) without intermediate layers. Therefore, the phrase "layer directly on a substrate surface" refers to a layer in direct contact with the substrate surface without any intermediate layers.

[0023] As used in this specification and the appended claims, the terms "precursor", "reactant", "reactive gas" etc. are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0024] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. This involves exposing the substrate or a portion thereof to two or more reactive compounds in a reaction zone introduced into a processing chamber. In time-domain ALD processes, exposure to each reactive compound is separated by a time delay to allow each compound to adhere to and / or react on the substrate surface before being decontaminated from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In spatial ALD processes, the substrate surface or different portions of the material on the substrate surface are simultaneously exposed to two or more reactive compounds such that no given point on the substrate is substantially exposed to more than one reactive compound simultaneously. As used herein and in the claims of the appended patent applications, the term "substantially" as used herein means, as will be understood by one of ordinary skill in the art, that small portions of the substrate may be simultaneously exposed to multiple reactive gases due to diffusion, and that such simultaneous exposure is unintentional.

[0025] In one embodiment of the time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, for example, an aluminum precursor) is pulsed into the reaction zone, followed by a first time delay. Then, a second precursor or compound B (e.g., an oxidant) is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds are alternately pulsed until a desired film or film thickness is formed on the substrate surface. In either embodiment, the ALD process of pulsed compound A, purge gas, compound B, and purge gas constitutes one cycle. A cycle may begin with either compound A or compound B and continue in an individual sequence until a film of a predetermined thickness is achieved.

[0026] In an embodiment of the space ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen) are simultaneously delivered to the reaction zone, but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery equipment such that any given point on the substrate is exposed to the first and second reactive gases.

[0027] As used herein, "chemical vapor deposition" refers to a process in which the surface of a substrate is simultaneously or substantially simultaneously exposed to a precursor and / or a common reagent. As used herein, "substantially simultaneously" means a situation where there is a co-flow or a substantial overlap in the exposure of the precursor.

[0028] As used throughout this specification, "substantially simultaneously" means that the duration of exposure to the first reactive compound overlaps with the duration of exposure to the second reactive compound.

[0029] As used herein, the term "purification" includes any suitable purification process that removes unreacted precursors, reaction products, and byproducts from a process area. A suitable purification process includes moving a substrate through a gas curtain to a portion or section of the processing area that does not contain or is substantially free of reactants. In one or more embodiments, purifying the processing chamber includes applying a vacuum. In some embodiments, purifying the processing area includes flowing a purifying gas over the substrate. In some embodiments, the purification process includes flowing an inert gas. In one or more embodiments, the purifying gas is selected from one or more of nitrogen (N2), helium (He), and argon (Ar). In some embodiments, the purification of the substrate surface or reaction chamber can be carried out for a period of time, the duration of which is in the range of 0.2 seconds to 30 seconds, 0.2 seconds to 10 seconds, 0.2 seconds to 5 seconds, 0.5 seconds to 30 seconds, 0.5 seconds to 10 seconds, 0.5 seconds to 5 seconds, 1 second to 30 seconds, 1 second to 10 seconds, 1 second to 5 seconds, 5 seconds to 30 seconds, 5 seconds to 10 seconds, or 10 seconds to 30 seconds.

[0030] As used herein, the terms "Dynamic Random Access Memory" or "DRAM" refer to a memory cell that stores data bits by storing a charge packet (i.e., a binary one) or no charge (i.e., a binary zero) on a capacitor. The charge is gated onto the capacitor via a access transistor and sensed by turning on the same transistor and observing the voltage disturbance generated by dumping the charge packet onto the interconnects at the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor. DRAM devices are formed by arrays of DRAM cells. Columns on the access transistors are connected by word lines, and transistor inputs / outputs are connected by bit lines. Historically, DRAM capacitors have evolved from planar polysilicon oxide substrate parallel plate capacitors to 3D structures, which have diverged into "stack" capacitors where both plates are on top of the substrate, and "trench" capacitors that use etched cavities in the substrate as common plates. Current DRAM buried word line (bWL) processes involve titanium nitride (TiN) and tungsten (W) stacking. As bWL dimensions further shrink, a key focus is removing the titanium nitride barrier from the stack to form a barrier-free metal filler within the trench structure. However, due to poor adhesion between the metal and the trench structure, voiding and delamination of the metal filler are frequently observed during high-temperature post-annealing. Such voiding and delamination are undesirable as they cause problems for subsequent planarization or etching processes. Voiding and delamination also increase stack resistance. Therefore, embodiments of this disclosure relate to providing a process for fabricating a stack in DRAM buried word lines (bWLs) on a substrate, which advantageously reduces resistance in DRAM devices. This resistance is reduced by eliminating nitrogen-based layers (e.g., nitride capping layers and / or nitride padding layers).

[0031] Traditionally, DRAM cells have recessed high work function metal structures in buried word line (bWL) structures. In DRAM devices, bit lines are formed in a metal layer above the substrate, while word lines are formed in a polysilicon gate layer at the surface of the substrate. In buried word line (bWL) devices, word lines are buried below the surface of a semiconductor substrate using metal as the gate electrode.

[0032] The choice of metal used as the gate electrode can greatly affect the performance of the device. To avoid being bound by theory, it is believed that using a low-melting-point metal with low resistance advantageously provides bWL DRAM with reduced resistance. However, when exposed to the thermal process requirements used in manufacturing bWL DRAM, these materials are often found to delaminate from the surface. Delamination can affect the final array resistance and lead to reliability issues.

[0033] In one or more embodiments, the resistance (µΩ-cm) of the embedded character line having a total thickness of 100 Å is measured. In one or more embodiments, the embedded character line has a resistance of less than or equal to 40 µΩ-cm, less than or equal to 30 µΩ-cm, less than or equal to 25 µΩ-cm, less than or equal to 20 µΩ-cm, or less than or equal to 15 µΩ-cm at a total thickness of 100 Å. In some embodiments, the embedded character line has a resistance of less than or equal to 20 µΩ-cm at a total thickness of 100 Å. In one or more embodiments, the embedded character line formed by method 100 has a resistance at a total thickness of 100 Å in the range of 50 µΩ-cm to 5 µΩ-cm, 40 µΩ-cm to 10 µΩ-cm, 30 µΩ-cm to 10 µΩ-cm, 25 µΩ-cm to 10 µΩ-cm, and 20 µΩ-cm to 10 µΩ-cm.

[0034] Figure 1 illustrates a process flow diagram of a method according to one or more embodiments of the present disclosure. Figures 2 through 8 are cross-sectional views illustrating the memory device 200 in various processing stages of forming embedded word lines (bWL) according to one or more embodiments.

[0035] Referring to Figures 1 through 8, one or more embodiments of this disclosure relate to a method 100 for forming embedded character lines (bWL) 215 on a substrate surface 202.

[0036] Referring to Figure 2, a substrate 202 is provided, wherein the substrate 202 has a plurality of trenches 204. The trenches 204 form recessed channels. The trenches have a bottom 206 and at least one sidewall 208. The plurality of trenches 204 may be formed to have widths in the range of about 10 nm to about 100 nm, including but not limited to the ranges of about 10 nm to about 80 nm, about 10 nm to about 70 nm, about 10 nm to about 60 nm, about 10 nm to about 50 nm, or about 10 nm to about 40 nm. As will be appreciated by those skilled in the art, the width of the plurality of trenches 204 is defined by the distance W1 from one sidewall 208 to another sidewall 208. The plurality of trenches 204 may be formed to have a depth in the range of about 120 nm to about 250 nm, including but not limited to the ranges of about 120 nm to about 150 nm, about 150 nm to about 200 nm, about 200 nm to about 250 nm, about 120 nm to about 200 nm, or about 150 nm to about 250 nm. As will be appreciated by those skilled in the art, the depth of the plurality of trenches 204 is defined by the distance D1 from the substrate surface 203 to the bottom 206 of the plurality of trenches 204.

[0037] One or more embodiments of this disclosure relate to a method of depositing a film in a high aspect ratio feature. A high aspect ratio feature is a trench, via, or pillar having a height-to-width ratio greater than or equal to about 10, 20, or 50 or greater. In some embodiments, the film is conformally deposited on / in the high aspect ratio feature. When used in this manner, the thickness of the conformal film near the top of the feature is in the range of about 80-120% of the thickness at the bottom of the feature.

[0038] In order to form a plurality of trenches 204, a buffer insulating layer (e.g., a silicon oxide layer, not shown) may be formed on the substrate surface 203, and / or a hard masking layer (e.g., a nitride layer, not shown) may be formed. Such techniques are known to those skilled in the art and therefore are not shown.

[0039] Referring to Figure 3, the gate oxide layer 210 is conformally deposited on the substrate 202, on the substrate surface 203, and along one (or more) sidewalls 208 and the bottom 206 of a plurality of trenches 204. In one or more embodiments, the gate oxide layer 210 comprises one or more of silicon oxynitride (SiON), silicon oxide, or a high dielectric constant (K) dielectric material.

[0040] Although the term "silicon oxide" may be used to describe the gate oxide layer 210, those skilled in the art will recognize that this disclosure is not limited to a specific stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" can be used to describe materials with silicon and oxygen atoms having any suitable stoichiometric ratio. The same applies to other materials listed in this disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, etc.

[0041] In one or more embodiments, the term "high dielectric constant dielectric material" refers to a material having a high dielectric constant (compared to, for example, silicon dioxide). In one or more embodiments, the high dielectric constant dielectric material is selected from one or more of hafnium dioxide (HfO2), zirconium dioxide (ZrO2), vanadium dioxide (VO2), titanium dioxide (TiO2), tin dioxide (SnO2), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium silicon oxide (HfSiO) or zirconium silicon oxide (ZrSiO).

[0042] In one or more embodiments, the gate oxide layer 210 has a thickness in the range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm or about 7 nm.

[0043] Referring to Figure 4, in some embodiments, a work function metal layer 212 is formed on the gate oxide layer 210. As used herein, the term "work function" refers to the bulk chemical potential energy of a material (e.g., a metal) relative to the vacuum level. In one or more embodiments, the work function metal layer has a work function greater than or equal to 4.3 eV. In some embodiments, the work function metal layer 212 has a work function greater than or equal to 4.5 eV. In other embodiments, the work function metal layer 212 has a work function greater than or equal to 4.3 eV, including greater than or equal to 4.4 eV, greater than or equal to 4.5 eV, greater than or equal to 4.6 eV, greater than or equal to 4.7 eV, greater than or equal to 4.8 eV, greater than or equal to 4.9 eV, greater than or equal to 5.0 eV, greater than or equal to 5.1 eV, or greater than or equal to 5.2 eV.

[0044] In one or more embodiments, the work function metal layer 212 comprises a metal nitride. In one or more embodiments, the work function metal layer 212 comprises one or more of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, or WN / TiN. In one or more embodiments, the work function metal layer 212 is selected from the group consisting of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, WN / TiN, and combinations thereof. In one or more embodiments, the work function metal layer 212 comprises titanium nitride.

[0045] In one or more embodiments, the work function metal layer 212 has a thickness in the range of about 1 nm to about 5 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm or about 5 nm.

[0046] Referring to Figure 1, in some embodiments, method 100 includes an optional pretreatment operation 105. The pretreatment may be any suitable pretreatment known to those skilled in the art. Suitable pretreatments include, but are not limited to, preheating, cleaning, soaking, removal of native oxides, or deposition of an adhesive layer. In some embodiments, the pretreatment includes polishing, etching, reduction, oxidation, halogenation, hydroxylation, annealing, baking, etc.

[0047] In some embodiments, method 100 begins with deposition operation 110. Referring to Figures 1 and 5, in physical vapor deposition (PVD) operation 110, a process is performed to form a metal capping layer 213 in a plurality of trenches 204 on gate oxide layer 210 and work function metal layer 212. PVD processes are familiar to those skilled in the art. In some embodiments, the metal capping layer 213 comprises a tungsten- or molybdenum-containing species. Figure 5 illustrates the metal capping layer 213 formed in a plurality of trenches 204 on gate oxide layer 210. The metal capping layer 213 has a third surface 270 (or top surface) facing the trenches 204.

[0048] In some embodiments, the metal capping layer 213 is deposited directly on the gate oxide layer 210. In other embodiments, the metal capping layer 213 is deposited directly on the work function metal layer 212.

[0049] In some embodiments, the physical vapor deposition (PVD) process includes one or more of direct current (DC) or radio frequency (RF) PVD. In some embodiments, the PVD process includes both RF and DC. In some embodiments, DC is supplied to a substrate and RF is supplied to a metal target. In one or more embodiments, the DC component has a power range from 0 kW to 100 kW, from 10 kW to 80 kW, from 20 kW to 60 kW, from 30 kW to 50 kW, and from 40 kW to 50 kW. In one or more embodiments, the radio frequency component has a power range from 1 kW to 10 kW, from 3 kW to 10 kW, from 5 kW to 10 kW, from 7 kW to 10 kW, from 1 kW to 7 kW, from 3 kW to 7 kW, from 5 kW to 7 kW, from 1 kW to 5 kW, from 3 kW to 5 kW, or from 1 kW to 3 kW.

[0050] In some embodiments, the PVD process includes biasing the substrate to provide directional deposition. In one or more embodiments, the bias voltage is in the range of 0 W to 1200 W, 0 W to 1000 W, 0 W to 800 W, 0 W to 600 W, 0 W to 400 W, 0 W to 200 W, 0 W to 1200 W, 200 W to 1000 W, 200 W to 800 W, 200 W to 600 W, 200 W to 400 W, 400 W to 1200 W, 400 W to 1000 W, 400 W to 800 W, 400 W to 600 W, 600 W to 1200 W, 600 W to 1000 W, 600 W to 800 W, 800 W to 1200 W, 800 W to 1000 W, or 1000 W to 1200 W.

[0051] In some embodiments, the PVD process occurs at temperatures ranging from 200°C to 450°C, from 250°C to 450°C, from 300°C to 450°C, from 350°C to 450°C, from 400°C to 450°C, from 200°C to 400°C, from 250°C to 400°C, from 300°C to 400°C, from 350°C to 400°C, from 200°C to 350°C, from 250°C to 350°C, from 300°C to 350°C, from 200°C to 300°C, from 250°C to 300°C, or from 200°C to 250°C.

[0052] In some embodiments, the PVD process occurs at pressures ranging from 0.5 mTorr to 500 mTorr, or from 10 mTorr to 500 mTorr, or from 25 mTorr to 250 mTorr, or from 50 mTorr to 150 mTorr.

[0053] In some embodiments, the metal capping layer 213 comprises an elemental metal. In some embodiments, the metal capping layer 213 is essentially composed of metal. As used in this manner, the term "essentially composed of metal" means that the metal content in the film is greater than or equal to about 80%, 85%, 90%, 95%, 98%, 99%, or 99.5% metal in atomic percentage. Measurement of the composition of the metal capping layer 213 refers to the main portion of the metal capping layer 213, excluding the interface regions where diffusion of elements from adjacent films may occur.

[0054] In some embodiments, the metal capping layer 213 effectively inhibits and / or eliminates unwanted element diffusion into the substrate and / or silicon diffusion out of the substrate. In some embodiments, the metal capping layer 213 is substantially deposited only on the bottom 206 of the feature. As used in this manner, the term "substantially only" means that less than or equal to 5%, 2%, or 1% of the metal capping layer is formed on the sidewalls of the feature.

[0055] In one or more embodiments, the metal capping layer 213 may have any suitable thickness. For example, the metal capping layer 213 may have a thickness in the range of 10 Å to 200 Å, 20 Å to 200 Å, 50 Å to 200 Å, 100 Å to 200 Å, 150 Å to 200 Å, 10 Å to 150 Å, 50 Å to 150 Å, 100 Å to 150 Å, 10 Å to 100 Å, 50 Å to 100 Å, 10 Å to 50 Å, or 10 Å to 30 Å.

[0056] Once the predetermined thickness of the metal capping layer has been formed, method 100 moves to atomic layer deposition 130, as illustrated in Figure 1. Referring to Figures 1 and 6, at deposition 130, a process is performed to deposit a molybdenum conductor layer 214 on substrate 202 (substrate surface). Deposition process 130 may include one or more operations to form the molybdenum conductor layer 214 on substrate 202. In some embodiments, deposition process 130 is selective for deposition on the metal capping layer 213.

[0057] Some embodiments of the atomic layer deposition 130 process include sequential exposure to a precursor and a reactant. In operation 132, substrate 202 (or substrate surface) is optionally exposed to the reactant. In some embodiments, a third surface 270 is exposed to the reactant. In some embodiments, the reactant includes a reducing agent. The reducing agent may be any suitable compound known to those skilled in the art. In some embodiments, the reducing agent includes hydrogen (H2).

[0058] In some embodiments, the substrate 202 (or substrate surface) is exposed to a reducing agent at a temperature ranging from 350°C to 550°C, from 400°C to 550°C, from 450°C to 550°C, from 500°C to 550°C, from 350°C to 500°C, from 400°C to 500°C, from 450°C to 500°C, from 350°C to 450°C, from 400°C to 450°C, or from 350°C to 400°C.

[0059] In some embodiments, the substrate 202 (or substrate surface) is exposed to the reducing agent for a duration ranging from 5 seconds to 60 minutes, from 1 minute to 60 minutes, from 5 minutes to 60 minutes, from 10 minutes to 60 minutes, from 20 minutes to 60 minutes, from 40 minutes to 60 minutes, from 5 seconds to 40 minutes, from 1 minute to 40 minutes, from 5 minutes to 40 minutes, from 10 minutes to 40 minutes, from 20 minutes to 40 minutes, from 5 seconds to 20 minutes, from 1 minute to 20 minutes, from 5 minutes to 20 minutes, from 10 minutes to 20 minutes, from 5 seconds to 10 minutes, from 1 minute to 10 minutes, or from 5 minutes to 10 minutes.

[0060] In some embodiments, the substrate 202 (or substrate surface) is subjected to a temperature range of 100 sccm to 7000 sccm, 500 sccm to 7000 sccm, 1000 sccm to 7000 sccm, 3000 sccm to 7000 sccm, 5000 sccm to 7000 sccm, 100 sccm to 5000 sccm, 500 sccm to 5000 sccm, 1000 sccm to 5000 sccm, 3000 sccm to 5000 sccm, 100 sccm to 3000 sccm, 500 sccm to 3000 sccm, 1000 sccm to 1000 sccm, 500 sccm to 3000 sccm, 100 sccm to 1000 sccm, 500 sccm to 1000 sccm. Exposure to reducing agents at doses ranging from 100 sccm to 500 sccm.

[0061] In some embodiments, the substrate 202 (or substrate surface) is exposed to a reducing agent under pressure ranging from 5 Torr to 50 Torr, from 10 Torr to 50 Torr, from 25 Torr to 50 Torr, from 5 Torr to 25 Torr, from 10 Torr to 25 Torr, or from 5 Torr to 10 Torr.

[0062] Referring to Figure 1, in operation 134, the processing chamber is optionally cleaned to remove unreacted reactants, reaction products, and byproducts. When used in this manner, the term "processing chamber" also includes a portion of the processing chamber adjacent to the substrate surface, but does not encompass the entire internal volume of the processing chamber. For example, in spatially partitioned processing chamber sections, the portion of the processing chamber adjacent to the substrate surface is cleaned of metal precursors by any suitable technique, including but not limited to moving the substrate through an air curtain to a portion or section of the processing chamber that does not contain or substantially does not contain metal precursors. In one or more embodiments, cleaning the processing chamber includes applying a vacuum. In some embodiments, cleaning the processing chamber includes flowing a clean gas over the substrate. In some embodiments, a portion of the processing chamber refers to a micro-volume or small-volume process station within the processing chamber. The term "adjacent" as used with reference to the substrate surface means the physical space immediately adjacent to the substrate surface, which provides sufficient space for surface reactions (e.g., precursor adsorption) to occur. In one or more embodiments, the purifying gas is selected from one or more of argon (Ar), nitrogen (N2), hydrogen (H2), and helium (He).

[0063] Referring to Figures 1 and 6, in operation 136, substrate 202 (or substrate surface) is exposed to a molybdenum precursor to deposit a molybdenum conductor layer 214 on substrate 202 (or substrate surface). In operation 136, substrate 202 (or substrate surface) is exposed to a molybdenum precursor to deposit a molybdenum conductor layer 214 on a metal capping layer 213. In operation 136, substrate 202 (or substrate surface) is exposed to a molybdenum precursor to deposit a molybdenum conductor layer 214 on a reduced metal capping layer.

[0064] The molybdenum precursor can be any suitable molybdenum-containing compound that can react with the substrate surface (i.e., adsorb onto the substrate surface or chemisorb onto the substrate surface) to leave molybdenum-containing species on the substrate surface.

[0065] Figure 6 illustrates a molybdenum conductor layer 214 deposited on a metal capping layer 213. In some embodiments, the molybdenum conductor layer 214 includes a molybdenum-containing species. In some embodiments, the molybdenum conductor layer 214 includes a combination of multiple layers to provide active contacts and / or metal contacts.

[0066] In some embodiments, the molybdenum conductor layer 214 is deposited directly on the metal capping layer 213 without air interruption. This process is also known as an in-situ process. In some embodiments of the in-situ process, the atomic layer deposition 130 process begins at operation 136, exposing the substrate to the molybdenum precursor.

[0067] In one or more embodiments, the molybdenum precursor comprises any suitable precursor known to those skilled in the art. The molybdenum precursors in one or more embodiments are volatile and thermally stable, and therefore suitable for vapor deposition. In some embodiments, the molybdenum precursor comprises molybdenum halide.

[0068] As used herein, the term "halide" refers to a binary phase in which one part is a halogen atom and the other part is an element or radical with a lower electronegativity than the halogen, for the preparation of fluorides, chlorides, bromides, iodides, or arsenic compounds. A halide ion is a negatively charged halogen atom. As is known to those skilled in the art, halide anions include fluoride ions (F-), chloride ions (Cl-), bromide ions (Br-), iodide ions (I-), and arsenic ions (At-). Therefore, as used herein, the term "molybdenum halide" refers to any coordination complex of molybdenum with one or more halogen or halide ligands. The term molybdenum halide includes mixed molybdenum halides having at least two different halogen atoms.

[0069] In one or more embodiments, the molybdenum halide is selected from one or more of molybdenum chloride, molybdenum pentachloride, molybdenum bromide, molybdenum iodide, molybdenum bromochloride, molybdenum bromoiodide, molybdenum chlorobromide, molybdenum chloroiodide, molybdenum iodobromide, and molybdenum iodochloride.

[0070] In some embodiments, the molybdenum precursor includes molybdenum halide species. In some embodiments, the molybdenum halide species include one or more of molybdenum tetrachloride oxide (MoCl4O), molybdenum tetrabromide oxide (MoBr4O), molybdenum tetraiodide oxide (MoI4O), molybdenum dibromide dioxide (MoO2Br2), molybdenum dichloride dioxide (MoCl2O2), and / or molybdenum diiodide dioxide (MoI2O2).

[0071] In one or more specific embodiments, the molybdenum precursor includes one or more of molybdenum pentachloride (MoCl5), molybdenum hexafluoride (MoF6), molybdenum iodide (MoI6), molybdenum bromide (MoBr3), molybdenum hexacarbonyl (Mo(CO)6), molybdenum dichloride dioxide (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), tetrakis(dimethylamino)molybdenum(IV) and bis(tert-butylimido)-bis(dimethylamido)molybdenum.

[0072] In some embodiments, the substrate 202 (or substrate surface) is exposed to a molybdenum precursor at a temperature ranging from 350°C to 550°C, from 400°C to 550°C, from 450°C to 550°C, from 500°C to 550°C, from 350°C to 500°C, from 400°C to 500°C, from 450°C to 500°C, from 350°C to 450°C, from 400°C to 450°C, or from 350°C to 400°C.

[0073] In some embodiments, the substrate 202 (or substrate surface) is exposed to the molybdenum precursor for a duration ranging from 0.25 seconds to 20 minutes, from 10 seconds to 20 minutes, from 1 minute to 20 minutes, from 5 minutes to 20 minutes, from 10 minutes to 20 minutes, from 0.25 seconds to 10 minutes, from 10 seconds to 10 minutes, from 1 minute to 10 minutes, from 5 minutes to 10 minutes, from 0.25 seconds to 5 minutes, from 10 seconds to 5 minutes, from 1 minute to 5 minutes, from 0.25 seconds to 1 minute, or from 10 seconds to 1 minute.

[0074] In some embodiments, the substrate 202 (or substrate surface) is exposed to a molybdenum precursor at doses ranging from 50 sccm to 700 sccm, from 100 sccm to 700 sccm, from 300 sccm to 700 sccm, from 500 sccm to 700 sccm, from 50 sccm to 500 sccm, from 100 sccm to 500 sccm, from 300 sccm to 500 sccm, from 50 sccm to 300 sccm, from 100 sccm to 300 sccm, or from 50 sccm to 100 sccm.

[0075] In some embodiments, the substrate 202 (or substrate surface) is exposed to the molybdenum precursor under pressure ranging from 5 to 50 to 10 to 50 to 25 to 50 to 50 to 50 to 10 to 25 to 10 to 50 ...

[0076] In some embodiments, the formed molybdenum conductor layer 214 comprises elemental molybdenum. In some embodiments, the molybdenum conductor layer 214 is essentially composed of molybdenum. As used in this manner, the term "essentially composed of molybdenum" means that the molybdenum content in the film is greater than or equal to about 80%, 85%, 90%, 95%, 98%, 99%, or 99.5% molybdenum in atomic percentage. Measurement of the composition of the molybdenum conductor layer 214 refers to the bulk portion of the molybdenum conductor layer 214, excluding the interface regions where diffusion of elements from adjacent films may occur.

[0077] A repeatable deposition operation 130 is performed to deposit a molybdenum conductor layer 214 having a predetermined thickness. In some embodiments, the thickness T1 of the molybdenum conductor layer 214 is controlled. In some embodiments, referring to Figure 6, the thickness T1 of the molybdenum conductor layer 214 is controlled relative to the depth D1 of the plurality of trenches 204. In some embodiments, the thickness T1 is greater than or equal to approximately 90% of the depth D1 of the plurality of trenches 204.

[0078] Referring to Figure 7, in some embodiments, the thickness T1 of the molybdenum conductor layer 214 exceeds the depth D1 of the trench 204, which may form an overburden layer of the molybdenum conductor layer 214 on the substrate. In some embodiments, repeated deposition operation 130 is used to provide a molybdenum conductor layer 214 having a thickness in the range of 1 nm to 50 nm, 5 nm to 50 nm, 10 nm to 50 nm, 25 nm to 50 nm, 1 nm to 25 nm, 5 nm to 25 nm, 10 nm to 25 nm, 1 nm to 10 nm, 5 nm to 10 nm, or 1 nm to 5 nm.

[0079] In some embodiments, the molybdenum precursor further includes a co-reactant. In some embodiments, the co-reactant is a reducing agent. In some embodiments, the co-reactant is hydrogen (H2).

[0080] In some embodiments, a molybdenum precursor is used to pretreat the metal capping layer 213 before depositing the molybdenum conductor layer 214. In some embodiments, the pretreatment includes etching. In some embodiments, etching is performed for a duration ranging from 5 seconds to 20 minutes, from 10 seconds to 20 minutes, from 1 minute to 20 minutes, from 5 minutes to 20 minutes, from 10 minutes to 20 minutes, from 5 seconds to 10 minutes, from 10 seconds to 10 minutes, from 1 minute to 10 minutes, from 5 minutes to 10 minutes, from 5 seconds to 5 minutes, from 10 seconds to 5 minutes, from 1 minute to 5 minutes, from 5 seconds to 1 minute, or from 10 seconds to 1 minute. In some embodiments, etching is performed by a molybdenum precursor at doses ranging from 5 sccm to 700 sccm, from 50 sccm to 700 sccm, from 100 sccm to 700 sccm, from 300 sccm to 700 sccm, from 5 sccm to 500 sccm, from 50 sccm to 500 sccm, from 100 sccm to 500 sccm, from 300 sccm to 500 sccm, from 5 sccm to 300 sccm, from 50 sccm to 300 sccm, from 100 sccm to 300 sccm, from 5 sccm to 100 sccm, from 50 sccm to 100 sccm, or from 5 sccm to 50 sccm.

[0081] Referring to Figure 1, in operation 138, the processing chamber is optionally cleaned to remove unreacted molybdenum precursors, reaction products, and byproducts. The cleaning of the processing chamber in operation 138 can be the same process as or a different process than the cleaning in operation 134. The cleaning of the processing chamber, portions of the processing chamber, and areas adjacent to the substrate surface removes unreacted molybdenum precursors, reaction products, and byproducts from areas adjacent to the substrate surface.

[0082] In the embodiment illustrated in Figure 1, during deposition operation 130, a substrate (or substrate surface) 202 is sequentially exposed to the reactant and the molybdenum precursor. In some embodiments, the substrate (or substrate surface) is first exposed to the molybdenum precursor and then to the reactant. In other embodiments, the substrate (or substrate surface) is first exposed to the reactant and then to the molybdenum precursor. In another embodiment not illustrated, the substrate (or substrate surface) is substantially simultaneously exposed to both the molybdenum precursor and the reactant.

[0083] In some embodiments, a molybdenum conductor layer 214 is formed inside feature 204 on the third surface 270 of metal capping layer 213. In some embodiments, the molybdenum conductor layer 214 fills the gaps formed by the feature in a bottom-up manner. As used in this manner, "bottom-up" means that the deposition substantially occurs on the bottom of the feature relative to the sidewalls.

[0084] At decision 140, the thickness of the molybdenum conductor layer 214 is considered. If the molybdenum conductor layer 214 has reached a predetermined thickness, method 100 moves to an optional post-processing operation 150. If the thickness of the molybdenum conductor layer 214 or the number of process cycles has not reached a predetermined threshold, method 100 returns to operation 130 and continues.

[0085] Optional post-processing operation 150 may be, for example, a process for modifying the film properties (e.g., annealing) or a further film deposition process (e.g., an additional ALD or CVD process) to grow an additional film. In some embodiments, optional post-processing operation 150 may be a process for modifying the properties of the deposited film. In some embodiments, optional post-processing operation 150 includes annealing the deposited film. In some embodiments, annealing is performed at a temperature in the range of about 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, 900°C, or 1000°C. The annealing environment in some embodiments includes one or more of an inert gas (e.g., molecular nitrogen (N2), argon (Ar)) or a reducing gas (e.g., molecular hydrogen (H2) or ammonia (NH3)) or an oxidizing agent, such as, but not limited to, oxygen (O2), ozone (O3), or peroxides. Annealing can be performed for any suitable duration. In some embodiments, the film is annealed for a predetermined time ranging from about 15 seconds to about 90 minutes or from about 1 minute to about 60 minutes. In some embodiments, annealing the deposited film increases the film density, decreases the film resistivity, and / or increases the film purity. In one or more embodiments, annealing can also be performed by gas under plasma. In one or more embodiments, the annealing temperature using plasma can be lower.

[0086] In one or more embodiments, the plasma includes one or more of nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), carbon monoxide (CO), carbon dioxide (CO2), methane (CH4), and ammonia (NH3). In some embodiments, the plasma is a distal plasma. In other embodiments, the plasma is a direct plasma.

[0087] In one or more embodiments, the plasma may be generated remotely or within the processing chamber. In one or more embodiments, the plasma is inductively coupled plasma (ICP) or capacitively coupled plasma (CCP). In other embodiments, the plasma is microwave plasma. Depending on the reactants or other process conditions, for example, any suitable power may be used. In some embodiments, the plasma is generated at a plasma power in the range of about 10 W to about 3000 W. In some embodiments, the plasma is generated at a plasma power of less than or equal to about 3000 W, less than or equal to about 2000 W, less than or equal to about 1000 W, less than or equal to about 500 W, or less than or equal to about 250 W.

[0088] Referring to Figure 8, in some embodiments, the molybdenum conductor layer 214 is recessed (embedded) by chemical mechanical polishing (CMP) and etch back, so that the molybdenum conductor layer 214 and the work function metal layer 212 do not protrude beyond the substrate surface 203 (e.g., so that the molybdenum conductor layer 214 is completely embedded in the substrate 202).

[0089] In one or more embodiments, a buried character line 215 (i.e., a recessed molybdenum conductor layer 214) may be formed. In some embodiments, as illustrated in Figure 8, the work function metal layer 212 is recessed to the same level as the buried character line 215. The top surface 217 of the buried character line 215 and the work function metal layer 212 is the recess depth or distance D2 from the substrate surface 203 in the plurality of trenches 204.

[0090] After the embedded character lines 215 are formed, the substrate can be further processed to form a memory device. The above process is known to those skilled in the art.

[0091] In one or more embodiments, the method includes: depositing a metal overlay layer in features of a substrate in a first processing chamber; moving the substrate to a second processing chamber integrated with the first processing chamber such that there is no air interruption between the first and second processing chambers; and depositing a molybdenum conductor layer on the metal overlay layer. In one or more embodiments, the method includes: depositing a metal overlay layer in features of a substrate in a first processing chamber; moving the substrate to a second processing chamber integrated with the first processing chamber such that there is no air interruption between the first and second processing chambers; exposing the metal overlay layer to a reactant; moving the substrate to a third processing chamber integrated with the second processing chamber such that there is no air interruption between the second and third processing chambers; and depositing a molybdenum conductor layer on the reducing agent-treated metal overlay layer.

[0092] Some embodiments of this disclosure pertain to a method for bottom-up gap filling of a feature. A bottom-up gap filling process fills the feature from the bottom, whereas a conformal process fills the feature from both the bottom and sides. In some embodiments, the feature has a first material at the bottom and a second material on the sidewalls. In some embodiments, a metal overlay is selectively deposited on the first material relative to the second material, such that the metal overlay fills the feature in a bottom-up manner. In some embodiments, a molybdenum conductor layer is selectively deposited on the first material relative to the second material, such that the molybdenum conductor layer fills the feature in a bottom-up manner.

[0093] According to one or more embodiments, the substrate may be subjected to processing before and / or after the formation of the layer. This processing may be performed in the same chamber or in one or more separate processing chambers. In some embodiments, the substrate is moved from a first chamber to a separate second chamber for further processing. The substrate may be moved directly from the first chamber to the separate processing chamber, or the substrate may be moved from the first chamber to one or more transfer chambers and then to the separate processing chambers. Thus, the processing apparatus may include multiple chambers communicating with transfer stations. Such an apparatus may be referred to as a "cluster tool" or "cluster system," etc.

[0094] Generally, clustering tools are modular systems comprising multiple chambers that perform various functions, including substrate centering and orientation, degassing, annealing, deposition, and / or etching. According to one or more embodiments, a clustering tool includes at least a first chamber and a central transfer chamber. The central transfer chamber houses a robot that can transport substrates between the processing chamber and the load lock chamber. The transfer chamber is typically maintained under vacuum conditions and provides an intermediate stage for transporting substrates from one chamber to another and / or to the load lock chamber located at the front end of the clustering tool. Two well-known clustering tools applicable to this disclosure are Centura® and Endura®, both available from Applied Materials, Santa Clara, California. However, the exact arrangement and combination of the chambers may be varied for the purpose of performing the specific steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, circulating layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, thermal treatments such as RTP, plasma nitriding, degassing, orientation, hydroxylation, and other substrate processes. By performing the process in a chamber on a cluster tool, oxidation is avoided before the deposition of subsequent films, thus preventing contamination of the substrate surface by atmospheric impurities.

[0095] According to one or more embodiments, the substrate is continuously under vacuum or "loading gate" conditions and is not exposed to ambient air as it moves from one chamber to the next. The transfer chamber is therefore under vacuum and is "pumped down" under vacuum pressure. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, the inert gas is used as a purge gas to remove some or all of the reactants (e.g., reactants). According to one or more embodiments, purge gas is injected at the outlet of the deposition chamber to prevent reactants (e.g., reactants) from moving from the deposition chamber to the transfer chamber and / or another processing chamber. Thus, the flow of inert gas forms a curtain at the outlet of the chamber.

[0096] Substrates can be processed in a single substrate deposition chamber, wherein a single substrate is loaded, processed, and unloaded before processing another substrate. Substrates can also be processed continuously, similar to a conveyor belt system, wherein multiple substrates are individually loaded into a first portion of the chamber, move through the chamber, and are unloaded from a second portion of the chamber. The shape of the chamber and the associated conveyor belt system can form a straight path or a curved path. Alternatively, the processing chamber can be a carousel, in which multiple substrates move about a central axis and are exposed to processes such as deposition, etching, annealing, and cleaning throughout the carousel path.

[0097] During processing, the substrate may be heated or cooled. This heating or cooling may be accomplished by any suitable means, including, but not limited to, changing the temperature of the substrate support and allowing heated or cooled gases to flow to the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to change the substrate temperature conductively. In one or more embodiments, the gas used (whether reactive or inert) is heated or cooled to locally change the substrate temperature. In some embodiments, the heater / cooler is located within a chamber adjacent to the substrate surface to change the substrate temperature convectively.

[0098] During processing, the substrate may be stationary or rotating. The rotating substrate may rotate continuously or in discrete steps (about the substrate axis). For example, the substrate may rotate throughout the entire process, or the substrate may rotate slightly between exposures to different reactive or purge gases. Rotating the substrate during processing (whether continuously or in multiple steps) can help produce more uniform deposition or etching by minimizing, for example, the effect of localized changes in airflow geometry.

[0099] This disclosure will now be described with reference to the following examples. Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or process steps described below. This disclosure can have other embodiments and can be practiced or performed in various ways.

[0100] To facilitate the description of the relationship between one element or feature and another (or more) elements or features illustrated in the diagrams, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" are used herein. It should be understood that, in addition to the orientation depicted in the diagrams, spatial relative terms are intended to cover different orientations of the device during use or operation. For example, if the device in the diagrams is flipped, an element described as "below" or "under" other elements or features will be oriented as "above" other elements or features. Therefore, the exemplary term "below" can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0101] In the context of describing the materials and methods discussed herein (especially in the context of the following claims), the terms “a,” “an,” and “the,” and similar designations, shall be construed as encompassing both the singular and plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the enumeration of ranges of numerical values ​​herein is intended only as a shorthand method for individually referring to each individual value falling within that range, and each individual value is incorporated into the specification as if it were individually enumerated herein. Unless otherwise indicated herein or otherwise clearly contradicted by the context, all methods described herein may be performed in any suitable order. The use of any and all examples or exemplary language provided herein (e.g., “such as”) is intended only to better illustrate the materials and methods and does not constitute a limitation on the scope, unless otherwise stated. No language in the specification should be construed as indicating that any unclaimed element is necessary for the practice of the disclosed materials and methods.

[0102] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "embodiment" mean that a particular feature, structure, material, or characteristic described in connection with this embodiment is included in at least one embodiment of this disclosure. Therefore, phrases appearing throughout this specification such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" do not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, the particular feature, structure, material, or characteristic is combined in any suitable manner.

[0103] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is contemplated that the present disclosure includes modifications and variations within the scope of the appended claims and their equivalents. [Simplified Explanation of the Diagram]

[0009] In order to understand in detail the above-described features of this disclosure, a more specific description of this disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should not be regarded as limiting the scope of this disclosure, as other equivalent embodiments are permissible.

[0010] Figure 1 illustrates a process flow diagram of a method according to one or more embodiments of this disclosure;

[0011] Figure 2 is a cross-sectional view of an apparatus according to one or more embodiments;

[0012] Figure 3 is a cross-sectional view of an apparatus according to one or more embodiments;

[0013] Figure 4 is a cross-sectional view of an apparatus according to one or more embodiments;

[0014] Figure 5 is a cross-sectional view of an apparatus according to one or more embodiments;

[0015] Figure 6 is a cross-sectional view of an apparatus according to one or more embodiments;

[0016] Figure 7 is a cross-sectional view of an apparatus according to one or more embodiments; and

[0017] Figure 8 is a cross-sectional view of an apparatus according to one or more embodiments.

[0018] This document describes the exemplary embodiments with reference to cross-sectional drawings that serve as schematic diagrams of exemplary embodiments (and intermediate structures). Therefore, variations in the shape of the drawings due to, for example, manufacturing techniques and / or tolerances are expected. Thus, the exemplary embodiments should not be construed as limited to a specific shape within the area illustrated herein, but may include, for example, shape deviations caused by manufacturing processes. [Biomaterial Storage]

[0105] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for forming an embedded character line, the method comprising the steps of: depositing a metal capping layer on a substrate by physical vapor deposition (PVD), the substrate including at least one feature and the at least one feature having one or more of a gate oxide layer and a work function metal layer deposited thereon, wherein the at least one feature has at least one sidewall and a bottom, the metal capping layer being substantially deposited on the bottom of the at least one feature and less than or equal to 5% deposited on the at least one sidewall of the at least one feature; and depositing a molybdenum conductor layer on the metal capping layer by atomic layer deposition (ALD).

2. The method as described in claim 1, wherein the metal coating comprises one or more of tungsten or molybdenum.

3. The method as described in claim 1, wherein the metal overlay is deposited by a DC PVD process.

4. The method as described in claim 1, wherein the metal overlay is deposited by an RF PVD process.

5. The method as described in claim 1, wherein the PVD process includes biasing the substrate to provide a directional deposition.

6. The method as described in claim 1, wherein the metal coating is deposited at a temperature in the range of 300°C to 350°C.

7. The method as described in claim 1, wherein the metal capping layer is deposited to a thickness in the range of 10 Å to 200 Å.

8. The method as described in claim 1, wherein the ALD process is a thermal process.

9. The method as described in claim 1, wherein the molybdenum conductor layer is selectively deposited on the metal capping layer.

10. The method as claimed in claim 1, wherein the ALD process includes sequentially exposing the substrate to a reactant and a molybdenum precursor.

11. The method as described in claim 10, wherein the molybdenum precursor comprises molybdenum halide or molybdenum halide oxide.

12. The method as claimed in claim 11, wherein the molybdenum precursor comprises one or more of molybdenum pentachloride or molybdenum dichloride dioxide.

13. The method as described in claim 10, wherein the reactant comprises hydrogen (H2).

14. The method as described in claim 10, wherein the molybdenum conductor layer is deposited to a thickness in the range of 1 nm to 50 nm.

15. The method as described in claim 10, wherein the ALD process occurs at a temperature in the range of 450°C to 500°C.

16. The method as described in claim 1, wherein the embedded character line has a resistance of less than or equal to 20 µΩ-cm at a total thickness of 100 Å.

17. The method as described in claim 16, wherein the at least one feature has a width in the range of 10 nm to 12 nm.

18. The method as described in claim 16, wherein the at least one feature is filled in a bottom-up manner.

19. A method of forming an embedded word line having a resistance in the range of 10 µΩ-cm to 20 µΩ-cm, the method comprising the steps of: a. depositing a metal capping layer on a substrate including at least one feature by DC physical vapor deposition (PVD), the metal capping layer substantially deposited on the bottom of one of the at least one feature and less than or equal to 5% deposited on at least one sidewall of the at least one feature, wherein the substrate is exposed to a metal precursor including tungsten at a DC current of 35 kW and a bias voltage of 1160 W, and depositing a molybdenum conductor layer on the metal capping layer by thermal atomic layer deposition, wherein the metal capping layer is exposed to a molybdenum precursor; b. depositing a metal capping layer on a substrate including at least one feature by RF physical vapor deposition (PVD), the metal capping layer substantially deposited on the bottom of one of the at least one feature and less than or equal to 5% deposited on at least one sidewall of the at least one feature, wherein the substrate is exposed to a 3 kW radio frequency of 50 W and a bias voltage of 1160 W; The substrate is exposed to a metal precursor including tungsten under a bias voltage of 3 kW and a pressure of 230 mTorr, and a molybdenum conductor layer is deposited on the metal capping layer by thermal atomic layer deposition, wherein the metal capping layer is exposed to the molybdenum precursor; or c. A metal capping layer is deposited on a substrate including at least one feature by RF physical vapor deposition (PVD), the metal capping layer being substantially deposited on the bottom of one of the at least one feature and less than or equal to 5% deposited on at least one sidewall of the at least one feature, wherein the substrate is exposed to a metal precursor including molybdenum under a RF voltage of 3 kW, a bias voltage of 50 W and a pressure of 100 mTorr, and a molybdenum conductor layer is deposited on the metal capping layer by thermal atomic layer deposition, wherein the metal capping layer is exposed to the molybdenum precursor.

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