Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package includes: a first substrate including a first under-bump pattern, a second under-bump pattern, and a third under-bump pattern; a semiconductor wafer disposed on the first substrate; a conductive structure disposed on the first substrate; and a second substrate disposed on the semiconductor wafer and the conductive structure. The third under-bump pattern is electrically isolated from the first under-bump pattern and the second under-bump pattern. The conductive structure includes: a first conductive structure coupled to the first under-bump pattern; a second conductive structure coupled to the second under-bump pattern; and a third conductive structure coupled to the third under-bump pattern and disposed adjacent to the first and second conductive structures. The third conductive structure is disposed between the first and second conductive structures, wherein the first under-bump pattern is wider than the third under-bump pattern, and the second under-bump pattern is wider than the third under-bump pattern.

Description

Technical Field

[0001] [Cross - reference to Related Applications]

[0002] This application claims the priority of Korean Patent Application No. 10 - 2021 - 0100753, filed on Jul. 30, 2021 with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

[0003] A method, apparatus, and system consistent with exemplary embodiments relate to a semiconductor package, and more particularly, to a semiconductor package including a redistribution substrate and a method of manufacturing the semiconductor package. Prior Art

[0004] A semiconductor package is configured to use a semiconductor chip as part of an electronic product. The semiconductor package may include a printed circuit board (PCB) and a semiconductor chip mounted on the PCB and electrically connected to the PCB using bonding wires or bumps. With the development of the electronics industry, many studies are being conducted to improve the reliability and electrical characteristics of semiconductor packages. Summary of the Invention

[0005] Exemplary embodiments provide a semiconductor package having improved reliability and electrical characteristics and a method of manufacturing the semiconductor package.

[0006] According to an exemplary embodiment, a semiconductor package includes: a first substrate including a first under - bump pattern, a second under - bump pattern, and a third under - bump pattern; a semiconductor chip disposed on the first substrate; a conductive structure disposed on the first substrate, laterally spaced from the semiconductor chip and laterally spaced from each other; and a second substrate disposed on the semiconductor chip and the conductive structure. The third under - bump pattern is electrically isolated from the first under - bump pattern and the second under - bump pattern. The conductive structure includes: a first conductive structure coupled to the first under - bump pattern; a second conductive structure coupled to the second under - bump pattern; and a third conductive structure coupled to the third under - bump pattern and disposed adjacent to the first conductive structure and the second conductive structure. The third conductive structure is disposed between the first conductive structure and the second conductive structure. The first under - bump pattern is wider than the third under - bump pattern. The second under - bump pattern is wider than the third under - bump pattern.

[0007] According to an exemplary embodiment, a semiconductor package includes: a first substrate; a semiconductor chip disposed on the first substrate; a conduction structure disposed on the first substrate and laterally spaced apart from the semiconductor chip; and a second substrate disposed on the semiconductor chip and the conduction structure. The conduction structure includes a first conduction structure, a second conduction structure, and a third conduction structure adjacent to each other. The third conduction structure is disposed between the first conduction structure and the second conduction structure and is electrically isolated from the first conduction structure and the second conduction structure. The second substrate includes: a first redistribution pattern electrically connected to the first conduction structure; a second redistribution pattern electrically connected to the second conduction structure; and a third redistribution pattern electrically connected to the third conduction structure. The area of the top surface of the first redistribution pattern is larger than the area of the top surface of the third redistribution pattern, and the area of the top surface of the second redistribution pattern is larger than the area of the top surface of the third redistribution pattern.

[0008] According to an exemplary embodiment, a semiconductor package includes: a first substrate including a first insulating layer, an under bump pattern, an under bump seed pattern, a first ground / power conduction pattern, a second ground / power conduction pattern, and a signal conduction pattern; a semiconductor chip disposed on the top surface of the first substrate; a conduction structure disposed on the top surface of the first substrate and laterally spaced apart from both the semiconductor chip and each other; a molding layer disposed on the top surface of the first substrate, the side surfaces of the semiconductor chip, and the side surfaces of the conduction structure; and a second substrate disposed on the molding layer and the conduction structure and electrically connected to the conduction structure. The conduction structure includes: a first conduction structure coupled to the first ground / power conduction pattern; a second conduction structure coupled to the second ground / power conduction pattern; a third conduction structure coupled to the signal conduction pattern; and a fourth conduction structure coupled to the first ground / power conduction pattern. The third conduction structure is disposed between the first conduction structure and the second conduction structure. The under bump seed pattern is disposed on the side surface of the under bump pattern and spaced apart from the bottom surface of the under bump pattern. Brief Description of the Drawings

[0009] By reading the following description in conjunction with the accompanying drawings, the above and other aspects, features, and advantages will be more clearly understood. In the drawings: FIG. 1A is a plan view showing a semiconductor package according to an exemplary embodiment. FIG. 1B is a plan view showing a first redistribution substrate according to an exemplary embodiment. FIG. 1C is a plan view showing the layout structure of a lower ground / power redistribution pattern, a lower signal redistribution pattern, and a conduction structure according to an exemplary embodiment. FIG. 1D is a cross-sectional view taken along line A-B shown in FIG. 1A. FIG. 1E is an enlarged cross-sectional view showing portion E shown in FIG. 1D. FIG. 1F is a cross-sectional view taken along line C-D shown in FIG. 1A. FIG. 2 is a plan view showing the layout structure of a conduction structure according to an exemplary embodiment. FIGS. 3A and 3B are cross-sectional views showing a semiconductor package according to an exemplary embodiment. FIGS. 4A and 4B are cross-sectional views showing a semiconductor package according to an exemplary embodiment. FIGS. 5A and 5B are cross-sectional views showing a semiconductor package according to an exemplary embodiment. FIGS. 6A and 6B are cross-sectional views showing a semiconductor package according to an exemplary embodiment. FIG. 7A is a plan view of a semiconductor package according to an exemplary embodiment. FIG. 7B is a cross-sectional view taken along line A'-B' shown in FIG. 7A. FIG. 7C is a cross-sectional view taken along line C'-D' shown in FIG. 7A. FIG. 8A is a plan view of a semiconductor package according to an exemplary embodiment. FIG. 8B is a cross-sectional view taken along line A''-B'' shown in FIG. 8A. FIG. 8C is a cross-sectional view taken along line C''-D'' shown in FIG. 8A. FIGS. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, 9I, 9J, 9K, and 9L are cross-sectional views showing a method of manufacturing a semiconductor package according to an exemplary embodiment. FIGS. 10A, 10B, and 10C are cross-sectional views showing a method of manufacturing a semiconductor package according to an exemplary embodiment. Embodiments

[0010] Exemplary embodiments will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown. Throughout the specification, like reference numerals refer to like elements. It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly" on, "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When expressions such as "at least one of" appear before a series of elements, the expression modifies the entire series of elements and does not modify each individual element of the series. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0011] FIG. 1A is a plan view showing a semiconductor package according to an exemplary embodiment. FIG. 1B is a plan view showing a first redistribution substrate according to an exemplary embodiment. FIG. 1C is a plan view showing an arrangement structure of a lower ground / power redistribution line pattern, a lower signal redistribution line pattern, and a conduction structure according to an exemplary embodiment. FIG. 1D is a cross-sectional view taken along line A-B shown in FIG. 1A and corresponding to a cross-section taken along line A-B shown in FIGS. 1B and 1C. FIG. 1E is an enlarged cross-sectional view showing a portion E shown in FIG. 1D. FIG. 1F is a cross-sectional view taken along line C-D shown in FIG. 1A and corresponding to a cross-section taken along line C-D shown in FIGS. 1B and 1C.

[0012] Referring to FIGS. 1A, 1B, 1C, 1D, and 1E, the semiconductor package 10 may include a first redistribution substrate 100, solder balls 500, a semiconductor chip 200, a conduction structure 300, a molding layer 400, and a second redistribution substrate 600.

[0013] The solder balls 500 may be disposed on the bottom surface of the redistribution substrate. The solder balls 500 may be used as terminals of the semiconductor package 10. The solder balls 500 may include ground / power solder balls 500PG and signal solder balls 500S. The ground / power solder balls 500PG and the signal solder balls 500S may be laterally spaced apart from each other and may be electrically disconnected from each other (i.e., electrically isolated). A ground voltage or a power voltage may be applied to one or more of the ground / power solder balls 500PG. The voltage applied to one of the ground / power solder balls 500PG may be different from the voltage applied to another of the ground / power solder balls 500PG. The signal solder balls 500S may be used as signal paths for inputting data signals to or outputting data signals from the semiconductor chip 200. The solder balls 500 may be formed of or include a solder material. The solder material may include tin, bismuth, lead, silver, or an alloy thereof.

[0014] The first redistribution substrate 100 may include a first insulating layer 101, under-bump patterns 170PG and 170S, under-bump seed patterns 175, ground / power conduction patterns 130PG, signal conduction patterns 130S, a first seed pattern 135, seed pads 155, and first redistribution pads 150PG and 150S. The first insulating layer 101 may be formed of or include an organic material (e.g., a photosensitive insulating material). The photosensitive insulating material may include a polymer. For example, the photosensitive insulating material may be formed of or include at least one of photosensitive polyimide, polybenzoxazole, phenolic polymer, or benzocyclobutene-based polymer. In an exemplary embodiment, a plurality of first insulating layers 101 may be provided. The number of stacked first insulating layers 101 may be varied in various ways. In an exemplary embodiment, the first insulating layers 101 may be formed of or include the same material. There may be no observable interface between adjacent first insulating layers 101 in the first insulating layer 101.

[0015] The first direction D1 may be parallel to the bottom surface 101b of the lowermost one of the first insulating layers 101. The second direction D2 may be parallel to the bottom surface 101b of the lowermost one of the first insulating layers 101 and may be substantially perpendicular to the first direction D1. The third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2.

[0016] The under-bump patterns 170PG and 170S may include a ground / power under-bump pattern 170PG and a signal under-bump pattern 170S. Each of the under-bump patterns 170PG and 170S may be disposed in and on the lowermost one of the first insulating layers 101. The lower portion of each of the under-bump patterns 170PG and 170S may be disposed in the lowermost one of the first insulating layers 101. The lower portion of each of the under-bump patterns 170PG and 170S may serve as a solder pad. For example, a ground / power solder ball 500PG may be disposed on the bottom surface of the ground / power under-bump pattern 170PG and may be coupled to the ground / power under-bump pattern 170PG. A signal solder ball 500S may be disposed on the bottom surface of the signal under-bump pattern 170S and may be coupled to the signal under-bump pattern 170S. The upper portion of each of the under-bump patterns 170PG and 170S may have a width greater than that of the lower portion and may extend to a region on the top surface of the lowermost one of the first insulating layers 101.

[0017] As shown in FIG. 1D, the width of each of the ground / power under-bump patterns 170PG may be greater than the width of each of the signal under-bump patterns 170S. For example, the width of the top surface of each of the ground / power under-bump patterns 170PG may be greater than the width of the top surface of each of the signal under-bump patterns 170S. In an exemplary embodiment, the under-bump patterns 170PG and 170S may include a first under-bump pattern 171 and a second under-bump pattern 172 that are laterally spaced apart from each other. The signal under-bump pattern 170S may include a third under-bump pattern 173. The width W1 of the top surface of the first under-bump pattern 171 and the width W2 of the top surface of the second under-bump pattern 172 may be greater than the width W3 of the top surface of the third under-bump pattern 173. The width of the component may be measured in the first direction D1.

[0018] As shown in FIG. 1B, the length of each of the ground / power under-bump patterns 170PG may be greater than the length of each of the signal under-bump patterns 170S. For example, the length of the top surface of each of the ground / power under-bump patterns 170PG may be greater than the length of the top surface of each of the signal under-bump patterns 170S. In an exemplary embodiment, the length L1 of the top surface of the first under-bump pattern 171 and the length L2 of the top surface of the second under-bump pattern 172 may be greater than the length L3 of the top surface of the third under-bump pattern 173. The length of the component may be measured in the second direction D2.

[0019] When observed in a plan view, the area of the top surface of each of the patterns 170PG under the ground / power bumps can be greater than the area of the top surface of each of the patterns 170S under the signal bumps. For example, the area of the top surface of the third bump pattern 173 can be smaller than the area of the top surface of the first bump pattern 171 and the area of the top surface of the second bump pattern 172.

[0020] Since the upper portion of the pattern 170PG under the ground / power bumps has a relatively large width and length, the upper portion of each of the patterns 170PG under the ground / power bumps can be used to transfer the voltage transmitted from the solder terminal connected thereto in the horizontal direction. The voltage can be a ground voltage or a power voltage. The term "horizontal" can be used to represent a direction parallel to the first direction D1 or the second direction D2.

[0021] Since the top surface of the pattern 170PG under the ground / power bumps has a relatively large width and length, the pattern 170PG under the ground / power bumps can be used to shield the electrical signals generated from the signal conduction pattern 130S or an external device. Due to the shielding provided by the pattern 170PG under the ground / power bumps, the occurrence of electrical interference problems between the signal conduction pattern 130S and the external device can be prevented or reduced. The reliability in operating the semiconductor package 10 can be improved.

[0022] Hereinafter, the planar layout and shape of the patterns 170PG and 170S under the bumps will be described in more detail. As shown in FIG. 1B, the planar shape of each of the patterns 170S under the signal bumps can be circular. The patterns 170S under the signal bumps can have the same planar area, but the exemplary embodiments are not limited thereto. If an element is described as having the same level, width, length, or area, the element can be formed to have a level, width, length, or area within a specific process tolerance. In this specification, unless the context clearly indicates otherwise, the planar area of an element can represent the area of the top surface of the element. The planar shape of an element can represent the planar shape of the top surface of the element. The top surface of the pattern 170PG under the ground / power bumps can be different from the top surface of the pattern 170S under the signal bumps in terms of its shape and area. At least two of the patterns 170PG under the ground / power bumps can have different shapes. At least two of the patterns 170PG under the ground / power bumps can have different areas.

[0023] In a case where one of the ground / power bump-under patterns 170PG has a relatively large planar area, the one of the ground / power bump-under patterns 170PG may further have a first hole 179. The first hole 179 may be provided to penetrate the ground / power bump-under pattern 170PG from the top and the bottom. The first insulating layers 101 adjacent to the ground / power bump-under pattern 170PG may be in direct contact with each other through the first hole 179. Even when the ground / power bump-under pattern 170PG has a large planar area, due to the provision of the first hole 179, when observed in a plan view, it is possible to prevent the ground / power bump-under pattern 170PG from being densely arranged in a specific area. Accordingly, the reliability of the first rewiring substrate 100 can be improved. The presence or absence and the number of the first holes 179 may be determined based on the planar area of the ground / power bump-under pattern 170PG. As an example, one of the ground / power bump-under patterns 170PG may not have the first hole 179. As another example, another one of the ground / power bump-under patterns 170PG may have a plurality of first holes 179. At least two of the first holes 179 may be provided to have different shapes. At least two of the first holes 179 may have different diameters. The size and shape of the first hole 179 may be changed in various ways. Each of the signal bump-under patterns 170S may not have any holes penetrating each of the signal bump-under patterns 170S.

[0024] The bump-under patterns 170PG and 170S may be formed of a metal material (e.g., copper) or include a metal material (e.g., copper). In an exemplary embodiment, the bump-under patterns 170PG and 170S may not include titanium.

[0025] Referring to FIGS. 1D and 1E, the bottom surfaces 170b of the bump-under patterns 170PG and 170S may be placed at a level higher than the bottom surface 101b of the first insulating layer 101. The level may represent a vertical level, and the level difference between elements may be measured in the third direction D3.

[0026] The under-bump seed pattern 175 can be sandwiched between the lowermost one of the first insulating layers 101 and the under-bump patterns 170PG and 170S. For example, the under-bump seed pattern 175 can be disposed on the side surfaces of the lower portions of the under-bump patterns 170PG and 170S and on the bottom surfaces of the upper portions of the under-bump patterns 170PG and 170S. The under-bump seed pattern 175 can be formed of or include at least one of various conductive seed materials. The conductive seed material can be formed of or include at least one of copper, titanium, and / or their alloys. The under-bump seed pattern 175 can be used as a barrier layer and can prevent the materials in the under-bump patterns 170PG and 170S from diffusing into other components. The under-bump seed pattern 175 can be used as an adhesion layer. For example, the adhesion strength between the lowermost one of the first insulating layers 101 and the under-bump patterns 170PG and 170S can be improved by the under-bump seed pattern 175. Therefore, the under-bump patterns 170PG and 170S can be prevented from being damaged. In addition, the reliability and durability of the semiconductor package 10 can be improved.

[0027] The bonding strength between the solder ball 500 and the conductive seed material may be relatively low. The under-bump seed pattern 175 may not be disposed on the bottom surface 170b of the under-bump patterns 170PG and 170S. The solder ball 500 can be in direct contact and physical contact with the bottom surface 170b of the under-bump patterns 170PG and 170S. The adhesion strength between the solder ball 500 and the under-bump patterns 170PG and 170S can be greater than the bonding strength between the solder ball 500 and the conductive seed material. Therefore, the solder ball 500 can be stably bonded to the under-bump patterns 170PG and 170S.

[0028] As shown in FIG. 1E, each of the under-bump seed patterns 175 may have a first thickness T. The first thickness T may be the thickness of the first portion of each of the under-bump patterns 170PG and 170S, and the bottom surface of the first portion may be parallel to the first direction D1. The bottommost surface 175b of each of the under-bump seed patterns 175 may be placed at a level equal to or higher than the bottom surface 170b of the corresponding under-bump pattern 170PG or 170S. As an example, the level difference between the bottommost surface 175b of the under-bump seed pattern 175 and the bottom surface 170b of the under-bump pattern 170PG or 170S may be greater than the first thickness T and may be less than 10 times the first thickness T. The bottom surface 170b of each of the under-bump patterns 170PG and 170S may be disposed at a level higher than the bottom surface 101b of the lowermost one of the first insulating layers 101. The level difference between the bottom surface 170b of each of the under-bump patterns 170PG and 170S and the bottom surface 101b of the lowermost one of the first insulating layers 101 may be substantially equal to the first thickness T.

[0029] Referring to FIGS. 1D and 1F, the conductive patterns 130PG and 130S may be disposed on the under-bump patterns 170PG and 170S. The conductive patterns 130PG and 130S may include a ground / power conductive pattern 130PG and a signal conductive pattern 130S. The conductive patterns 130PG and 130S may be formed of a metal material (e.g., copper) or may include a metal material (e.g., copper). The expression "an element is coupled to the first redistribution substrate 100" may mean that the element may be coupled to at least one of the conductive patterns 130PG and 130S.

[0030] The ground / power conductive pattern 130PG may be electrically connected to the ground / power under-bump pattern 170PG. Each of the ground / power conductive patterns 130PG may include a first ground / power conductive pattern 131PG, a second ground / power conductive pattern 132PG, and a third ground / power conductive pattern 133PG. The first ground / power conductive pattern 131PG may be disposed on the corresponding one of the ground / power under-bump patterns 170PG and coupled to the corresponding one. The second ground / power conductive pattern 132PG may be disposed between the first ground / power conductive pattern 131PG and the third ground / power conductive pattern 133PG and may be coupled to the first ground / power conductive pattern 131PG and the third ground / power conductive pattern 133PG. The number of stacked ground / power conductive patterns 130PG is not limited to the illustrated example and may be varied in various ways.

[0031] Each of the signal conduction patterns 130S may include a first signal conduction pattern 131S, a second signal conduction pattern 132S, and a third signal conduction pattern 133S. The first signal conduction pattern 131S may be disposed on a corresponding one of the signal bump underlying patterns 170S and coupled to the corresponding one. The second signal conduction pattern 132S may be disposed between the first signal conduction pattern 131S and the third signal conduction pattern 133S, and may be coupled to the first signal conduction pattern 131S and the third signal conduction pattern 133S. The first signal conduction pattern 131S, the second signal conduction pattern 132S, and the third signal conduction pattern 133S may be laterally spaced apart from the first ground / power conduction pattern 131PG, the second ground / power conduction pattern 132PG, and the third ground / power conduction pattern 133PG, respectively. The expression "components are laterally spaced apart from each other" may mean that the components are spaced apart from each other in the horizontal direction. Each of the first signal conduction pattern 131S, the second signal conduction pattern 132S, and the third signal conduction pattern 133S may be formed of the same material as or include the same material as a corresponding one of the first ground / power conduction pattern 131PG, the second ground / power conduction pattern 132PG, and the third ground / power conduction pattern 133PG.

[0032] Each of the ground / power conduction patterns 130PG and each of the signal conduction patterns 130S may include a via portion and a line portion. The via portion may be disposed in a corresponding one of the first insulating layers 101. The line portion may be disposed on the via portion and may be directly connected to the via portion without an interface therebetween. The width of the line portion may be greater than the width of the via portion. The line portion may extend to a region on the top surface of the corresponding first insulating layer 101. In this specification, the via portion may be an element for vertical interconnection, and the line portion may be an element for horizontal interconnection. The term "vertical" may be used to represent a direction perpendicular to the bottom surface 101b of the lowermost one of the first insulating layers 101 (i.e., the third direction D3).

[0033] The first seed pattern 135 can be disposed on the bottom surface of a corresponding one of the conductive patterns 130PG and 130S. For example, the first seed pattern 135 can be disposed on the bottom surface of the signal conductive pattern 130S and on the bottom surface of the ground / power conductive pattern 130PG. For example, each of the first seed patterns 135 can be disposed on the bottom surface and side surface of the via portion of the corresponding conductive pattern 130PG or 130S and on the bottom surface of the line portion of the corresponding conductive pattern 130PG or 130S. The first seed pattern 135 may not extend to the side surface of the line portion. The first seed pattern 135 can be formed of a material different from the under-bump patterns 170PG and 170S, the ground / power conductive patterns 130PG, and the signal conductive pattern 130S or include a material different from the under-bump patterns 170PG and 170S, the ground / power conductive patterns 130PG, and the signal conductive pattern 130S. For example, the first seed pattern 135 can be formed of a conductive seed material or include a conductive seed material. The first seed pattern 135 can be used as a barrier layer and can prevent the diffusion of the materials included in the ground / power conductive patterns 130PG and the signal conductive pattern 130S.

[0034] The redistribution line pads 150PG and 150S can be disposed in the uppermost one of the first insulating layers 101. The redistribution line pads 150PG and 150S can further extend to a region on the top surface of the uppermost one of the first insulating layers 101. The redistribution line pads 150PG and 150S can include the ground / power redistribution line pads 150PG and the signal redistribution line pads 150S. Each of the ground / power redistribution line pads 150PG can be disposed on a corresponding one of the third ground / power conductive patterns 133PG. The ground / power redistribution line pads 150PG can be coupled to the ground / power under-bump pattern 170PG through the ground / power conductive pattern 130PG. Each of the signal redistribution line pads 150S can be disposed on a corresponding one of the third signal conductive patterns 133S. The signal redistribution line pads 150S can be electrically connected to the signal under-bump pattern 170S through the signal conductive pattern 130S. The signal redistribution line pads 150S can be electrically disconnected (i.e., electrically isolated) from the ground / power redistribution line pads 150PG. Due to the provision of the conductive patterns 130PG and 130S, at least one of the redistribution line pads 150PG and 150S may not be aligned with the under-bump pattern 170PG or 170S to which it is electrically connected in the vertical direction. Therefore, the setting of the under-bump patterns 170PG and 170S or the setting of the redistribution line pads 150PG and 150S can be designed more freely.

[0035] The redistribution pads 150PG and 150S can be formed of a metallic material (e.g., copper) or include a metallic material (e.g., copper). Each of the redistribution pads 150PG and 150S may further include a protective pad. The protective pad may be disposed on the top surface of the redistribution pads 150PG and 150S and can be formed of or include at least one of nickel, gold, and / or their alloys.

[0036] The seed pads 155 can be respectively disposed on the bottom surfaces of the redistribution pads 150PG and 150S. Each of the seed pads 155 may be sandwiched between the third signal conduction pattern 133S and the corresponding signal redistribution pad 150S, or sandwiched between the third ground / power conduction pattern 133PG and the corresponding ground / power redistribution pad 150PG. The seed pads 155 can extend into the region between the uppermost one of the first insulating layers 101 and the redistribution pads 150PG and 150S. The seed pads 155 can be formed of a material different from that of the first redistribution pads 150PG and 150S or include a material different from that of the first redistribution pads 150PG and 150S. The seed pads 155 can be formed of or include a conductive seed material.

[0037] In an exemplary embodiment, as shown in FIG. 1D, the under-bump patterns 170PG and 170S can have a relatively large thickness T1. For example, the thickness T1 of the under-bump patterns 170PG and 170S can be greater than the thickness T2 of the line portions of each of the ground / power conduction patterns 130PG and the thickness T3 of the line portions of each of the signal conduction patterns 130S. Accordingly, the first redistribution substrate 100 can have improved reliability. In a case where the thickness T1 of the under-bump patterns 170PG and 170S is less than 5 micrometers, the reliability of the semiconductor package 10 may deteriorate. In a case where the thickness T1 of the under-bump patterns 170PG and 170S is greater than 20 micrometers, it may be difficult to reduce the size of the semiconductor package 10. In an exemplary embodiment, the thickness T1 of the under-bump patterns 170PG and 170S can range from about 5 micrometers to 20 micrometers. The semiconductor package 10 can have improved reliability and a reduced size.

[0038] In a case where each of the upper portions of the under-bump patterns 170PG and 170S has the same width as its lower portion, due to the thickness T1 of the under-bump patterns 170PG and 170S, the top surface of the first insulating layer 101 may have an undulating shape. In such a case, the undulating shape of the top surface of the first insulating layer 101 may cause a failure in the electrical connection between the stacked first signal conduction patterns to the third signal conduction patterns 131S, 132S, and 133S or between the first ground / power conduction patterns to the third ground / power conduction patterns 131PG, 132PG, and 133PG. According to an exemplary embodiment, each of the upper portions of the under-bump patterns 170PG and 170S may have a width greater than that of its lower portion. Therefore, it is possible to prevent or suppress the top surface of the first insulating layer 101 from having an undulating shape. Accordingly, a highly reliable electrical connection structure can be provided between the stacked first signal conduction patterns to the third signal conduction patterns 131S, 132S, and 133S and between the stacked first ground / power conduction patterns to the third ground / power conduction patterns 131PG, 132PG, and 133PG.

[0039] The semiconductor wafer 200 may be mounted on the top surface of the first redistribution substrate 100. When observed in a plan view, the semiconductor wafer 200 may be disposed on the central region of the first redistribution substrate 100. The semiconductor wafer 200 may be one of a logic wafer, a buffer wafer, and a memory wafer. The logic wafer may include an application specific integrated circuit (ASIC) wafer or an application processor (AP) wafer. The ASIC wafer may include an application specific integrated circuit. In another exemplary embodiment, the semiconductor wafer 200 may include a central processing unit (CPU) or a graphic processing unit (GPU).

[0040] The semiconductor wafer 200 may include wafer pads 230 and an integrated circuit. The integrated circuit may be disposed in the semiconductor wafer 200. The wafer pads 230 may be disposed on the bottom surface of the semiconductor wafer 200 and may be coupled to the integrated circuit in the semiconductor wafer 200. The electrical connection with the semiconductor wafer 200 may represent an electrical connection with the integrated circuit through the wafer pads 230 of the semiconductor wafer 200.

[0041] A bump 250 may be sandwiched between the first redistribution substrate 100 and the semiconductor chip 200. For example, the bump 250 may be coupled to the redistribution pads 150PG and 150S and the chip pads 230. Thus, the semiconductor chip 200 may be coupled to the first redistribution substrate 100 by the bump 250. The ground chip pad of the chip pad 230 may be coupled to at least one of the first to third ground / power conduction patterns 131PG, 132PG, and 133PG by the bump 250. The power chip pad of the chip pad 230 may be coupled to at least one of the first to third ground / power conduction patterns 131PG, 132PG, and 133PG by the bump 250. The signal chip pad of the chip pad 230 may be coupled to at least one of the first to third signal conduction patterns 131PG, 132PG, and 133PG by the bump 250. The bump 250 may be formed of or include at least one of soldering materials. The bump 250 may further include a pillar pattern, and the pillar pattern may be formed of or include a metal material (e.g., copper). In such a case, the pillar pattern may contact the chip pad 230.

[0042] The conduction structure 300 may be disposed on the top surface of the first redistribution substrate 100. When observed in a plan view, the conduction structure 300 may be disposed on the edge region of the first redistribution substrate 100. When observed in a plan view, the edge region of the first redistribution substrate 100 may be disposed between the central region and the side surface of the first redistribution substrate 100. When observed in a plan view, the edge region of the first redistribution substrate 100 may be arranged to surround the central region. The conduction structure 300 may be laterally spaced from the semiconductor chip 200. The conduction structures 300 may be laterally spaced from each other. The width of the conduction structure 300 may be smaller than the width of the top surfaces of the redistribution pads 150PG and 150S.

[0043] The conduction structure 300 may include a ground / power structure 300PG and a signal structure 300S. The ground / power structure 300PG may be disposed on the ground / power redistribution line pad 150PG. The ground / power structure 300PG may be electrically connected to the ground / power under bump pattern 170PG through the ground / power conduction pattern 130PG. In this specification, the expression "electrically connected to each other" between components may mean that the components are directly connected to each other or indirectly connected to each other through another component. The signal structure 300S may be disposed on the signal redistribution line pad 150S. The signal structure 300S may be electrically connected to the signal under bump pattern 170S or the semiconductor chip 200 through the signal conduction pattern 130S. The width of the signal structure 300S may be equal to or different from the width of the ground / power structure 300PG. The number of the signal structures 300S may be less than the number of the ground / power structures 300PG. As another option, the number of the signal structures 300S may be equal to or greater than the number of the ground / power structures 300PG.

[0044] The conduction structure 300 may be used as an electrical conduction path between the first redistribution line substrate 100 and the second redistribution line substrate 600. For example, the ground / power structure 300PG may be used to transfer a ground voltage or a power voltage. The signal structure 300S may be used to transmit data signals to an external device or the semiconductor chip 200.

[0045] The ground / power structure 300PG may include a first ground / power structure 310 and a second ground / power structure 320. The first ground / power structure 310 and the second ground / power structure 320 may be the first conduction structure and the second conduction structure respectively. The ground / power structure 300PG may further include a fourth ground / power structure 340 and a fifth ground / power structure 350. The fourth ground / power structure 340 and the fifth ground / power structure 350 may be the fourth conduction structure and the fifth conduction structure respectively. The fourth ground / power structure 340 and the fifth ground / power structure 350 will be described in more detail below.

[0046] The signal structure 300S may include a third conductive structure 330. The third conductive structure 330 can be used as a conductive path for fast transmission of data signals. In a case where other signal structures 300S in the signal structure 300S are disposed near the third conductive structure 330, coupling noise may occur between the other signal structures 300S in the signal structure 300S and the third conductive structure 330. In an exemplary embodiment, the third conductive structure 330 may be disposed between the first ground / power structure 310 and the second ground / power structure 320 in a first direction D1. Here, the third conductive structure 330 may be adjacent to the first ground / power structure 310 and the second ground / power structure 320. For example, none of the conductive structures 300 may be disposed in a first region between the third conductive structure 330 and the first ground / power structure 310 and a second region between the third conductive structure 330 and the second ground / power structure 320. The ground / power structure 300PG can prevent electrical interference between the conductive elements 300. Since the third conductive structure 330 is disposed between the first ground / power structure 310 and the second ground / power structure 320, coupling noise problems in the third conductive structure 330 can be prevented. Therefore, the reliability and electrical characteristics of the semiconductor package 10 can be improved.

[0047] As shown in FIG. 1A, the third conductive structure 330 may be disposed between the ground / power structures 300PG in a second direction D2. Therefore, the reliability and electrical characteristics of the semiconductor package 10 can be further improved. The planar layout of the signal structure 300S and the ground / power structure 300PG is not limited to the illustrated examples and can be changed in various ways.

[0048] As shown in FIG. 1D, the molding layer 400 may be disposed on the first redistribution substrate 100 and the semiconductor wafer 200. The molding layer 400 may be disposed on the uppermost one of the first insulating layers 101. The molding layer 400 may be disposed on the side surfaces of the conductive structure 300. The top surface of the molding layer 400 may be substantially at the same level as the top surface of the conductive structure 300. The molding layer 400 may further extend into the gap between the semiconductor wafer 200 and the first redistribution substrate 100 to hermetically seal the bumps 250. The molding layer 400 may be formed of an insulating polymer (e.g., epoxy molding compound) or include an insulating polymer (e.g., epoxy molding compound). The molding layer 400 may not extend to the region below the bottom surface of the semiconductor wafer 200, and an under-fill layer may be further disposed in the gap region between the first redistribution substrate 100 and the semiconductor wafer 200. The under-fill layer may be formed of an insulating polymer (e.g., epoxy polymer) or include an insulating polymer (e.g., epoxy polymer).

[0049] The second rewiring substrate 600 may be disposed on the molding layer 400 and the conduction structure 300 and may be electrically connected to the conduction structure 300. For example, the second rewiring substrate 600 may be disposed on the semiconductor wafer 200 and may be spaced apart from the top surface of the semiconductor wafer 200. The molding layer 400 may extend into the region between the top surface of the semiconductor wafer 200 and the second rewiring substrate 600.

[0050] The second rewiring substrate 600 may include a second insulating layer 601, a rewiring pattern, a second seed pattern 615, a third seed pattern 625, an upper seed pad 655, and bonding pads 650PG and 650S. The second insulating layer 601 may include a plurality of second insulating layers 601. The second insulating layer 601 may be stacked on the molding layer 400. The second insulating layer 601 may be formed of or include at least one of a photosensitive insulating material or an insulating polymer. In an exemplary embodiment, the second insulating layer 601 may be formed of or include the same material. There may be no observable interface between adjacent second insulating layers 601 in the second insulating layer 601, but the exemplary embodiment is not limited thereto. The number of the second insulating layers 601 may be changed in various ways.

[0051] The redistribution pattern may include lower redistribution patterns 610PG and 610S and upper redistribution patterns 620PG and 620S. The lower redistribution patterns 610PG and 610S may include a lower ground / power redistribution pattern 610PG and a lower signal redistribution pattern 610S. The lower redistribution pattern 610PG and the lower redistribution pattern 610S may be laterally spaced apart from each other and may be electrically disconnected from each other (i.e., electrically isolated). Each of the lower redistribution patterns 610PG and 610S may include a first via portion and a first line portion. The first via portion of each of the lower redistribution patterns 610PG and 610S may be disposed in the lowermost one of the second insulating layers 601 to contact the top surface of the corresponding conduction structure 300. The width of the first via portion of each of the lower redistribution patterns 610PG and 610S may be smaller than the width of the corresponding conduction structure 300. The first line portion may be disposed on the first via portion and may be connected to the first via portion without an interface therebetween. The width of the first line portion of each of the lower redistribution patterns 610PG and 610S may be greater than the width of the top surface of the first via portion. The first line portion may extend to an area on the top surface of the corresponding second insulating layer 601. At least one of the lower ground / power redistribution patterns 610PG may include a plurality of first via portions, and the first line portion may be connected to the first via portion. The lower redistribution patterns 610PG and 610S may be formed of a metal material (e.g., copper) or may include a metal material (e.g., copper).

[0052] The lower ground / power redistribution pattern 610PG may be disposed on the ground / power structure 300PG and may be electrically connected to the ground / power structure 300PG. The lower ground / power redistribution pattern 610PG may include a first ground / power redistribution pattern 611 and a second ground / power redistribution pattern 612. The first ground / power redistribution pattern 611 may be electrically connected to the first ground / power structure 310. The second ground / power redistribution pattern 612 may be electrically connected to the second ground / power structure 320. The second ground / power redistribution pattern 612 may be laterally spaced apart from the first ground / power redistribution pattern 611 and may be electrically disconnected from the first ground / power redistribution pattern 611 (i.e., electrically isolated), but the exemplary embodiments are not limited thereto.

[0053] The lower signal redistribution line pattern 610S can be disposed on the signal structure 300S and can be electrically connected to the signal structure 300S. As an example, the lower signal redistribution line pattern 610S can correspond to the signal structure 300S in a one-to-one manner. That is, as shown in FIGS. 1C and 1D, each of the lower signal redistribution line patterns 610S can be electrically connected to a corresponding one of the signal structures 300S. The lower signal redistribution line pattern 610S can include a third redistribution line pattern 613. The third redistribution line pattern 613 can be electrically connected to the third conduction structure 330. The third redistribution line pattern 613 may not be electrically connected to other conduction structures 300 in the conduction structure 300 other than the third conduction structure 330. Hereinafter, the lower ground / power redistribution line pattern 610PG and the lower signal redistribution line pattern 610S will be described in more detail below.

[0054] As shown in FIG. 1C, the top surface of each of the lower ground / power redistribution line patterns 610PG can have a planar area greater than the top surface of each of the lower signal redistribution line patterns 610S. For example, the planar area of the top surface of the first ground / power redistribution line pattern 611 can be greater than the planar area of the top surface of the third redistribution line pattern 613. The area of the top surface of the second ground / power redistribution line pattern 612 can be greater than the planar area of the top surface of the third redistribution line pattern 613.

[0055] In a case where one of the lower ground / power redistribution line patterns 610PG has a relatively large planar area, the one of the lower ground / power redistribution line patterns 610PG can have a second hole 619. The second hole 619 can be formed to penetrate the lower ground / power redistribution line pattern 610PG from top to bottom. For example, the planar area of the first ground / power redistribution line pattern 611 can be relatively large. The first ground / power redistribution line pattern 611 can have the second hole 619. Due to the provision of the second hole 619, when observed in a plan view, it is possible to prevent the lower ground / power redistribution line patterns 610PG from being densely disposed in a specific area. Therefore, the reliability of the second redistribution line substrate 600 can be improved. The second hole 619 may not be provided in the second ground / power redistribution line pattern 612. As another option, the second hole 619 can be further provided in the second ground / power redistribution line pattern 612. The presence or absence of the second hole 619 and the number of the second holes 619 can be determined based on the planar area of the lower ground / power redistribution line pattern 610PG. The second insulating layers 601 adjacent to the lower ground / power redistribution line pattern 610PG can be in direct contact with each other through the second hole 619. Each of the lower signal redistribution line patterns 610S may not have a hole that penetrates each of the lower signal redistribution line patterns 610S.

[0056] As shown in FIGS. 1C, 1D, and 1E, when observed in a plan view, at least one of the lower ground / power redistribution line patterns 610PG may overlap with the plurality of ground / power structures 300PG. One of the lower ground / power redistribution line patterns 610PG may be electrically connected to the ground / power structure 300PG. For example, the first ground / power redistribution line pattern 611 may be disposed on the fourth ground / power structure 340 and may be electrically connected to the fourth ground / power structure 340. The fourth ground / power structure 340 may be electrically connected to the first ground / power structure 310 through the first ground / power redistribution line pattern 611. In other words, the first ground / power structure 310 and the fourth ground / power structure 340 may be coupled to each other through the first ground / power redistribution line pattern 611 to form a single conductive element / structure. The same voltage may be applied to the first ground / power structure 310 and the fourth ground / power structure 340.

[0057] As shown in FIGS. 1C and 1F, the second ground / power redistribution line pattern 612 may be further disposed on the fifth ground / power structure 350 and may be electrically connected to the fifth ground / power structure 350. The fifth ground / power structure 350 may be electrically connected to the second ground / power structure 320 through the second ground / power redistribution line pattern 612. The second ground / power structure 320 and the fifth ground / power structure 350 may be coupled to each other through the second ground / power redistribution line pattern 612 to form a single conductive element / structure. The same voltage may be applied to the second ground / power structure 320 and the fifth ground / power structure 350. The number of ground / power structures 300PG coupled to the first ground / power redistribution line pattern 611 and the number of ground / power structures 300PG coupled to the second ground / power redistribution line pattern 612 may be changed in various ways.

[0058] The second seed pattern 615 may be respectively disposed under the bottom surfaces of the lower ground / power redistribution line pattern 610PG and the lower signal redistribution line pattern 610S. For example, the second seed pattern 615 may be in direct contact with the top surface of the conductive structure 300. The second seed pattern 615 may extend into the region between the lower redistribution line patterns 610PG and 610S and the lowermost one of the second insulating layer 601. The second seed pattern 615 may be formed of or include a conductive seed material. The second seed pattern 615 may be used as a barrier layer.

[0059] The upper redistribution line patterns 620PG and 620S may include an upper ground / power redistribution line pattern 620PG and an upper signal redistribution line pattern 620S. Each of the upper redistribution line patterns 620PG and 620S may include a second via portion and a second line portion. The second via portion of each of the upper redistribution line patterns 620PG and 620S may be disposed in a corresponding second insulating layer 601. The second line portion may be disposed on the second via portion and connected to the second via portion, and in this case, there may be no observable interface between the second line portion and the second via portion. The width of the second line portion may be greater than the width of the top surface of the second via portion. The second line portion may extend to a region on the top surface of the corresponding second insulating layer 601. The upper redistribution line patterns 620PG and 620S may be formed of a metal material (e.g., copper) or include a metal material (e.g., copper).

[0060] The upper signal redistribution line pattern 620S may be disposed on the lower signal redistribution line pattern 610S and may be electrically connected to the lower signal redistribution line pattern 610S. The upper signal redistribution line pattern 620S may be coupled to the signal structure 300S in a one-to-one manner by the lower redistribution line pattern 610S.

[0061] The upper ground / power redistribution line pattern 620PG may be disposed on the lower signal redistribution line pattern 610S and may be electrically connected to the lower signal redistribution line pattern 610S. At least one of the upper ground / power redistribution line patterns 620PG may be electrically connected to a plurality of ground / power structures 300PG. The upper ground / power redistribution line pattern 620PG may be laterally spaced apart from the upper signal redistribution line pattern 620S and may be electrically disconnected (i.e., electrically isolated) from the upper signal redistribution line pattern 620S. The top surface of each of the upper ground / power redistribution line patterns 620PG may have an area that may be greater than the top surface of each of the upper signal redistribution line patterns 620S. In this case, at least one of the upper ground / power redistribution line patterns 620PG may further have a hole. The hole may be provided to have characteristics similar to the second hole 619 in the previous exemplary embodiment described with reference to FIG. 1C. However, the exemplary embodiment is not limited to this example.

[0062] The first ground / power structure 310 and the fourth ground / power structure 340 may be coupled to each other by one of the upper ground / power redistribution line patterns 620PG to form a single conductive element / structure. As another example, the second ground / power structure 320 and the fifth ground / power structure 350 may be coupled to each other by another of the upper ground / power redistribution line patterns 620PG to form a single conductive element / structure.

[0063] The electrical connection with the second wiring substrate 600 may represent an electrical connection with at least one of the lower ground / power redistribution line pattern 610PG, the lower signal redistribution line pattern 610S, the upper ground / power redistribution line pattern 620PG, and the upper signal redistribution line pattern 620S.

[0064] The third seed pattern 625 may be disposed on the bottom surfaces of the upper ground / power redistribution line pattern 620PG and the upper signal redistribution line pattern 620S. For example, the third seed pattern 625 may be sandwiched between the lower redistribution line patterns 610PG and 610S and the upper redistribution line patterns 620PG and 620S. For example, the second seed pattern 615 may be formed of or include a conductive seed material. The second seed pattern 615 may be used as a barrier layer.

[0065] The bonding pads 650PG and 650S may include a ground / power bonding pad 650PG and a signal bonding pad 650S. The ground / power bonding pad 650PG may be disposed on the upper ground / power redistribution line pattern 620PG and coupled to the upper ground / power redistribution line pattern 620PG. The signal bonding pad 650S may be disposed on the upper signal redistribution line pattern 620S and coupled to the upper signal redistribution line pattern 620S. The bonding pad 650PG and the bonding pad 650S may be laterally spaced apart from each other.

[0066] The lower portions of each of the bonding pads 650PG and 650S may be disposed in the uppermost one of the second insulating layers 601. The upper portions of each of the bonding pads 650PG and 650S may further extend to a region on the top surface of the uppermost one of the second insulating layers 601. The upper portions of each of the bonding pads 650PG and 650S may have a width greater than that of the lower portions. The bonding pads 650PG and 650S may be formed of or include a metal material (e.g., copper). Since the upper redistribution line patterns 620PG and 620S and the lower redistribution line patterns 610PG and 610S are provided, at least one of the bonding pads 650PG or 650S may not be aligned with the conductive structure 300 to which it is electrically connected in the vertical direction. Therefore, the arrangement of the bonding pads 650PG and 650S can be designed more freely.

[0067] The upper seed pads 655 can be respectively disposed on the bottom surfaces of the bonding pads 650PG and 650S. The upper seed pads 655 can be sandwiched between the upper redistribution line patterns 620PG and 620S and the bonding pads 650PG and 650S. The upper seed pads 655 can be formed of or include a conductive seed material.

[0068] FIG. 2 is a plan view showing an arrangement structure of a conductive structure according to an exemplary embodiment. To simplify the description, the previously described elements may be identified by the same reference numerals, and overlapping descriptions thereof will not be repeated.

[0069] Referring to FIG. 2, the conductive structure 300 may include a ground / power structure 300PG and a signal structure 300S. When observed in a plan view, the ground / power structure 300PG and the signal structure 300S may be alternately disposed. For example, the ground / power structure 300PG and the signal structure 300S may be alternately arranged in a first direction D1. The ground / power structure 300PG and the signal structure 300S may be alternately arranged in a second direction D2. The third conductive structure 330 of the signal structure 300S may be disposed between the first ground / power structure 310 and the second ground / power structure 320. The arrangement of the conductive structure 300 can be changed in various ways.

[0070] FIG. 3A is a cross-sectional view taken along line A-B shown in FIG. 1A to show a semiconductor package according to an exemplary embodiment. FIG. 3B is a cross-sectional view taken along line C-D shown in FIG. 1A to show a semiconductor package according to an exemplary embodiment. To simplify the description, the previously described elements may be identified by the same reference numerals, and overlapping descriptions thereof will not be repeated.

[0071] Referring to FIGS. 1A, 3A and 3B, the semiconductor package 10A may include a first redistribution substrate 100, solder balls 500, a semiconductor wafer 200, a conductive structure 300, a molding layer 400, and a second redistribution substrate 600. The conductive structure 300, the signal under bump pattern 170S, and the ground / power under bump pattern 170PG may be configured to have substantially the same features as those in the previous exemplary embodiments described with reference to FIGS. 1A to 1F. For example, respectively, the width of the ground / power under bump pattern 170PG may be greater than the width of the signal under bump pattern 170S, and the length of the ground / power under bump pattern 170PG may be greater than the length of the signal under bump pattern 170S. The planar area of the ground / power under bump pattern 170PG may be greater than the planar area of the signal under bump pattern 170S, respectively. The conductive structure 300 may include a ground / power structure 300PG and a signal structure 300S. However, the ground / power structures 300PG may not be coupled to each other by the lower ground / power redistribution pattern 610PG.

[0072] At least two of the ground / power structures 300PG may be coupled to each other by the ground / power conduction pattern 130PG of the first redistribution substrate 100. For example, the ground / power conduction pattern 130PG may include a first ground / power sharing pattern 1301PG and a second ground / power sharing pattern 1302PG. The first ground / power sharing pattern 1301PG and the second ground / power sharing pattern 1302PG may be referred to as the first sharing conduction pattern and the second sharing conduction pattern, respectively. The first ground / power sharing pattern 1301PG may have a relatively large planar area. The first ground / power sharing pattern 1301PG may be one of the second ground / power conduction patterns 132PG. The first ground / power structure 310 may be electrically connected to the first ground / power sharing pattern 1301PG by a corresponding third ground / power conduction pattern 133PG. The fourth ground / power structure 340 may be electrically connected to the first ground / power sharing pattern 1301PG by a corresponding third ground / power conduction pattern 133PG. Therefore, the first ground / power structure 310 and the fourth ground / power structure 340 may be electrically connected to each other by the first ground / power sharing pattern 1301PG. The first ground / power structure 310 and the fourth ground / power structure 340 may be applied with the same voltage by the first under bump pattern 171. Due to the provision of the first ground / power sharing pattern 1301PG, the electrical conduction path between the first under bump pattern 171 and the first ground / power structure 310 and the fourth ground / power structure 340 can be simplified. That is, the ground / power conduction pattern 130PG can be designed in a more simplified manner.

[0073] The second ground / power sharing pattern 1302PG can be electrically connected to the second under-bump pattern 172. The second ground / power sharing pattern 1302PG can be another one of the second ground / power conduction patterns 132PG. The second ground / power sharing pattern 1302PG can have a relatively large planar area. As shown in FIG. 3B, the second ground / power sharing pattern 1302PG can be electrically connected to the second ground / power structure 320 and the fifth ground / power structure 350 through the third ground / power conduction pattern 133PG and the ground / power redistribution line pad 150PG. Therefore, the second ground / power structure 320 and the fifth ground / power structure 350 can be electrically connected to each other through the second ground / power sharing pattern 1302PG. The same voltage can be applied to the second ground / power structure 320 and the fifth ground / power structure 350. Due to the provision of the second ground / power sharing pattern 1302PG, the ground / power conduction pattern 130PG can be designed in a more simplified manner.

[0074] For example, the first ground / power sharing pattern 1301PG can be one of the first ground / power conduction patterns 131PG or one of the third ground / power conduction patterns 133PG.

[0075] As another example, the second ground / power sharing pattern 1302PG can be one of the first ground / power conduction patterns 131PG or one of the third ground / power conduction patterns 133PG.

[0076] At least one of the first ground / power sharing pattern 1301PG and the second ground / power sharing pattern 1302PG can further have a hole passing through the at least one. The hole can be similar to the first hole 179 of the under-bump patterns 170PG and 170S shown in FIG. 1B.

[0077] FIG. 4A is a cross-sectional view taken along line A-B shown in FIG. 1A to show a semiconductor package according to an exemplary embodiment. FIG. 4B is a cross-sectional view taken along line C-D shown in FIG. 1A to show a semiconductor package according to an exemplary embodiment.

[0078] Referring to FIGS. 1A, 4A and 4B, the semiconductor package 10B may include a first redistribution substrate 100, solder balls 500, a semiconductor die 200, a conductive structure 300, a molding layer 400, and a second redistribution substrate 600. The semiconductor die 200, the conductive structure 300, the molding layer 400, and the second redistribution substrate 600 may be configured to have substantially the same features as described above. However, the semiconductor package 10B may not include the bumps 250 described with reference to FIG. 1D.

[0079] The first redistribution substrate 100 may include under-bump patterns 170PG and 170S, an under-bump seed pattern 175, a first insulating layer 101, a ground / power conductive pattern 130PG, a signal conductive pattern 130S, and a first seed pattern 135. In the present exemplary embodiment, the first redistribution substrate 100 may not include the redistribution pads 150PG and 150S and the seed pads 155 shown in FIG. 1D.

[0080] The first redistribution substrate 100 may be in direct contact with the semiconductor die 200 and the molding layer 400. For example, the uppermost one of the first insulating layer 101 may be in direct contact and physical contact with the bottom surface of the semiconductor die 200 and the bottom surface of the molding layer 400. The first seed pattern 135 in the uppermost one of the first insulating layer 101 may be directly coupled to the die pads 230 and the conductive structure 300. The first seed pattern 135 may be disposed on the top surface of the ground / power conductive pattern 130PG and the top surface of the signal conductive pattern 130S. The line portion of each of the ground / power conductive pattern 130PG and the signal conductive pattern 130S may be disposed below the bottom surface of its via portion.

[0081] The lower portion of each of the signal bump-down patterns 170S may have a width greater than that of its upper portion. The signal solder balls 500S may be respectively disposed on the bottom surfaces of the signal bump-down patterns 170S. The lower portion of each of the ground / power bump-down patterns 170PG may have a width greater than that of its upper portion. The ground / power solder balls 500PG may be respectively disposed on the bottom surfaces of the ground / power bump-down patterns 170PG. The width of the bottom surface of the ground / power bump-down pattern 170PG may be greater than the width of the bottom surface of the signal bump-down pattern 170S. For example, both the width W1' of the bottom surface of the first bump-down pattern 171 and the width W2' of the second bump-down pattern 172 may be greater than the width W3' of the bottom surface of the third bump-down pattern 173. The length of the bottom surface of each of the ground / power bump-down patterns 170PG may be greater than the length of the bottom surface of each of the signal bump-down patterns 170S. The area of the bottom surface of each of the ground / power bump-down patterns 170PG may be greater than the area of the bottom surface of each of the signal bump-down patterns 170S.

[0082] The first ground / power redistribution line pattern 611 may be electrically connected to the first ground / power structure 310 and the fourth ground / power structure 340. As shown in FIG. 4B, the second ground / power redistribution line pattern 612 may be electrically connected to the second ground / power structure 320 and the fifth ground / power structure 350.

[0083] As another alternative, as described with reference to FIG. 3A, the first ground / power structure 310 and the fourth ground / power structure 340 may be electrically connected to one of the ground / power conduction patterns 130PG of the first redistribution line substrate 100. One of the ground / power conduction patterns 130PG may be the first ground / power sharing pattern 1301PG shown in FIG. 3A. The second ground / power structure 320 and the fifth ground / power structure 350 may be electrically connected to the other of the ground / power conduction patterns 130PG. The other of the ground / power conduction patterns 130PG may be the second ground / power sharing pattern 1302PG described with reference to FIGS. 3A and 3B.

[0084] The semiconductor package 10B may be manufactured by a chip-first process, but the exemplary embodiments are not limited to this example.

[0085] FIG. 5A is a cross-sectional view taken along line A-B shown in FIG. 1A to show a semiconductor package according to an exemplary embodiment. FIG. 5B is a cross-sectional view taken along line C-D shown in FIG. 1A to show a semiconductor package according to an exemplary embodiment.

[0086] Referring to FIGS. 5A and 5B, the semiconductor package 1 may include a lower package 10' and an upper package 20. The lower package 10' may be configured to have substantially the same features as the semiconductor package 10 described with reference to FIGS. 1A to 1F. The lower package 10' may include a first redistribution substrate 100, solder balls 500, semiconductor wafers 200, a molding layer 400, a conductive structure 300, and a second redistribution substrate 600. As another example, the lower package 10' may be substantially the same as the semiconductor package 10A shown in FIGS. 3A and 3B or the semiconductor package 10B shown in FIGS. 4A and 4B.

[0087] The upper package 20 may include an upper semiconductor wafer 720, upper bumps 750, and an upper molding layer 740. The upper semiconductor wafer 720 may be a wafer of a different type from the semiconductor wafer 200. As an example, the upper semiconductor wafer 720 may be a memory wafer, and the semiconductor wafer 200 may be a logic wafer. The upper semiconductor wafer 720 may be mounted on the top surface of the second redistribution substrate 600. For example, the upper bumps 750 may be disposed between the second redistribution substrate 600 and the upper semiconductor wafer 720. The upper bumps 750 may be respectively coupled to the bonding pads 650PG and 650S and the upper wafer pads 730 of the upper semiconductor wafer 720. The upper bumps 750 may be formed of or include a soldering material. The upper bumps 750 may further include a pillar pattern. The upper semiconductor wafer 720 may be coupled to the semiconductor wafer 200 or the solder balls 500 through the second redistribution substrate 600 and the conductive structure 300.

[0088] The upper molding layer 740 may be disposed on the side surfaces of the second redistribution substrate 600 and the upper semiconductor wafer 720. The upper molding layer 740 may further be disposed on the lower surface of the upper semiconductor wafer 720. The upper molding layer 740 may be directly disposed on the second redistribution substrate 600. The upper molding layer 740 may not be disposed on the top surface of the upper semiconductor wafer 720. The upper molding layer 740 may be formed of or include an insulating polymer (e.g., an epoxy molding compound).

[0089] The upper package 20 may further include a heat dissipation structure 790. The heat dissipation structure 790 may be disposed on the top surface of the upper semiconductor chip 720 and the top surface of the upper molding layer 740. In an exemplary embodiment, the heat dissipation structure 790 may extend along the side surface of the upper molding layer 740. The heat dissipation structure 790 may include a heat sink, a heat slug, or a thermal interface material (TIM) layer. The heat dissipation structure 790 may be formed of or include at least one of, for example, a metal material.

[0090] The upper package 20 may not include the heat dissipation structure 790, and the upper molding layer 740 may be disposed on the top surface of the upper semiconductor chip 720.

[0091] FIG. 6A is a cross-sectional view taken along line A-B shown in FIG. 1A to show a semiconductor package according to an exemplary embodiment. FIG. 6B is a cross-sectional view taken along line C-D shown in FIG. 1A to show a semiconductor package according to an exemplary embodiment.

[0092] Referring to FIGS. 6A and 6B, the semiconductor package 1A may include a lower package 10', an upper package 20A, and connection bumps 675. The lower package 10' may be configured to have substantially the same features as the semiconductor package 10 described with reference to FIGS. 1A to 1F. As another example, the lower package 10' may be configured to have substantially the same features as the semiconductor package 10A shown in FIGS. 3A and 3B or the semiconductor package 10B shown in FIGS. 4A and 4B.

[0093] The upper package 20A may include an upper substrate 710, an upper semiconductor chip 720, upper bumps 750', and an upper molding layer 740. The upper substrate 710 may be disposed on the top surface of the second redistribution substrate 600 and spaced apart from the top surface of the second redistribution substrate 600. The upper substrate 710 may be a printed circuit board or a redistribution layer. The upper bumps 750' may be sandwiched between the upper substrate 710 and the upper semiconductor chip 720, and may be coupled to the upper substrate 710 and the upper chip pads 730. The expression "an element is coupled to the upper substrate 710" may mean that the element is electrically connected to a metal line in the upper substrate 710. The upper molding layer 740 may be disposed on the upper substrate 710 and the upper semiconductor chip 720.

[0094] The connection bumps 675 can be clamped between the lower package 10’ and the upper package 20A. For example, the connection bumps 675 can be clamped between the second rewiring substrate 600 and the upper substrate 710, and can be electrically connected to the bonding pads 650PG and 650S and the upper substrate 710. The connection bumps 675 can be formed of a solder material or include a solder material. The connection bumps 675 can further include a metal pillar pattern, but the exemplary embodiment is not limited to this example.

[0095] The upper package 20A can further include a heat dissipation structure 790.

[0096] FIG. 7A is a plan view of a semiconductor package according to an exemplary embodiment. FIG. 7B is a cross-sectional view taken along line A’-B’ shown in FIG. 7A. FIG. 7C is a cross-sectional view taken along line C’-D’ shown in FIG. 7A.

[0097] Referring to FIGS. 7A, 7B, and 7C, the semiconductor package 1B can include a lower package 11 and an upper package 21B. The lower package 11 can include a first rewiring substrate 100, solder balls 500, a semiconductor wafer 200, a conduction structure 300, a molding layer 400, and a second rewiring substrate 600. The upper package 21B can include an upper semiconductor wafer 720, upper bumps 750, and an upper molding layer 740. The upper package 21B can further include a heat dissipation structure 790.

[0098] When observed in a plan view, the first rewiring substrate 100 can have a first region R1 and a second region R2. The first region R1 of the first rewiring substrate 100 can be adjacent to the first side surface of the first rewiring substrate 100. The second region R2 of the first rewiring substrate 100 can be adjacent to the second side surface of the first rewiring substrate 100. For example, the second region R2 of the first rewiring substrate 100 can be disposed between the first region R1 and the second side surface. The second side surface of the first rewiring substrate 100 can be opposite to the first side surface.

[0099] The semiconductor wafer 200 can be disposed on the top surface of the first region R1 of the first rewiring substrate 100. The conduction structure 300 can be disposed on the top surface of the second region R2 of the first rewiring substrate 100.

[0100] When observed in a plan view, the upper semiconductor wafer 720 may be disposed on the second wiring substrate 600 and may overlap with the first region R1 and the second region R2 of the first wiring substrate 100. At least a portion of the upper semiconductor wafer 720 may overlap with the conduction structure 300 in a vertical direction (i.e., along the third direction D3). The upper wafer pad 730 may overlap with the second region R2 of the first wiring substrate 100 in a vertical direction. Accordingly, the length of the electrical conduction path between the upper semiconductor wafer 720 and the conduction structure 300 may be reduced. The semiconductor package 1B may exhibit improved electrical characteristics.

[0101] FIG. 8A is a plan view of a semiconductor package according to an exemplary embodiment. FIG. 8B is a cross-sectional view taken along line A''-B'' shown in FIG. 8A. FIG. 8C is a cross-sectional view taken along line C''-D'' shown in FIG. 8A.

[0102] Referring to FIGS. 8A, 8B, and 8C, the semiconductor package 1C may include a lower package 12 and an upper package 21C. The lower package 12 may include a first wiring substrate 100, solder balls 500, a first semiconductor wafer 201, a second semiconductor wafer 202, a conduction structure 300, a molding layer 400, and a second wiring substrate 600. Each of the first semiconductor wafer 201 and the second semiconductor wafer 202 may be arranged to have the same or similar features as the semiconductor wafer 200 described with reference to FIG. 1D. The second semiconductor wafer 202 may be laterally spaced apart from the first semiconductor wafer 201. The second semiconductor wafer 202 may be of the same type as the first semiconductor wafer 201, or may be of a different type from the first semiconductor wafer 201. The first bump 251 may be disposed between the first wiring substrate 100 and the first semiconductor wafer 201 and may be coupled to the redistribution pads 150PG and 150S and the wafer pad 231 of the first semiconductor wafer 201. The second bump 252 may be disposed between the first wiring substrate 100 and the second semiconductor wafer 202 and may be coupled to the redistribution pads 150PG and 150S and the wafer pad 232 of the second semiconductor wafer 202. The first bump 251 and the second bump 252 may be arranged to have the same or similar features as the bump 250 described with reference to FIG. 1D.

[0103] When observed in a plan view, the conduction structure 300 may be spaced apart from the first semiconductor wafer 201 and the second semiconductor wafer 202 and may be arranged to surround the first semiconductor wafer 201 and the second semiconductor wafer 202. For example, the conduction structure 300 may be disposed between the first semiconductor wafer 201 and the second semiconductor wafer 202.

[0104] The upper package 21C may include a first upper semiconductor chip 721, a second upper semiconductor chip 722, a first upper bump 751, a second upper bump 752, and an upper molding layer 740. The upper package 21C may further include a heat dissipation structure 790.

[0105] Each of the first upper semiconductor chip 721 and the second upper semiconductor chip 722 may be configured to have the same or similar characteristics as the upper semiconductor chip 720 described with reference to FIG. 5A. For example, the first upper semiconductor chip 721 and the second upper semiconductor chip 722 may be mounted on the second redistribution substrate 600. The first upper bump 751 may be disposed between the second redistribution substrate 600 and the first upper semiconductor chip 721, and may be coupled to the bonding pads 650PG and 650S and the first upper chip pad 731 of the first upper semiconductor chip 721. The first upper semiconductor chip 721 may be electrically connected to the first semiconductor chip 201, the second semiconductor chip 202, and the solder balls 500 through the conduction structure 300. The first upper semiconductor chip 721 may be of the same type as the first semiconductor chip 201 and the second semiconductor chip 202, or may be of a different type from the first semiconductor chip 201 and the second semiconductor chip 202.

[0106] The second upper semiconductor chip 722 may be laterally spaced apart from the first upper semiconductor chip 721. The second upper bump 752 may be disposed between the second redistribution substrate 600 and the second upper semiconductor chip 722, and may be coupled to the bonding pads 650PG and 650S and the second upper chip pad 732 of the second upper semiconductor chip 722. The first upper bump 751 and the second upper bump 752 may be configured to have the same or similar characteristics as the upper bump 750 described with reference to FIG. 5A. The second upper semiconductor chip 722 may be electrically connected to the first semiconductor chip 201, the second semiconductor chip 202, and the solder balls 500 through the conduction structure 300. The second upper semiconductor chip 722 may be of the same type as the first upper semiconductor chip 721, or may be of a different type from the first upper semiconductor chip 721.

[0107] The foregoing exemplary embodiments can be combined with each other. For example, at least two packages selected from semiconductor package 10 shown in FIGS. 1A to 1F, semiconductor package 10A shown in FIGS. 3A and 3B, semiconductor package 10B selected from FIGS. 4A and 4B, semiconductor package 1 shown in FIGS. 5A and 5B, semiconductor package 1A shown in FIGS. 6A and 6B, semiconductor package 1B shown in FIGS. 7A and 7B, and semiconductor package 1C shown in FIGS. 8A and 8B can be combined. As an example, semiconductor package 1B shown in FIGS. 7A and 7B can be configured to include upper package 20 included in semiconductor package 1 described with reference to FIGS. 5A and 5B.

[0108] FIGS. 9A to 9L are cross-sectional views showing a method of manufacturing a semiconductor package according to an exemplary embodiment.

[0109] Referring to FIG. 9A, a first insulating layer 101, an under-bump seed layer 175Z, a first resist pattern 981, and under-bump patterns 170PG and 170S can be formed on a carrier substrate 910. The formation of the first insulating layer 101 can include coating a photosensitive polymer. The first insulating layer 101 can be patterned to form a first opening 1011Z in the first insulating layer 101. The first opening 1011Z can be formed to expose the top surface of the carrier substrate 910 and the inner surface of the first insulating layer 101. The first insulating layer 101 can be a first sub-insulating layer 1011.

[0110] The under-bump seed layer 175Z can be formed on the exposed top surface of the carrier substrate 910 and the first sub-insulating layer 1011. For example, the under-bump seed layer 175Z can be conformally formed on the inner surface and the top surface of the first sub-insulating layer 1011. The under-bump seed layer 175Z can be formed by a deposition process.

[0111] The first resist pattern 981 can be formed on the top surfaces of the first insulating layer 101 and the under-bump seed layer 175Z. A first guiding opening 981Z can be formed in the first resist pattern 981 to expose the under-bump seed layer 175Z. The first guiding opening 981Z can overlap the first opening 1011Z in the vertical direction. The width of each of the first guiding openings 981Z can be greater than the width of the corresponding one of the first openings 1011Z.

[0112] The under-bump patterns 170PG and 170S can be formed in the first opening 1011Z and the first guiding opening 981Z respectively, and on the under-bump seed layer 175Z. The under-bump patterns 170PG and 170S can be formed by performing an electroplating process using the under-bump seed layer 175Z as an electrode. The electroplating process for forming the under-bump patterns 170PG and 170S can be completed before the under-bump patterns 170PG and 170S reach the top surface of the first resist pattern 981. Therefore, the top surfaces of the under-bump patterns 170PG and 170S can be lower than the top surface of the first resist pattern 981, and during the process of forming the under-bump patterns 170PG and 170S, a separate planarization process need not be performed.

[0113] The lower portions of the under-bump patterns 170PG and 170S can be disposed in the first opening 1011Z, and the upper portions of the under-bump patterns 170PG and 170S can be disposed in the first guiding opening 981Z. Since the width of the first guiding opening 981Z is greater than the width of the first opening 1011Z, the upper portions of the under-bump pattern 170PG or 170S can have a width greater than the width of its lower portion.

[0114] In a case where the under-bump seed pattern 175 is formed on a single flat surface and has a flat top surface, it may be difficult to form the under-bump patterns 170PG and 170S to a large thickness. According to an exemplary embodiment, the under-bump seed layer 175Z can be conformally formed on the bottom surface of the first opening 1011Z and the side and top surfaces of the first sub-insulating layer 1011. Since the under-bump patterns 170PG and 170S are formed using the under-bump seed layer 175Z as an electrode, the under-bump patterns 170PG and 170S can be easily formed to a relatively large thickness T1.

[0115] The under-bump patterns 170PG and 170S can include a signal under-bump pattern 170S and a ground / power under-bump pattern 170PG. Since the under-bump patterns 170PG and 170S are formed using the first resist pattern 981, the under-bump pattern 170PG and the under-bump pattern 170S can be laterally spaced apart from each other without an additional patterning process. Therefore, the process of forming the under-bump patterns 170PG and 170S can be simplified.

[0116] Referring to FIG. 9B, the first resist pattern 981 can be removed to expose a first portion of the under-bump seed layer 175Z. In an exemplary embodiment, the first resist pattern 981 can be removed by a strip process.

[0117] The first sub-insulating layer 1011 can be exposed by removing an exposed first portion of the under-bump seed layer 175Z through an etching process. A second portion of the under-bump seed layer 175Z can be respectively disposed below the bottom surfaces 170b of the under-bump patterns 170PG and 170S, and may not be exposed to the etching process. Thus, the second portion of the under-bump seed layer 175Z may not be removed due to the etching process, but may be left. After the etching process, a second left portion of the under-bump seed layer 175Z can form the under-bump seed pattern 175. The under-bump seed patterns 175 can be spaced apart from each other and can be electrically separated from each other.

[0118] Referring to FIG. 9C, a second sub-insulating layer 1012 can be formed on the first sub-insulating layer 1011 and the under-bump patterns 170PG and 170S to, for example, cover the under-bump patterns 170PG and 170S.

[0119] The second sub-insulating layer 1012 can be patterned to form a second opening 1012Z in the second sub-insulating layer 1012. The patterning of the second sub-insulating layer 1012 can be performed by an exposure process and a development process. The second opening 1012Z can be formed to expose the top surfaces of the under-bump patterns 170PG and 170S, respectively.

[0120] A first seed layer 135Z, a second resist pattern 982, a first ground / power conduction pattern 131PG, and a first signal conduction pattern 131S can be formed on the second sub-insulating layer 1012. In an exemplary embodiment, the first seed layer 135Z can be conformally formed on the second sub-insulating layer 1012 and in the second opening 1012Z.

[0121] The second resist pattern 982 can be formed on the first seed layer 135Z. The second resist pattern 982 can be patterned to form a second guiding opening 982Z. The second guiding opening 982Z can be respectively connected to the second opening 1012Z. The width of the second guiding opening 982Z can be greater than the width of the corresponding second opening 1012Z. Each of the second guiding openings 982Z can be formed to expose the first seed layer 135Z.

[0122] The first ground / power conduction pattern 131PG and the first signal conduction pattern 131S can be formed in the second opening 1012Z to be disposed on the first seed layer 135Z. For example, each of the first ground / power conduction pattern 131PG and the first signal conduction pattern 131S can be formed to fill a corresponding one of the second opening 1012Z. Each of the first ground / power conduction pattern 131PG and the first signal conduction pattern 131S can be formed in a lower portion of the corresponding second guiding opening 982Z and may not extend to the area on the top surface of the second resist pattern 982. The first ground / power conduction pattern 131PG and the first signal conduction pattern 131S can be formed by performing an electroplating process using the first seed layer 135Z as an electrode. In an exemplary embodiment, during the process of forming the first ground / power conduction pattern 131PG and the first signal conduction pattern 131S, a separate planarization process may not be performed.

[0123] The first ground / power conduction pattern 131PG and the first signal conduction pattern 131S can be laterally spaced apart from each other. Since the first ground / power conduction pattern 131PG and the first signal conduction pattern 131S are formed using the second resist pattern 982, a separate etching process for separating the first ground / power conduction pattern 131PG and the first signal conduction pattern 131S may not be necessary. Therefore, the process of forming the first ground / power conduction pattern 131PG and the first signal conduction pattern 131S can be simplified.

[0124] Referring to FIGS. 9C and 9D, the second resist pattern 982 can be removed to expose the top surface of the first portion of the first seed layer 135Z. Thereafter, the first seed pattern 135 can be formed by removing the exposed first portion of the first seed layer 135Z through an etching process. The etching process can be a wet etching process. In the etching process, the first ground / power conduction pattern 131PG and the first signal conduction pattern 131S can have etching selectivity with respect to the first seed layer 135Z. The second portion of the first seed layer 135Z can be disposed below the bottom surface of the first ground / power conduction pattern 131PG or the first signal conduction pattern 131S and can be exposed to the etching process. After the etching process, the second portion on the left side of the first seed layer 135Z can form a plurality of first seed patterns 135. The first seed patterns 135 can be spaced apart from each other.

[0125] Referring to FIG. 9E, multiple stacked first insulating layers 101 can be formed by repeatedly performing the process of forming the first insulating layer 101. A second ground / power conduction pattern 132PG, a second signal conduction pattern 132S, a third ground / power conduction pattern 133PG, a third signal conduction pattern 133S, a ground / power redistribution line pad 150PG, and a signal redistribution line pad 150S can be formed on the first ground / power conduction pattern 131PG and the first signal conduction pattern 131S. For example, a first seed pattern 135 can be formed under the bottom surfaces of the second ground / power conduction pattern 132PG, the second signal conduction pattern 132S, the third ground / power conduction pattern 133PG, and the third signal conduction pattern 133S. In an exemplary embodiment, the second ground / power conduction pattern 132PG and the second signal conduction pattern 132S can be formed by the same method as the method for forming the first ground / power conduction pattern 131PG and the first signal conduction pattern 131S described with reference to FIGS. 9C and 9D. In an exemplary embodiment, the third ground / power conduction pattern 133PG and the third signal conduction pattern 133S can be formed by the same method as the methods for the first ground / power conduction pattern 131PG and the first signal conduction pattern 131S respectively described with reference to FIGS. 9C and 9D. Therefore, a ground / power conduction pattern 130PG including the first ground / power conduction pattern to the third ground / power conduction patterns 131PG, 132PG, and 133PG can be formed, and a signal conduction pattern 130S including the first signal conduction pattern to the third signal conduction patterns 131S, 132S, and 133S can be formed.

[0126] A third opening 1013Z can be formed in the uppermost one of the first insulating layers 101. Seed pads 155 can be respectively formed in the third opening 1013Z. The seed pads 155 can extend to an area on the top surface of the uppermost one of the first insulating layers 101. The first redistribution line pads 150PG and 150S can be formed by performing an electroplating process using the seed pads 155 as electrodes. Therefore, a first redistribution line substrate 100 can be manufactured. The first redistribution line substrate 100 can include the first insulating layer 101, the under-bump patterns 170PG and 170S, the first seed pattern 135, the ground / power conduction pattern 130PG, the signal conduction pattern 130S, the seed pads 155, and the redistribution line pads 150PG and 150S.

[0127] Referring to FIG. 9F, a conduction structure 300 can be formed on the redistribution line pads 150PG and 150S. In an exemplary embodiment, the conduction structure 300 can be formed by an electroplating process. The conduction structure 300 can include a ground / power structure 300PG and a signal structure 300S.

[0128] Referring to FIG. 9G, the semiconductor chip 200 can be mounted on the top surface of the first wiring substrate 100. The mounting of the semiconductor chip 200 can include forming bumps 250 between the first wiring substrate 100 and the semiconductor chip 200.

[0129] The molding layer 400 can be formed on the top surface of the first wiring substrate 100 to be disposed on the semiconductor chip 200 and the conduction structure 300. The top surface of the molding layer 400 can be disposed at a level higher than the top surface of the conduction structure 300.

[0130] Referring to FIG. 9H, a grinding process can be performed on the molding layer 400. For example, the grinding process can include a chemical mechanical polishing process. As a result of the grinding process, the top surface of the conduction structure 300 can be exposed. The top surface of the molding layer 400 on which the grinding process is performed can be coplanar with the top surface of the conduction structure 300.

[0131] Referring to FIG. 9I, a second insulating layer 601, a second seed pattern 615, a lower signal redistribution line pattern 610S, and a lower ground / power redistribution line pattern 610PG can be formed on the molding layer 400. For example, the second insulating layer 601 can be directly formed on the top surface of the molding layer 400. An upper opening 609 can be formed in the second insulating layer 601 to expose the top surface of the conduction structure 300, respectively. The second seed pattern 615 can be conformally formed in the upper opening 609 and on the top surface of the second insulating layer 601. The lower redistribution line patterns 610PG and 610S can be formed on the second seed pattern 615 in the upper opening 609 and on the top surface of the second insulating layer 601. In an exemplary embodiment, the lower redistribution line patterns 610PG and 610S can be formed by an electroplating process using the second seed pattern 615 as a seed electrode.

[0132] Referring to FIG. 9J, multiple stacked second insulating layers 601 can be formed by repeatedly performing the process of forming the second insulating layer 601. A second seed pattern 615, upper redistribution line patterns 620PG and 620S, upper seed pads 655, and bonding pads 650PG and 650S can be formed on the lower ground / power redistribution line pattern 610PG. In an exemplary embodiment, the upper redistribution line patterns 620PG and 620S can be formed by an electroplating process using the third seed pattern 625 as a seed electrode. In an exemplary embodiment, the upper seed pads 655 and the bonding pads 650PG and 650S can be formed by a method the same as or similar to the method for the seed pad 155 and the redistribution line pads 150PG and 150S shown in FIG. 9E. Thus, the second redistribution line substrate 600 can be manufactured. The second redistribution line substrate 600 can include the second insulating layer 601, the second seed pattern 615, the lower redistribution line patterns 610PG and 610S, the third seed pattern 625, the upper redistribution line patterns 620PG and 620S, the upper seed pads 655, and the bonding pads 650PG and 650S.

[0133] Referring to FIG. 9K, the carrier substrate 910 can be removed to expose the bottom surface of the first redistribution line substrate 100. For example, the bottom surface 101b of the lowermost one of the first insulating layers 101 and the bottom surface 175b' of the under-bump seed pattern 175 can be exposed.

[0134] Referring to FIG. 9L, a first portion of the exposed under-bump seed pattern 175 can be removed to expose the bottom surface 170b of the under-bump patterns 170PG and 170S. In an exemplary embodiment, the under-bump seed pattern 175 can be removed by an etching process. The first portion of the under-bump seed pattern 175 can be the portion located on the bottom surface 170b of the under-bump patterns 170PG and 170S. In the etching process, the under-bump patterns 170PG and 170S and the lowermost one of the first insulating layers 101 can have an etching selectivity relative to the under-bump seed pattern 175.

[0135] Since the under-bump seed pattern 175 is removed, the bottom surface 170b of the under-bump patterns 170PG and 170S can be disposed at a level higher than the bottom surface 101b of the lowermost one of the first insulating layers 101. The level difference between the bottom surface 170b of the under-bump patterns 170PG and 170S and the bottom surface 101b of the lowermost one of the first insulating layers 101 can be substantially equal to the first thickness T of each of the under-bump seed patterns 175 (e.g., FIG. 1C).

[0136] After the etching process, each of the underbump seed patterns 175 may have an undercut structure. The undercut structure of each of the underbump seed patterns 175 may be formed between the side surface of the corresponding underbump pattern 170PG or 170S and the first insulating layer 101. Thus, as shown in FIG. 1C, the bottommost surface 175b of the underbump seed pattern 175 may be located at a level higher than the bottommost surface 170b of the corresponding underbump pattern 170PG or 170S.

[0137] As another example, the process conditions in the etching process may be controlled such that the bottommost surface 175b of the underbump seed pattern 175 is located at a level substantially the same as the bottom surface 170b of the underbump pattern 170PG or 170S.

[0138] Referring back to FIG. 1D, solder balls 500 may be formed on the bottom surfaces 170b of the underbump patterns 170PG and 170S, respectively, and the solder balls 500 may be coupled to the underbump patterns 170PG and 170S. The semiconductor package 10 may be manufactured by the foregoing process.

[0139] A method of manufacturing a single semiconductor package 10 has been shown and described. However, the method of manufacturing the semiconductor package 10 is not limited to such a chip-level manufacturing method, and other manufacturing methods may be used to manufacture a semiconductor package consistent with the exemplary embodiments. For example, the semiconductor package 1 may be manufactured at the chip level, panel level, or wafer level.

[0140] FIGS. 10A to 10C are cross-sectional views showing a method of manufacturing a semiconductor package according to an exemplary embodiment. For the sake of brevity of description, the elements described previously may be identified by the same reference numerals, and overlapping descriptions thereof will not be repeated.

[0141] Referring to FIG. 10A, a first redistribution substrate 100, a semiconductor wafer 200, a conductive structure 300, a molding layer 400, and a second redistribution substrate 600 may be formed on a carrier substrate 910. The first redistribution substrate 100, the semiconductor wafer 200, the conductive structure 300, the molding layer 400, and the second redistribution substrate 600 may be formed by a method substantially the same as the method in the exemplary embodiments shown in FIGS. 9A to 9J.

[0142] Thereafter, an upper semiconductor chip 720 can be installed on the second wiring substrate 600. The installation of the upper semiconductor chip 720 can include forming upper bumps 750. A molding layer 400 can be formed on the second wiring substrate 600 to be disposed on the upper semiconductor chip 720. A heat dissipation structure 790 can be further formed on the upper molding layer 740.

[0143] Referring to FIG. 10B, the carrier substrate 910 can be removed to expose the bottom surface 101b of the lowermost one of the first insulating layers 101 and the bottom surface 175b' of the under-bump seed pattern 175.

[0144] Referring to FIG. 10C, a first portion of the exposed under-bump seed pattern 175 can be removed to expose the bottom surfaces 170b of the under-bump patterns 170PG and 170S. In an exemplary embodiment, the removal of the under-bump seed pattern 175 can be performed by a method substantially the same as the method described with reference to FIG. 9L. The lowermost surface 175b of the under-bump seed pattern 175 can be disposed at a level higher than the bottom surfaces 170b of the under-bump patterns 170PG and 170S.

[0145] Referring back to FIG. 5A, solder balls 500 can be bonded to the exposed bottom surfaces 170b of the under-bump patterns 170PG and 170S. Thus, the manufacturing of the semiconductor package 1 can be completed.

[0146] In a case where the manufacturing of the semiconductor package 1 is performed at a wafer level or a panel level, before the bonding process of the solder balls 500, a sawing process can be further performed. The wafer-level semiconductor package can be divided into wafer-level semiconductor packages 1 by the sawing process.

[0147] According to an exemplary embodiment, the conduction structure can include a signal structure, a first ground structure, and a second ground structure. The signal structure can be sandwiched between the first ground structure and the second ground structure and can be adjacent to the first ground structure and the second ground structure. Thus, the coupling noise of the signal structure can be prevented or reduced, and a semiconductor package with improved reliability and electrical characteristics can be achieved.

[0148] Although the exemplary embodiments have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and details can be made thereto without departing from the spirit and scope of the patent application.

[0149] 1, 1A, 1B, 1C, 10, 10A, 10B: Semiconductor package 10’, 11, 12: Lower package 20, 20A, 21B, 21C: Upper package 100: First wiring substrate 101: First insulating layer 101b, 170b, 175b, 175b’: Bottom surface 130PG: Conduction pattern / Ground / Power conduction pattern 130S: Conduction pattern / Signal conduction pattern 131PG: First ground / power conduction pattern 131S: First signal conduction pattern 132PG: Second ground / power conduction pattern 132S: Second signal conduction pattern 133PG: Third ground / power conduction pattern 133S: Third signal conduction pattern 135: First seed pattern 135Z: First seed layer 150PG: First wiring pad / Rewiring pad / Ground / power rewiring pad 150S: First wiring pad / Rewiring pad / Signal rewiring pad 155: Seed pad 170PG: Under bump pattern / Ground / power under bump pattern 170S: Under bump pattern / Signal under bump pattern 171: First under bump pattern 172: Second under bump pattern 173: Third under bump pattern 175: Under bump seed pattern 175Z: Under bump seed layer 179: First via 200: Semiconductor chip 201: First semiconductor chip 202: Second semiconductor chip 230, 231, 232: Chip pad 250: Bump 251: First bump 252: Second bump 300: Conduction structure 300PG: Ground / power structure 300S: Signal Structure 310: First Ground / Power Structure 320: Second Ground / Power Structure 330: Third Conduction Structure 340: Fourth Ground / Power Structure 350: Fifth Ground / Power Structure 400: Molding Layer 500: Solder Balls 500PG: Ground / Power Solder Balls 500S: Signal Solder Balls 600: Second Redistribution Substrate 601: Second Insulating Layer 609: Upper Opening 610PG: Lower Redistribution Pattern / Lower Ground / Power Redistribution Pattern 610S: Lower Redistribution Pattern / Lower Signal Redistribution Pattern 611: First Ground / Power Redistribution Pattern 612: Second Ground / Power Redistribution Pattern 613: Third Redistribution Pattern 615: Second Seed Pattern 619: Second Hole 620PG: Upper Redistribution Pattern / Upper Ground / Power Redistribution Pattern 620S: Upper Redistribution Pattern / Upper Signal Redistribution Pattern 625: Third Seed Pattern 650PG: Bonding Pad / Ground / Power Bonding Pad 650S: Bonding Pad / Signal Bonding Pad 655: Upper Seed Pad 675: Connection Bump 710: Upper Substrate 720: Upper Semiconductor Wafer 721: First Upper Semiconductor Wafer 722: Second Upper Semiconductor Wafer 730: Upper Wafer Pad 731: First Upper Wafer Pad 732: Second Upper Wafer Pad 740: Upper Molding Layer 750, 750’: Upper Bumps 751: First Upper Bump 752: Second upper bump 790: Heat dissipation structure 910: Carrier substrate 981: First resist pattern 981Z: First guiding opening 982: Second resist pattern 982Z: Second guiding opening 1011: First sub-insulating layer 1011Z: First opening 1012: Second sub-insulating layer 1012Z: Second opening 1013Z: Third opening 1301PG: First ground / power sharing pattern 1302PG: Second ground / power sharing pattern A-B, A’-B’, A’’-B’’, C-D, C’-D’, C’’-D’’: Lines D1: First direction D2: Second direction D3: Third direction E: Portion L1, L2, L3: Lengths R1: First region R2: Second region T: First thickness T1, T2, T3: Thicknesses W1, W1’, W2, W2’, W3, W3’: Widths

Claims

1. A semiconductor package, comprising: A first substrate includes a first under-bump pattern, a second under-bump pattern, and a third under-bump pattern; a semiconductor wafer is disposed on the first substrate; A conductive structure is disposed on the first substrate, spaced laterally from the semiconductor wafer, and spaced laterally from each other; A second substrate is disposed on the semiconductor wafer and the conductive structure, wherein the third under-bump pattern is electrically isolated from the first under-bump pattern and the second under-bump pattern, wherein the conductive structure includes: a first conductive structure coupled to the first under-bump pattern; a second conductive structure coupled to the second under-bump pattern; and a third conductive structure coupled to the third under-bump pattern and disposed adjacent to the first conductive structure and the second conductive structure, wherein the first conductive structure is a ground structure or a power supply structure, wherein the second conductive structure is a ground structure or a power supply structure, wherein the third conductive structure is a signal structure, wherein the third conductive structure is disposed between the first conductive structure and the second conductive structure, wherein the first conductive structure is disposed between the third conductive structure and the semiconductor wafer, wherein the first under-bump pattern is wider than the third under-bump pattern, wherein the second under-bump pattern is wider than the third under-bump pattern, wherein the second substrate includes a first rewiring pattern electrically connected to the first conductive structure, and wherein the first rewiring pattern overlaps with the semiconductor wafer in the vertical direction.

2. The semiconductor package of claim 1, wherein the area of ​​the top surface of the first under-bump pattern is greater than the area of ​​the top surface of the third under-bump pattern, and wherein the area of ​​the top surface of the second under-bump pattern is greater than the area of ​​the top surface of the third under-bump pattern.

3. The semiconductor package of claim 1, wherein both the top surface of the first underbump pattern and the top surface of the second underbump pattern are wider than the top surface of the third underbump pattern.

4. The semiconductor package as claimed in claim 1, wherein the first under-bump pattern defines a hole penetrating through the first under-bump pattern.

5. The semiconductor package of claim 1, wherein the first under-bump pattern and the second under-bump pattern are configured to provide a ground or power supply voltage, and wherein the third under-bump pattern is configured to provide a signal.

6. The semiconductor package of claim 1, wherein the second substrate comprises: The second wiring pattern is electrically connected to the second conductive structure; And a third wiring pattern, electrically connected to the third conductive structure, wherein the area of ​​the top surface of the first wiring pattern and the area of ​​the top surface of the second wiring pattern are both greater than the area of ​​the top surface of the third wiring pattern.

7. The semiconductor package as claimed in claim 6, wherein the conductive structure further comprises: The fourth conductive structure is electrically connected to the first wiring pattern; And a fifth conductive structure, electrically connected to the second wiring pattern.

8. The semiconductor package of claim 1, wherein the conductive structure further includes a fourth conductive structure, wherein the first substrate further includes a first shared conductive pattern, and wherein the first shared conductive pattern is electrically connected to the first conductive structure and the fourth conductive structure.

9. The semiconductor package of claim 8, wherein the conductive structure further includes a fifth conductive structure, wherein the first substrate includes a second shared conductive pattern, and wherein the second shared conductive pattern is electrically connected to the second conductive structure and the fifth conductive structure.

10. The semiconductor package of claim 1, wherein the first substrate further includes an under-bump seed pattern disposed on a side surface of the first under-bump pattern to the third under-bump pattern, and wherein at least a portion of the bottom surface of each of the first under-bump pattern, the second under-bump pattern and the third under-bump pattern is exposed by the under-bump seed pattern.

11. The semiconductor package as claimed in claim 1, wherein the first conductive structure, the second conductive structure and the third conductive structure are arranged sequentially in the conductive structure without any other conductive structure sandwiched therebetween.

12. A semiconductor package, comprising: First base; A semiconductor wafer is disposed on the first substrate; A conductive structure is disposed on the first substrate and spaced laterally from the semiconductor wafer; A second substrate is disposed on the semiconductor wafer and the conductive structure, wherein the conductive structure includes a first conductive structure, a second conductive structure, and a third conductive structure that are adjacent to each other, wherein the third conductive structure is disposed between the first conductive structure and the second conductive structure and is electrically isolated from the first conductive structure and the second conductive structure, wherein the first conductive structure is disposed between the third conductive structure and the semiconductor wafer, wherein the second substrate includes: a first redistribution pattern electrically connected to the first conductive structure and overlapping the semiconductor wafer in the vertical direction; A second wiring pattern electrically connected to the second conductive structure; and a third wiring pattern electrically connected to the third conductive structure, wherein the area of ​​the top surface of the first wiring pattern is greater than the area of ​​the top surface of the third wiring pattern, wherein the area of ​​the top surface of the second wiring pattern is greater than the area of ​​the top surface of the third wiring pattern, wherein the first conductive structure and the second conductive structure are configured to provide a ground or power supply voltage, and wherein at least one of the first conductive structure and the second conductive structure is configured to provide the power supply voltage.

13. The semiconductor package of claim 12, wherein the first overlay pattern defines a hole through the first overlay pattern.

14. The semiconductor package of claim 12, wherein the conductive structure further includes a fourth conductive structure and a fifth conductive structure, the fourth conductive structure being electrically connected to the first superwiring pattern and the fifth conductive structure being electrically connected to the second superwiring pattern.

15. The semiconductor package as claimed in claim 12, wherein the third conductive structure is configured to provide a signal.

16. The semiconductor package as described in claim 12, further comprising: The upper semiconductor wafer is disposed on the second substrate; And an upper molding layer, which is directly disposed on the second substrate to cover the upper semiconductor wafer.

17. A semiconductor package, comprising: A first substrate includes a first insulating layer, an under-bump pattern, an under-bump seed pattern, a first ground / power conduction pattern, a second ground / power conduction pattern, and a signal conduction pattern; a semiconductor wafer is disposed on the top surface of the first substrate; a conductive structure is disposed on the top surface of the first substrate and is spaced apart from and from the semiconductor wafer in the lateral direction; a molding layer is disposed on the top surface of the first substrate, the side surface of the semiconductor wafer, and the side surface of the conductive structure. A second substrate is disposed on the molding layer and the conductive structure and electrically connected to the conductive structure, wherein the conductive structure includes: a first conductive structure coupled to the first ground / power conductive pattern; a second conductive structure coupled to the second ground / power conductive pattern; a third conductive structure coupled to the signal conductive pattern; and a fourth conductive structure coupled to the first ground / power conductive pattern, wherein the first conductive structure is a ground structure or a power structure, wherein the second conductive structure is a ground structure or a power structure, wherein the third conductive structure is a signal structure, wherein the third conductive structure is disposed between the first conductive structure and the second conductive structure, wherein the first conductive structure is disposed between the third conductive structure and the semiconductor wafer, wherein the second substrate includes a first redistribution pattern electrically connected to the first conductive structure, wherein the first redistribution pattern overlaps with the semiconductor wafer in the vertical direction, and wherein the under-bump seed pattern is disposed on the side surface of the under-bump pattern and spaced apart from the bottom surface of the under-bump pattern.

18. The semiconductor package of claim 17, wherein the under-bump pattern comprises: The pattern below the first bump is electrically connected to the first grounding / power conduction pattern; The pattern below the second bump is electrically connected to the second grounding / power conduction pattern; And a third bump pattern, electrically connected to the signal conduction pattern, wherein the top surface of the first bump pattern and the top surface of the second bump pattern are wider than the top surface of the third bump pattern.

19. The semiconductor package of claim 17, wherein the second substrate further comprises: The second wiring pattern is electrically connected to the second conductive structure; And a third wiring pattern electrically connected to the third conductive structure, wherein the area of ​​the top surface of the first wiring pattern is greater than the area of ​​the top surface of the third wiring pattern, and wherein the area of ​​the top surface of the second wiring pattern is greater than the area of ​​the top surface of the third wiring pattern.

20. The semiconductor package of claim 17, wherein the thickness of each of the under-bump patterns ranges from 5 micrometers to 20 micrometers.

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