Semiconductor devices and methods for forming the same

Abstract

A semiconductor device includes: a plurality of semiconductor layers vertically separated from each other. The semiconductor device includes: a gate structure including a lower portion and an upper portion. The lower portion surrounds each semiconductor layer. The semiconductor device includes: a gate spacer extending along a sidewall of the upper portion of the gate structure, and including a first layer and a second layer. The first layer contacts a first portion of the sidewall, and the second layer contacts a second portion of the sidewall.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a non-planar transistor device and a method for manufacturing the same. [Previous Technology]

[0002] This disclosure generally relates to semiconductor devices, and more specifically to methods for manufacturing non-planar transistor devices.

[0003] The semiconductor industry has experienced rapid growth due to continuous improvements in the integrated density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In most cases, improvements in integrated density come from repeated reductions in the size of the smallest component, which allows more components to be integrated into a given area. [Summary of the Invention]

[0004] Some embodiments of the present invention provide a semiconductor device, including: a plurality of semiconductor layers vertically separated from each other; a gate structure including a lower portion and an upper portion, wherein the lower portion wraps around each semiconductor layer; and a gate spacer extending along a sidewall of the upper portion of the gate structure and including a first layer and a second layer; wherein the first layer contacts a first portion of the sidewall and the second layer contacts a second portion of the sidewall.

[0005] Other embodiments of the present invention provide a semiconductor device, including: a fin structure disposed above a substrate; a gate structure including a lower portion and an upper portion, wherein the lower portion straddles the fin structure; and a gate spacer extending along a sidewall of the upper portion of the gate structure and including a first layer and a second layer; wherein the first layer has a vertical portion that contacts and extends along the sidewall; and wherein the second layer includes: a vertical portion that extends along the sidewall and is separated from the sidewall by the first layer; and a horizontal portion that contacts the sidewall.

[0006] Some embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: forming a fin structure extending along a first lateral direction; forming a dummy gate structure above a portion of the fin structure, wherein the dummy gate structure extends along a second direction perpendicular to the first lateral direction; growing a source / drain structure, respectively coupled to an end of a portion of the fin structure; removing the dummy gate structure to form a gate trench; lining the inner sidewall of the gate trench with a gate spacer; and forming an active gate structure in the gate trench.

Implementation Method

[0008] The following provides many different embodiments or examples to implement different components of the embodiments disclosed herein. Specific examples of components and configurations are described below to simplify the embodiments disclosed herein. Of course, these are merely examples and not intended to limit the embodiments disclosed herein. For example, the size of an element is not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the apparatus. Furthermore, the following description of forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component is formed between the first and second components, such that the first and second components do not need to be in direct contact. Additionally, the embodiments of the present invention may repeat element symbols and / or letters in many examples. These repetitions are for simplification and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0009] Spatially relative terms, such as "below," "below," "lower," "above," "higher," etc., may be used here to facilitate the description of the relationship between one or more components or features in the diagram and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0010] Some embodiments disclosed herein are discussed in the case of forming a fully wound gate (GAA) field-effect transistor (FET) device, and more specifically in the case of forming an alternative gate for a fully wound gate field-effect transistor device. In some embodiments, a dummy gate structure is formed on a fin, the fin including a plurality of first semiconductor layers and a plurality of second semiconductor layers, serving as a sacrificial layer and a channel layer, respectively. The dummy gate structure may be formed of a material unfavorable to epitaxial growth. Subsequently, source / drain structures are formed on opposite sides of the dummy gate structure and covered with an interlayer dielectric (ILD). While forming the interlayer dielectric, the dummy gate structure is removed to form a gate trench. Then, a gate spacer is formed over the gate trench, and subsequently, a portion of the gate spacer is penetrated to expose the topmost first or second semiconductor layer. Subsequently, the sacrificial layer is removed to extend the gate trench. Then, an active gate structure is formed in the gate trench to wrap around each channel layer.

[0011] The active gate structure formed by the above method can provide various benefits in advanced technology nodes. Generally, the dummy gate structure is replaced by the active gate structure, so the critical size of the active gate structure can inherit the size of the formed dummy gate structure. The disclosed dummy gate structure does not include a gate spacer before the formation of the interlayer dielectric, and it can be formed wider by incorporating the real state (e.g., thickness) of the gate spacer. Therefore, it can significantly reduce the chance of the dummy gate structure collapsing in subsequent process steps. In addition, since the disclosed dummy gate structure includes one or more materials that are unfavorable to epitaxial growth, undesirable epitaxial growth around the dummy gate structure (e.g., when forming the source / drain structure) can be avoided. Furthermore, since the gate spacer is formed after the source / drain structure is grown, more choices are available for the material of the gate spacer. This is because concerns about undesirable epitaxial growth around the gate spacer can be eliminated.

[0012] According to various embodiments of the present disclosure, Figure 1 illustrates a view of an exemplary fully wound gate field-effect transistor device 100. The fully wound gate field-effect transistor device 100 includes a substrate 102 and a plurality of nanostructures 104 (e.g., nanosheets, nanowires, etc.) above the substrate 102. Semiconductor layers 104 are perpendicularly separated from each other. Isolation regions 106 are formed on both sides of protrusions on the substrate 102, and the nanostructures 104 are disposed above the protrusions. Gate structures 108 surround each nanostructure 104 (e.g., the entire periphery of each nanostructure 104). Source / drain structures are disposed on both sides of the gate structure 108, such as the source / drain structure 110 shown in Figure 1. Interlayer dielectric (ILD) 112 is disposed above the source / drain structure 110.

[0013] Figure 1 illustrates a simplified fully wound gate field-effect transistor device. Therefore, it should be understood that one or more components of a complete fully wound gate field-effect transistor device may not be shown in Figure 1. For example, another source / drain structure opposite to the source / drain structure 110 and the gate structure 108, and the interlayer dielectric disposed above this source / drain structure, are not shown in Figure 1. Furthermore, Figure 1 is provided for reference to illustrate several cross-sections in subsequent figures. As indicated, section AA extends along the longitudinal axis of the gate structure 108 (e.g., in the X direction). Section BB, perpendicular to section AA, extends along the longitudinal axis of the semiconductor layer 104 and along the current flow direction between the source / drain structures (e.g., in the Y direction). For clarity, subsequent figures refer to the aforementioned reference cross-sections.

[0014] According to one or more embodiments of the present disclosure, Figure 2 illustrates a flowchart of a method 200 for forming a non-planar transistor device. For example, at least some operations (or steps) of method 200 can be used to form a fin field-effect transistor device, a fully wound gate field-effect transistor device (e.g., fully wound gate field-effect transistor device 100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, a fully wound gate (GAA) transistor device, etc. It should be noted that method 200 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional operations may be provided before, during, and after method 200 of Figure 2, and some other operations may only be briefly described in this disclosure. In some embodiments, the operation of method 200 may be related to cross-sectional views of fully wound gate field-effect transistor devices at various manufacturing stages shown in Figures 3, 4A, 4B, 5, 6, 7, 8A, 8B, 9, 10, 11A, 11B, 11C, 12, 13A, 13B, 13C, 13D, 14, and 15, which will be discussed in more detail below.

[0015] In short, method 200 begins with operation 202 of providing a substrate. Method 200 continues to operation 204 of forming a fin structure, the fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers. Method 200 continues to operation 206 of forming one or more dummy gate structures. Method 200 continues to operation 208 of removing a portion of the fin structure. Method 200 continues to operation 210 of forming an inner spacer. Method 200 continues to operation 212 of forming a source / drain structure. Method 200 continues to operation 214 of removing one or more dummy gate structures. Method 200 continues to operation 216 of forming a gate spacer. Method 200 continues to operation 218 of etching the gate spacer. Method 200 continues to operation 220 of removing the first semiconductor layers. Method 200 continues to operation 222 of forming one or more active gate structures.

[0016] As described above, Figures 3 to 15 each show a portion of the fully wound gate field-effect transistor device 300 at various manufacturing stages of the method 200 in Figure 2 in cross-sectional view. The fully wound gate field-effect transistor device 300 is similar to the fully wound gate field-effect transistor device 100 shown in Figure 1, but has multiple gate structures. Although Figures 3 to 15 depict the fully wound gate field-effect transistor device 300, it should be understood that the fully wound gate field-effect transistor device 300 may include many other devices, such as inductors, fuses, capacitors, coils, etc., which are not shown in Figures 3 to 15 for clarity.

[0017] Corresponding to operation 202 in Figure 2, Figure 3 is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of the various manufacturing stages, which includes a semiconductor substrate 302. The cross-sectional view in Figure 3 is taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structure of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0018] The substrate 302 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 302 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 302 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0019] Corresponding to operation 204 in Figure 2, Figure 4A is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of various manufacturing stages, which includes a plurality of first semiconductor layers 410 and a plurality of second semiconductor layers 420 formed on the substrate 302. Continuing to correspond to operation 204 in Figure 2, Figure 4B is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of various manufacturing stages, which includes different numbers of first semiconductor layers 410 and the same number of second semiconductor layers 420 formed on the substrate 302. The cross-sectional views of Figures 4A and 4B are each taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structure of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0020] Referring first to Figure 4A, a first semiconductor layer 410 and a second semiconductor layer 420 are alternately disposed on top of each other (e.g., along the Z direction) to form a first stack. For example, one second semiconductor layer 420 is disposed on top of one first semiconductor layer 410, then another first semiconductor layer 420 is disposed on top of the second semiconductor layer 410, and so on. Figure 4B is similar to the above, with the first semiconductor layer 410 and the second semiconductor layer 420 alternately disposed on top of each other (e.g., along the vertical direction) to form a second stack.

[0021] The first stack and the second stack may each include any number of alternating first semiconductor layers 410 and second semiconductor layers 420. For example, in Figure 4A, the first stack includes four first semiconductor layers 410, three second semiconductor layers 420 alternating between them, and one of the first semiconductor layers 410 is the top semiconductor layer; and, for example, in Figure 4B, the second stack includes three first semiconductor layers 410, two second semiconductor layers 420 alternating between them, and one of the second semiconductor layers 420 is the top semiconductor layer. It should be understood that the fully wound gate field-effect transistor device 300 may include any number of first semiconductor layers and any number of second semiconductor layers, wherein one of the first semiconductor layer or the second semiconductor layer is the top semiconductor layer, all of which are covered within the scope of this disclosure. Therefore, in most of the following discussion, the stack shown in Figure 4A will be used as a representative example.

[0022] Semiconductor layers 410 and 420 may each have different thicknesses. Furthermore, the first semiconductor layer 410 may have different thicknesses from one layer to another. The second semiconductor layer 420 may have different thicknesses from one layer to another. The thickness of each of semiconductor layers 410 and 420 may be from a few nanometers to tens of nanometers. The stacked first layer may be thicker than the other semiconductor layers 410 and 420. In one embodiment, each first semiconductor layer 410 has a thickness of approximately 5 nanometers (nm) to approximately 20 nanometers, and each second semiconductor layer 420 has a thickness of approximately 5 nanometers to approximately 20 nanometers.

[0023] The two semiconductor layers 410 and 420 have different compositions. In various embodiments, the two semiconductor layers 410 and 420 have compositions that provide different oxidation rates and / or different etch selectivity between the layers. In one embodiment, the first semiconductor layer 410 comprises silicon germanium (Si1-xGex), and the second semiconductor layer comprises silicon (Si). In one embodiment, each semiconductor layer 420 is silicon, which may be undoped or substantially doped (i.e., having an external dopant concentration of about 0 cm⁻³ to about 1 × 10¹⁷ cm⁻³), for example, without deliberate doping when the semiconductor layer 420 (e.g., silicon) is formed.

[0024] In various embodiments, the semiconductor layers 420 may be intentionally doped. For example, when the fully wound gate field-effect transistor device 300 is configured as n-type (and operates in enhancement mode), each semiconductor layer 420 may be silicon and doped with p-type dopants, such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the fully wound gate field-effect transistor device 300 is configured as p-type (and operates in enhancement mode), each semiconductor layer 420 may be silicon and doped with n-type dopants, such as phosphorus (P), arsenic (As), and antimony (Sb). In another example, when the fully wound gate field-effect transistor device 300 is configured as n-type (operating in depletion mode), each semiconductor layer 420 may be silicon and alternatively doped with n-type dopants; and when the fully wound gate field-effect transistor device 300 is configured as p-type (operating in depletion mode), each semiconductor layer 420 may be silicon and alternatively doped with p-type dopants. In some embodiments, each semiconductor layer 410 is Si1-xGex, comprising Ge with a molar ratio of less than 50% (x < 0.5). For example, in the molar ratio, Ge may account for approximately 15% to 35% of the Si1-xGex semiconductor layer 410. Furthermore, the first semiconductor layer 410 may include different compositions, and the second semiconductor layer 420 may include different compositions.

[0025] Either semiconductor layer 410 or semiconductor layer 420 may include other materials, such as compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, alloy semiconductors such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP, or combinations thereof. The materials of semiconductor layers 410 and 420 may be selected based on providing different oxidation rates and / or etching selectivity.

[0026] Semiconductor layers 410 and 420 can be epitaxially grown from semiconductor substrate 302. For example, semiconductor layers 410 and 420 can each be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes such as metal-organic CVD (MOCVD), and / or other suitable epitaxial growth processes. During epitaxial growth, the crystalline structure of semiconductor substrate 302 extends upward, so that semiconductor layers 410 and 420 have the same crystalline orientation as semiconductor substrate 302.

[0027] After semiconductor layers 410 and 420 (as a stack) are grown on semiconductor substrate 302, the stack can be patterned to form one or more fin structures (e.g., 401). Each fin structure extends laterally (e.g., in the Y direction) and includes a stack of patterned semiconductor layers 410-420 that are staggered with each other. The fin structure 401 is formed by patterning the semiconductor layers 410-420 and semiconductor substrate 302 using, for example, lithography and etching techniques. For example, a mask layer (which may include multiple layers, e.g., a pad oxide layer and an overlying pad nitride layer) is formed over the topmost semiconductor layer (e.g., 410 in Figure 4A or 420 in Figure 4B). The pad oxide layer may be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer may serve as an adhesive layer between the topmost semiconductor layer 410 (or semiconductor layer 420 in some other embodiments) and the overlying pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. For example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) can be used to form the pad nitride layer.

[0028] The mask layer can be patterned using lithography. Generally, lithography utilizes a photoresist material (not shown), which is deposited, irradiated (exposed), and developed to remove portions of the photoresist. The remaining photoresist protects the underlying material, such as the mask layer in this example, from subsequent process steps, such as etching. For example, the photoresist material is used to pattern pad oxide layers and pad nitride layers to form a patterned mask.

[0029] A patterned mask can then be used to pattern the exposed portions of the semiconductor layers 410-420 and the substrate 302 to form trenches (or openings), thereby defining the fin structure 401 between adjacent trenches. When multiple fin structures are formed, trenches can be disposed between any adjacent fin structures. In some embodiments, the fin structure 401 is formed by etching trenches in the semiconductor layers 410-420 and the substrate 302 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. In some embodiments, the trenches can be strips that are parallel to each other and closely spaced from each other (when viewed from above). In some embodiments, the trenches can be continuous and surround the fin structure 401.

[0030] Corresponding to operation 206 in Figure 2, Figure 5 is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of various manufacturing stages, which includes one or more dummy gate structures 510A and 510B. The cross-sectional view of Figure 5 is taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structures of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0031] Prior to forming the dummy gate structures 510A-B, an etch stop layer (ESL) 502 may be formed over the fin structure 401. Although not shown, a cladding layer (similar to the first semiconductor layer) and a dummy fin structure (covered or protected by a high-dielectric-constant dielectric layer) may be formed on each side (along the X direction) of the fin structure 401 to produce a generally flat top surface shared by the fin structure 401, the cladding layer, and the dummy fin structure. As used in this disclosure, the term "generally flat" refers to a structure whose deviation from a plane is within the range of statistical atomic-level variations inherent in semiconductor fabrication methods known in the art. In some embodiments, the etch stop layer 502 may be formed over such a generally flat top surface. In some other embodiments, the etch stop layer 502 may be formed only over the top surface of the fin structure 401. The etch stop layer 502 may include silicon oxide. The etch stop layer 502 can be formed by a deposition process, such as chemical vapor deposition (CVD) process (e.g., plasma-assisted chemical vapor deposition (PECVD), high aspect ratio process (HARP) or a combination thereof), atomic layer deposition (ALD) process, another applicable process or a combination thereof.

[0032] Subsequently, dummy gate structures 510A-B are formed above the etch stop layer 502. The dummy gate structures 510A-B may each extend in a lateral direction (e.g., the X direction) perpendicular to the lateral direction in which the fin structure 401 extends. In various embodiments, the dummy gate structures 510A-B may be positioned where a corresponding active (e.g., metallic) gate structure is subsequently formed. For example, in Figure 5, the dummy gate structures 510A-B are each positioned above a corresponding portion of the fin structure 401, with the etch stop layer 502 sandwiched between them. This overlaid portion of the fin structure 401 is then formed as a conductive channel, including a portion of the second semiconductor layer 420, and the dummy gate structures 510A-B are each replaced by an active gate structure to surround a portion of their respective second semiconductor layer 420.

[0033] In some embodiments, each of the dummy gate structures 510A-B includes a material that is detrimental to epitaxial growth. Therefore, in the later stages of the epitaxial growth process (e.g., when forming the source / drain structure), epitaxial growth can be significantly restricted around the dummy gate structures 510A-B (e.g., along the sidewalls of the dummy gate structures 510A-B). In some embodiments, each of the dummy gate structures 510A-B may include one or more silicon-based dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, silicon oxynitride, silicon carbide, multilayers thereof, or combinations thereof, and may be deposited. In some embodiments, each of the dummy gate structures 510A-B may include one or more metal-based materials, such as cobalt, tungsten, hafnium oxide, aluminum oxide, or combinations thereof, and may be deposited.

[0034] Corresponding to operation 208 in Figure 2, Figure 6 is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of the various manufacturing stages, wherein the portion of the fin structure 401 not covered by the dummy gate structure 510A-B is removed. The cross-sectional view in Figure 6 is taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structure of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0035] The dummy gate structures 510A-B can be used as masks to etch the uncovered portions of the fin structure 401, so that the fin structure 401 has one or more alternating stacks, including semiconductor layers 410 and 420 and the remaining portions of the etch stop layer 502. Thus, along the Z direction, the newly formed sidewalls of each fin structure 401 are aligned with the sidewalls of the dummy gate structures 510A or 510B. For example, in Figure 6, semiconductor layers 610A, 620A and etch stop layer 630A are the remaining portions of semiconductor layers 410, 420 and etch stop layer 502 respectively covered by the dummy gate structure 510A; and semiconductor layers 610B, 620B and etch stop layer 630B are the remaining portions of semiconductor layers 410, 420 and etch stop layer 502 respectively covered by the dummy gate structure 510B. In some embodiments, semiconductor layers 610A, 620A, 610B and 620B may sometimes be referred to as nanostructures 610A, 620A, 610B and 620B, respectively.

[0036] Corresponding to operation 210 in Figure 2, Figure 7 is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of the various manufacturing stages, including inner spacers 710A and 710B. The cross-sectional view of Figure 7 is taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structure of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0037] Inner spacers 710A are formed along the etched ends of semiconductor layer 610A; inner spacers 710B are formed along the etched ends of semiconductor layer 610B. To form the inner spacers 710A-B, the respective ends of semiconductor layers 610A-B can be removed first. The ends of semiconductor layers 610A-B can be removed (e.g., etched) using a "pull-back" process to pull back semiconductor layers 610A-B by an initial pull-back distance. Although the etched ends of semiconductor layers 610A-B are approximately vertical (e.g., parallel to the sidewalls of the dummy gate structure 510A-B) in the embodiment shown in Figure 7, it should be understood that the etched ends can be bent inward or outward, as will be shown in Figures 8A and 8B. In the example where semiconductor layers 620A-B comprise Si and semiconductor layers 610A-B comprise Si1-xGex, the pull-back process can include an isotropic etching process using hydrogen chloride (HCl) gas, which etches SiGe without etching Si. Therefore, the semiconductor (Si) layer 620A-B can remain intact during the manufacturing process.

[0038] Subsequently, inner spacers 710A-B can be formed along the respective etched ends of semiconductor layers 610A-B. Therefore, the inner spacers 710A-B (e.g., their respective inner sidewalls) can follow the contour of the etched ends of semiconductor layers 610A-B. In some embodiments, the inner spacers 710A-B can be formed conformally by chemical vapor deposition (CVD) or by monolayer doping (MLD) followed by reactive ion etching of the spacers. The inner spacers 710A-B can be deposited using, for example, a conformal deposition process, followed by isotropic or anisotropic etching back to remove excess spacer material on the sidewalls of the stacked fin structure 401 and on the surface of the semiconductor substrate 302. The material of the inner spacers 710A-B can be formed from the same or different material as the dummy gate structure 510A-B. For example, the inner spacers 710A-B can be formed of silicon nitride, boron silicon carbonitride, silicon carbonitride, silicon oxynitride, or any other type of dielectric material (e.g., a dielectric material with a dielectric constant of less than about 5), which is suitable as insulating gate sidewall spacers for transistors.

[0039] Figures 8A and 8B illustrate other embodiments of the outline of the inner spacers 710A-B, with the inner spacer 710A serving as a representative example. As shown in Figure 8A, the inner spacer 710A follows the outline of the etched end of the semiconductor layer 610A, having a curvature-based outline projecting inward toward the semiconductor layer 610A. Therefore, the inner spacer 710A may have convex inner sidewalls. As shown in Figure 8B, the inner spacer 710A follows the outline of the etched end of the semiconductor layer 610A, having a curvature-based outline projecting outward from the semiconductor layer 610A. Therefore, the inner spacer 710A may have concave inner sidewalls.

[0040] Corresponding to operation 212 in Figure 2, Figure 9 is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of various manufacturing stages, which includes source / drain structures 910A, 910B, and 910C covered by interlayer dielectric (ILD) 920. The cross-sectional view of Figure 9 is taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structure of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0041] Source / drain structures 910A-C can be formed on the exposed ends of semiconductor layers 620A-B using an epitaxial growth process. In some embodiments, the bottom surface of the source / drain structure 910A-C may be flush with the top surface of the isolation structure (not shown) at the lower part of the embedded fin structure 401. In some other embodiments, the bottom surface of the source / drain structure 910A-C may be lower than the top surface of the isolation structure. On the other hand, in some embodiments, the top surface of the source / drain structure 910A-C may be higher than the top surface of the topmost semiconductor layer 610A-B, as shown in Figure 9. In some other embodiments, the top surface of the source / drain structure 910A-C may be flush with or lower than the top surface of the topmost semiconductor layer 610A-B. Since the dummy gate structure 510A-B is formed of a material that is not conducive to epitaxial growth, the top surface of the source / drain structure 910A-C may not be higher than the bottom surface of the dummy gate structure 510A-B (or the top surface of the etch stop layer 630A-B).

[0042] The source / drain structures 910A-C are electrically coupled to the corresponding semiconductor layers 620A-B. For example, the source / drain structures 910A-B may be electrically coupled to the semiconductor layer 620A; and the source / drain structures 910B-C may be electrically coupled to the semiconductor layer 620B. In various embodiments, the semiconductor layers 620A may collectively serve as the conductive channel for a first fully wound gate transistor (hereinafter referred to as "fully wound gate transistor 950A"); and the semiconductor layers 620B may collectively serve as the conductive channel for a second fully wound gate transistor (hereinafter referred to as "fully wound gate transistor 950B"). It should be noted that at this stage of manufacturing, the fully wound gate transistors 950A-B are not yet completed.

[0043] In-situ doping (ISD) can be applied to form doped source / drain structures 910A-C, thereby creating junctions for fully wound gate transistors 950A-B. n-type and p-type field-effect transistors are formed by implanting different types of dopants into selected regions of the device (e.g., source / drain structures 910A-C) to form junctions. n-type devices can be formed by implanting arsenic (As) or phosphorus (P), and p-type devices can be formed by implanting boron (B).

[0044] After forming the source / drain structures 910A-C, the interlayer dielectric 920 can be formed by bulk deposition of dielectric material on the partially formed fully wound gate transistors 950A-B and polishing the bulk oxide back (e.g., using CMP) to the level of the dummy gate structures 510A-B. The dielectric material of the interlayer dielectric 920 includes silica, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or combinations thereof.

[0045] Corresponding to operation 214 in Figure 2, Figure 10 is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of the various manufacturing stages, wherein the dummy gate structure 510A-B (Figure 9) is removed. The cross-sectional view in Figure 10 is taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structure of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0046] After forming the interlayer dielectric 920 (Figure 9), the dummy gate structures 510A-B are removed, thereby forming gate trenches 1000A and 1000B, respectively. The dummy gate structures 510A-B can be removed by known etching processes, such as reactive ion etching or chemical oxide removal (COR). After removing the dummy gate structures 510A-B (forming gate trenches 1000A-B), the top surface of the etch stop layer 630A-B is exposed. In some embodiments, although not shown in the cross-sectional view of Figure 10, it should be understood that, in addition to the top surface of the etch stop layer 630A-B, the respective sidewalls (facing the X direction) of the semiconductor layers 610A-B and 620A-B can be exposed.

[0047] Corresponding to operation 216 in Figure 2, Figure 11A is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of various manufacturing stages, including gate spacer 1110. Continuing to correspond to operation 216 in Figure 2, Figure 11B is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of various manufacturing stages, including gate spacer 1120. Continuing to correspond to operation 216 in Figure 2, Figure 11C is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of various manufacturing stages, including gate spacer 1130. The cross-sectional views of Figures 11A-C are each taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structure of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0048] First, referring to Figure 11A, gate spacer 1110 is formed in gate trenches 1000A and 1000B. Gate spacer 1110 may be formed as a single compliant layer that liners the bottom surface and sidewalls of gate trenches 1000A-B (and the top surface of interlayer dielectric 920). Then, referring to Figure 11B, gate spacer 1120 is formed in gate trenches 1000A and 1000B. Gate spacer 1120 may be formed as a combination of two compliant layers (e.g., 1122 and 1124), each compliant layer lining the bottom surface and sidewalls of gate trenches 1000A-B (and the top surface of interlayer dielectric 920). Then, referring to Figure 11C, gate spacer 1130 is formed in gate trenches 1000A and 1000B. Gate spacer 1130 can be formed as a combination of three compliant layers (e.g., 1132, 1134, and 1136), each compliant layer lining the bottom surface and sidewalls of the gate trenches 1000A-B (and the top surface of the interlayer dielectric 920). It should be understood that any combination of any number of compliant layers can be formed in the gate trenches 1000A-B, and all such gate spacers are covered within the scope of this disclosure.

[0049] In some embodiments, the compliant layers (e.g., 1110, 1122, 1124, 1132, 1134, 1136) each comprise a dielectric material selected from silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, and combinations thereof. For example, the compliant layers can be formed using atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma-assisted chemical vapor deposition (PECVD). The compliant layers can each have a thickness from approximately 2 angstroms (Å) to approximately 500 Å.

[0050] Corresponding to operation 218 in Figure 2, Figure 12 is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of the various manufacturing stages, wherein part of the gate spacer 1120 and the etch stop layer 630A-B are removed. The cross-sectional view of Figure 12 is taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structure of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0051] The gate spacer 1120 and portions of the etch stop layers 630A-B that do not extend along the sidewalls of the gate trenches 1000A-B can be removed by an etching process 1201, which may include one or more steps. For example, a first step of the etching process 1201 can remove portions of the gate spacer 1120 disposed on the top surface of the interlayer dielectric 920 and portions of the gate spacer 1120 disposed on the bottom surface of the gate trenches 1000A-B (the top surface of the etch stop layers 630A-B), exposing a portion of the etch stop layers 630A-B. Subsequently, the exposed portions of the etch stop layers 630A-B can be removed by a second step of the etching process 1201. In another example, the aforementioned portions of the gate spacer 1120 and the etch stop layers 630A-B can be removed together by a single step of the etching process 1201. By removing the aforementioned portions of the gate spacer 1120 and the etch stop layers 630A-B, the top surface of the top semiconductor layer 610A-B is exposed.

[0052] The etching process 1201 may include a plasma etching process, which may have a certain amount of anisotropic characteristics. In such a plasma etching process (including free radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gas sources such as chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), nitrogen trifluoride (NF3), and other suitable gas sources and combinations thereof may be used with passivating gases such as nitrogen (N2), oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivating gases and combinations thereof. Furthermore, for plasma etching processes, the gas source and / or passivation gas can be diluted with, for example, argon (Ar), helium (He), neon (Ne), and other suitable diluent gases or combinations thereof to control the aforementioned etching rate. As a non-limiting example, in etching process 1201, a power supply of 10 watts to 3000 watts, a bias power of 0 watts to 3000 watts, a pressure of 1 millitor to 5 Torr, and an etching gas flow rate of 0 standard cubic centimeters per minute to 5000 standard cubic centimeters per minute can be used. However, it should be noted that power supplies, bias powers, pressures, and flow rates outside the aforementioned ranges can also be considered.

[0053] In another example, etching process 1201 may include a wet etching process in combination with a plasma etching process, which may have a certain amount of isotropic properties. In such a wet etching process, primary etching chemicals such as hydrofluoric acid (HF), fluorine gas (F2), and other suitable primary etching chemicals and combinations thereof may be used with auxiliary etching chemicals such as sulfuric acid (H2SO4), hydrogen chloride (HCl), hydrogen bromide (HBr), ammonia (NH3), phosphoric acid (H3PO4), and other suitable auxiliary etching chemicals and combinations thereof, as well as solvents such as deionized water, alcohol, acetone, and other suitable solvents and combinations thereof to control the etching rate described above.

[0054] When the gate spacer comprises multiple layers (e.g., 1120 in Figure 11B, 1130 in Figure 11C), after etching process 1201, the gate spacer may include a first layer having a sidewall exposed in the gate trench, and one or more second layers having an L-shaped profile. Specifically, the L-shaped second layer includes a vertical portion and a horizontal portion, wherein the vertical portion is separated from the gate trench by the first layer, and one sidewall of the horizontal portion is exposed in the gate trench.

[0055] For example, in Figure 12, where the gate spacer 1120 comprises two layers, after etching process 1201, layer 1124 has one sidewall exposed in gate trenches 1000A-B, and the other sidewall contacts one of the sidewalls of the vertical portion 1122V of layer 1122. Furthermore, layer 1122 includes a horizontal portion 1122H connected to the vertical portion 1122V, which has one sidewall exposed in gate trenches 1000A-B and another sidewall contacting the interlayer dielectric 920. In another example where the gate spacer comprises three layers (e.g., gate spacer 1130 in Figure 11C), after etching process 1201, layer 1136 may have one sidewall exposed in gate trenches 1000A-B, and the other sidewall contacting one of the sidewalls of the vertical portion of layer 1134. Furthermore, layer 1134 may include a horizontal portion connected to its vertical portion, having one sidewall exposed in the gate trenches 1000A-B and another sidewall exposed in the vertical portion of contact layer 1132. Additionally, layer 1132 may include a horizontal portion connected to its vertical portion, having one sidewall exposed in the gate trenches 1000A-B and another sidewall exposed in the interlayer dielectric 920.

[0056] Alternatively or additionally, according to some embodiments, the L-shaped profile can be removed by etching process 1201. For example, in Figure 12, a portion of layer 1124 and the horizontal portion 1122H below layer 1124 can be removed during etching process 1201. Therefore, the gate spacer 1120 may contain only the remaining layer 1122. In this case, the critical dimensions of gate trenches 1000A-B can be increased, which can increase the critical dimensions of the active gate structure that will subsequently fill gate trenches 1000A-B.

[0057] The remaining portions of the etch stop layers 630A-B each have sidewalls perpendicularly aligned with the sidewalls formed by one or more layers (e.g., 1122 and 1124) of the gate spacers 1120. These two perpendicularly aligned sidewalls are exposed in the gate trenches 1000A-B. Therefore, the etch stop layers 630A-B and the gate spacers 1120 may share a critical dimension CD1, measured along the Y direction between their respective sidewalls. Furthermore, the inner spacers 710A-B may each have a critical dimension CD2, measured along the Y direction between their respective sidewalls. In the example shown in Figure 12, CD1 is approximately equal to CD2. It should be understood that CD1 may be greater than or less than CD2, both of which are covered within the scope of this disclosure. In some other embodiments, a portion of the exposed sidewalls of the gate spacers 1120 and / or the exposed sidewalls of the etch stop layers 630A-B may not be formed as vertical sidewalls, which will be discussed below.

[0058] Figures 13A, 13B, 13C, and 13D show enlarged views of the different contours of the gate spacer 1120 and the etch stop layers 630A / B formed by the etching process 1201 (Figure 12). As shown in Figure 13A, layers 1122 and 1124 of the gate spacer 1120 together present vertical sidewalls exposed in the gate trench 1000A / B (e.g., forming an angle of approximately 90° between the top surfaces of the exposed semiconductor layer 610A), while the sidewalls of the etch stop layers 630A / B extending from the vertical sidewalls present curvature-based contours exposed in the gate trench 1000A / B (e.g., sidewall 1301 shown). In detail, the horizontal portion 1122H of layer 1122 presents one of its sidewalls exposed in the gate trench 1000A / B as part of the vertical sidewall. As shown in Figure 13B, layers 1122 and 1124 of the gate spacer 1120 together present vertical sidewalls exposed in the gate trench 1000A / B (e.g., forming an angle of approximately 90° between the top surfaces of the exposed semiconductor layer 610A), while the sidewalls of the etch stop layer 630A / B extending from the vertical sidewalls present an edge-based profile exposed in the gate trench 1000A / B (e.g., sidewall 1303 shown). Specifically, the horizontal portion 1122H of layer 1122 presents one of its sidewalls exposed in the gate trench 1000A / B as part of the vertical sidewalls.

[0059] As shown in Figure 13C, layer 1124 of gate spacer 1120 presents vertical sidewalls exposed in gate trenches 1000A / B (e.g., forming an angle of approximately 90° between the top surfaces of the exposed semiconductor layers 610A), while the sidewalls of layer 1122 and the sidewalls of etch stop layers 630A / B together present a curvature-based profile exposed in gate trenches 1000A / B (e.g., sidewalls 1305 and 1307 shown). Specifically, the horizontal portion 1122H of layer 1122 presents one of its sidewalls 1305 exposed in gate trenches 1000A / B as part of the curvature-based profile. Such gate spacers may sometimes be referred to as having a curvature-based footing protruding from the vertical sidewalls. As shown in Figure 13D, layer 1124 of gate spacer 1120 presents vertical sidewalls exposed in gate trenches 1000A / B (e.g., forming an angle of approximately 90° between the top surfaces of the exposed semiconductor layers 610A), while the sidewalls of layer 1122 and the sidewalls of etch stop layers 630A / B together present an edge-based profile exposed in gate trenches 1000A / B (e.g., sidewalls 1309 and 1311 shown). Specifically, the horizontal portion 1122H of layer 1122 presents one of its sidewalls 1309 exposed in gate trenches 1000A / B as part of the edge-based profile. Such a gate spacer may sometimes be referred to as an edge-based substrate with projections from the vertical sidewalls.

[0060] The example gate spacer shown in Figures 13C-D comprises two layers, such that at least one of the layers has a curvature-based substrate or an edge-based substrate. However, it should be understood that the disclosed gate spacer, regardless of the number of layers, may have one or more of its layers presenting a curvature-based substrate or an edge-based substrate, all of which are covered within the scope of this disclosure. For example, when the gate spacer comprises one layer (e.g., gate spacer 1110 in Figure 11A), after etching process 1201, gate spacer 1110 may have a curvature-based substrate or an edge-based substrate projecting toward gate trench 1000A / B. In another example, when the gate spacer comprises three layers (e.g., gate spacer 1130 in Figure 11C), after etching process 1201, one or more layers of gate spacer 1130 (e.g., layers 1132, 1134 and / or 1136) may have a curvature-based substrate or an edge-based substrate protruding toward gate trench 1000A / B.

[0061] Corresponding to operation 220 in Figure 2, Figure 14 is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of the various manufacturing stages, wherein semiconductor layers 610A-B are removed. The cross-sectional view of Figure 14 is taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structure of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0062] After exposing the top semiconductor layers 610A-B (refer again to Figure 12), the semiconductor layers 610A-B are removed by selective etching (e.g., hydrochloric acid (HCl)) while leaving the semiconductor layers 620A-B substantially intact. According to various embodiments, after removing the semiconductor layers 610A-B, the respective bottom and / or top surfaces of each of the semiconductor layers 620A-B can be exposed by the "extended" gate trenches 1000A-B. For example, after removing the semiconductor layers 610A-B, the gate trenches 1000A-B can further extend from the region above the top semiconductor layers 610A-B to the region below the top semiconductor layers 610A-B. Therefore, the bottom surfaces of each of the top semiconductor layers 620A-B can be exposed, and the respective top and bottom surfaces of the remaining semiconductor layers 620A-B can also be exposed.

[0063] Corresponding to operation 222 in Figure 2, Figure 15 is a cross-sectional view of the fully wound gate field-effect transistor device 300 at one of various manufacturing stages, which includes active gate structures 1500A and 1500B. The cross-sectional view of Figure 15 is taken in a direction perpendicular to the longitudinal direction of the active / dummy gate structures of the fully wound gate field-effect transistor device 300 (e.g., cross-section BB shown in Figure 1).

[0064] The active gate structures 1500A-B are formed in the extended gate trenches 1000A-B (Figure 14) by filling the gate dielectric and gate metal, while keeping other components (e.g., gate spacers 1120) largely intact. Therefore, the active gate structures 1500A-B can each inherit the size and profile of the gate trenches 1000A-B. For example, in Figure 15, the active gate structures 1500A-B can each include an upper and a lower portion, which can be separated by etch stop layers 630A / B (if still present). The upper portion can be surrounded by the gate spacers 1120, while the lower portion can surround each semiconductor layer 620A / B. In some embodiments, the gate spacers 1120 can include at least one layer (e.g., 1122) with an L-shaped profile, having a horizontal portion protruding toward the active gate structure (and away from the interlayer dielectric 920). In detail, layer 1124 of gate spacer 1120 has a sidewall of a first portion that contacts the upper sidewall of active gate structure 1500A / B, and another sidewall that contacts one of the sidewalls of the vertical portion of layer 1122. Furthermore, layer 1122 includes a horizontal portion connected to the vertical portion, which has a sidewall of a second portion that contacts the sidewall of active gate structure 1500A / B, and another sidewall that contacts the interlayer dielectric 920.

[0065] In some embodiments, the active gate structures 1500A-B each include a gate dielectric and a gate metal. For example, in Figure 15, the active gate structures 1500A-B each include a gate dielectric 1502 and a gate metal 1504. Although the gate dielectric 1502 and the gate metal 1504 are each shown as a single layer, it should be understood that the gate dielectric 1502 and the gate metal 1504 may each be formed as a multilayer stack, all of which are covered within the scope of this disclosure.

[0066] Gate dielectric 1502 may surround each semiconductor layer 620A-B (e.g., top and bottom surfaces and sidewalls facing the X direction). Gate dielectric 1502 may be formed of different high-dielectric-constant dielectric materials or similar high-dielectric-constant dielectric materials. Exemplary high-dielectric-constant dielectric materials include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Gate dielectric 1502 may include a stack of multiple high-dielectric-constant dielectric materials. Gate dielectric 1502 may be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), plasma-assisted chemical vapor deposition, etc. In some embodiments, gate dielectric 1502 may optionally include a very thin oxide (e.g., SiOx) layer, which may be a native oxide layer formed on the respective surfaces of semiconductor layers 620A-B.

[0067] Gate metal 1504 may surround each semiconductor layer 620A-B, with gate dielectric 1502 disposed between them. More specifically, gate metal 1504 may include multiple gate metal portions abutting each other along the Z direction. Each gate metal portion may extend not only along a horizontal plane (e.g., a plane extended by the X and Y directions) but also along a vertical direction (e.g., the Z direction). Therefore, two adjacent gate metal portions may be abutted together to surround a corresponding semiconductor layer 620A-B, with gate dielectric 1502 disposed between them.

[0068] The gate metal 1504 may comprise a stack of various metallic materials. For example, the gate metal 1504 may be a p-type work function layer, an n-type work function layer, multiple layers thereof, or a combination thereof. The work function layer may also be referred to as a work function metal. Exemplary p-type work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function value is related to the material composition of the work function layer; therefore, the material of the work function layer is selected to adjust its work function value, thereby achieving the target critical voltage Vt in the device to be formed. The work function layer may be deposited by chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition, and / or other suitable processes.

[0069] According to one or more embodiments of the present disclosure, Figure 16 illustrates a flowchart of a method 1600 for forming a non-planar transistor device. For example, at least some operations (or steps) of method 1600 can be used to form a fin field-effect transistor device, a fully wound gate field-effect transistor device (e.g., fully wound gate field-effect transistor device 100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, a fully wound gate (GAA) transistor device, etc. It should be noted that method 1600 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional operations may be provided before, during, and after method 1600 of Figure 16, and some other operations may only be briefly described in this disclosure.

[0070] In some embodiments, some operations of method 1600 are similar to those of method 200 (Figure 2), therefore, the following discussion will focus on the differences. For example, method 1600 begins with operation 1602 of providing a substrate. Method 1600 continues to operation 1604 of forming a fin structure, the fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers. Method 1600 continues to operation 1606 of forming one or more dummy gate structures. Unlike method 200, method 1600 then continues to operation 1608, forming a first gate spacer around the dummy gate structure. Method 1600 then continues to operation 1610 of removing a portion of the fin structure, continues to operation 1612 of forming an inner spacer, and continues to operation 1614 of forming a source / drain structure. Subsequently, in operation 1616, one or more dummy gate structures are removed. Method 1600 continues to operation 1618 of forming a second gate spacer. Method 1600 continues to operation 1620, which involves etching the second gate spacer. Method 1600 continues to operation 1622, which involves removing the first semiconductor layer. Method 1600 continues to operation 1624, which involves forming one or more active gate structures.

[0071] A fully wound gate field-effect transistor (FFET) device is formed using method 1600. The FFET device may have a first gate spacer and a second gate spacer, wherein the first gate spacer (when including multiple layers) may present an L-shaped profile protruding away from the active gate structure and toward the interlayer dielectric, and the second gate spacer (when including multiple layers) may also present an L-shaped profile protruding toward the active gate structure and away from the interlayer dielectric. According to various embodiments, Figures 17A, 17B, 17C, and 17D respectively show enlarged cross-sectional views of different profiles of the first and second gate spacers around the upper portion of the active gate structure 1701 formed by method 1600 of Figure 16. It should be understood that the enlarged views of Figures 17A-D represent only a portion of the FFET device 1700, which includes various other components (e.g., substrate, source / drain structure, semiconductor layer as a channel, etc.) which are not shown for clarity.

[0072] Referring first to Figure 17A, the fully wound gate field-effect transistor device 1700 includes a first gate spacer 1702 (e.g., formed by operation 1608) and a second gate spacer 1704 (e.g., formed by operations 1618 and 1620), both extending along the upper sidewall of the active gate structure 1701. Furthermore, the fully wound gate field-effect transistor device 1700 includes an interlayer dielectric 1710 extending along the respective sidewalls of the upper portion of the active gate structure 1701, with the gate spacers 1702 and 1704 sandwiched between them. In the example of Figure 17A, the gate spacers 1702 and 1704 each comprise a single layer, thus allowing the gate spacers 1702 and 1704 to each present a vertical profile.

[0073] In some embodiments, the first gate spacer 1702 may include a low dielectric constant spacer and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, etc. The second gate spacer 1704 may include a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, etc. or combinations thereof. For example, the first gate spacer 1702 and the second gate spacer 1704 may be formed using atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma-assisted chemical vapor deposition (PECVD), respectively.

[0074] Referring now to Figure 17B, the fully wound gate field-effect transistor device 1700 includes a first gate spacer 1712 (e.g., formed by operation 1608) and a second gate spacer 1718 (e.g., formed by operations 1618 and 1620), both extending along the upper sidewall of the active gate structure 1701. An interlayer dielectric 1710 extends along the respective sidewall of the upper portion of the active gate structure 1701, with the gate spacers 1712 and 1718 sandwiched between them. In the example of Figure 17B, the first gate spacer 1712 comprises multiple layers (e.g., 1714 and 1716), and the second gate spacer 1718 comprises a single layer. Thus, the layer 1714 of the first gate spacer 1712 may have an L-shaped profile, while the layer 1716 of the first gate spacer 1712 and the second gate spacer 1718 may each have a vertical profile. The L-shaped profile may have a horizontal portion that protrudes away from the active gate structure 1701 and toward the interlayer dielectric 1710.

[0075] In detail, one sidewall of the second gate spacer 1718 contacts the upper sidewall of the active gate structure 1701, while the other sidewall contacts one of the sidewalls of the vertical portion 1714V of the layer 1714 of the first gate spacer 1712. The other sidewall of the vertical portion 1714V may contact the layer 1716. Furthermore, the layer 1714 includes a horizontal portion 1714H connected to the vertical portion, having one sidewall contacting the second gate spacer 1718 and another sidewall contacting the interlayer dielectric 1710. It should be understood that the first gate spacer 1712 may include any number of layers greater than two, all of which are covered within the scope of this disclosure. Therefore, one or more layers of the first gate spacer 1712 may present an L-shaped profile. For example, when the gate spacer 1712 has three layers, the gate spacer 1712 may further include an L-shaped layer located between layers 1714 and 1716 as shown in Figure 17B.

[0076] In some embodiments, each layer of the first gate spacer 1712 may include a low dielectric constant spacer and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, etc. The second gate spacer 1718 may include a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, etc. or combinations thereof. For example, the first gate spacer 1712 and the second gate spacer 1718 may be formed using atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma-assisted chemical vapor deposition (PECVD), respectively.

[0077] Referring now to Figure 17C, the fully wound gate field-effect transistor device 1700 includes a first gate spacer 1722 (e.g., formed by operation 1608) and a second gate spacer 1724 (e.g., formed by operations 1618 and 1620), both extending along the upper sidewall of the active gate structure 1701. An interlayer dielectric 1710 extends along the respective sidewall of the upper portion of the active gate structure 1701, with the gate spacers 1722 and 1724 sandwiched between them. In the example of Figure 17C, the second gate spacer 1724 comprises multiple layers (e.g., 1726 and 1728), and the first gate spacer 1722 comprises a single layer. Thus, the layer 1726 of the second gate spacer 1724 can have an L-shaped profile, while the layer 1728 of the second gate spacer 1724 and the first gate spacer 1722 can each have a vertical profile. The L-shaped profile may have a horizontal portion that protrudes toward the active gate structure 1701 and away from the interlayer dielectric 1710.

[0078] In detail, layer 1728 of the second gate spacer 1724 has a sidewall of a first portion contacting the sidewall of the upper part of the active gate structure 1701, and another sidewall of one of the sidewalls of the vertical portion 1726V of the contact layer 1726. Furthermore, layer 1726 includes a horizontal portion 1726H connected to the vertical portion, having a sidewall of a second portion contacting the sidewall of the upper part of the active gate structure 1701, and another sidewall contacting the first gate spacer 1722. It should be understood that the second gate spacer 1724 may include any number of layers greater than two, all of which are covered within the scope of this disclosure. Therefore, one or more layers of the second gate spacer 1724 may present an L-shaped profile. For example, when the gate spacer 1724 has three layers, the gate spacer 1724 may further include an L-shaped layer located between layers 1726 and 1728 shown in Figure 17C.

[0079] In some embodiments, the first gate spacer 1722 may include a low dielectric constant spacer and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, etc. Each layer of the second gate spacer 1724 may include a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, etc. or combinations thereof. For example, the first gate spacer 1722 and the second gate spacer 1724 may be formed using atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma-assisted chemical vapor deposition (PECVD), respectively.

[0080] Referring now to Figure 17D, the fully wound gate field-effect transistor device 1700 includes a first gate spacer 1732 (e.g., formed by operation 1608) and a second gate spacer 1742 (e.g., formed by operations 1618 and 1620), both extending along the upper sidewall of the active gate structure 1701. An interlayer dielectric 1710 extends along the respective sidewall of the upper portion of the active gate structure 1701, with the gate spacers 1732 and 1742 sandwiched between them. In the example of Figure 17D, both the first gate spacer 1732 and the second gate spacer 1742 comprise multiple layers (e.g., 1734 and 1736 and 1744 and 1746, respectively). Therefore, layer 1734 of the first gate spacer 1732 can have an L-shaped profile, while layer 1736 of the first gate spacer 1732 can have a vertical profile; layer 1744 of the second gate spacer 1742 can have an L-shaped profile, while layer 1746 of the second gate spacer 1742 can have a vertical profile. The L-shaped profile of the first gate spacer 1732 can have a horizontal portion protruding away from the active gate structure 1701 and toward the interlayer dielectric 1710; and the L-shaped profile of the second gate spacer 1742 can have a horizontal portion protruding toward the active gate structure 1701 and away from the interlayer dielectric 1710.

[0081] In detail, layer 1746 of the second gate spacer 1742 has a sidewall that contacts a first portion of the sidewall of the upper part of the active gate structure 1701, and another sidewall that contacts one of the sidewalls of the vertical portion 1744V of layer 1744 of the second gate spacer 1742. The other sidewall of the vertical portion 1744V may contact the vertical portion 1734V of layer 1734 of the first gate spacer 1732. Furthermore, layer 1744 of the second gate spacer 1742 includes a horizontal portion 1744H connected to the vertical portion 1744V, which has a sidewall that contacts a second portion of the sidewall of the upper part of the active gate structure 1701, and another sidewall that contacts the layer 1734 of the first gate spacer 1732. Furthermore, layer 1734 of the first gate spacer 1732 includes a horizontal portion 1734H connected to the vertical portion 1734V, having one sidewall in contact with layer 1744 of the first gate spacer and another sidewall in contact with the interlayer dielectric 1710. It should be understood that the first gate spacer 1732 and the second gate spacer 1742 may comprise any number of layers greater than two, all of which are covered within the scope of this disclosure. Therefore, one or more layers of the first gate spacer 1732 may have an L-shaped profile; and one or more layers of the second gate spacer 1742 may have an L-shaped profile.

[0082] In some embodiments, each layer of the first gate spacer 1732 may include a low dielectric constant spacer and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, etc. Each layer of the second gate spacer 1742 may include a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, etc. or combinations thereof. For example, the first gate spacer 1732 and the second gate spacer 1742 may be formed using atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma-assisted chemical vapor deposition (PECVD), respectively.

[0083] In one example aspect, this disclosure provides a semiconductor device comprising: a plurality of semiconductor layers vertically separated from each other; a gate structure including a lower portion and an upper portion, wherein the lower portion wraps around each semiconductor layer; and a gate spacer extending along a sidewall of the upper portion of the gate structure and including a first layer and a second layer; wherein the first layer contacts a first portion of the sidewall and the second layer contacts a second portion of the sidewall.

[0084] In some embodiments, the gate spacer further includes a third layer, the third layer contacting a third portion of the sidewall.

[0085] In some embodiments, the first portion of the sidewall is vertically aligned with the second portion of the sidewall.

[0086] In some embodiments, the second portion of the sidewall is inclined toward the gate structure away from the first portion of the sidewall.

[0087] In some embodiments, the second portion of the sidewall has a curvature-based profile.

[0088] In some embodiments, the second portion of the sidewall has an edge-based profile.

[0089] In some embodiments, the first layer of the gate spacer includes a first side surface, the first side surface contacting a first portion of the sidewall, a second side surface, the second side surface contacting a first portion of the second layer, and a bottom surface, the bottom surface contacting a second portion of the second layer.

[0090] In some embodiments, an etch stop layer is further included, disposed between the upper and lower parts of the gate structure.

[0091] In some embodiments, the etch stop layer includes a top surface that contacts the bottom surface of a second layer of the gate spacer.

[0092] In some embodiments, the etch stop layer includes a side surface that extends from the sidewall of the upper part of the gate structure and has a profile selected from a group consisting of a curvature-based profile and an edge-based profile.

[0093] In another example aspect, this disclosure provides a semiconductor device including: a fin structure disposed above a substrate; a gate structure including a lower portion and an upper portion, wherein the lower portion straddles the fin structure; and a gate spacer extending along a sidewall of the upper portion of the gate structure and including a first layer and a second layer; wherein the first layer has a vertical portion that contacts and extends along the sidewall; and wherein the second layer includes: a vertical portion that extends along the sidewall and is separated from the sidewall by the first layer; and a horizontal portion that contacts the sidewall.

[0094] In other embodiments, the fin structure includes one or more semiconductor layers that are vertically separated from each other, and a gate structure surrounds each semiconductor layer.

[0095] In some other embodiments, the horizontal portion of the second layer also contacts the bottom surface of the first layer.

[0096] In some other embodiments, the interface between the sidewall and the first layer is vertically aligned with the interface between the sidewall and the second layer.

[0097] In some other embodiments, the interface between the sidewall and the second layer is inclined from the interface between the sidewall and the first layer toward the gate structure.

[0098] In other embodiments, the interface between the sidewall and the second layer has a curvature-based profile.

[0099] In other embodiments, the interface between the sidewall and the second layer has an edge-based profile.

[0100] In another example aspect, this disclosure provides a method of manufacturing a semiconductor device, comprising: forming a fin structure extending along a first lateral direction; forming a dummy gate structure above a portion of the fin structure, wherein the dummy gate structure extends along a second direction perpendicular to the first lateral direction; growing source / drain structures, respectively coupled to the ends of a portion of the fin structure; removing the dummy gate structure to form a gate trench; lining the inner sidewalls of the gate trench with a gate spacer; and forming an active gate structure in the gate trench.

[0101] In some other embodiments, the fin structure includes a plurality of semiconductor layers, and a gate structure surrounds each semiconductor layer.

[0102] In some other embodiments, the dummy gate structure includes a dielectric material that is unfavorable to the growth of the source / drain structure.

[0103] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0007] The various aspects of this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the cells may be arbitrarily enlarged or reduced to clearly demonstrate the features of this disclosure. According to some embodiments of this disclosure, Figure 1 illustrates a view of a gate-all-around (GAA) field-effect transistor (FET). According to some embodiments of this disclosure, Figure 2 illustrates a flowchart of an example method for manufacturing a non-planar transistor device. According to some embodiments of this disclosure, Figures 3, 4A, 4B, 5, 6, 7, 8A, 8B, 9, 10, 11A, 11B, 11C, 12, 13A, 13B, 13C, 13D, 14, and 15 illustrate cross-sectional views of an example fully wound gate field-effect transistor device (or a portion of an example fully wound gate field-effect transistor device) manufactured by the method of Figure 2 during various manufacturing stages. According to some embodiments of this disclosure, Figure 16 illustrates a flowchart of another example method for manufacturing a non-planar transistor device. According to some embodiments of this disclosure, Figures 17A, 17B, 17C, and 17D respectively illustrate enlarged cross-sectional views of different contours of a plurality of gate spacers formed by the method of Figure 16.

Claims

1. A semiconductor device, comprising: Multiple semiconductor layers, vertically separated from each other; A gate structure includes a lower portion and an upper portion, wherein the lower portion wraps around each of the semiconductor layers; and a gate spacer extending along a sidewall of the upper portion of the gate structure, and including a first layer having a rectangular profile and a second layer having an L-shaped profile, the second layer contacting the first layer; wherein the first layer contacts a first portion of the sidewall, and the second layer contacts a second portion of the sidewall; and wherein the second layer includes: a vertical portion separated from the sidewall by the first layer; And a horizontal portion that contacts the sidewall, wherein the entire top surface of the horizontal portion contacts the entire bottom surface of the first layer.

2. The semiconductor device as claimed in claim 1, wherein the gate spacer further includes a third layer that contacts a third portion of the sidewall.

3. The semiconductor device as claimed in claim 1, wherein the first portion of the sidewall is vertically aligned with the second portion of the sidewall.

4. The semiconductor device as claimed in claim 1, wherein the second portion of the sidewall is inclined toward the gate structure away from the first portion of the sidewall.

5. The semiconductor device as claimed in claim 4, wherein the second portion of the sidewall has a curvature-based profile.

6. The semiconductor device as claimed in claim 4, wherein the second portion of the sidewall has an edge-based profile.

7. The semiconductor device as claimed in claim 1, wherein the first layer of the gate spacer includes a first side surface that contacts the first portion of the sidewall; and a second side surface that contacts a first portion of the second layer.

8. The semiconductor device as claimed in claim 1 further includes an etch stop layer disposed between the upper and lower portions of the gate structure.

9. The semiconductor device as claimed in claim 8, wherein the etch stop layer includes a top surface that contacts a bottom surface of the second layer of the gate spacer.

10. The semiconductor device as claimed in claim 8, wherein the etch stop layer includes a side surface extending from the sidewall of the upper portion of the gate structure and has a profile selected from a group consisting of a curvature-based profile and an edge-based profile.

11. A semiconductor device, comprising: A fin structure is disposed above a substrate; A gate structure includes a lower portion and an upper portion, wherein the lower portion straddles the fin structure; and a gate spacer extending along a sidewall of the upper portion of the gate structure, and including a first layer and a second layer; wherein the first layer has a rectangular profile and a vertical surface that contacts and extends along the sidewall; and wherein the second layer has an L-shaped profile and includes: a vertical portion extending along the sidewall and separated from the sidewall by the first layer; And a horizontal portion that contacts the sidewall, wherein the entire top surface of the horizontal portion contacts the entire bottom surface of the first layer.

12. A method for manufacturing a semiconductor device, comprising: A fin structure is formed, extending along a first lateral direction; A dummy gate structure is formed above a portion of the fin structure, wherein the dummy gate structure extends along a second direction perpendicular to the first lateral direction; a plurality of source / drain structures are grown and coupled to a plurality of ends of the portion of the fin structure; the dummy gate structure is removed to form a gate trench. A gate spacer is used to line multiple inner sidewalls of the gate trench; and an active gate structure is formed in the gate trench, wherein the gate spacer extends along an upper sidewall of the active gate structure and includes a first layer having a rectangular profile and a second layer having an L-shaped profile, the second layer contacting the first layer, and wherein the second layer includes: a vertical portion separated from the sidewall by the first layer; And a horizontal portion that contacts the sidewall, wherein the entire top surface of the horizontal portion contacts the entire bottom surface of the first layer.

13. The method of manufacturing a semiconductor device as described in claim 12, wherein the dummy gate structure includes a dielectric material that is unfavorable to the growth of the source / drain structures.

14. A semiconductor device, comprising: A gate structure includes a lower part and an upper part, wherein the lower part is surrounded by a plurality of fins; And a gate spacer extending along one side wall of the upper portion, and including a first layer and a second layer, the first layer and the second layer being in contact with each other; The first layer has a rectangular outline and extends along the sidewall; and the second layer has an L-shaped outline and includes: a vertical portion separated from the sidewall by the first layer; And a horizontal portion having a top surface that completely contacts the entire bottom surface of the first layer.

15. The semiconductor device as claimed in claim 14, wherein the top surface of the horizontal portion separates the bottom surface of the first layer from the upper portion of the gate structure.

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