Methods of micro-via formation for advanced packaging

Abstract

This disclosure relates to microvia structures for interconnects in advanced wafer-level semiconductor packaging. The methods described herein enable the formation of high-quality, low aspect ratio microvia structures with improved uniformity, thus facilitating thin, small form factor semiconductor devices with high I / O density and improved bandwidth and power.

Description

Technical Field

[0001] The embodiments described herein are generally related to micro-via structures for advanced wafer-level semiconductor packaging and methods for forming them. Prior Technology

[0002] With the development of miniaturized electronic components and parts, the demand for faster processing capabilities with greater circuit density places corresponding demands on the materials, structures, and processes used in the manufacture of integrated circuit chips, circuit boards, and package structures. Therefore, a key area of ​​semiconductor device development is the structure and manufacturing methods of interconnects (i.e., interconnects or interconnect structures) with reduced lateral dimensions.

[0003] As is well known, vertical interconnect access (or "via") is an example of an interconnect structure, and laser drilling is the established method for forming vias. While there is a trend towards smaller vias for higher interconnect density, the conventional approach of forming vias with such small diameters (e.g., close to 10 µm or less), especially in high-volume manufacturing settings, may sacrifice certain quality parameters of the via to achieve the desired dimensions. Examples of such quality parameters typically include via morphology, uniformity, and via pad cleanliness.

[0004] Furthermore, current methods for laser drilling through-holes typically rely on ultraviolet (UV) lasers or pulsed CO2 lasers to drill directly into the panel. Both methods require complex beam-shaping optics to convert the Gaussian laser beam profile emitted from the laser source into a top-hat (i.e., flat-top) beam profile, which often cannot consistently and cost-effectively drill diameters smaller than 40 µm. Therefore, masking can be used in conjunction with laser drilling to achieve the desired through-hole size. However, current masking techniques require wet etching and / or laser drilling for mask patterning, which can damage any underlying layers and / or create unwanted debris. Additionally, some methods utilize masks formed from substantially the same material as the underlying conductive layers and / or interconnects, making mask removal difficult after laser drilling of the through-hole.

[0005] Therefore, there is a need in the art for improved methods to form high-quality, small-diameter through-holes, such as micro-holes. Summary of the Invention

[0006] This disclosure relates generally to microvia structures for advanced wafer-level semiconductor packaging and methods for forming them.

[0007] In some embodiments, a method for forming a microvia structure in a semiconductor device is provided. This method includes: laminating a dielectric layer over the semiconductor device; depositing a metal layer over the dielectric layer; and applying, patterning, and developing a resist over the metal layer to form trenches in the resist layer corresponding to desired lateral dimensions of the microvia structure. The method further includes etching the metal layer through the trenches in the developed resist layer to extend the trenches into the metal layer and expose a portion of the dielectric layer. The method also includes laser ablation of the exposed portions of the dielectric layer to form a microvia structure having desired lateral dimensions therein.

[0008] In some embodiments, a method for forming a microvia structure in a semiconductor device is provided. This method includes: laminating a dielectric layer over a conductive layer of the semiconductor device; depositing a metal layer over the dielectric layer; and applying, patterning, and developing a resist over the metal layer to form trenches in the resist layer corresponding to desired lateral dimensions of the microvia structure. The method further includes: selectively etching the metal layer via the trenches in the developed resist layer to extend the trenches into the metal layer and expose a portion of the dielectric layer; laser-ablating the exposed portion of the dielectric layer to form a microvia structure having desired lateral dimensions therein; exposing the microvia structure to a cleaning process to remove debris from the microvia structure; and selectively removing the metal layer from the dielectric layer.

[0009] In some embodiments, a method for forming a microvia structure in a semiconductor device is provided. This method includes: laminating a dielectric layer over a conductive layer of the semiconductor device; depositing a chromium layer over the dielectric layer; and applying, patterning, and developing a resist over the chromium layer to form trenches in the resist layer corresponding to desired lateral dimensions of the microvia structure. The method further includes: selectively etching the chromium layer via trenches in the developed resist layer to extend the trenches into the chromium layer and expose a portion of the dielectric layer; laser-ablating the exposed portion of the dielectric layer to form a microvia structure having desired lateral dimensions therein, wherein the conductive layer of the semiconductor device serves as a laser stop. The method further includes: removing the resist from the chromium layer; exposing the microvia structure to a cleaning process to remove debris from the microvia structure; and selectively removing a metal layer from the dielectric layer by a wet etching process. The cleaning process includes dry fluorine-based plasma etching and methanol-based wet cleaning. Simple Explanation of the Diagram

[0010] To gain a more detailed understanding of the features described above in this disclosure, a more specific description of the disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should not be construed as limiting its scope, as other equivalent embodiments are permissible.

[0011] Figure 1 illustrates a process flow diagram for forming microvias in semiconductor devices according to the embodiments described herein.

[0012] Figures 2A through 2J schematically illustrate cross-sectional views of a portion of a semiconductor device at different stages of a manufacturing process as depicted in Figure 1 according to the embodiments described herein.

[0013] Figures 3A to 3B schematically illustrate cross-sectional views of microvias formed by the process depicted in Figure 1 according to the embodiments described herein.

[0014] Figure 4 schematically illustrates a cross-sectional view of an exemplary semiconductor device comprising a microvia formed by the process depicted in Figure 1, according to an embodiment described herein. Implementation

[0015] This disclosure relates to microvia structures for advanced wafer-level semiconductor packaging and methods for forming the same. The ongoing demand for miniaturized package structures with higher density drives the need for corresponding small-size interconnects (e.g., vias). However, as circuit density increases and via size decreases, via formation becomes increasingly difficult, primarily due to limitations related to the quality and uniformity of laser-drilled narrow via structures. This results in low-quality and non-uniform vias, which can lead to performance degradation. The methods described herein provide an improved approach for forming high-quality and uniform microvia structures.

[0016] Figure 1 illustrates a flowchart of a method 100 for forming microvias in a semiconductor device (e.g., in a redistribution layer (RDL) of a semiconductor package) according to certain embodiments of this disclosure. Figures 2A to 2J schematically illustrate cross-sectional views of a portion of a semiconductor device 200 at different stages of the method 100 represented in Figure 1. Therefore, for clarity, Figures 1 and 2A to 2J are described together herein. Note that although the description pertains to the formation of a single microvia, the methods disclosed herein can be used to form a plurality of microvias or an array of microvias simultaneously or sequentially in a semiconductor device.

[0017] Generally, method 100 begins at operation 102, corresponding to Figure 2A, in which an insulating layer 208 is laminated over the semiconductor element 200. As mentioned above, only a portion of the semiconductor element 200 is illustrated in Figures 2A to 2J, and an RDL can be formed thereon using the insulating layer 208. The semiconductor element 200 can be any suitable type of semiconductor element, including but not limited to 3D semiconductor packages (e.g., 3D wafer-level package (WLP), 3D system-in-package (SiP), stacked integrated circuit (SiC), 3D package-on-package (POP), etc.), 2.5D interposers, 2D semiconductor packages, etc. Therefore, the semiconductor element 200 may include one or more embedded active and / or passive components (e.g., semiconductor dies, memory dies, capacitors, inductors, RF components, etc.) (not shown) and one or more conductive interconnects (not shown) wired therebetween.

[0018] As illustrated in Figure 2A, semiconductor device 200 includes substrate 202, which can serve as a framework or core structure for semiconductor device 200. Typically, substrate 202 is formed of any suitable substrate material, including but not limited to III-V compound semiconductor materials, silicon (e.g., having a resistivity between about 1 and about 10 Ohm-cm or a conductivity of about 100 W / mK), and crystalline silicon (e.g., Si). <100> or Si <111> Materials used include silicon oxide (SiO₂), silicon germanium (SiGe), doped or undoped silicon, undoped high-resistivity silicon (e.g., floating-region silicon with low dissolved oxygen content and resistivity between about 5000 and about 10000 ohm-cm), doped or undoped polycrystalline silicon, silicon nitride (Si₃N₄), silicon carbide (SiC) (e.g., with a conductivity of about 500 W / mK), quartz, glass (e.g., borosilicate glass), sapphire or alumina (Al₂O₃), and / or ceramic materials. In some embodiments, substrate 202 is a monocrystalline p-type or n-type silicon substrate. In some embodiments, substrate 202 is a polycrystalline p-type or n-type silicon substrate. In some embodiments, substrate 202 is a p-type or n-type silicon solar cell substrate.

[0019] The substrate 202 may further have any suitable shape and / or size. For example, the substrate 202 may have a polygonal or circular shape. In some embodiments, the substrate 202 comprises a substantially square silicon substrate having a lateral dimension between about 120 mm and about 220 mm, for example, about 160 mm or between about 156 mm and about 166 mm, with or without chamfered edges. In some other embodiments, the substrate 202 comprises a circular silicon-containing wafer having a diameter between about 100 mm and about 450 mm, for example, between about 150 mm and about 300 mm, for example, about 200 mm.

[0020] Unless otherwise stated, the embodiments and examples described herein are performed on a substrate having a thickness between about 50 µm and about 1500 µm, for example, between about 90 µm and about 780 µm. For example, substrate 202 has a thickness between about 100 µm and about 300 µm, for example, between about 110 µm and about 200 µm. In another example, substrate 202 has a thickness between about 60 µm and about 180 µm, for example, between about 80 µm and about 120 µm.

[0021] In some embodiments, the semiconductor element 202 further includes an insulating layer 204 formed on the substrate 202. Typically, the insulating layer 204 may be formed of a dielectric and polymeric material, such as epoxy resin. For example, the insulating layer 204 may be formed of an epoxy resin containing ceramic filler, such as an epoxy resin filled with (e.g., containing) substantially spherical silicon dioxide (SiO2) particles. As used herein, the term "spherical" refers to any round, ellipsoidal, or spherical shape. For example, in some embodiments, the ceramic filler may have an elliptical, elongated elliptical, or other similar circular shape. However, other morphologies may also be considered. Other examples of ceramic fillers that can be used to form dielectric film 220 include aluminum nitride (AlN), alumina (Al₂O₃), silicon carbide (SiC), silicon nitride (Si₃N₄), Sr₂Ce₂Ti₅O₁₆ ceramics, zirconium silicate (ZrSiO₄), wollastonite (CaSiO₃), beryllium oxide (BeO), cerium dioxide (CeO₂), boron nitride (BN), calcium copper titanium oxide (CaCu₃Ti₄O₁₂), magnesium oxide (MgO), titanium dioxide (TiO₂), zinc oxide (ZnO), etc.

[0022] In some instances, the ceramic filler used to form the insulating layer 204 has particles with a size ranging from about 40 nm to about 1.5 µm, for example, between about 80 nm and about 1 µm. For example, the ceramic filler used to form the insulating layer 204 has particles with a size ranging from about 200 nm to about 800 nm, for example, between about 300 nm and about 600 nm. In some embodiments, the ceramic filler comprises particles smaller than about 25% of the width or diameter of a desired structure patterned in the substrate 202, the structure including through-holes for interconnection and cavities for active and / or passive elements. In some embodiments, the ceramic filler has particles smaller than about 15% of the width or diameter of the desired patterned structure.

[0023] In a further embodiment, the insulating layer 204 is formed of a polyimide material, such as a photodefinable or non-photosensitive polyimide material, a polybenzoxazole (PBO) material, a silicon dioxide material, and / or a silicon nitride material.

[0024] As further illustrated in Figure 2A, semiconductor device 202 includes a conductive layer 206 formed over insulating layer 204. Conductive layer 206 may represent a trace layer, wiring layer, pad layer, or any other type of lateral interconnect structure for electrically coupling one or more active and / or passive components. In some embodiments, conductive layer 206 has a thickness between about 2 µm and about 20 µm, for example, between about 3 µm and about 18 µm, such as between about 6 µm and about 18 µm. Conductive layer 206 is typically formed of one or more layers of any suitable conductive material, including but not limited to copper (Cu), aluminum (Al), gold (Au), nickel (Ni), silver (Ag), palladium (Pd), tin (Sn), etc. In some embodiments, an adhesive layer (not shown) and / or a seed layer (not shown) are formed between the surface of insulating layer 204 and the surface of conductive layer 206 to better adhere conductive layer 206 to insulating layer 204 and to prevent diffusion of conductive material. For example, in some embodiments, a molybdenum (Mo), titanium (Ti), tantalum (Ta), or titanium-tungsten (WTi) adhesive layer and / or a copper seed layer are formed between the insulating layer 204 and the conductive layer 206.

[0025] Returning to Figure 1 and method 100, in operation 102, an insulating layer 208 is laminated over the semiconductor element 200. In some embodiments, the insulating layer 208 is substantially similar to the insulating layer 204. For example, in some embodiments, the insulating layer 208 is formed of a dielectric material, such as epoxy resin containing ceramic filler, polyimide material, PBO material, silicon dioxide material, and / or silicon nitride material. However, in some other embodiments, the insulating layer 208 is formed of a different material than the insulating layer 204. Typically, the insulating layer 208 has a thickness between about 2 µm and about 20 µm, for example between about 4 µm and about 18 µm, for example between about 6 µm and about 14 µm.

[0026] During lamination, an insulating layer 208 (e.g., as a film) is placed over a semiconductor element 200, and then the insulating layer 208 is exposed to elevated temperatures, causing it to soften and adhere to, for example, a conductive layer 206 of the semiconductor element 200. In some embodiments, the lamination operation includes a vacuum lamination process that can be performed in a laminator or other suitable apparatus. In some embodiments, the lamination operation is performed using a hot pressing process.

[0027] In some embodiments, the lamination operation is performed at a temperature of about 80°C to about 200°C for a duration between about 5 seconds and about 90 seconds, for example, between about 30 seconds and about 60 seconds. In some embodiments, the lamination operation involves applying a pressure between about 1 psig and about 50 psig while exposing the semiconductor device 200 having the insulating layer 208 placed thereon to a temperature between about 80°C and about 140°C for a duration between about 5 seconds and about 90 seconds. For example, the lamination operation is performed at a pressure between about 5 psig and about 40 psig and a temperature between about 100°C and about 120°C for a duration between about 10 seconds and about 1 minute. In some examples, the lamination operation is performed at a temperature of about 110°C for about 20 seconds.

[0028] Once the insulating layer 208 is laminated onto the semiconductor device 200, in operation 104 corresponding to Figure 2B, a metal masking layer 210 is deposited over the insulating layer 208. The metal masking layer 210 may be formed of one or more suitable metals, including but not limited to chromium (Cr), tungsten (W), molybdenum, copper, and / or the like. In some embodiments, the metal masking layer 210 is formed of a refractory metal. Typically, the metal masking layer 210 has a thickness between about 50 nm and about 500 nm, for example, between about 100 nm and about 400 nm, or for example, between about 100 nm and about 300 nm. For example, in some embodiments, the metal masking layer 210 has a thickness of about 200 nm. The metal masking layer 210 may be deposited over the insulating layer 208 by any suitable deposition technique, including but not limited to sputtering deposition processes (i.e., sputtering by a PVD deposition process).

[0029] In operations 106 and Figure 2C, a spin-coated / spray-coated or dry-film resist layer 212, such as photoresist, is applied, laminated, and patterned over a metallic mask layer 210. In some embodiments, the resist layer 212 is patterned by selectively exposing it to UV radiation to form one or more patterned regions 213. For example, in some embodiments, maskless lithography, such as direct write digital lithography, is used to selectively expose the resist layer 212 to UV radiation. After patterning, the resist layer 212 is developed in operations 108 and Figure 2D to form one or more trenches 214 therein. As shown in Figure 2D, in an example where the resist layer 212 is a negative photoresist, the trenches 212 are formed in areas where the unpatterned resist layer 212 was previously left in operation 106. In an example where the resist layer 212 is a positive photoresist, the trenches 212 correspond to the patterned regions 213 formed in operation 106. In some embodiments, the development process is a wet process, which includes exposing the resist layer 212 to a solvent. For example, the development process may be a wet etching process utilizing an aqueous etching process. In other examples, the film development process may be a wet etching process utilizing a buffered etching process that is selective to the desired material. However, any suitable combination of wet solvent or wet etchant can be used in the resist film development process.

[0030] As depicted in Figures 2C through 2D, the resist layer 212 is patterned and developed according to the desired morphology and lateral dimensions of the subsequently formed microvias. Typically, microvias have a cylindrical or circular tubular shape corresponding to the shape of the interconnects through which wiring will pass. Therefore, in some embodiments, the resist layer 212 is patterned and developed to form cylindrical trenches 214 therein, allowing the cylindrical pattern to be transferred downstream to the metal mask layer 210 and the insulating layer 208. However, in further embodiments, non-cylindrical or non-annular interconnects and / or vias are desired, thus forming non-cylindrical trenches 214. For example, in some embodiments, during operation 108, the trenches 214 formed in the resist layer 212 may be oval, elliptical, or polygonal in shape.

[0031] In operation 110 and Figure 2E, the semiconductor device 200, on which the patterned and developed resist layer 212 is now formed, is exposed to an etching process to transfer the pattern of the resist layer 212 to the metal mask layer 210. Consequently, trenches 214 extend into the metal mask layer 210, thus exposing the underlying insulating layer 208. As shown in Figure 2E, a portion of the resist layer 212 may also be consumed during the process.

[0032] In some embodiments, the etching process is a plasma-based dry etching process performed in an inductively coupled plasma (ICP) dry etching chamber. For example, in embodiments where the metal mask layer 210 is a chromium mask layer, the semiconductor device 200 can be exposed to a dry chromium selective etching process. In such embodiments, the dry etching process can utilize reactive gases such as oxygen (O2), ammonia (NH3), nitrogen (N2), helium (He), chlorine (Cl2), and / or argon (Ar). For example, in some embodiments, a reactive gas mixture of 90:5:20 Cl2:O2:Ar is used. The chromium selective etching process can further utilize plasma generation power between about 200 watts (W) and about 2000 W (e.g., about 600 W), and bias power between about 100 W and about 400 W (e.g., about 220 W), and can be performed at pressures between about 2 millitors (mTorr) and about 100 mTorr (e.g., about 10 mT).

[0033] After etching the metal mask layer 210, in operation 112 and Figure 2F, the semiconductor device 200 is exposed to a laser ablation process to ablate the portion of the insulating layer 208 exposed through the metal mask layer 210, thereby forming a microvia 216 therein. The laser ablation process can be performed using any suitable type of laser system with adjustable laser process parameters and characteristics, including but not limited to laser power, focused beam diameter, focused height, pulse energy, pulse width, burst energy, number of pulses per burst train (e.g., a sequence of pulses separated by a desired duration), pulse frequency, burst frequency, beam spot size, and spatial beam profile (Gaussian or high-hat). Typically, in operation 112, the laser system can generate a laser beam with a spot size larger than the micro-lithography defining aperture in the metal mask layer 210, because the metal mask layer 210 protects the portion of the insulating layer 208 disposed beneath it.

[0034] In some embodiments, the laser ablation process in operation 112 is performed using an ultraviolet (UV) laser, such as a femtosecond (fs) UV laser with an Innoslab laser source, emitting a laser beam with an emission wavelength between about 180 nm and about 400 nm, for example, between about 300 nm and about 360 nm, such as about 345 nm or about 355 nm. In such embodiments, the UV laser can ablate the insulating layer 208 by generating a pulsed laser beam, which can be emitted in one or more pulse-bursts at a fixed frequency (e.g., 50 MHz or higher) with pulse energies between about 5 nJ and about 10 nJ. Since metals such as copper are not resistant to UV laser beams, the pulse-burst mode with a precise energy dose between about 5 and 10 nJ promotes the ablation of the insulating layer 208, reduces debris formation, and causes minimal damage to the underlying conductive layer 206 compared to continuous or continuous pulsed UV laser beams. Therefore, the conductive layer 206 can act as a laser termination during the laser ablation process of operation 112. Furthermore, the combination of the above-described UV laser conditions with the pre-patterned metal mask layer 210 enables very precise control of the via shape, including the top / bottom opening size, opening shape, and taper between the top / bottom openings.

[0035] In some embodiments, the laser ablation process in operation 112 is performed using a laser source that operates at wavelengths between approximately 700 nm and approximately 1 mm, such as near-infrared (NIR) wavelengths between approximately 700 nm and approximately 2.5 µm, or mid-infrared (mid-IR) wavelengths between approximately 2.5 µm and approximately 24 µm. For example, in some embodiments, the laser ablation process in operation 112 is performed using a laser source having a near-infrared to mid-infrared wavelength between approximately 2 µm and approximately 3 µm. The 2–3 µm wavelength is highly selective for polymer materials relative to metallic materials, thus allowing for a higher alignment tolerance between the emitted laser beam and the pre-patterned trenches 214 in the metal shielding layer 210, since the metal shielding layer 210 will simply reflect any misaligned portions of the laser beam. Furthermore, the improved ablation efficiency of the 2–3 µm wavelength for polymer materials (e.g., the improved ablation efficiency of the polymer material for insulating layer 208) and the relatively low ablation efficiency for metals contribute to minimal damage to the underlying conductive layer 206 during operation 112. In some embodiments, the near-infrared or mid-infrared laser is a fiber laser that generates a laser beam via one or more cascaded processes in an optical fiber. For example, in some embodiments, the fiber laser can inject nanosecond (ns) or picosecond (ps) seed laser beams (e.g., at a wavelength of about 1 µm) into a series of passive or active optical fibers, which have propagation extended across the desired IR wavelength range for nonlinear frequency conversion. In some other embodiments, the fiber laser can pump short-pulse, high-intensity seed laser beams (e.g., femtosecond seed laser beams) into a highly nonlinear optical medium with normal dispersion, such as chalcogenide glass fibers. In yet another embodiment, the fiber laser may utilize erbium-doped or fluoride-doped fiber, or other doped mid-infrared fiber, to emit at a wavelength of approximately 3 µm.

[0036] In embodiments where a plurality of vias 216 or an array of vias 216 is desired, the laser system may include a scanner 220, such as a single-axis or multi-axis large-angle galvanometer optical scanner (e.g., a galvo scanner), to allow one or more laser beams from a laser source to sweep across the surface of the semiconductor element 200 to form a plurality of vias 216 or an array of vias 216. The term "galvanometer scanner" generally refers to any type of device capable of altering the projection or reflection angle of one or more laser beams to allow one or more laser beams to sweep across the semiconductor element 200. For example, scanner 220 may include one or more adjustable and electromechanically controlled mirrors to diverge (e.g., multiply) and / or manipulate the laser beams throughout the semiconductor element 200 during the laser ablation process of operation 112. In some embodiments, the scanner 220 is used to make it possible to drill a single microvia 216 in the semiconductor element 200 at one time, or to drill multiple microvias 216 simultaneously, or to make a laser beam sweep across the surface of the semiconductor element 200 to form a plurality of microvias 216 by sweeping several times.

[0037] In operation 114 and Figure 2G, a resist removal process is performed to strip the resist layer 212 from the semiconductor device 200. Operation 114 can be performed before or after the laser ablation process of operation 112. In some embodiments, the resist layer 212 is removed by one or more dry processes, such as dry etching or ashing. In some embodiments, the resist removal process includes exposing the semiconductor device 200 to microwave O2 plasma while maintaining the semiconductor device 200 at a temperature between about 60°C and about 100°C, for example, about 80°C, which allows the resist layer 212 to be removed without damaging the conductive layer 206 exposed through the microvia 216. Temperature is a critical factor in operation 114 because using too low a temperature will significantly reduce the resist stripping rate, while using too high a temperature may cause damage to the underlying conductive layer 206.

[0038] Following resist removal, in operations 116 and Figure 2H, the semiconductor device 200 is exposed to a cleaning process to remove any unwanted debris remaining in the microvia 216 from the previous laser ablation process and to smooth the surface (e.g., walls) of the microvia 216 exposed to the laser drill. The cleaning process may comprise any combination of dry and / or wet processes. In some embodiments, the semiconductor device 200 is exposed to a dry etching process, such as a plasma-based dry etching process. In such embodiments, the plasma-based dry etching process may utilize reactive gases such as O₂, CF₄, NH₃, N₂, Cl₂, and / or Ar. For example, in some embodiments, the plasma-based dry etching process utilizes a reactive gas mixture of O₂:CF₄:Ar in a ratio of 50:3:5, with plasma generation power between about 200 watts (W) and about 2000 W, such as about 500 W, and bias power between about 25 W and about 100 W, such as about 50 W. In further embodiments, the semiconductor device 200 is exposed to a wet process, which may be used in conjunction with one or more dry processes. For example, in some embodiments, the semiconductor device 200 is exposed to a 5% aqueous solution of methanol:copper chloride (CuCl₂) in a 3:1 ratio, which may be used in conjunction with a plasma-based dry etching process, such as a plasma-based dry etching process utilizing reactive fluorine gas.

[0039] In operation 118 and Figure 2I, the now-cleaned semiconductor device 200 is selectively etched to remove the metal mask layer 210. Therefore, unlike some conventional methods, the metal mask layer 210 is not retained on the semiconductor device 200 during downstream interconnect formation, thus enabling the deposition of a seed layer and / or barrier layer directly over the insulating layer 208 prior to interconnect formation. In some embodiments, the etching process in operation 118 is a wet etching process utilizing any suitable wet etchant or a combination of multiple wet etchants in an aqueous solution. For example, for embodiments where the metal mask layer 210 comprises chromium, the semiconductor device 200 may be immersed in an etching aqueous solution comprising 50% NaOH and 33% K₃[FE(CN)₆] (1:3) at approximately room temperature (27°C) for approximately 2 minutes to approximately 10 minutes, for example, approximately 3 minutes to approximately 5 minutes.

[0040] After selectively etching the metal mask layer 210, interconnects 222 can be formed within the microvia 216, as illustrated in Figure 2J. Interconnects 222 can be formed above the sidewalls of the microvia 216 defined by the insulating layer 208 and extend through the microvia 216 to the underlying conductive layer 206. Interconnects 222 can be deposited in the microvia 216 by any suitable method, including electroless deposition or a combination of physical vapor deposition (PVD) and electrochemical deposition (ECD). In some embodiments, interconnects 222 are deposited to fill or "plug" the microvia 216, thus creating a solid or filled conductor therein. However, in some other embodiments, interconnects 222 are deposited only to the line surface of the microvia 216.

[0041] Interconnect 222 can typically be formed of one or more layers of any suitable conductive material, including but not limited to copper (Cu), aluminum (Al), gold (Au), nickel (Ni), silver (Ag), palladium (Pd), tin (Sn), etc. In some embodiments, as described above, an adhesive layer (not shown) and / or a seed layer (not shown) may be formed above the surface of the microvia 216 prior to the deposition of interconnect 222. For example, in some embodiments, a molybdenum, titanium, tantalum, or titanium-tungsten adhesive layer and / or a copper seed layer are deposited above the sidewalls of the microvia 216 prior to the deposition of interconnect 222 to improve the adhesion of interconnect 222 and prevent the diffusion of conductive material.

[0042] Figures 3A and 3B schematically illustrate cross-sectional views of exemplary microvia structures that can be formed in, for example, a semiconductor element 200 by the method 100 described above, according to certain embodiments. Note that only a portion of the semiconductor element 200 is illustrated in Figures 3A to 3B.

[0043] As shown in Figure 3A, via 316a is an example of a via formed in a redistribution layer (which may be a semiconductor package) of semiconductor element 200. Therefore, via 316a is depicted as being disposed through an insulating layer 208 above a substrate 202, which further includes an insulating layer 204 and a conductive layer 206 formed thereon. Typically, via 316a is formed to penetrate the entire thickness of the insulating layer 208, so the conductive layer 206 can be used as a laser termination during laser ablation of via 316a. In some embodiments, via 316a has a height between about 2 µm and about 20 µm, which may be equal to the thickness of the insulating layer 208. In some embodiments, via 316a has substantially vertical sidewalls, and therefore may have a uniform diameter between about 2 µm and about 10 µm, for example, a uniform diameter between about 3 µm and about 7 µm. In some embodiments, the ratio of the diameter of the microvia 316a to the thickness of the insulating layer 208 is between about 1:2 and about 1:1.

[0044] In some other embodiments, as shown in Figure 3A, the microvia has tapered or sloping sidewalls. For example, the sidewalls of the microvia 316 may have a taper angle α between about 60° and about 90°, such as between about 80° and about 90°. In such embodiments, the top diameter DT of the microvia 316a is between about 2 µm and about 15 µm, such as between about 4 µm and about 12 µm, and the bottom diameter DB of the microvia 316a is between about 1 µm and about 8.5 µm, such as between about 2 µm and about 6 µm. The tapered or conical shape can be achieved, for example, by moving a laser beam of a laser system, such as that used in operation 112, in a helical (e.g., circular, spiral) motion relative to the central axis of the microvia 316a. A motion system can also be used to angle the laser beam to form a tapered microvia 316a.

[0045] As shown in Figure 3B, the microvia 316b is an example of a microvia formed through the substrate 202 of the semiconductor element 200, for example, extending from a first surface 303a to a second surface 303b of the substrate 202. In such an embodiment, the microvia 316b is laser-ablated through the insulating layer 204 of the semiconductor element 200, the insulating layer 204 encapsulating (e.g., surrounding) the substrate 202 and passing through a through-silicon via 314 formed in the substrate 202. Therefore, in order to form the microvia 316b, prior to the method 100 described above, the through-silicon via 314 must first be formed through the substrate 202 by any suitable substrate patterning method, and then, in operation 100, the insulating layer 204 is laminated over the substrate 202 to adhere to the substrate and flow into the through-silicon via 314.

[0046] In some embodiments, the through-silicon via 314 is formed by laser ablation, for example, using an IR, UV, or CO2 laser. For example, the laser used to ablate the through-silicon via 314 may be a picosecond or femtosecond UV laser. In some examples, the laser is a femtosecond green laser. In still other embodiments, the through-silicon via 314 is formed by a suitable etching process, for example, a dry etching process or a bead blasting process. Typically, the through-silicon via 314 may have a cylindrical or conical shape, as shown in Figure 3B. Similar to the microvia 316a, the formation of a conical or tapered shape can be achieved, for example, by moving the laser beam used during substrate patterning in a helical (e.g., circular, spiral) motion relative to the central axis of the through-silicon via 314. A motion system can also be used to angle the laser beam. A similar method can also be used to form a cylindrical silicon through-hole 314 with a uniform diameter passing through it.

[0047] After the through-silicon vias 314 are formed, for example, in operation 102 of method 100, the insulating layer 204 may be placed on the substrate 202 and laminated, thus flowing into and filling the through-silicon vias 314. In some embodiments, the lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable apparatus. In some embodiments, the lamination process is performed using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C and for a duration between about 5 seconds and about 1.5 minutes. In such embodiments, the lamination process can be performed at a pressure between about 1 psig and about 50 psig. For example, the lamination process can be performed at a pressure between about 5 psig and about 40 psig and a temperature between about 100°C and about 120°C for a duration between about 10 seconds and about 1 minute.

[0048] After lamination, by method 100, a microvia 316b is formed in the portion of the insulating layer 204 that extends through the silicon via 314, as shown in Figure 3B. Typically, the microvia 316b may have a similar lateral shape and / or size to the microvia 316a, for example, a tapered or conical shape.

[0049] Figure 4 illustrates a schematic cross-sectional side view of an exemplary semiconductor package 400 having microvias formed by method 100 described above, according to certain embodiments. As shown, the semiconductor package 400 includes a substrate 402, such as a silicon substrate, which serves as a package frame and has one or more cavities 408 and one or more through-silicon vias 414 formed therein. An insulating layer 404 is laminated over the substrate 402 and extends from a first side 403a of the substrate 402 through the cavities 408 and the through-silicon vias 414 to a second side 403b. One or more semiconductor dies 406 are disposed in each cavity 408 and embedded within the insulating layer 404 therein. Similarly, one or more interconnects 412 are disposed in each through-silicon via 414 and surrounded by the insulating layer 404 therein. On either side of the semiconductor package 400 is a redistribution layer 420, which is composed of one or more redistribution interconnects 422 electrically connected to the one or more interconnects 412. The redistributed interconnect 422 may include vertical interconnects and lateral interconnects, such as traces, wires, and pads.

[0050] During the formation of the semiconductor package 400, the lamination of the insulating layer 404 causes its dielectric material to flow in and fill the through-silicon vias 414. Therefore, in order to form a channel or path through the entire substrate 402 for interconnects 412 after the lamination of the insulating layer 404, vias 416a can be laser-drilled through the dielectric material of the insulating layer 404 within the through-silicon vias 414, thus forming a via-in-via structure for wiring of the interconnects 412. Similarly, after the interconnects 412 are formed, redistribution interconnects 422 can be formed within redistribution vias 416b on either side of the semiconductor package 400 (this redistribution via 416b can also be laser-drilled into the insulating layer 404). Therefore, the vias 416a and redistribution vias 416b formed in the insulating layer 404 can be microvias formed by the methods described above with reference to Figures 1 and 2A to 2J.

[0051] In summary, the methods and microvia structures described above offer numerous advantages over conventional via fabrication techniques and architectures implemented for semiconductor devices. These benefits include the ability to form high-quality, low aspect ratio microvia structures that, compared to conventional packaging techniques, advantageously enable high-density packaging architectures for advanced integrated semiconductor devices with improved performance and flexibility, as well as relatively lower manufacturing costs.

[0052] Although the foregoing description is an embodiment of this disclosure, other and further embodiments of this disclosure may be designed without departing from the basic scope of this disclosure, and the scope of this disclosure is determined by the following claims.

[0053] 100: Method 102: Operation 104: Operation 106: Operation 108: Operation 110: Operation 112: Operation 114: Operation 116: Operation 118: Operation 200: Semiconductor components 202:Substrate 204: Insulation layer 206: Conductive layer 208: Insulation layer 210: Metallic masking layer 212: Resistant layer 213: Patterned area 214: Trench 216: Micro via hole 220: Scanner 222: Interconnection 303a: First surface 303b: Second surface 314: Through-hole silicon 316a: Micro-via 316b: Micro-via 400: Semiconductor Packaging 402:Substrate 403a: First side 403b: Second side 404: Insulation layer 406: Semiconductor die 408: Cavity 412: Interconnection 414: Through-hole silicon 416a: Through hole 416b: Redistribution via 420: Redistribution layer 422: Redistributed Interconnect DB: Bottom Diameter DT: Top diameter H: Height α: Cone angle

[0054] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a microvia structure in a semiconductor device, comprising the following steps: A dielectric layer is laminated over a conductive layer of a semiconductor device, wherein the semiconductor device includes: a substrate; an insulating layer over the substrate; and the conductive layer over the insulating layer; a metal mask layer is deposited over the dielectric layer; a resist layer is applied, patterned, and developed over the metal mask layer, wherein the development step of the resist layer forms a trench in the resist layer, the trench corresponding to a desired lateral dimension of the microvia structure; the metal mask layer is etched through the trench in the developed resist layer, wherein the etching step of the metal mask layer extends the trench into the metal mask layer and exposes a portion of the dielectric layer; and the exposed portion of the dielectric layer is laser-ablated using a pulse-burst mode ultraviolet (UV) laser, wherein the pulse-burst mode provides a frequency of 50 MHz or higher and between 5 nJ and 10 nJ. A pulse of energy between nJ, and the step of laser ablation of the exposed portion of the dielectric layer therein forming the microvia structure having the desired lateral dimensions and exposing the conductive layer.

2. The method as described in claim 1, wherein the dielectric layer comprises an epoxy resin material having a ceramic filler.

3. The method as described in claim 1, wherein the metal masking layer comprises chromium (Cr), tungsten (W), molybdenum, or copper.

4. The method as described in claim 3, wherein the metal masking layer is deposited over the dielectric layer by physical vapor deposition (PVD).

5. The method as described in claim 1, wherein the resist layer is a photoresist, and the resist layer is patterned by selective exposure to UV radiation.

6. The method as described in claim 1, wherein the resist layer is patterned using direct write digital lithography.

7. The method as described in claim 1, wherein an oxygen-based plasma is used to dry etch the metal mask layer.

8. The method as described in claim 1, wherein the dielectric layer is laser-ablated using an ultraviolet (UV) laser having a wavelength between 345 nm and 355 nm.

9. A method for forming a microvia structure in a semiconductor device, comprising the steps of: laminating a dielectric layer over a conductive layer of the semiconductor device, wherein the semiconductor device comprises: One substrate; An insulating layer is provided above the substrate; The conductive layer is deposited over the insulating layer; a metal masking layer is deposited over the dielectric layer; a resist layer is applied, patterned, and developed over the metal masking layer, wherein the development step of the resisting layer forms a trench in the resisting layer, the trench corresponding to a desired lateral dimension of the microvia structure; the metal masking layer is selectively etched via the trench in the developed resisting layer, wherein the selective etching step of the metal masking layer extends the trench into the metal masking layer and exposes a portion of the dielectric layer; the exposed portion of the dielectric layer is laser-ablated using an ultraviolet (UV) laser in a pulsed burst mode, wherein the pulsed burst mode provides a pulse at a frequency of 50 MHz or higher and an energy between 5 nJ and 10 nJ, and wherein the laser ablation step of the exposed portion of the dielectric layer forms the microvia structure having the desired lateral dimension and exposes the conductive layer. The microvia structure is exposed to a cleaning process to remove debris from the microvia structure; and the metal masking layer is selectively removed from the dielectric layer.

10. The method as described in claim 9, wherein the metal masking layer comprises chromium (Cr).

11. The method as described in claim 10, wherein the metal masking layer is deposited over the dielectric layer by physical vapor deposition (PVD).

12. The method as described in claim 9, wherein the resist layer is patterned using direct-write digital lithography.

13. The method as described in claim 9, wherein an oxygen-based plasma is used to selectively dry-etch the metal mask layer.

14. The method as described in claim 9, wherein the dielectric layer is laser-ablated using an ultraviolet (UV) laser having a wavelength between 345 nm and 355 nm.

15. The method as described in claim 9, wherein the microvia structure has a lateral dimension between about 2 µm and about 10 µm.

16. The method as claimed in claim 9, wherein the microvia structure has a first lateral dimension between about 2 µm and about 15 µm, and a second lateral dimension between about 1 µm and about 8.5 µm.

17. A method for forming a microvia structure in a semiconductor device, comprising the steps of: laminating a dielectric layer over a conductive layer of the semiconductor device, wherein the semiconductor device comprises: One substrate; An insulating layer is provided above the substrate; The conductive layer is deposited over the insulating layer; a chromium masking layer is deposited over the dielectric layer; a resist layer is applied, patterned, and developed over the chromium masking layer, wherein the development step of the resist layer forms a trench in the resist layer, the trench corresponding to a desired lateral dimension of the microvia structure; the chromium masking layer is selectively etched via the trench in the developed resist layer, wherein the selective etching step of the chromium masking layer extends the trench into the chromium masking layer and exposes a portion of the dielectric layer; the exposed portion of the dielectric layer is laser-ablated using an ultraviolet (UV) laser in a pulsed burst mode, wherein the pulsed burst mode provides a pulse at a frequency of 50 MHz or higher and an energy between 5 nJ and 10 nJ, wherein the laser ablation step of the exposed portion of the dielectric layer forms the microvia structure having the desired lateral dimension therein, and wherein the conductive layer of the semiconductor element serves as a laser stop. Remove the resist layer from the chromium masking layer; expose the microvia structure to a cleaning process to remove debris from the microvia structure, wherein the cleaning process includes a dry fluorine-based plasma etching and a methanol-based wet cleaning; and selectively remove the chromium masking layer from the dielectric layer by a wet etching process.

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