Image sensing device

Abstract

This application relates to an image sensing device. An image sensing device may include: a substrate having a first surface on which light is incident and a second surface facing the first surface; a plurality of detection structures, each of the plurality of detection structures including a control node configured to exhibit a conductivity type and generate a potential gradient in the substrate, and a detection node configured to capture photocharge generated in response to incident light and migrated in response to the potential gradient; and a first well region configured to adjoin the control nodes of the plurality of detection structures and containing impurities having a conductivity type different from that of the control nodes.

Description

Technical Field

[0001] Various embodiments generally relate to an image sensing device for sensing the distance to a target object. Prior Technology

[0002] Image sensing devices are devices used to capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react with light. With the development of the automotive, medical, computer, and communications industries, the demand for high-performance image sensing devices is increasing in various fields such as smartphones, digital cameras, game consoles, IoT (Internet of Things), robotics, security cameras, and medical miniature cameras.

[0003] Image sensing devices can be broadly categorized into CCD (Charge-Coupled Device) image sensing devices and CMOS (Complementary Metal-Oxide-Semiconductor) image sensing devices. Compared to CMOS image sensing devices, CCD image sensing devices offer better image quality, but they tend to consume more power and are larger. CMOS image sensing devices are smaller and consume less power than CCD image sensing devices. Furthermore, CMOS sensors are manufactured using CMOS fabrication technology, allowing photosensitive elements and other signal processing circuitry to be integrated onto a single chip, enabling the low-cost production of miniaturized image sensing devices. For these reasons, CMOS image sensing devices are being developed for many applications, including mobile devices. Summary of the Invention

[0004] Various embodiments relate to image sensing devices that include ToF pixels capable of reducing unnecessary power consumption.

[0005] The technical problems disclosed herein are not limited to those described above, and those skilled in the art will clearly understand, based on the following description, other technical problems not mentioned herein.

[0006] In an embodiment, an image sensing device may include: a substrate having a first surface on which light is incident and a second surface facing the first surface; a plurality of detection structures, each of the plurality of detection structures including a control node configured to exhibit a conductivity type and generate a potential gradient in the substrate, and a detection node configured to capture photocharge generated in response to incident light and migrated in response to the potential gradient; and a first well region configured to be adjacent to the control nodes of the plurality of detection structures and containing impurities having a conductivity type different from that of the control nodes.

[0007] In an embodiment, an image sensing device may include: a detection structure disposed in a pixel and configured to generate a potential gradient in a substrate and capture photocharge generated by incident light and migrated through the potential gradient; a first well region disposed adjacent to the detection structure and including impurities having a first conductivity type; a pixel transistor region disposed along the edge of the pixel and including a pixel transistor configured to convert the captured photocharge into a pixel signal; an STI region including a trench disposed between the pixel transistor region and each detection structure; and one or more bunker regions disposed in the STI region without trenches.

[0008] According to this embodiment, the image sensing device can improve the performance of ToF pixels while reducing the power consumption of ToF pixels.

[0009] In addition, various effects can be provided that can be understood directly or indirectly through this document. Simple Explanation of the Diagram

[0010] Figure 1 is a configuration diagram that schematically illustrates the configuration of an image sensing device according to an embodiment. Figure 2 is a simplified illustration of the pixel layout shown in Figure 1. Figure 3 is the circuit diagram of the pixel shown in Figure 2. Figure 4 is an example of a cross-section obtained by cutting pixels along the first or second cutting line of Figure 2. Figure 5 is a diagram illustrating the photocharge flowing across the cross-section of a pixel during the first time period. Figure 6 is a diagram illustrating the photocharge flowing across the cross-section of a pixel during the second time period. Figure 7 is an example of a cross-section obtained by cutting pixels along the fifth or sixth cutting line of Figure 2. Figure 8 is a diagram illustrating the hole flow through pixels arranged in a matrix during the first time period. Figure 9 is a diagram illustrating the hole flow through pixels arranged in a matrix during the second time period. Implementation

[0011] In the following description, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0012] The demand for methods to measure depth using image sensors is rapidly increasing across various fields, including security devices, medical devices, vehicles, gaming consoles, VR / AR, and mobile devices. Representative examples of methods for depth measurement include triangulation, Time-of-Flight (ToF), and interferometry. Among these methods, ToF stands out for its wide applicability, high processing speed, and low implementation cost. Therefore, the importance of ToF methods is rising.

[0013] Time-of-Flight (ToF) methods can be broadly categorized into direct methods, which measure distance by directly calculating the round-trip time, and indirect methods, which measure distance using phase differences, based on the common principle of measuring distance using emitted and reflected light. Direct methods are suitable for long distances and are commonly used in vehicles. Indirect methods, suitable for short distances, are used in game consoles or mobile cameras that require high processing speeds. Indirect methods require simpler circuitry and less memory, and can be implemented at a relatively low cost.

[0014] CAPD (Current-Assisted Photonic Demodulator) pixels, as one type of pixel operated via an indirect Time-of-Flight (ToF) method, apply a substrate voltage and use a majority current based on the potential difference of the electric field to detect electrons generated within the pixel. Because CAPD pixels use a majority current, they can detect electrons rapidly. Furthermore, since CAPD pixels can even detect electrons formed deep within the light-incident surface, they can be considered to possess excellent efficiency.

[0015] Figure 1 is a configuration diagram that schematically illustrates the configuration of an image sensing device according to an embodiment.

[0016] Referring to Figure 1, the image sensing device ISD can use a Time-of-Flight (ToF) method to measure the distance to a target object 1. ToF methods can be divided into direct ToF methods and indirect ToF methods. A direct ToF method refers to measuring the distance to the target object 1 by emitting light towards it and measuring the time of flight (ToF) of the light traveling from the ISD's light source to the target object 1 and back, as the reflected light from the target object reaches the ISD. This distance is half the speed of light multiplied by the ToF. An indirect ToF method refers to emitting modulated light towards the target object 1, sensing the light reflected and incident from the target object 1, and indirectly measuring the distance between the image sensing device ISD and the target object 1 based on the phase difference between the modulated and reflected light. In this embodiment, the case where the image sensing device ISD uses an indirect ToF method will be described as an example. However, the scope of this embodiment is not limited to this. Furthermore, the target object 1 can refer not only to a single object but also to a scene captured by the image sensing device ISD.

[0017] An image sensing device (ISD) may include a light source 10, a lens module 20, a pixel array 30, and a control block 40.

[0018] Light source 10 emits light onto target object 1 in response to a light modulation signal (MLS) provided from control block 40. Examples of light source 10 may include LD (laser diode) or LED (light-emitting diode), NIR (near-infrared laser), point light source, monochromatic illumination source, and combinations of other laser sources. LD or LED emits light in a specific wavelength band (e.g., near-infrared, infrared, or visible light), while monochromatic illumination sources are configured by combining white lamps and monochromators. For example, light source 10 may emit infrared light with wavelengths from 800 nm to 1000 nm. The light emitted from light source 10 may be light modulated at a predetermined frequency. For ease of description, only one light source 10 is illustrated in Figure 1, but multiple light sources may be arranged around lens module 20.

[0019] Lens module 20 can collect light reflected from target object 1 and focus the collected light onto pixels PX of pixel array 30. For example, lens module 20 may include a focusing lens or cylindrical optical element with a glass or plastic surface. Lens module 20 may include multiple lenses aligned with the optical axis.

[0020] The pixel array 30 may include a plurality of unit pixels PX arranged in a 2D matrix, for example, a plurality of unit pixels PX arranged in the column direction and the row direction. The unit pixels PX may be formed in a semiconductor substrate, and each unit pixel PX can convert light incident through the lens module 20 into an electrical signal corresponding to the intensity of the light, and output the electrical signal as a pixel signal. In this case, the pixel signal may be a signal indicating the distance to the target object 1. For example, each unit pixel PX may be a CAPD (Current Assisted Photonic Demodulator) pixel or a QEM (Quantum Efficiency Modulation) pixel. In this embodiment, a CAPD pixel will be described as an example. However, the essentially the same technical concept as in this embodiment can be applied to QEM pixels or other types of pixels. The structure and operation of the unit pixel PX will be described in more detail below with reference to FIG2 and the following.

[0021] The control block 40 can control the light source 10 to emit light onto the target object 1, and drive the unit pixels PX of the pixel array 30 to process the pixel signal corresponding to the light reflected from the target object 1, thereby measuring the distance to the surface of the target object 1.

[0022] Such a control block 40 may include a line driver 41, a demodulation driver 42, a light source driver 43, a timing controller (T / C) 44, and a readout circuit 45.

[0023] The line driver 41 and the demodulation driver 42 can be collectively referred to as the control circuit.

[0024] The control circuit can drive the unit pixels PX of the pixel array 30 in response to the timing signal output from the timing controller 44.

[0025] The control circuitry can generate control signals capable of selecting and controlling one or more row lines among a plurality of row lines of the pixel array 30. Such control signals may include demodulation control signals for generating pixel current within the substrate, reset signals for controlling the reset transistor, transmission signals for controlling the transfer of photocharge generated and accumulated in the detection node in response to incident light, floating diffusion signals for providing additional capacitance under high illumination conditions, and selection signals for controlling the selection transistor. Pixel current may indicate or be related to the current associated with or related to the migration of photocharge generated in the substrate toward the detection node.

[0026] The line driver 41 can generate a reset signal, a transmission signal, a floating diffusion signal, and a selection signal, and the demodulation driver 42 can generate a demodulation control signal. In this embodiment, the line driver 41 and the demodulation driver 42 are configured as independent circuit elements. However, in another embodiment, the line driver 41 and the demodulation driver 42 can be configured as a single circuit element and disposed on one side of the pixel array 30.

[0027] The light source driver 43 can generate an optical modulation signal MLS capable of driving the light source 10 under the control of the timing controller 44. The optical modulation signal MLS can be a signal modulated at a predetermined frequency, such that the output light from the light source 10 is modulated at the predetermined frequency.

[0028] The timing controller 44 can generate timing signals for controlling the operation of the line driver 41, demodulation driver 42, light source driver 43, and readout circuit 45.

[0029] Under the control of the timing controller 44, the readout circuit 45 can generate pixel data in digital signal form by processing the pixel signals output from the pixel array 30. For this operation, the readout circuit 45 may include a CDS (Correlated Double Sampler) for performing correlated double sampling on the pixel signals output from the pixel array 30. The readout circuit 45 may include an analog-to-digital converter for converting the output signal from the CDS into a digital signal. Furthermore, the readout circuit 45 may include a buffer circuit that temporarily stores the pixel data output from the analog-to-digital converter under the control of the timing controller 44 and outputs the pixel data externally. Since the pixel array 30 is composed of CAPD pixels, each column of the pixel array 30 may include two column lines for transmitting pixel signals, and elements for processing the pixel signals output from the column lines may also be provided for each column line.

[0030] Light source 10 can emit light modulated at a predetermined frequency toward a scene captured by image sensing device ISD, and image sensing device ISD can sense the modulated light (i.e., incident light) reflected from target object 1 within the scene, and generate depth information on each unit pixel PX. Depending on the distance between image sensing device ISD and target object 1, the modulated light and incident light have a time delay present therebetween. This time delay manifests as the phase difference between the signal generated by image sensing device ISD and the light modulation signal MLS used to control light source 10. Image processor (not shown) can generate a depth image containing depth information on each unit pixel PX by calculating the phase difference appearing in the signal output from image sensing device ISD.

[0031] Figure 2 is an example of the pixel layout shown in Figure 1.

[0032] Referring to Figure 2, pixel 200 can be any of the pixels PX shown in Figure 1. Although Figure 2 shows a schematic diagram of a single pixel 200, the same or similar structures and operations can be applied to any pixel included in the pixel array 30.

[0033] Pixel 200 may include a first tap TA1, a second tap TB2, a third tap TB3, a fourth tap TA4, a pilot well region GW, a potential control region PC, a pixel transistor region PTA, first voltage stabilization regions VS1 to fourth voltage stabilization regions VS4, a shallow trench isolation (STI) region STI, and first well shelter regions WBA1 to fourth well shelter regions WBA4. In this embodiment, the case where one pixel 200 includes four taps TA1, TB2, TB3, and TA4 is described as an example. However, the number of taps included in pixel 200 is not limited to four, and other embodiments are also feasible. Therefore, one pixel 200 may include three or fewer taps or five or more taps. In this case, multiple taps can receive the same or different types of demodulation control signals. Different types of demodulation control signals can indicate demodulation control signals received at different timings.

[0034] Taps TA1 and TA4 can be defined as a first tap group receiving the same demodulation control signal, while taps TB2 and TB3 can be defined as a second tap group receiving the same demodulation control signal. The first and second tap groups can receive different demodulation control signals. The demodulation control signal received by the first tap group can be defined as the first demodulation control signal, and the demodulation control signal received by the second tap group can be defined as the second demodulation control signal.

[0035] First taps TA1 and fourth taps TA4 can be positioned on either side of the center of pixel 200 along a first diagonal direction, while second taps TB2 and third taps TB3 can be positioned on either side of the center of pixel 200 along a second diagonal direction. The first diagonal direction indicates the direction of the line AA′ passing through the first vertex located at the upper left of pixel 200 and the fourth vertex located at the lower right of pixel 200, and the second diagonal direction indicates the direction of the line BB′ passing through the second vertex located at the upper right of pixel 200 and the third vertex located at the lower left of pixel 200. Therefore, first taps TA1 and fourth taps TA4 can be positioned facing each other relative to the center of pixel 200 in the first diagonal direction, and second taps TB2 and third taps TB3 can be positioned facing each other relative to the center of the pixel in the second diagonal direction.

[0036] The first tap TA1 may include a first control node CA1, a first detection node DA1, and a first bottom well area BW1.

[0037] Figure 2 illustrates a first control node CA1 with a rectangular shape, and a first detection node DA1 surrounding the upper and left sides of the first control node CA1, but the scope of this embodiment is not limited thereto. In the example shown in Figure 2, the first detection node DA1 spans a larger area surrounding the first control node CA1, which makes it easier for the first detection node DA1 to capture signal carriers migrating along the potential gradient formed by the first control node CA1. The potential described in this disclosure can indicate the potential.

[0038] The first bottom well area BW1 can be configured to overlap with the first control node CA1 and the first detection node DA1, and have a larger area than the first control node CA1. The first bottom well area BW1 can be perpendicularly spaced from the first control node CA1 and the first detection node DA1, and the guide well area GW can be located between the first control node CA1 and the first detection node DA1 and the first bottom well area BW1.

[0039] In one embodiment, the first control node CA1 and the first detection node DA1 can be configured to be adjacent to each other and physically isolated from each other by reverse doping through junction isolation.

[0040] According to another embodiment, the first control node CA1 and the first detection node DA1 can be separated from each other by a predetermined distance, and insulating material can be disposed between the first control node CA1 and the first detection node DA1.

[0041] The second tap TB2 may include the second control node CB2, the second detection node DB2, and the second bottom well area BW2.

[0042] Figure 2 illustrates a rectangular shape for the second control node CB2, with the second detection node DB2 surrounding the upper and right sides of the second control node CB2; however, the scope of this disclosure is not limited thereto. In the example shown in Figure 2, the second detection node DB2 spans a larger area surrounding the second control node CB2, which makes it easier for the second detection node DB2 to capture signal carriers migrating according to the potential gradient formed by the second control node CB2.

[0043] The second bottom well zone BW2 can be configured to overlap with the second control node CB2 and the second detection node DB2, and have a larger area than the second control node CB2. The second bottom well zone BW2 can be perpendicularly spaced from the second control node CB2 and the second detection node DB2, and the guide well zone GW can be located between the second control node CB2, the second detection node DB2, and the second bottom well zone BW2.

[0044] The arrangement and structure of the second control node CB2, the second detection node DB2, and the second bottom well area BW2 can correspond to the arrangement and structure of the first control node CA1, the first detection node DA1, and the first bottom well area BW1. Therefore, this paper will omit the repeated description.

[0045] Except that the third tap TB3 and the second tap TB2 are located in different positions, and the third detection node DB3 surrounds the lower and left sides of the third control node CB3, the arrangement shape and structure of the third tap TB3 are basically the same as those of the second tap TB2. Therefore, this paper will omit its repeated description.

[0046] Except that the fourth tap TA4 is located in a different position from the first tap TA1, and the fourth detection node DA4 surrounds the lower and right sides of the fourth control node CA4, the arrangement shape and structure of the fourth tap TA4 are basically the same as those of the first tap TA1. Therefore, this paper will omit its repeated description.

[0047] The pilot well region GW can be configured to overlap with at least a portion of each of the first to fourth detection nodes DA1, DB2, DB3, and DA4, and at least a portion of each of the first to fourth bottom well regions BW1 to BW4, while surrounding the first to fourth control nodes CA1, CB2, CB3, and CA4. The pilot well region GW can be doped with impurities having a conductivity type different from that of the first to fourth control nodes CA1, CB2, CB3, and CA4, and is electrically floating.

[0048] Because the pilot well region GW is configured to be adjacent to each of the first to fourth control nodes CA1, CB2, CB3, and CA4, and each of the first to fourth bottom well regions BW1 to BW4, the pilot well region GW can include a depletion region formed by a PN junction. The potential of the depletion region adjacent to each of the first to fourth control nodes CA1, CB2, CB3, and CA4 can be controlled according to the voltage applied to each of the first to fourth control nodes CA1, CB2, CB3, and CA4 (i.e., a first demodulation control signal or a second demodulation control signal). For example, suppose an active voltage is applied to the first control node CA1 and the fourth control node CA4, and an inactive voltage is applied to the second control node CB2 and the third control node CB3. In this case, the depletion region adjacent to each of the first control node CA1 and the fourth control node CA4 has a momentary rise to maintain the potential of the PN junction, and the depletion region adjacent to each of the second control node CB2 and the third control node CB3 has a relatively low potential. Therefore, the photocharge generated in the substrate in response to the incident light can migrate through the depletion region adjacent to the first control node CA1 and the fourth control node CA4 with a high potential, and be captured by the first detection node DA1 and the fourth detection node DA4.

[0049] Therefore, the pilot well region GW can provide a potential gradient, allowing photocharge generated in the substrate in response to incident light to migrate to the corresponding detection node. According to this embodiment, it is not necessary to generate a separate current (e.g., hole current) to facilitate signal carrier migration. The potential of the depletion region can be instantaneously controlled to perform demodulation operations at high speed without wasting power. Therefore, this embodiment allows well-based optical modulation, which captures photocharge generated from modulated light by adjusting the potential of the floating pilot well region GW.

[0050] Because the interior of the pilot well region GW is mostly filled with depletion regions formed by the PN junctions with taps TA1, TB2, TB3, and TA4, hole current hardly flows between the activated and non-activated taps within the pilot well region GW due to the absence of charge carriers (i.e., holes and electrons). In this embodiment, it is assumed that there is no hole current (or almost zero hole current) flowing between the activated and non-activated taps.

[0051] The pilot well region GW may include well openings WO that do not overlap with the first bottom well regions BW1 to the fourth bottom well regions BW4. The well openings WO that are not provided in the first bottom well regions BW1 to the fourth bottom well regions BW4 may correspond to the paths that introduce photocharge from the substrate into the pilot well region GW.

[0052] The well opening WO can be set to overlap with the potential control area PC, and the potential of the guide well area GW corresponding to the well opening WO can be controlled according to the voltage applied to the potential control area PC. The potential control area PC can be set in the center of pixel 200 or in the center of the first to fourth taps TA1, TB2, TB3 and TA4.

[0053] The potential of the potential control area PC can be controlled by a potential control voltage generated by the line driver 41 or the demodulation driver 42. The absolute value of the potential control voltage can be less than the absolute value of the active voltage of the first demodulation control signal and the second demodulation control signal and greater than the absolute value of their inactive voltage. While assuming the active and inactive voltages have the same polarity, the potential control voltage can have a polarity opposite to that of the active and inactive voltages. According to an embodiment, the potential control voltage can have an absolute value corresponding to the average voltage of the active and inactive voltages (e.g., 0.6V). To reduce unnecessary power consumption, the potential control area PC can receive the potential control voltage only during the period when pixel 200 is operated.

[0054] As a potential control voltage is applied to the potential control region PC, a potential gradient is formed in the PC, allowing photocharge to easily migrate toward the first to fourth taps TA1, TB2, TB3, and TA4. For example, when an active voltage is applied to the first tap TA1 and the fourth tap TA4, and an inactive voltage is applied to the second tap TB2 and the third tap TB3, the guide well region GW adjacent to the first tap TA1 and the fourth tap TA4 can have the highest potential, the guide well region GW adjacent to the second tap TB2 and the third tap TB3 can have the lowest potential, and the guide well region GW corresponding to the well opening WO can have an intermediate potential. Therefore, the photocharge generated in the substrate is introduced into the well opening WO and can be easily captured after migrating to the first tap TA1 and the fourth tap TA4 by the potential gradient formed by the potential control region PC.

[0055] The pixel transistor region (PTA) can be configured in a shape surrounding the area where the first to fourth taps TA1, TB2, TB3, and TA4 are located. The PTA may include pixel transistors (TX1, RX1, BX1, SF1, and SX1 in FIG. 3) for processing photocharge captured by the first tap TA1 and the fourth tap TA4 corresponding to the first tap group, and pixel transistors (TX2, RX2, BX2, SF2, and SX2 in FIG. 3) for processing photocharge captured by the second tap TB2 and the third tap TB3 corresponding to the second tap group. According to an embodiment, the pixel transistors included in the PTA may be arranged in a row along the boundary between adjacent pixels. However, the scope of this disclosure is not limited thereto.

[0056] The first voltage stabilization region VS1 to the fourth voltage stabilization region VS4 can be set at the first vertex to the fourth vertex of pixel 200, respectively.

[0057] Each transistor included in the pixel transistor region PTA may include: a gate configured as a gate electrode, disposed on a dielectric layer formed on one surface of the substrate; a source and a drain configured as impurity regions, disposed on both sides of the gate electrode in the substrate; and a channel region corresponding to the lower region of the gate electrode in the substrate. The source and drain may be surrounded by P-wells doped with a predetermined concentration of P-type impurities, and the P-wells may even extend and be disposed in the lower region of the gate electrode. The P-wells may also extend to the bottom of the first voltage stabilization regions VS1 to the fourth voltage stabilization regions VS4, and surround the first voltage stabilization regions VS1 to the fourth voltage stabilization regions VS4 while being adjacent to them. In other words, the P-wells surrounding the voltage stabilization regions may extend to the bottom of the pixel transistors adjacent to each other.

[0058] The first voltage stabilization region VS1 to the fourth voltage stabilization region VS4 can be P+ impurity regions in the substrate that are doped with a higher concentration than P-wells.

[0059] The first voltage stabilization region VS1 to the fourth voltage stabilization region VS4 can receive a specific voltage (e.g., ground voltage) and clamp the voltage of the P-wells adjacent to the first voltage stabilization region VS1 to the fourth voltage stabilization region VS4 to the specific voltage. The specific voltage can indicate an inactive voltage (or ground voltage). The P-wells can be located below the pixel transistor region PTA and form the body of each pixel transistor, and the voltage of the P-wells can affect the threshold voltage of each pixel transistor. The first voltage stabilization region VS1 to the fourth voltage stabilization region VS4 can provide the body voltage of the pixel transistors, thereby ensuring stable operation of the pixel transistors included in the pixel transistor region PTA.

[0060] The voltage-stabilized regions included in the pixel array 30 can be electrically coupled to each other in a grid pattern. Such coupling can prevent the ground voltage from being improperly supplied to a specific voltage-stabilized region due to the IR voltage drop of the signal line used to provide the ground voltage.

[0061] The STI region can be configured to surround the area where the first to fourth taps TA1, TB2, TB3, and TA4 are located, and is surrounded by the pixel transistor region PTA. In other words, the STI region can be located between the pixel transistor region PTA and the area where the first to fourth taps TA1, TB2, TB3, and TA4 are located, so as to isolate the two regions from each other.

[0062] STI regions can include dielectric layers formed by filling trenches (or STI structures) with a dielectric material through gaps, the trenches being formed via an STI process. For example, the dielectric material can include one or more of silicon oxynitride (SixOyNz), silicon oxide (SixOy), and silicon nitride (SixNy), where x, y, and z are natural numbers. The trenches in the STI regions can be formed by etching the substrate to such that the trenches have a predetermined depth from one surface of the substrate (e.g., the front surface).

[0063] The first well shelter area WBA1 to the fourth well shelter area WBA4 can each have an L-shape. The first well shelter area WBA1 to the fourth well shelter area WBA4 can be located within the STI zone, extending along the corresponding side of the STI zone, and positioned at the corresponding corner where the STI zone intersects with the first diagonal direction or the second diagonal direction. In other words, the first well shelter area WBA1 to the fourth well shelter area WBA4 can be respectively located between the first voltage stabilization zone VS1 to the fourth voltage stabilization zone VS4 and the first tap to the fourth tap TA1, TB2, TB3, and TA4.

[0064] Each of the first wellbore shelter areas WBA1 to the fourth wellbore shelter area WBA4 may exclude (or omit) the area from which the STI process used to form the STI area STI is performed. Therefore, each of the first wellbore shelter areas WBA1 to the fourth wellbore shelter area WBA4 may not include trenches (or STI structures) or dielectric layers. Therefore, the STI areas STIs adjacent vertically or horizontally to each of the first wellbore shelter areas WBA1 to the fourth wellbore shelter area WBA4 can be isolated (disconnected) through the corresponding wellbore shelter area.

[0065] Between two adjacent well shelter zones, from the first well shelter zone WBA1 to the fourth well shelter zone WBA4, a shelter disconnection zone can be established. Therefore, the first shelter disconnection zone BDA1 can be located between the first well shelter zone WBA1 and the fourth well shelter zone WBA4; the second shelter disconnection zone BDA2 can be located between the first well shelter zone WBA1 and the second well shelter zone WBA2; the third shelter disconnection zone BDA3 can be located between the second well shelter zone WBA2 and the third well shelter zone WBA3; and the fourth shelter disconnection zone BDA4 can be located between the third well shelter zone WBA3 and the fourth well shelter zone WBA4.

[0066] Each of the first shelter disconnection zones BDA1 to the fourth shelter disconnection zone BDA4, corresponding to a portion of the STI zone, may include trenches (or STI structures) and dielectric layers, similar to the STI zone. Each of the first shelter disconnection zones BDA1 to the fourth shelter disconnection zone BDA4 may be configured to disconnect adjacent well shelter zones from each other.

[0067] The bending points from the first well shelter area WBA1 to the fourth well shelter area WBA4 are defined as the first bending point to the fourth bending point, respectively. The length of the first bending point of the first well shelter area WBA1 extending along a first direction (horizontal or row direction) can be greater than the length of the first bending point extending along a second direction (vertical or column direction). The length of the second bending point of the second well shelter area WBA2 extending along a second direction can be greater than the length of the second bending point extending along a first direction. The length of the third bending point of the third well shelter area WBA3 extending along a first direction can be greater than the length of the third bending point extending along a second direction. The length of the fourth bending point of the fourth well shelter area WBA4 extending along a second direction can be greater than the length of the fourth bending point extending along a first direction.

[0068] In some embodiments, the first well shelter area WBA1 and the first well shelter disconnection area BDA1 can be rotated 90 degrees clockwise around pixel 200 and overlap with the second well shelter area WBA2 and the second well shelter disconnection area BDA2, respectively. The second well shelter area WBA2 and the second well shelter disconnection area BDA2 can be rotated 90 degrees clockwise around pixel 200 and overlap with the third well shelter area WBA3 and the third well shelter disconnection area BDA3, respectively. The third well shelter area WBA3 and the third well shelter disconnection area BDA3 can be rotated 90 degrees clockwise around pixel 200 and overlap with the fourth well shelter area WBA4 and the fourth well shelter disconnection area BDA4, respectively. The fourth well shelter area WBA4 and the fourth well shelter disconnection area BDA4 can be rotated 90 degrees clockwise around pixel 200 and overlap with the first well shelter area WBA1 and the first well shelter disconnection area BDA1, respectively.

[0069] Therefore, the first well bunker area WBA1 to the fourth well bunker area WBA4 can be rotated symmetrically about pixel 200.

[0070] The first well shelter area WBA1 to the fourth well shelter area WBA4 can be asymmetrically positioned based on either a first straight line extending in a first direction through the center of pixel 200 or a second straight line extending in a second direction through the center of pixel 200. That is, the first shelter disconnection area BDA1 can be located above the first straight line, while the third shelter disconnection area BDA3, located on the opposite side of the first shelter disconnection area BDA1 relative to the second straight line, can be located below the first straight line. Furthermore, the second shelter disconnection area BDA2 can be located to the right of the second straight line, while the fourth shelter disconnection area BDA4, located on the opposite side of the second shelter disconnection area BDA2 relative to the first straight line, can be located to the left of the second straight line.

[0071] Therefore, the first well bunker area WBA1 to the fourth well bunker area WBA4 can be bilaterally asymmetrical with respect to the first or second straight line.

[0072] Figure 3 is the circuit diagram of the pixel shown in Figure 2.

[0073] Referring to Figure 3, pixel 300 has a configuration obtained by illustrating pixel 200 of Figure 2 as a circuit diagram. Pixel 300 may generally include a photoelectric conversion region 310 and a circuit region 320.

[0074] The photoelectric conversion region 310 may include a photoelectric conversion element PD and a first variable resistor VR1 to a fourth variable resistor VR4.

[0075] Photoelectric conversion element (PD) can generate and accumulate photocharge corresponding to the intensity of incident light.

[0076] As described above, the first to fourth taps, TA1, TB2, TB3, and TA4, can be formed in the substrate. With light incident, photocharge corresponding to the intensity of the incident light can be generated and accumulated in the substrate. In other words, the photoelectric conversion element PD can correspond to the region in the substrate where photocharge is generated by incident light.

[0077] One side of the photoelectric conversion element PD can be coupled to the first variable resistor VR1 to the fourth variable resistor VR4, and the other side of the photoelectric conversion element PD can receive the substrate voltage Vsub. The substrate voltage Vsub can be the substrate voltage applied to the surface doped region 404, which will be described with reference to FIG4.

[0078] A first variable resistor VR1 can be coupled between one side of the photoelectric conversion element PD and the first common node CN1. The first variable resistor VR1 can transfer the accumulated photocharge in the photoelectric conversion element PD to the first common node CN1 in response to a first demodulation control signal DCS1. The first demodulation control signal DCS1 can have an active voltage (e.g., 1.2 V) and an inactive voltage (e.g., 0 V).

[0079] When the first demodulation control signal DCS1 has an active voltage, the first variable resistor VR1 can have a relatively low resistance, allowing the photocharge accumulated in the photoelectric conversion element PD to be transferred to the first common node CN1. When the first demodulation control signal DCS1 has an inactive voltage, the first variable resistor VR1 can have a relatively high resistance, preventing the photocharge accumulated in the photoelectric conversion element PD from being transferred to the first common node CN1.

[0080] A second variable resistor VR2 can be coupled to one side of the photoelectric conversion element PD and between the second common node CN2. The second variable resistor VR2 can transfer the accumulated photocharge in the photoelectric conversion element PD to the second common node CN2 in response to a second demodulation control signal DCS2. The second demodulation control signal DCS2 can have an active voltage (e.g., 1.2 V) and an inactive voltage (e.g., 0 V).

[0081] When the second demodulation control signal DCS2 has an active voltage, the second variable resistor VR2 can have a relatively low resistance, allowing the photocharge accumulated in the photoelectric conversion element PD to be transferred to the second common node CN2. When the second demodulation control signal DCS2 has an inactive voltage, the second variable resistor VR2 can have a relatively high resistance, preventing the photocharge accumulated in the photoelectric conversion element PD from being transferred to the second common node CN2.

[0082] The third variable resistor VR3 can be coupled in parallel with the second variable resistor VR2 on one side of the photoelectric conversion element PD and between the second common node CN2, and in response to the second demodulation control signal DCS2, it transfers the photocharge accumulated in the photoelectric conversion element PD to the second common node CN2. Since the operation of the third variable resistor VR3 is performed in essentially the same way as the operation of the second variable resistor VR2, its repeated description will be omitted here.

[0083] The fourth variable resistor VR4 can be coupled in parallel with the first variable resistor VR1 between one side of the photoelectric conversion element PD and the first common node CN1, and in response to the first demodulation control signal DCS1, it transfers the photocharge accumulated in the photoelectric conversion element PD to the first common node CN1. Since the operation of the fourth variable resistor VR4 is performed in essentially the same way as the operation of the first variable resistor VR1, its repeated description will be omitted here.

[0084] The first variable resistor VR1 to the fourth variable resistor VR4 can respectively correspond to the components configured by modeling the first tap to the fourth tap TA1, TB2, TB3 and TA4 as circuit elements.

[0085] The actual operation of the first to fourth taps, TA1, TB2, TB3 and TA4, will be described below. Since the operation of the third tap TB3 and the fourth tap TA4 correspond to the operation of the second tap TB2 and the first tap TA1, respectively, the following description will focus on the operation of the first tap TA1 and the second tap TB2.

[0086] The first tap TA1 may include a first control node CA1 and a first detection node DA1, while the second tap TB2 may include a second control node CB2 and a second detection node DB2.

[0087] The first control node CA1 and the second control node CB2, as well as the first detection node DA1 and the second detection node DB2, can be formed in the substrate. Based on the dopant used for doping, such control nodes can be doped to exhibit either N-type or P-type conductivity. For example, the substrate can be a P-type semiconductor substrate, and the first control node CA1 and the second control node CB2 can be P-type impurity regions doped with one or more P-type impurity materials, while the first detection node DA1 and the second detection node DB2 can be N-type impurity regions doped with one or more N-type impurity materials. In this embodiment, P-type can be defined as the first conductivity type, and N-type can be defined as the second conductivity type.

[0088] The first control node CA1 and the second control node CB2 can be configured to be adjacent to the pilot well region GW, and the pilot well region GW can be an N-type impurity region. That is, the first control node CA1 and the second control node CB2, each forming a P-type impurity region, can each form a PN junction between their respective control nodes and the pilot well region GW, which is formed as an N-type impurity region. Therefore, the pilot well region GW can include depletion regions adjacent to the first control node CA1 and the second control node CB2, respectively.

[0089] The first control node CA1 and the second control node CB2 can receive the first demodulation control signal DCS1 and the second demodulation control signal DCS2 from the demodulation driver 42, respectively. The potential difference between the first demodulation control signal DCS1 and the second demodulation control signal DCS2 generates a potential gradient to control the flow of photocharge, which is a signal carrier generated by the incident light in the substrate. When the potential of the first demodulation control signal DCS1 is higher than the potential of the second demodulation control signal DCS2, the potential difference between them forms a potential gradient that decreases from the first control node CA1 towards the second control node CB2. When the potential of the first demodulation control signal DCS1 is lower than the potential of the second demodulation control signal DCS2, the potential difference between them forms a potential gradient that decreases from the second control node CB2 towards the first control node CA1.

[0090] Each of the first detection node DA1 and the second detection node DB2 can perform the function of capturing and accumulating photocharges that migrate from the low potential region to the high potential region along the potential gradient.

[0091] According to an embodiment, the photocharge capture operation of the photoelectric conversion region 310 can be performed on a first time period and a second time period, which are consecutive time periods. In this embodiment, the image sensing device operates according to a two-phase demodulation method in which the first to fourth taps TA1, TB2, TB3, and TA4 use two demodulation control signals. In another embodiment, the image sensing device can operate according to a four-phase demodulation method in which the first to fourth taps TA1, TB2, TB3, and TA4 use four demodulation control signals.

[0092] During the first time period, light incident on pixel 300 can be photoelectrically converted according to the photoelectric effect, generating electron-hole pairs corresponding to the intensity of the incident light. In this embodiment, the electrons generated in response to the intensity of the incident light can indicate photocharge. At this time, demodulation driver 42 can apply a first demodulation control signal DCS1 to the first control node CA1 and a second demodulation control signal DCS2 to the second control node CB2. The voltage of the first demodulation control signal DCS1 can be higher than the voltage of the second demodulation control signal DCS2. Therefore, the first demodulation control signal DCS1 can be set to an active voltage (e.g., 1.2 V), and the second demodulation control signal DCS2 can be set to an inactive voltage (e.g., 0 V).

[0093] The voltage difference between the voltage of the first demodulation control signal DCS1 and the voltage of the second demodulation control signal DCS2 can form a potential gradient that increases towards the first control node CA1. Therefore, electrons in the substrate migrate towards the first control node CA1.

[0094] Electrons can be generated in the substrate in response to the luminescence intensity of the incident light, and these generated electrons can migrate toward the first control node CA1 and be captured by the first detection node DA1 adjacent to the first control node CA1. Therefore, electrons in the substrate can be used as signal carriers for detecting the luminescence intensity of the incident light.

[0095] In the second time period following the first time period, light incident on pixel 300 can be photoelectrically converted according to the photoelectric effect, generating electron-hole pairs corresponding to the intensity of the incident light. At this time, demodulation driver 42 can apply a first demodulation control signal DCS1 to the first control node CA1 and a second demodulation control signal DCS2 to the second control node CB2. The voltage of the first demodulation control signal DCS1 can be lower than the voltage of the second demodulation control signal DCS2. At this time, the voltage of the first demodulation control signal DCS1 can be an inactive voltage (e.g., 0 V), and the voltage of the second demodulation control signal DCS2 can be an active voltage (e.g., 1.2 V).

[0096] The voltage difference between the voltage of the first demodulation control signal DCS1 and the voltage of the second demodulation control signal DCS2 can form a potential gradient that increases towards the second control node CB2. Therefore, electrons in the substrate migrate towards the second control node CB2.

[0097] Therefore, electrons can be generated within the substrate in response to the luminescence intensity of the incident light, and these generated electrons can migrate toward the second control node CB2 and be captured by the second detection node DB2 adjacent to the second control node CB2. Thus, the electrons within the substrate can be used as signal carriers for detecting the luminescence intensity of the incident light.

[0098] According to the embodiment, the order of the first time period and the second time period can be changed.

[0099] During the first time period when a first demodulation control signal DCS1 with an active voltage is applied to the first tap TA1 and the fourth tap TA4, and a second demodulation control signal DCS2 with an inactive voltage is applied to the second tap TB2 and the third tap TB3, the photocharge generated in the substrate can be captured by the first tap TA1 and the fourth tap TA4 and accumulated in the first common node CN1. The first detection node DA1 and the fourth detection node DA4 can be electrically coupled to each other to form a first common node CN1.

[0100] During the second time period, when a first demodulation control signal DCS1 with an inactive voltage is applied to the first tap TA1 and the fourth tap TA4, and a second demodulation control signal DCS2 with an active voltage is applied to the second tap TB2 and the third tap TB3, the photocharge generated in the substrate can be captured by the second tap TB2 and the third tap TB3 and accumulated in the second common node CN2. The second detection node DB2 and the third detection node DB3 can be electrically coupled to each other to form a second common node CN2.

[0101] Circuit area 320 may include multiple elements for converting photocharge captured by the first detection nodes through the fourth detection nodes DA1, DB2, DB3, and DA4 into electrical signals by processing the photocharge. Control signals RST1, RST2, TG1, TG2, SEL1, SEL2, and Vbt may be provided to the multiple elements from the row driver 41. The pixel voltage VDD may be the power supply voltage.

[0102] First, elements for processing the photocharge accumulated in the first common node CN1 will be described. Circuit region 320 may include a first reset transistor RX1, a first transfer transistor TX1, a first boost transistor BX1, a first source follower transistor SF1, and a first select transistor SX1.

[0103] The first reset transistor RX1 can be turned on in response to a logic high level of the first reset signal RST1 provided to its gate, and reset the potentials of the first floating diffusion node FD1 and the first common node CN1 to a predetermined level (i.e., pixel voltage VDD). Furthermore, when the first reset transistor RX1 is turned on, the first transmission transistor TX1 can be turned on simultaneously to reset the first common node CN1.

[0104] The first transmission transistor TX1 can be turned on in response to the logic high level of the first transmission signal TG1 provided to its gate, and transfer the photocharge accumulated in the first common node CN1 to the first floating diffusion node FD1.

[0105] The first boost transistor BX1 can provide additional capacitance to the first floating diffusion node FD1 in response to the boost voltage Vbt supplied to its gate. The first boost transistor BS1 can be coupled to the first floating diffusion node FD1 while its source and drain form a node, and thus operate as a capacitive element (e.g., a MOS (metal-oxide-semiconductor) capacitor) and have a capacitance corresponding to the boost voltage Vbt.

[0106] The line driver 41 can adjust the capacitance of the first floating diffusion node FD1 by controlling the boost voltage Vbt according to the luminous intensity of the incident light. Therefore, under high illumination conditions, the first floating diffusion node FD1 can accumulate more photocharge, which ensures a high dynamic range.

[0107] According to another embodiment, the boost voltage Vbt can be kept constant to continuously provide a predetermined capacitance to the first floating diffusion node FD1.

[0108] According to yet another embodiment, the first boost transistor BX1 can be omitted.

[0109] The first source follower transistor SF1 may have a drain coupled to the pixel voltage VDD and a source coupled to the first select transistor SX1, and transmit a current to the first select transistor SX1 corresponding to the potential of the first floating diffusion node FD1 coupled to its gate.

[0110] The first selection transistor SX1 can be turned on in response to the logic high level of the first selection signal SEL1 provided to its gate, and outputs the first pixel output signal OUT1 transmitted from the first source follower transistor SF1. The first pixel output signal OUT1 can be transmitted to the readout circuit 45 via a vertical signal line (not shown) extending in the column direction of the pixel array 30.

[0111] To handle the accumulated photocharge in the second common node CN2, circuit region 320 may include a second reset transistor RX2, a second transmission transistor TX2, a second boost transistor BX2, a second source follower transistor SF2, and a second select transistor SX2. Since the elements used to handle the accumulated photocharge in the second common node CN2 are configured and operate in substantially the same manner as the elements used to handle the accumulated photocharge in the first common node CN1, except for the timing of operation, their repeated description will be omitted herein.

[0112] The first demodulation control signal DCS1 can be completely out of phase with the second demodulation control signal DCS2. For example, the first demodulation control signal DCS1 can have the same phase as the optical modulation signal MLS, while the second demodulation control signal DCS2 can have a 180-degree phase difference with the optical modulation signal MLS. Therefore, the operating timing of the elements RX1, TX1, BX1, SF1, and SX1 used to process the photocharge accumulated in the first common node CN1 in response to the first demodulation control signal DCS1 can be different from the operating timing of the elements RX2, TX2, BX2, SF2, and SX2 used to process the photocharge accumulated in the second common node CN2 in response to the second demodulation control signal DCS2.

[0113] The pixel output signals OUT1 and OUT2 output from circuit area 320 to readout circuit 45 can be converted into image data through noise removal and analog-to-digital conversion.

[0114] The image processor (not shown) can calculate the phase difference with the optical modulation signal MLS by performing operations on image data acquired from the photocharge accumulated in the first common node CN1 and image data acquired from the photocharge accumulated in the second common node CN2, calculate depth information indicating the distance to the target object 1 based on the phase difference corresponding to each pixel, and generate a depth image including the depth information corresponding to each pixel.

[0115] Figure 4 is an example of a cross-section obtained by cutting pixels along the first or second cutting line of Figure 2.

[0116] The cross section 400 shown in Figure 4 can correspond to the cross section obtained by cutting pixel 200 along the first cutting line AA′ or the second cutting line BB′ in Figure 2.

[0117] Section 400 may include a substrate 402, a surface doped region 404, a surface depletion region 406, a first doped region 410, a control electrode 415, a second doped region 420, a detection electrode 425, a first well region 430, a second well region 440, a third well region 445, an STI region 450, a well shield region 455, a third doped region 460, a voltage stabilizing electrode 462, a transistor well region 465, a potential control electrode 470, a potential control dielectric layer 475, and a substrate dielectric layer 480.

[0118] Substrate 402 can be a semiconductor substrate, such as a P-type body substrate, a substrate obtained by growing a P-type epitaxial layer in a P-type body substrate, or a substrate obtained by growing a P-type epitaxial layer in an N-type body substrate. According to another embodiment, substrate 402 can be an N-type body substrate, a substrate obtained by growing an N-type epitaxial layer in a P-type body substrate, or a substrate obtained by growing an N-type epitaxial layer in an N-type body substrate. In this embodiment, it is assumed that substrate 402 corresponds to an N-type epitaxial layer.

[0119] Although Figure 4 illustrates that components 404, 406, 410, 415, 420, 425, 430, 440, 445, 450, 455, 460, 462, and 465 are disposed above substrate 402, substrate 402 disposed below these components can be considered as part of the substrate. Components 404, 406, 410, 415, 420, 425, 430, 440, 445, 450, 455, 460, 462, and 465 are formed in the substrate by separate subsequent processes (e.g., implantation, trenching, etc.), and therefore can be considered as components 404, 406, 410, 415, 420, 425, 430, 440, 445, 450, 455, 460, 462, and 465 being formed in the substrate. In one embodiment, the substrate has a top surface (e.g., the surface adjacent to the first doped region 410) and a bottom surface (e.g., the surface adjacent to the surface doped region 404), and the top and bottom surfaces face each other.

[0120] Surface-doped regions 404 may be disposed in the substrate 402 along the surface of the substrate 402 to which light is incident, and may include P-type impurities having a higher doping concentration than the substrate 402. According to an embodiment, the surface-doped regions 404 may form a potential gradient related to a tap activated by a substrate voltage applied thereto, such that photocharge generated around the surface of the substrate 402 can be detected in the activated tap. For example, the substrate voltage may be a voltage lower than the active voltage, such as an inactive voltage.

[0121] The surface depletion region 406 can be formed by a PN junction between the substrate 402 and the surface doped region 404, since the surface doped region 404 is implanted into the substrate 402. No charge carriers (i.e., holes and electrons) are present in the surface depletion region 406. Although the surface depletion region 406 is designed to be devoid of charge carriers, those skilled in the art will understand that a very small number of charge carriers may still be present for various reasons, and the disclosed technology does not exclude this possibility. The surface depletion region 406 can reduce or prevent hole currents that may flow between the surface doped region 404 and the start-up tap, thereby reducing unnecessary power consumption.

[0122] The first doped region 410 can correspond to the first control node CA1 and the fourth control node CA4 when the cross section 400 corresponds to the first dicing line AA′, and can correspond to the second control node CB2 and the third control node CB3 when the cross section 400 corresponds to the second dicing line BB′. The first doped region 410 can be a region formed by implanting P+ type impurities with a relatively high doping concentration into the substrate 402.

[0123] The control electrode 415 can receive a first demodulation control signal DCS1 or a second demodulation control signal DCS2 from the demodulation driver 42, and transmit the first demodulation control signal DCS1 or the second demodulation control signal DCS2 to the first doped region 410. The control electrode 415 may include a metal or polycrystalline silicon with high conductivity. The control electrode 415 may be formed on one surface of the substrate 402.

[0124] The second doped region 420 can correspond to the first detection node DA1 and the fourth detection node DA4 when the cross section 400 corresponds to the first dicing line AA′, and can correspond to the second detection node DB2 and the third detection node DB3 when the cross section 400 corresponds to the second dicing line BB′. The second doped region 420 can be a region formed by implanting N+ type impurities with a relatively high doping concentration into the substrate 402.

[0125] The detection electrode 425 can transfer the photocharge (i.e., electrons) captured by the second doped region 420 to the first transport transistor TX1 or the second transport transistor TX2. Since the second doped region 420 forms a node, the photocharge accumulated in the second doped region 420 can be output through the detection electrode 425, which is formed as a portion of the second doped region 420. Therefore, the detection electrode 425 does not need to be formed across the entire second doped region 420. In this embodiment, the detection electrode 425 can be formed in the region of the second doped region 420 that overlaps with the first cleaving line AA′ or the second cleaving line BB′. The detection electrode 425 can comprise a highly conductive metal or polycrystalline silicon. The detection electrode 425 can be formed on one surface of the substrate 402.

[0126] The first well area 430 can correspond to the pilot well area GW described with reference to FIG2.

[0127] A first well region 430 may be disposed between the first doped regions 410, thereby adjacent to a surface of the substrate 402, and surrounding the first doped regions 410. Furthermore, the first well region 430 may extend to adjacent to portions of the second doped region 420. Additionally, the first well region 430 may be configured to adjacent to the second well region 440 and the third well region 445 respectively disposed on its bottom and side surfaces. The first well region 430 may extend toward the rear surface of the substrate 402 through an opening region around the center of the pixel 200 where the second well region 440 is not disposed. The extended region of the first well region 430 may be defined as a well opening 435. The well opening 435 may correspond to the well opening WO described with reference to FIG2.

[0128] After the first doped region 410, the second doped region 420, the second well region 440 and the third well region 445 are formed in sequence, the shape of the first well region 430 can be formed around the center of the pixel 200 through the top surface of the substrate 402 by an impurity implantation process.

[0129] The first well region 430 may include an N-type impurity having a lower doping concentration than the first doped region 410 and the second doped region 420.

[0130] The second well region 440 may be spaced apart from the first doped region 410 by a predetermined distance and extend parallel to a surface of the substrate 402 while overlapping with the first doped region 410. As described above, the second well region 440 may be opened around the center of the pixel 200 or omitted, and the first well region 430 may have a well opening 435 extending through the opening region toward the bottom (the rear surface of the substrate 402) to a predetermined depth. The second well region 440 may include a P-type impurity having a lower doping concentration than the first doped region 410 and the second doped region 420.

[0131] The third well region 445 may extend downward along the side surfaces of the first well region 430 and the second well region 440 while adjacent to the second doped region 420. The third well region 445 may include a P-type impurity having a lower doping concentration than the first doped region 410 and the second doped region 420. The third well region 445 may be formed to have a greater depth from one surface of the substrate 402 than the second well region 440.

[0132] The second well region 440 can be configured to overlap with the first doped region 410, and the third well region 445 can be configured to overlap with the second doped region 420. The second well region 440 and the third well region 445 can constitute the bottom well region described with reference to FIG2. Therefore, when the cross-section 400 corresponds to the first dicing line AA′, the second well region 440 and the third well region 445 can correspond to the first bottom well region BW1 or the fourth bottom well region BW4, and when the cross-section 400 corresponds to the second dicing line BB′, they can correspond to the second bottom well region BW2 or the third bottom well region BW3.

[0133] The second well region 440 and the third well region 445, which include P-type impurities, may each have a depletion region at the boundary between the first well region 430, which includes N-type impurities, and the substrate 402. These depletion regions can block the flow of photocharge generated in the substrate 402 through the second well region 440 and the third well region 445. Because the second well region 440 and the third well region 445 are located below the first doped region 410 and the second doped region 420, and the first well region 430 is located between the first doped region 410 and the second doped region 420 and the second well region 440 and the third well region 445, photocharge can be guided to rapidly migrate through the depletion region of the first well region 430 to the startup tap.

[0134] STI region 450 can correspond to STI region STI in Figure 2. STI region 450 can have the following structure: wherein the trench is formed to a predetermined depth from the surface of substrate 402 by the STI process and the trench is filled with dielectric material.

[0135] When section 400 corresponds to the first cutting line AA′, well shelter area 455 can correspond to the first well shelter area WBA1 and the fourth well shelter area WBA4, and when section 400 corresponds to the second cutting line BB′, it can correspond to the second well shelter area WBA2 and the third well shelter area WBA3. As described with reference to FIG2, well shelter area 455 may be without trenches and dielectric material disposed therein, and STI area 450 may correspond to the disconnected area.

[0136] The third doped region 460 can correspond to the first voltage-stable region VS1 and the fourth voltage-stable region VS4 when the cross section 400 corresponds to the first cleavage line AA′, and can correspond to the second voltage-stable region VS2 and the third voltage-stable region VS3 when the cross section 400 corresponds to the second cleavage line BB′. The third doped region 460 can be a P+ type impurity region doped with a higher concentration than the transistor well region 465.

[0137] The voltage stabilizing electrode 462 can be positioned adjacent to the top of the third doped region 460 and transmit inactive voltage to the third doped region 460.

[0138] Transistor well region 465 may correspond to the P-well disposed below the pixel transistor region PTA and the corresponding voltage stabilization region in FIG2. Transistor well region 465 may include P-type impurities with a lower doping concentration than the third doping region 460, and form the body of the pixel transistor, thereby determining the element characteristics (e.g., threshold voltage) of the pixel transistor.

[0139] At least a portion of the transistor well region 465 may be disposed within the well shelter region 455. Furthermore, at least a portion of the boundary between the transistor well region 465 and the substrate 402 may be disposed within the well shelter region 455. Depending on the sequence of the entire process, the implantation process of the transistor well region 465 may be performed after the trench of the STI region 450 is formed.

[0140] When assuming the well shield region 455 is absent and instead filled with the STI region 450, during the implantation process of the transistor well region 465, the transistor well region 465 can further diffuse along the bottom surface of the STI region 450 and be positioned closer to the well opening 435. The third doped region 460, with an inactive voltage applied, can generate a hole flow related to the first doped region 410, with an active voltage applied. Such a hole flow flows through the transistor well region 465, which has relatively low resistance, and then through the boundary between the transistor well region 465, which includes P-type impurities, and the substrate 402, i.e., the boundary with relatively high resistance due to the depletion region. When, as assumed above, the transistor well region 465 is positioned closer to the well opening 435, the hole flow can easily migrate to a location closer to the well opening 435. Therefore, the hole flow can more easily flow between the first doped region 410 and the third doped region 460.

[0141] However, in this embodiment, when the well shield region 455 is disposed in the STI region 450, during the implantation process of the transistor well region 465, the transistor well region 465 can diffuse into the well shield region 455 (i.e., diffuse along the side surface of the STI region 450 to the top surface of the substrate 402) and is configured to be further away from the well opening 435. Thus, when the transistor well region 465 is configured to be further away from the well opening 435, the hole flow will not easily migrate to a position close to the well opening 435, which prevents the hole flow from easily flowing between the first doped region 410 and the third doped region 460.

[0142] The potential control electrode 470 and the potential control dielectric layer 475 may correspond to the potential control region PC in FIG2. The potential control electrode 470 and the potential control dielectric layer 475 may be stacked on top of one surface of the substrate 402. The potential control electrode 470 may include a metal or polycrystalline silicon with high conductivity. The potential control dielectric layer 475 may include one or more of silicon oxynitride (Si xO yN z), silicon oxide (Si xO y), and silicon nitride (Si xN y), where x, y, and z are natural numbers.

[0143] As a potential control voltage is applied to the potential control electrode 470, the potential control electrode 470 can control the potential of the first well region 430 corresponding to the bottom of the potential control dielectric layer 475, and form a potential gradient that facilitates the migration of photocharge toward the activated tap. Due to the microlens (not shown) configured to overlap with the pixel 200 to focus light into the pixel 200, the maximum amount of photocharge can be generated near the center of the pixel 200. Therefore, since the well opening 435 is located at the center of the pixel 200, and a potential gradient is formed through the potential control region PC to induce photocharge toward the activated tap, the photocharge generated in the corresponding time period can be effectively captured by the activated tap, which improves the sensitivity and demodulation contrast of the pixel 200.

[0144] The substrate dielectric layer 480 can electrically insulate areas on one surface of the substrate that do not require the application or output of signals. The substrate dielectric layer 480 can be formed on one surface of the substrate 402. For example, the substrate dielectric layer 480 can include one or more of silicon oxynitride (Si xO yN z), silicon oxide (Si xO y), and silicon nitride (Si xN y), where x, y, and z are natural numbers.

[0145] Figure 5 is a diagram illustrating the flow of photocharge in a pixel during the first time period.

[0146] The cross section 500 in Figure 5 can correspond to the cross section obtained by cutting pixel 200 along the third cutting line AB or the fourth cutting line A′-B′.

[0147] When a cross-section 500 is obtained by cutting pixel 200 along the third cutting line AB, the first doped region 410 can correspond to the first control node CA1 and the third control node CB3 respectively, the second doped region 420 can correspond to the first detection node DA1 and the third detection node DB3 respectively, and the third doped region 460 can correspond to the first voltage stabilization region VS1 and the third voltage stabilization region VS3 respectively.

[0148] When the cross section 500 obtained by cutting pixel 200 along the fourth cutting line A′-B′ is obtained, the first doped region 410 can correspond to the fourth control node CA4 and the second control node CB2 respectively, the second doped region 420 can correspond to the fourth detection node DA4 and the second detection node DB2 respectively, and the third doped region 460 can correspond to the fourth voltage stabilization region VS4 and the second voltage stabilization region VS2 respectively.

[0149] Since section 500 in Figure 5 is basically the same as section 400 in Figure 4, its repeated description will be omitted in this paper.

[0150] During the first period when the first tap TA1 and the fourth tap TA4 are activated, the left first doped region 410 corresponding to the first control node CA1 or the fourth control node CA4 can receive the first demodulation control signal DCS1 with an active voltage, and the right first doped region 410 corresponding to the second control node CB2 or the third control node CB3 can receive the second demodulation control signal DCS2 with an inactive voltage.

[0151] Since a relatively high voltage is applied to the left first doped region 410 and a relatively low voltage is applied to the right first doped region 410, the voltage of the left depletion region in the first well region 430 becomes higher than the voltage of the right depletion region in the first well region 430, so as to maintain the PN junction.

[0152] Furthermore, the potential control electrode 470, which receives the potential control voltage, can form a potential gradient that increases from the right depletion region through the central depletion region including the well opening 435 within the first well region 430 toward the left depletion region. The photocharge generated in the substrate 402 in response to the intensity of the incident light can be introduced along the potential gradient into the well opening 435, then migrate toward the left first doped region 410 and be captured by the left second doped region 420. The captured photocharge can be transferred to the first common node CN1 connected to the left second doped region 420.

[0153] A ground voltage Vss corresponding to the inactive voltage can be applied to the third doped region 460. Therefore, a hole current can be generated between the left first doped region 410 and the left third doped region 460. However, when the transistor well region 465 is formed, the hole current can flow into the well shield region 455 due to the well shield region 455. Therefore, the distance between the well opening 435 and the boundary between the well shield region 455 and the substrate 402 can be further increased. Furthermore, due to the presence of the second well region 440 and the third well region 445, the hole current generated by the left first doped region 410 and the left third doped region 460 inevitably flows through the well opening 435. Therefore, the resistive elements present in the path of the hole current generated by the left first doped region 410 and the left third doped region 460 can be increased considerably. As a result, the amplitude of the hole current generated along such a path can be significantly reduced.

[0154] Figure 6 is a diagram illustrating the flow of photocharge in a pixel during the second time period.

[0155] The cross section 600 in Figure 6 can correspond to the cross section obtained by cutting pixel 200 along the third cutting line AB or the fourth cutting line A′-B′.

[0156] During the second period when the second tap TB2 and the third tap TB3 are activated, the left first doped region 410 corresponding to the first control node CA1 or the fourth control node CA4 can receive the first demodulation control signal DCS1 with an inactive voltage, while the right first doped region 410 corresponding to the second control node CB2 or the third control node CB3 can receive the second demodulation control signal DCS2 with an active voltage.

[0157] Since a relatively high voltage is applied to the right first doped region 410 and a relatively low voltage is applied to the left first doped region 410, the voltage of the right depletion region in the first well region 430 becomes higher than the voltage of the left depletion region in the first well region 430, so as to maintain the PN junction.

[0158] Furthermore, the potential control electrode 470, which receives the potential control voltage, can form a potential gradient that increases from the left depletion region through the central depletion region including the well opening 435 within the first well region 430 toward the right depletion region. The photocharge generated in the substrate 402 in response to the intensity of the incident light can be introduced along the potential gradient into the well opening 435, then migrate toward the right first doped region 410 and be captured by the right second doped region 420. The captured photocharge can be transferred to the second common node CN2 connected to the right second doped region 420.

[0159] A ground voltage Vss corresponding to the inactive voltage can be applied to the third doped region 460. Therefore, a hole current can be generated between the right first doped region 410 and the right third doped region 460. However, when the transistor well region 465 is formed, the hole current can flow into the well shield region 455 due to the well shield region 455. Therefore, the distance between the well opening 435 and the boundary between the well shield region 455 and the substrate 402 can be further increased. Furthermore, due to the presence of the second well region 440 and the third well region 445, the hole current generated by the right first doped region 410 and the right third doped region 460 inevitably flows through the well opening 435. Therefore, the resistive elements present in the path of the hole current generated by the right first doped region 410 and the right third doped region 460 can be significantly increased. As a result, the amplitude of the hole current generated along such a path can be significantly reduced.

[0160] Figure 7 is an example of a cross-section obtained by cutting pixels along the fifth or sixth cutting line of Figure 2.

[0161] The cross section 700 in Figure 7 can correspond to the cross section obtained by cutting pixel 200 along the fifth cutting line XX′ or the sixth cutting line YY′ in Figure 2.

[0162] Section 700 may include a substrate 402, a surface-doped region 404, a surface-depleted region 406, a first well region 430, an STI region 450, a well shield region 455, a shield disconnect region 457, a transistor well region 465, a potential control electrode 470, a potential control dielectric layer 475, and a substrate dielectric layer 480. For elements already described with reference to FIG4, their repeated descriptions will be omitted herein, and the following description will focus on the shield disconnect region 457.

[0163] The bunker disconnection zone 457 and the well bunker zone 455 can be set on the left and right sides of the first well zone 430, respectively.

[0164] While the well shelter area 455 has a structure in which trenches and dielectric material are omitted, the shelter disconnect area 457 may include trenches and dielectric material, such that the STI area 450 is continuously connected in the shelter disconnect area 457.

[0165] During the implantation process of transistor well region 465, the shield disconnect region 457 allows transistor well region 465 to diffuse further along the bottom surface of STI region 450, thus positioning transistor well region 465 closer to well opening 435. When transistor well region 465 is positioned closer to well opening 435, the hole current flowing between the third doped region 460 (applied with an inactive voltage) and the first doped region 410 (applied with an active voltage) can easily migrate to a position closer to well opening 435. Therefore, hole current can flow more easily between the first doped region 410 and the third doped region 460.

[0166] The hole current between the first doped region 410 and the third doped region 460 hardly flows through the bottom of the well shelter region 455, which has a relatively large resistance, but can easily flow through the bottom of the shelter disconnect region 457, which has a relatively small resistance.

[0167] Figure 8 is a diagram illustrating the hole flow through pixels arranged in a matrix during the first time period.

[0168] Figure 8 illustrates nine pixels arranged in a 3×3 matrix comprising three rows and three columns. In this embodiment, only nine pixels are used as an example, but other embodiments are also possible. The following description can also be applied to a pixel array 30 comprising N pixels arranged in a matrix, where N is any natural number.

[0169] In Figure 8, the first to fourth taps TA1, TB2, TB3 and TA4, the potential control area PC located at the center of each pixel, the voltage stabilization area VS located at the corresponding vertex of each pixel, and the pixel transistor area PTA located along the edge of each pixel are illustrated as different patterns.

[0170] A specific pixel can share the voltage stability region VS with pixels adjacent in the row direction (i.e., horizontal direction) (first adjacent pixel), pixels adjacent in the column direction (i.e., vertical direction) (second adjacent pixel), pixels adjacent in the first diagonal direction (third adjacent pixel), or pixels adjacent in the second diagonal direction (fourth adjacent pixel).

[0171] The pixels in the first row can be defined sequentially from left to right as the first to the third pixel, the pixels in the second row can be defined sequentially from left to right as the fourth to the sixth pixel, and the pixels in the third row can be defined sequentially from left to right as the seventh to the ninth pixel. Therefore, for the fifth pixel located at the center of the 3×3 matrix, its first adjacent pixels can be the fourth and sixth pixels, its second adjacent pixels can be the second and the eighth pixel, its third adjacent pixels can be the first and the ninth pixel, and its fourth adjacent pixels can be the third and the seventh pixel.

[0172] The pixel transistor region (PTA) of a specific pixel can be integrated with the pixel transistor region (PTA) of the first adjacent pixel or the second adjacent pixel.

[0173] Figure 8 illustrates the hole current flowing between the activated first tap group and the voltage stabilization region VS during the first time period when the first tap TA1 and the fourth tap TA4 of the first tap group are activated and the second tap TB2 and the third tap TB3 of the second tap group are deactivated. For ease of description, the following description will focus on the fifth pixel. However, the same description can also be applied to other pixels. The first tap group with an active voltage is labeled as active state H, while the second tap group with an inactive voltage and the voltage stabilization region VS are each labeled as inactive state L.

[0174] The first hole current HC1 can flow from the first tap group TA1 and TA4 to the voltage stable region VS.

[0175] In some embodiments, the first tap TA1 can generate a first hole current HC1 flowing toward a first voltage stabilization region and a second voltage stabilization region adjacent to the first tap TA1. In this case, the first hole current HC1 flowing between the first tap TA1 and the first voltage stabilization region can be output from the first tap TA1, flowing along a curved path toward and through the first shelter disconnection region. Then, the first hole current HC1 can flow along the curved path toward the first voltage stabilization region and be input into the first voltage stabilization region. Similarly, the first hole current HC1 flowing between the first tap TA1 and the second voltage stabilization region can be output from the first tap TA1, flowing along a curved path toward and through the second shelter disconnection region. Then, the first hole current HC1 can flow along the curved path toward the second voltage stabilization region and be input into the second voltage stabilization region. This is because the resistance of the shelter disconnection region is considerably lower than the resistance of the well shelter region, and the first hole current HC1 can flow essentially only through the shelter disconnection region. Furthermore, since the first shelter disconnection zone is set to be closer to the first voltage stabilization zone than the third voltage stabilization zone and the second shelter disconnection zone is set to be closer to the second voltage stabilization zone than the first voltage stabilization zone, the aforementioned flow of the first hole current HC1 can be induced.

[0176] In this embodiment, when the electrical flow passes through the well shelter area or the shelter disconnect area, this can indicate that the electrical flow passes through the bottom of the well shelter area or the shelter disconnect area.

[0177] The fourth tap TA4 can generate a first hole current HC1 flowing towards the third and fourth voltage stabilization regions adjacent to the fourth tap TA4. At this time, the first hole current HC1 flowing between the fourth tap TA4 and the third voltage stabilization region can be output from the fourth tap TA4 and flows along a curved path towards the third shelter disconnect region, passing through the third shelter disconnect region. Then, the first hole current HC1 can flow along the curved path towards the third voltage stabilization region and be input into the third voltage stabilization region. Similarly, the first hole current HC1 flowing between the fourth tap TA4 and the fourth voltage stabilization region can be output from the fourth tap TA4 and flows along a curved path towards the fourth shelter disconnect region, passing through the fourth shelter disconnect region. Then, the first hole current HC1 can flow along the curved path towards the fourth voltage stabilization region and be input into the fourth voltage stabilization region. This is because the resistance of the shelter disconnect region is considerably lower than the resistance of the well shelter region, and the first hole current HC1 can flow essentially only through the shelter disconnect region. Furthermore, since the third shelter disconnection zone is set to be closer to the fourth voltage stabilization zone than the second voltage stabilization zone and the fourth shelter disconnection zone is set to be closer to the third voltage stabilization zone than the fourth voltage stabilization zone, the aforementioned flow of the first hole current HC1 can be induced.

[0178] Therefore, the first hole current HC1 flows through various paths from the first tap group TA1 and TA4 to the voltage stable region VS, including the path of the shelter disconnection area.

[0179] The STI region (STI) can include a trench structure formed by the STI process, and the dielectric material filling the trench structure can create dangling bonds on the surface of the trench structure, which lead to dark current. When the wellbore shield region is connected as a whole without shield disconnection areas, the first hole current HC1 can flow through various paths from the first tap groups TA1 and TA4 to the voltage stabilization region VS. In this case, since the first hole current HC1 is in contact with the STI region (STI), this causes dangling bonds to span a larger area, thus the effect of dark current on the first hole current HC1 can be relatively increased to generate a large amount of noise.

[0180] When the first hole current HC1 flows concentratedly through the path including the shelter disconnect region as in this embodiment, the first hole current HC1 contacts the STI region, causing the dangling bond to span a smaller area. Therefore, the effect of the dark current on the first hole current HC1 can be relatively reduced to minimize noise.

[0181] As shown in Figure 8, the first hole current HC1 can flow through a curved path between the first tap groups TA1 and TA4 and the voltage stabilization region VS, instead of a straight path. The first hole current HC1 can flow from a position of high potential to a position of low potential. Since the shelter disconnection zone is set closer to the first or second straight line described with reference to Figure 2 than the first to fourth curved points of the first well shelter region WBA1 to the fourth well shelter region WBA4, the potential can change sequentially along a curved path such as the path of the first hole current HC1. When the potential changes along a curved path such as the path of the first hole current HC1, the first hole current HC1 can be suppressed as much as possible, which minimizes unnecessary power consumption. Furthermore, compared to when the potential changes along a straight path, an electric field can be formed across a larger area, which allows for efficient collection of photocharge. Therefore, demodulation contrast can be improved.

[0182] Figure 9 is a diagram illustrating the hole flow through pixels arranged in a matrix during the second time period.

[0183] Figure 9 illustrates the hole current flowing between the activated second tap group and the voltage stabilization region VS during the second time period when the first tap TA1 and the fourth tap TA4 of the first tap group are deactivated and the second tap TB2 and the third tap TB3 of the second tap group are activated for the pixel shown in Figure 8.

[0184] The second hole current HC2 can flow from the second tap group TB2 and TB3 to the voltage stable region VS.

[0185] Specifically, the second tap TB2 can generate a second hole current HC2 flowing towards the second and fourth voltage stabilization regions adjacent to the second tap TB2. At this time, the second hole current HC2 flowing between the second tap TB2 and the second voltage stabilization region can be output from the second tap TB2, flowing along a curved path towards and through the second shelter disconnection region. Then, the second hole current HC2 can flow along the curved path towards the second voltage stabilization region and be input into the second voltage stabilization region. Similarly, the second hole current HC2 flowing between the second tap TB2 and the fourth voltage stabilization region can be output from the second tap TB2, flowing along a curved path towards and through the third shelter disconnection region. Then, the second hole current HC2 can flow along the curved path towards the fourth voltage stabilization region and be input into the fourth voltage stabilization region. This is because the resistance of the shelter disconnection region is considerably lower than the resistance of the well shelter region, and the second hole current HC2 can flow essentially only through the shelter disconnection region. Furthermore, since the second shelter disconnection zone is set to be closer to the second voltage stabilization zone than the first voltage stabilization zone, and the third shelter disconnection zone is set to be closer to the fourth voltage stabilization zone than the second voltage stabilization zone, the aforementioned flow of the second hole current HC2 can be induced.

[0186] The third tap TB3 can generate a second hole current HC2 flowing towards the first and third voltage stabilization regions adjacent to the third tap TB3. At this time, the second hole current HC2 flowing between the third tap TB3 and the first voltage stabilization region can be output from the third tap TB3, flowing along a curved path towards and through the first shelter disconnect region. Then, the second hole current HC2 can flow along the curved path towards the first voltage stabilization region and be input into the first voltage stabilization region. Similarly, the second hole current HC2 flowing between the third tap TB3 and the third voltage stabilization region can be output from the third tap TB3, flowing along a curved path towards and through the fourth shelter disconnect region. Then, the second hole current HC2 can flow along the curved path towards the third voltage stabilization region and be input into the third voltage stabilization region. This is because the resistance of the shelter disconnect region is considerably lower than the resistance of the well shelter region, and the second hole current HC2 can flow essentially only through the shelter disconnect region. Furthermore, since the first shelter disconnection zone is set to be closer to the first voltage stabilization zone than the third voltage stabilization zone and the fourth shelter disconnection zone is set to be closer to the third voltage stabilization zone than the fourth voltage stabilization zone, the aforementioned flow of the second hole current HC2 can be induced.

[0187] The second hole current HC2 flows through various paths from the second tap groups TB2 and TB3 to the voltage stabilization zone VS, including the path through the bunker disconnection zone.

[0188] When the wellbore area is connected as a whole without any disconnected areas, the second hole current HC2 can flow through various paths from the second tap groups TB2 and TB3 to the voltage stabilization zone VS. In this case, since the second hole current HC2 contacts the STI zone, this causes the dangling bond to span a larger area, thus increasing the influence of the dark current on the second hole current HC2 and generating a large amount of noise.

[0189] However, when the second hole current HC2 flows concentratedly through the path including the shelter disconnect region as in this embodiment, the second hole current HC2 contacts the STI region, causing the dangling bond to span a smaller area. Therefore, the effect of the dark current on the second hole current HC2 can be reduced to minimize noise.

[0190] As shown in Figure 9, the second hole current HC2 can flow through a curved path between the second tap groups TB2 and TB3 and the voltage stabilization region VS, instead of a straight path. The second hole current HC2 flows from a position of high potential to a position of low potential. Since the shelter disconnection zone is set closer to the first or second straight line described with reference to Figure 2 than the first to fourth curved points of the first well shelter region WBA1 to the fourth well shelter region WBA4, the potential can change sequentially along a curved path such as the path of the second hole current HC2. When the potential changes along a curved path such as the path of the second hole current HC2, the second hole current HC2 can be suppressed as much as possible, which allows for minimizing power consumption. Furthermore, compared to when the potential changes along a straight path, an electric field can be formed across a larger area, which allows for efficient collection of photocharge. Therefore, demodulation contrast can be improved.

[0191] While various embodiments have been described above, it will be understood by those skilled in the art to which this invention pertains that the described embodiments are merely examples. Variations and improvements can be made to the disclosed embodiments and other embodiments of the disclosed technology based on the content disclosed in this patent document.

[0192] 1: Target object 10: Light source 20: Lens Module 30: pixel array 40: Control Block 41: Line driver 42: Demodulator driver 43: Light source driver 44: Timer Controller (T / C) 45: Readout Circuit 300 pixels 310: Photoelectric conversion area 320: Circuit Area 400: Section 402:Substrate 404: Surface doped region 406: Surface void region 410: First doped region 415: Control Electrode 420: Second doped region 425: Detection electrode 430: First Well Area 435: Well opening 440: Second Well Area 445: Third Well Area 450: STI area 455: Well Shelter Area 457: Bunker Disconnection Zone 460: Third doped region 462: Voltage stabilizing electrode 465: Tranquilizer Well Area 470: Potential control electrode 475: Potential-controlled dielectric layer 480:Substrate dielectric layer 500: Section 600: Section 700: Section AA′: First secant line BB′: Second cutting line AB: Third secant line A′-B′: Fourth secant line BDA1: First Bunker Disconnection Zone BDA2: Second Bunker Disconnection Zone BDA3: Third Bunker Disconnection Zone BDA4: Fourth Bunker Disconnection Zone BW1: First Bottom Well Area BW2: Second Bottom Well Area BW3: Third Bottom Well Area BW4: Fourth Bottom Well Area BX1: First boost transistor BX2: Second boost transistor CA1: First Control Node CB2: Second Control Node CB3: Third Control Node CA4: Fourth Control Node CN1: First Public Node CN2: Second Public Node DA1: First detection node DB2: Second Detection Node DB3: Third Detection Node DA4: Fourth Detection Node DCS1, DCS1(H): First demodulation control signal DCS2, DCS2(L): Second demodulation control signal FD1: First floating diffusion node FD2: Second floating diffusion node GW: Guiding Well Area H: Activity Status HC1: First hole current HC2: Second hole current ISD: Image Sensing Device L: Inactive state MLS: Optical Modulation Signal OUT1: First pixel output signal OUT2: Second pixel output signal PC: Potential Control Area PD: Photoelectric conversion element PTA: Pixel Transistor Area PX: Unit pixel RST1: First reset signal RST2: Second reset signal RX1: First Reset Transistor RX2: Second Reset Transistor SEL1: First Choice Signal SEL2: Second Choice Signal SF1: First source follower transistor SF2: Second source follower transistor STI: STI zone (shallow trench isolation) SX1: First Choice Transistor SX2: Second Choice Transistor TA1: First tap TB2: Second tap TB3: Third tap TA4: Fourth Tap T / C: Timer Controller TG1: First transmission signal TG2: Second transmission signal TX1: First Transmission Transistor TX2: Second Transmission Transistor Vbt: Boost voltage VDD: Pixel Voltage VS: Voltage stability region Vsub: Substrate voltage Vss: Grounding voltage VS1: First voltage stabilization region VS2: Second voltage stabilization region VS3: Third voltage stabilization region VS4: Fourth voltage stability region VR1: First variable resistor VR2: Second variable resistor VR3: Third Variable Resistor VR4: Fourth Variable Resistor WBA1: First Shaft Bunker Area WBA2: Second Well Bunker Area WBA3: Third Shaft Bunker Area WBA4: Fourth Well Bunker Area WO: Well opening XX′: Fifth secant line YY′: Sixth secant line

Claims

1. An image sensing device, the image sensing device comprising: A substrate having a first surface and a second surface facing the first surface, onto which light is incident; The system includes multiple detection structures, each comprising a control node exhibiting a conductivity type and generating a potential gradient in the substrate, and a detection node for capturing photocharge generated in response to incident light and migrating in response to the potential gradient; a first well region, configured to be adjacent to the control node of the multiple detection structures and containing impurities having a conductivity type different from that of the control node; and a second well region, spaced apart from and overlapping the control node by a predetermined distance, the second well region including impurities having a conductivity type identical to that of the control node; wherein the first well region includes well openings extending toward the first surface between adjacent second well regions.

2. The image sensing apparatus as claimed in claim 1, wherein, The first well region includes a depletion region formed by the PN junction of each of the control nodes, wherein the potential of the depletion region is controlled by the voltage applied to the control node adjacent to the depletion region.

3. The image sensing device as claimed in claim 1, further comprising: A pixel transistor region, wherein the pixel transistor region includes pixel transistors, each of the pixel transistors converting captured photocharge into pixel signals; STI (Shallow Trench Isolation) region, which isolates the pixel transistor region from each of the detection structures; and wellbore region, which is disposed in the STI region to isolate the STI region from another STI region.

4. The image sensing apparatus as claimed in claim 3, wherein, The STI area includes a trench at a predetermined depth from the second surface, wherein the trench is not located in the well shelter area.

5. The image sensing apparatus as claimed in claim 3, wherein, The pixel transistor region includes a transistor well region corresponding to the main body of the pixel transistor, wherein at least a portion of the transistor well region is disposed in the well shelter region.

6. The image sensing apparatus as claimed in claim 5, wherein, At least a portion of the boundary between the transistor well region and the substrate is disposed within the well shelter region.

7. The image sensing apparatus as claimed in claim 1, wherein, The control node includes impurities having a first conductivity type, and the detection node includes impurities having a second conductivity type different from the first conductivity type.

8. The image sensing apparatus as claimed in claim 7, wherein, The first well region includes impurities having the second conductivity type.

9. The image sensing device as claimed in claim 7, further comprising: A third well region, which is spaced at a predetermined distance from the control node and overlaps with the detection node, includes impurities having the first conductivity type.

10. The image sensing apparatus as claimed in claim 3, wherein, The detection structure includes a first tap, a second tap, a third tap, and a fourth tap respectively located at the upper left, upper right, lower left, and lower right of the pixel.

11. The image sensing apparatus of claim 10, further comprising a first voltage stabilization region, a second voltage stabilization region, a third voltage stabilization region, and a fourth voltage stabilization region respectively disposed at a first vertex, a second vertex, a third vertex, and a fourth vertex of the pixel and providing a bulk voltage of the pixel transistor.

12. The image sensing apparatus as claimed in claim 11, wherein, The well shelter area includes a first well shelter area, a second well shelter area, a third well shelter area, and a fourth well shelter area disposed between the first voltage stabilization area to the fourth voltage stabilization area and between the first tap and the fourth tap, wherein each of the first well shelter area to the fourth well shelter area has an L-shape.

13. The image sensing apparatus as claimed in claim 12, wherein, The STI area includes a first shelter disconnection area, a second shelter disconnection area, a third shelter disconnection area, and a fourth shelter disconnection area disposed between adjacent well shelter areas from the first well shelter area to the fourth well shelter area, wherein each of the first shelter disconnection area to the fourth shelter disconnection area includes a trench having a predetermined depth from the second surface.

14. The image sensing apparatus as claimed in claim 13, wherein, The first shelter disconnection zone is set to be closer to the first voltage stable zone than the third voltage stable zone, the second shelter disconnection zone is set to be closer to the second voltage stable zone than the first voltage stable zone, the third shelter disconnection zone is set to be closer to the fourth voltage stable zone than the second voltage stable zone, and the fourth shelter disconnection zone is set to be closer to the third voltage stable zone than the fourth voltage stable zone.

15. The image sensing apparatus as claimed in claim 12, wherein, The first well shelter area to the fourth well shelter area are rotationally symmetrical about the center of the pixel.

Images