Circuits and methods to alter a phase speed of an output clock

Abstract

In one particular embodiment, a method for reducing noise / clock jitter and generating a "stretched" output clock for optimization of output clock jitter is disclosed. The method includes: after detecting a transient voltage by a detector circuit, generating two or more clock phases; generating an output clock signal based on one of the two or more clock phases; and changing a phase velocity of the output clock signal to correspond to a phase velocity of an input clock signal.

Description

[Technical Field]

[0001] This disclosure is generally about circuits and methods for modifying the phase velocity of the output clock. [Previous Technology]

[0002] Technological advancements have led to smaller and more powerful computing devices. For example, various portable personal computing devices, including cordless phones (such as mobile phones and smartphones), tablets, and laptops, are small, lightweight, and easy for users to carry. These devices can transmit voice and data packets via wireless networks. Furthermore, many of these devices incorporate additional functionality, such as digital still cameras, digital video cameras, digital recorders, and audio file players. Moreover, such devices can process executable instructions, including software applications that can access the Internet, such as web browser applications. Therefore, these devices can include significant computing and networking capabilities. Nevertheless, the demand for computing devices to operate faster and / or with less power continues to increase.

[0003] In one instance, external jitter (i.e., added noise) at the output of a digital system can be a significant problem for clock circuitry due to various timing faults. In some operations, a delayed-locked loop (DLL) adds clock jitter to the input jitter of the main clock. Consequently, each output phase of the DLL will be "noisier" than the input clock signal. This added jitter cannot be filtered by offset circuitry. Therefore, there is a need in the art to provide clock systems, circuits, and methods that account for external jitter and keep it as low as possible, enabling digital systems to operate faster and / or consume less power. [Summary of the Invention]

[0004] According to one embodiment of this disclosure, a method for reducing noise / clock jitter and generating a "stretched" output clock for optimization of output clock jitter is disclosed. The method includes: after detecting a transient voltage by a detector circuit, generating two or more clock phases; generating an output clock signal based on one of the two or more clock phases; and changing a phase rate of the output clock signal to correspond to a phase rate of an input clock signal.

[0005] According to another embodiment of this disclosure, a circuit for reducing noise / clock jitter and generating a "stretched" output clock to optimize for output clock jitter is disclosed. The circuit includes: a detector circuit for monitoring a supply voltage of a transient voltage; after detecting the transient voltage, an input phase circuit is configured to generate two or more clock phases; a phase selector is configured to generate an output clock signal from at least one of the two or more clock phases; and a speed controller circuit is configured to change a phase speed of the output clock signal to correspond to a phase speed of an input clock signal.

[0006] According to another embodiment of this disclosure, a speed controller circuit is disclosed that allows for the reduction of noise / clock jitter and the ability to generate a "stretched" output clock to optimize for output clock jitter. The speed controller circuit may include: an OR gate; a NOR gate; an AND gate; and a multiplexer. The speed controller circuit can be configured to determine whether an input signal from a detector circuit contains a voltage level higher than a voltage threshold, and whether a selected phase speed is higher than a phase speed threshold.

Implementation Method

[0009] Specific embodiments of this disclosure are described below with reference to the drawings. In the description, common features are designated by common element symbols throughout the drawings.

[0010] Advantageously, the present invention provides an adaptive clock circuit system to dynamically adjust the clock frequency of a digital system in response to supply voltage disturbances (i.e., detected transient voltages, noise signals). For example, in some embodiments, when voltage decay is detected, the present invention allows for an "offset" (i.e., a change in phase velocity) to a clock phase with minimal noise, rather than "remaining" on a random clock phase.

[0011] As an advantage, after detecting an attenuation voltage, the speed controller circuit system of the present invention provides the ability to slow down the output clock, so that the output clock is "stretched" (and therefore, the frequency of the output clock is less than the frequency of the basic clock).

[0012] Referring to Figure 1, a fine-grained adaptive clock circuit 100 (i.e., system 100) is shown. A main clock 170 (PLL_CLK) (e.g., 2 to 4 GHz) may be transmitted to circuit 100 (as an example, from a phase-locked loop (PLL)) 110, and provides a clock signal 170 (PLL_CLK) for attenuation detector 120 (droop_dtct) to monitor the supply voltage (Vdd_core) of the larger digital circuitry (i.e., the digital system). In one example, the digital system (not shown) will receive an adaptive clock output clock 172 CPU_CLK (e.g., approximately 0.5 to 4 GHz).

[0013] In some embodiments, the delay-locked loop (DLL) 130 may be configured to generate two or more (e.g., several) phases (i.e., DLL phases) from the PLL 110 to be transmitted to the phase selector circuit 140 (i.e., phase shifter). As illustrated in FIG1, in one example, the DLL circuit 130 is configured to receive the master clock 170 (PLL_CLK) and output eight phases (PhiDLL[0] to [7] (i.e., DLL phases)). The phase selector circuit (i.e., offset / mask) 140 may then be configured to generate a composite clock signal 171 (DDL_CLK) from these DLL phases. In one embodiment, the composite clock signal 171 may be transmitted to the post-scaler circuit 150 to generate an adaptive clock output clock 172 (CPU_CLK).

[0014] Referring to FIG. 2, an example of the input and output signals of the DLL circuit 130 of FIG. 1 is shown. An input signal 210 is depicted as Mclk, and eight different expected output clock signals (i.e., output phases, output clock phases) 220 (e.g., 220(a) to 220(h)) are depicted as Ph0 to Ph7. In one example embodiment, one cycle (T) of the clock can be divided into eight segments (i.e., each with a different delay). As illustrated, the rising edge of each of the output phases 220(a) to 220(h) corresponds to each of the eight segments. In a particular operation, the phase selector circuit 140 will use one of the DLL output phases 220(a) to 220(h) to generate a rising edge of an output clock 172 (CPU_CLK). For example, when the adaptive clock mechanism is triggered (e.g., after detecting a transient voltage on VDD), the selected phase will be randomly selected by the offset operation. For example, after one or more adaptive clock mechanisms are triggered (e.g., offset between output clock phases) (e.g., when detecting transient voltage on VDD), the selected phase will be randomly selected by the phase selector circuit (140).

[0015] However, this operation would be suboptimal because the jitter of the output clock 172 CPU_CLK can be as high as the jitter of the selected phase of the DLL circuit 130. Accordingly, this jitter must also be taken into account in the digital circuit design that receives the output clock 172 CPU_CLK, and added to the timing margin as part of the clock uncertainty. As an example, if phase 7 of the 8-phase DLL exhibits a worst-case minimum period jitter of 5 picoseconds (ps), then 5 ps must also be added to the timing margin during the digital circuit design.

[0016] Advantageously, the present invention takes into account that in the DLL circuit 133, phase "noise" (e.g., clock jitter) will increase with subsequent delays through the provided delay lines (i.e., each additional segment of the cycle). Therefore, each subsequent phase will have "more noise" than the previous phase (e.g., phase "7" will have more noise than phase "6", phase "6" will have more noise than phase "5", etc.). As can be understood, the "cleanest" (i.e., the smallest) noise will be that of the initial phase (phase "0"), for example, noise that is close to (e.g., approximately equal to) the level of the input clock (PLL_CLK 170).

[0017] Referring to Figure 3, a block diagram of an adaptive clock circuit 300 (i.e., system 300) according to an example embodiment is shown. As illustrated, circuit 300 includes a detector circuit 310, an input phase circuit 330, a phase selector circuit 340, and a speed controller circuit 320. In some embodiments, detector circuit 310 includes an attenuation detector circuit (droop_dtct) configured to monitor the supply voltage (Vdd) for indicating transient voltages and output a detection signal 368 (i.e., [n:0], attenuated) to speed controller circuit 350. In some embodiments, detection signal 368 may be transmitted to a high-pass filter circuit 322 (e.g., an analog-to-digital converter) before a filtered detection signal 369 is transmitted to speed controller circuit 350.

[0018] In some operations, after the transient voltage of the detection circuit 310 is detected, the input phase circuit 330 can be configured to generate two or more (e.g., several, multiple) clock phases. In some operations, the input phase circuit 330 can be configured to receive a basic clock (CLK) signal and transmit two or more (e.g., eight, multiple) clock phases to the phase selector circuit 330. In different embodiments, the input phase circuit 330 may include a delay phase-locked loop (DLL), a phase-locked loop (PLL), a frequency-locked loop (FLL), or an oscillator.

[0019] As illustrated in Figure 3, in one example, the input phase circuit 330 is configured to receive a basic clock 370 and output two or more input phases (i.e., [m:0], clock phases). The phase selector circuit (i.e., offset / mask) 340 can then be configured to generate an output clock 372 from these input phases.

[0020] In some additional embodiments, circuit 300 may further include a phase-locked loop (PLL) circuit (not shown) to transmit the basic clock signal 370 to the input phase circuit 330. In some embodiments, circuit 300 may further include a post-scaler circuit (not shown) configured to receive the output clock signal 372 from the phase selector circuit 340.

[0021] In the scheme and technique described herein, advantageously, the phase selector circuit 340 (i.e., the offset circuit) has the ability to always be stabilized at phase "0" of the input phase circuit 330. For example, if a transient voltage is detected at the detection circuit 320, the phase selector circuit 340 may initially be stabilized at phase "4", for example, randomly, the phase selector circuit 340 will "offset" the clock signal (i.e., change its phase velocity) until the phase selector circuit 340 reaches phase "0". This operation will occur regardless of the attenuation detector signal ([n:0]) from the detection circuit 320.

[0022] For example, the overall loss would delay the digital system by half a cycle. In such cases, the maximum loss would be at most one cycle of lost CPU operation. Nevertheless, advantageously, if the clock jitter added to the input phase circuit 330 is 2% higher than the total clock cycle of the "last" input phase (e.g., the DLL phase) compared to the "initial" input phase (e.g., the DLL phase), the CPU can run 2% faster due to the reduction in clock uncertainty. Thus, the clock-adaptive circuitry and method of the present invention disclosed herein provide circuitry that operates faster and / or with less power.

[0023] Referring to FIG4, FIG400 (corresponding to speed controller circuit 350 in FIG3) and phase selector circuit 420 (corresponding to phase selector circuit 340 in FIG3) of speed controller circuit 410 according to an exemplary embodiment are shown. As illustrated, in exemplary operation, an exemplary input attenuation signal 468 (i.e., the first input signal) is transmitted to speed controller 410. At decision block 412, speed controller 410 determines whether input attenuation signal 468 is established (e.g., == 2) (i.e., whether input attenuation signal 468 includes a voltage level above the voltage threshold (i.e., transient voltage)) or not established (e.g., == 0). If it is "yes" at decision block 412, input signal 468 is provided to AND logic gate 416 (as bit "1"). In alternative embodiments, other equivalent circuit structures (e.g., two consecutive NAND logic gates) may be utilized. If the decision at decision block 412 is "No", then the first input signal 468 is provided as the first input (e.g., digit "0") to multiplexer 418 (e.g., a 2-to-1 multiplexer) (i.e., a control switch). A phase selector signal 474 (i.e., the second input signal) from phase selector circuit 420 (ph_sel, Set_phase[n:0] as shown in Figure 3) is also provided. At decision block 414, speed controller 410 determines whether phase selector signal 474 corresponds to (i.e., equals) the quietest phase (!=quietest) (e.g., phase "0", the least "noisy" phase would be the voltage threshold). If the decision at decision block 414 is "Yes", then the second input signal 474 is provided to AND gate 414. If both the first input signal 468 and the second input signal 474 are "yes", then the selector input 475 will transmit a bit "1" to the multiplexer 418, and the multiplexer 414 will output the bit "1" as an output signal 476 (inc as shown in Figure 3) to the phase selector circuit 420.

[0024] Subsequently, in some embodiments, the phase selector circuit 420 outputs the output clock signal 372 at a lower frequency than the basic clock 370 until its output corresponds to the phase of the output clock signal 371 at the "minimum noise" phase. When the minimum noise phase of the clock signal 371 feeds the output clock signal 372, the decision block 414 outputs logic "0", which then toggles the "AND" logic gate 416, regardless of the output of the decision block 412. The multiplexer 418 can then output the input signal 468. If the input signal 468 is "0" and the output of the decision block 414 is "0", then the phase selector input signal 476 (inc) will "lock" the phase selector 420 in the current state, where the output clock 372 is triggered from the minimum noise phase of the clock 371.

[0025] As an example, in operation, in response to the detection of the input attenuation signal 468, the speed controller 410 will slow down the output clock 372, causing the output clock 372 to be "stretched" and to have a frequency lower than the basic clock 370. If so, the output clock 372 will have a value of 1 (e.g., as a multiple of the frequency of the basic clock 370). However, due to voltage attenuation, the output clock will have a value of 0.7 or 0.8 (e.g., as a multiple of the frequency of the basic clock 370). Nevertheless, since the supply voltage (Vdd) will be stabilized, there will no longer be any problematic voltage attenuation, and therefore, no attenuation signal will be input to the speed controller circuit 410. Accordingly, the system 300 can return to a "normal" state, where the frequency of the output clock 372 corresponds to (i.e., approximately equivalent to) the frequency of the basic clock 370.

[0026] Referring to FIG. 5, FIG. 500 is shown, corresponding to FIG. 400 in FIG. 4 according to an example embodiment. In FIG. 5, compared to FIG. 4, in one embodiment, decision block 412 is represented by an "OR" logic gate 512, and decision block 414 is represented by a "NOR" logic gate 514. In an alternative embodiment, other equivalent circuit structures may be used for decision blocks 412 and 414. Thus, in a particular embodiment, the speed controller circuit 510 (i.e., corresponding to speed controller circuit 410) is configured to determine the quietest phase of the multiphase clock group as phase "0", which may include: an OR logic gate 512, a NOR logic gate 514, an AND logic gate 516, and a multiplexer 518 (i.e., a control switch). In an alternative embodiment, a lookup table may be used. The lookup table may be constructed from "memory" type elements or a multiplexer. Alternatively, any of the logic functions described herein may be constructed using only NAND gates, or, according to another implementation, only NOR gates.

[0027] In some embodiments, the speed controller circuit 510 may be coupled to the setting path of the phase selector circuit 520 (i.e., corresponding to the phase selector circuit 420). As illustrated, the circuit elements of the phase selector circuit 520 may be similar to other examples.

[0028] In one example, a register transfer level (RTL) description of a speed controller circuit may include: [email protected](d_fadc or d_bypass) begin if(d_bypass) phase_shift_speed <= 5'h00; else if(d_fadc[6]) phase_shift_speed <= 5'h07; else if(d_fadc[5]) phase_shift_speed <= 5'h06; else if(d_fadc[4]) phase_shift_speed <= 5'h05; else if(d_fadc[3]) phase_shift_speed <= 5'h04; else if(d_fadc[2]) phase_shift_speed <= 5'h03; else if(d_fadc[1]) phase_shift_speed <= 5'h02; else if(d_fadc[0]) phase_shift_speed <= 5'h01; else phase_shift_speed <= 5'h00; end

[0029] In some example implementations, the RTL description (i.e., RTL code) of the speed controller (such as 350, 410, 510 depicted with reference to Figures 3, 4, and 5) according to the example implementation includes: assign low_noise_shift = ~mask_phi1[0];[email protected](d_fadc or d_bypass or low_noise_shift) begin if(d_bypass) phase_shift_speed <= 5'h00; else if(d_fadc[6]) phase_shift_speed <= 5'h07; else if(d_fadc[5]) phase_shift_speed <= 5'h06; else if(d_fadc[4]) phase_shift_speed <= 5'h05; else if(d_fadc[3]) phase_shift_speed <= 5'h04; else if(d_fadc[2]) phase_shift_speed <= 5'h03; else if(d_fadc[1]) phase_shift_speed <= 5'h02; else if(d_fadc[0]) phase_shift_speed <= 5'h01; else if(low_noise_shift) phase_shift_speed <= 5'h01; else phase_shift_speed <= 5'h00;end

[0030] Advantageously, RTL code can be a description of digital hardware circuits and can be synthesized (i.e., converted) into digital circuits that perform the same operations.

[0031] Referring to FIG6, a diagram according to an exemplary embodiment is shown. As illustrated, the state machine operation 600 of the phase selector circuit is depicted before and after certain inventive states as described herein. As illustrated, the state machine depicts the operation of the phase selector when no voltage decay is detected. Accordingly, as shown, for example, eight different clocks (ph0 to ph7) are provided to trigger an adaptive clock circuit. For example, after randomly falling on a specific phase (e.g., phase 3, as shown in ph3), the adaptive clock circuit will remain on the same phase (e.g., ph3) (as shown by the dashed lines of each phase) without benefiting from the inventive states as described herein. However, in an embodiment of the circuit and method of the present invention as described herein, the adaptive clock circuit will initially fall on a specific phase (e.g., ph3), and then, subsequently, shift the phase sequentially (e.g., shift to ph4, then to ph5, then to ph6, then to ph7, then to ph0) until it reaches the minimum noise phase (e.g., ph0), and will remain there (e.g., stay at ph0) (as shown by the solid line of phase shifts) (i.e., incrementally changing the phase velocity).

[0032] Referring to FIG7, a flowchart of an example method 700 (i.e., procedure) for reducing noise / clock jitter is shown. Advantageously, in various embodiments, method 700 depicts a method for generating a "stretched" output clock and optimizing for output clock jitter. Method 700 can be implemented with reference to the circuit implementations and operations depicted in FIG1, FIG3, FIG4 and FIG5, and / or combinations thereof.

[0033] In block 710, the method includes generating two or more clock phases after a transient voltage is detected by the detector circuit. For example, referring to the various embodiments described in Figures 1 to 6, two or more clock phases (e.g., Ph[0] to Ph[7]; [m:0]) may be generated after a transient voltage is detected by the detector circuit (e.g., 120, 320).

[0034] In block 720, the method includes generating an output clock signal based on one of the two or more clock phases. For example, referring to the various embodiments described in Figures 1 to 6, an output clock signal (e.g., CPU_CLK, 172, 372) can be generated based on one of the two or more clock phases (e.g., Ph[0] to Ph[7]; [m:0]).

[0035] In block 730, the method includes changing a phase velocity of the output clock signal to correspond to a phase velocity of an input clock signal. For example, referring to the various embodiments described in Figures 1 to 6, a phase velocity of the output clock signal (e.g., CPU_CLK, 172, 372) may be changed (e.g., offset) (e.g., offset from ph(3) to ph(4), then to ph(5), then to ph(6), then to ph(7), and then finally to ph(0)) to correspond to a phase velocity (e.g., ph(0)) of an input clock signal (e.g., the basic clock 370).

[0036] Figure 8 illustrates an example hardware component in a computer system 800, which can be used to reduce noise clock jitter and generate a "stretched" output clock to optimize for output clock jitter. In some embodiments, the example computer system 800 (e.g., a network computer system and / or server) may include a circuit design tool 824 (i.e., a fine-grained adaptive clock circuit design tool) and is based on program execution software described with reference to method 700 in Figure 7. In some embodiments, the circuit design tool 824 may be included as a feature of existing memory compiler software programs.

[0037] In some cases, the circuit design tool 824 can provide a computer-aided physical layout design for the memory architecture. Programs (as described with reference to FIG7) can be stored as program code of instructions 817 in a computer-readable medium of storage device 816 (or alternatively, in memory 814), which can be executed by computer 810, or network computers 820, 830, other networked electronic devices (not shown), or combinations thereof. In some embodiments, each of computers 810, 820, 830 can be any type of computer, computer system, or other programmable electronic device. Furthermore, each of computers 810, 820, 830 can be implemented using one or more network computers (e.g., in a cluster or other distributed computing system).

[0038] In some embodiments, system 800 can be used with integrated circuit (IC) designs containing all standard cells, all blocks, or a mixture of standard cells and blocks. In a particular example embodiment, system 800 may include in its database structure: a collection of cell libraries, one or more technical files, a plurality of cell library format files, a set of top design format files, one or more Open Artwork System Interchange Standard (OASIS / OASIS.MASK) files, and / or at least one EDIF file. The database of system 800 may be stored in one or more of the memory 814 or storage device 816 of computer 810, or in network computers 820, 830.

[0039] System 800 can automatically perform the following functions via variable user input: after a transient voltage is detected by a detector circuit, generating two or more clock phases; generating an output clock signal based on one of the two or more clock phases; and changing (i.e., offsetting) a phase velocity of the output clock signal to correspond to a phase velocity of an input clock signal. In some cases, such functions can be performed substantially via user input control. Additionally, such functions can be used in conjunction with the manual capabilities of System 800 to produce the target results desired by the designer.

[0040] In one embodiment, computer 800 includes a processing unit 812 having at least one hardware-based processor coupled to memory 814. In some embodiments, processing unit 812 may include one or more of a central processing unit (CPU), a graphics processing unit (GPU), or a neural processing unit (NPU). Memory 814 may represent a random access memory (RAM) device of the main storage of computer 810, a supplemental level of memory (e.g., cache memory, non-volatile or backup memory (e.g., programmable or flash memory)), read-only memory, or a combination thereof. In addition to memory 814, computer system 800 may include other memory located elsewhere in computer 810, such as cache memory in processing unit 812, and any storage capacity used as virtual memory (e.g., stored on storage device 816 or on another computer coupled to computer 810).

[0041] Computer 810 can be further configured to externally transmit information. For interface with a user or operator (e.g., a circuit design engineer), computer 810 may include a user interface (I / F) 818 that integrates one or more user input devices (e.g., keyboard, mouse, touchpad, and / or microphone, etc.) and a display (e.g., monitor, liquid crystal display (LCD) panel, light emitting diode (LED), display panel, and / or speaker, etc.). In other instances, user input may be received via another computer or terminal. Furthermore, computer 810 may include a network interface (I / F) 815 that can be coupled to one or more networks 840 (e.g., wireless networks) to enable information communication with other computers and electronic devices. Computer 860 may include analog and / or digital interfaces between processing unit 812 and components 814, 815, 816, and 818. Additionally, other non-restrictive hardware environments can be used within the context of the instance implementation.

[0042] The computer 810 can operate under the control of the operating system 826 and can execute or otherwise depend on various computer software applications, components, programs, objects, modules, data structures, etc. (such as programs and related software associated with program 700). The operating system 828 can be stored in memory 814. The operating system includes, but is not limited to: UNIX® (a registered trademark of The Open Group), Linux® (a registered trademark of Linus Torvalds), Windows® (a registered trademark of Microsoft Corporation, Redmond, WA, United States), AIX® (a registered trademark of International Business Machines (IBM) Corp., Armonk, NY, United States), i5 / OS® (a registered trademark of IBM Corp.), and others that would be conceived by one of ordinary skill in the art. In the example of Figure 8, the operating system 826 is shown in memory 814, but the components of the aforementioned software may also be (or additionally) stored in non-volatile memory (e.g., on storage device 816 (data storage) and / or non-volatile memory (not shown). Furthermore, various applications, components, programs, objects, modules, etc., may also be executed on one or more processors in another computer coupled to computer 810 via network 840 (e.g., in a distributed or master-slave computing environment), where the processing of implementing the functions of the computer programs can be configured to multiple computers 820, 830 via network 840.

[0043] In the example implementation, the circuit diagrams and representations are provided in Figures 1 to 8, and their redundant descriptions are not repeated in the related descriptions of the analog circuit diagrams and representations. It is explicitly incorporated that, based on their corresponding figures(s), identical layout diagrams having the same symbols and / or reference numerals are included in each of the embodiments.

[0044] Although one or more of Figures 1 to 8 may illustrate a system, apparatus, or method according to the teachings of this disclosure, this disclosure is not limited to such illustrated systems, apparatus, or methods. One or more functions or components of any of Figures 1 to 8 illustrated or described herein may be combined with one or more other parts of the other of Figures 1 to 8. Therefore, the single embodiment described herein should not be construed as limiting, and embodiments of this disclosure may be suitably combined without departing from the teachings of this disclosure.

[0045] The present disclosure may be incorporated into systems, methods, and / or computer program products. A computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon for causing a processor to execute the present disclosure. The computer-readable storage medium may be a tangible means capable of holding and storing instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or raised structures in grooves with instructions recorded thereon), and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires. For example, memory 814, storage device 816, or both of them comprise tangible, non-transient computer-readable media or storage devices.

[0046] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to individual computing / processing devices or, via a network (e.g., the Internet, local area network, wide area network, and / or wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. Network adapters or network interfaces in each computing / processing device receive computer-readable program instructions from the network and forward such instructions for use on computer-readable storage media stored within the individual computing / processing device.

[0047] The computer-readable program instructions used to perform the operations disclosed herein may be compiler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, or similar, and program programming languages ​​such as "C" or similar. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network, or may establish a connection to an external computer (e.g., via the Internet using an Internet service provider). In some implementations, such as programmable logic circuit systems, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), electronic circuit systems can be personalized by executing computer-readable program instructions using state information of computer-readable program instructions to perform the state disclosed herein.

[0048] The embodiments disclosed herein are described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustration and / or block diagram, and combinations of blocks in the flowchart illustration and / or block diagram, can be implemented by computer-readable program instructions.

[0049] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to create a machine such that the instructions are executed by the processor of the computer or other programmable data processing device. The machine is an example of a component for implementing functions / behaviors specified in a flowchart and / or block diagram. The computer-readable program instructions can also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing device, and / or other apparatus to operate in a particular manner, such that the computer-readable storage medium having the instructions stored therein comprises an article of manufacture, the article of manufacture including instructions for implementing states of functions / behaviors specified in a flowchart and / or block diagram.

[0050] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other device to cause a series of operational steps to be performed on the computer, other programmable device, or other device to execute a computer-implemented program, such that the instructions executed on the computer, other programmable device, or other device perform the functions / actions specified in the flowchart and / or block diagram.

[0051] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing (multiple) specified logical functions. In some alternative embodiments, the functions mentioned in the blocks in the figures may not occur in the order mentioned in the figures. For example, depending on the functionality involved, two blocks shown consecutively may be executed substantially in parallel, or such blocks may sometimes be executed in reverse order. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions or implements a combination of dedicated hardware and computer instructions.

[0052] In the following description, numerous specific details are set forth to provide a thorough understanding of the disclosed concepts, which may be practiced without using some or all of these features. In other instances, details of known devices and / or procedures have been omitted to avoid unnecessarily obscuring this disclosure. Although some concepts will be described in conjunction with specific examples, it should be understood that such examples are not intended to be limiting.

[0053] Unless otherwise specified, the terms "first," "second," etc., are used herein only as designations and are not intended to impose ordinal, positional, or hierarchical requirements on the items referred to by these terms. Furthermore, the reference to an item "second" does not require or exclude, for example, the existence of an item "first" or a lower-numbered item and / or, for example, an item "third" or a higher-numbered item.

[0054] In this document, the reference to "one example" means that one or more features, structures, or characteristics described in that example are included in at least one embodiment. The phrase "one example" throughout this specification may or may not refer to the same example.

[0055] Illustrative, non-exhaustive examples of claims or non-claims of the subject matter of this disclosure are provided below. Different examples of the apparatus(s) and methods(s) disclosed herein include various components, features, and functionalities. It should be understood that the various examples of the apparatus(s) and methods(s) disclosed herein may include any components, features, and functionalities of any other examples of the apparatus(s) and methods(s) disclosed herein in any combination, and all such possibilities are intended to be within the scope of this disclosure. Numerous modifications to the examples set forth herein will be conceived by those skilled in the art to which this disclosure pertains and who benefit from the teachings shown in the foregoing description and related diagrams belong.

[0056] Therefore, it should be understood that this disclosure is not limited to the specific examples described, and is intended to include modifications and other examples within the scope of the appended claims. Furthermore, although the foregoing description and associated drawings describe examples of this disclosure in the context of certain illustrative combinations of elements and / or functions, it should be understood that different combinations of elements and / or functions may be provided by alternative embodiments without departing from the scope of the appended claims. Therefore, the reference numerals in parentheses in the appended claims are indicated for illustrative purposes only and are not intended to limit the scope of the claimed subject matter to the specific examples provided in this disclosure. [Simplified Explanation of the Diagram]

[0007] (Multiple) This technology will be further explained by way of example and reference to embodiments illustrated in the accompanying drawings. However, it should be understood that the drawings only illustrate various embodiments described herein and are not intended to limit the scope of the various technologies, methods, systems, circuits, or devices described herein. [Figure 1] is a schematic diagram of an example circuit and method implementation. [Figure 2] is a schematic diagram of an example circuit and method implementation. [Figure 3] is a schematic block diagram of an example circuit and method implementation. [Figure 4] is a schematic block diagram of an example circuit and method implementation. [Figure 5] is a schematic block diagram of an example circuit and method implementation. [Figure 6] is a schematic block diagram of an example circuit and method implementation. [Figure 7] is a flowchart of a specific illustrative form of an example method. [Figure 8] is a schematic block diagram of an example circuit and method implementation.

[0008] In the embodiments described below, reference is made to the accompanying drawings, which form a part thereof, wherein similar element symbols may designate corresponding or similar parts throughout. It should be understood that the drawings are not necessarily drawn to scale, for example, for simplicity and / or clarity. For example, the dimensions of some forms may be exaggerated relative to others. Furthermore, it should be understood that other embodiments may be used. In addition, structural changes and / or other variations may be made without departing from the claimed subject matter. The term "claimed subject matter" as used throughout this specification refers to the subject matter intended to be covered by one or more claims or any part thereof, and is not necessarily intended to refer to the complete set of claims, a particular combination of claims (e.g., a method claim, an apparatus claim, etc.), or a particular claim. It should also be noted that orientations and / or references (e.g., such as up, down, top, bottom, etc.) are used to assist in the discussion of the drawings and are not intended to limit the application of the claimed subject matter. Therefore, the embodiments described below should not be used to limit the claimed subject matter and / or equivalents.

Claims

1. A method of circuit operation comprising: detecting a transient voltage by means of a detector circuit to generate two or more clock phases; generating an output clock signal based on one of the two or more clock phases; and changing a phase velocity of the output clock signal to correspond to a phase velocity of an input clock signal by means of a speed controller circuit, wherein the speed controller circuit is configured to determine a minimum noise clock phase among the two or more clock phases.

2. The method of claim 1, wherein the phase velocity is changed based on a phase noise of the input clock signal to reduce a phase noise of the output clock signal.

3. The method of claim 1, wherein the phase velocity is altered to correspond to an approximate level of noise in an input clock signal.

4. The method of claim 1, wherein the phase velocity of the output clock signal is changed based on the determination that the phase velocity is higher than a phase velocity threshold.

5. The method of claim 4, wherein the phase velocity threshold corresponds to a phase velocity of the input clock signal.

6. The method of claim 1, wherein changing the phase velocity includes shifting from a first clock phase to a second clock phase, wherein the second clock phase includes noise at a level lower than the first clock phase.

7. The method of claim 6, wherein the second clock phase includes a minimum noise clock phase.

8. The method of claim 6, wherein changing the phase velocity includes shifting from a second clock phase to a third clock phase, wherein the third clock phase includes noise at a level lower than the second clock phase.

9. The method of claim 8, wherein the third clock phase includes a minimum noise clock phase.

10. The method of claim 1, wherein each of the plurality of clock phases corresponds to a different delay of a clock cycle.

11. The method of claim 1, wherein each of the plurality of clock phases is configured to initialize one leading edge of the output clock signal.

12. The method of claim 1, wherein the two or more clock phases comprise a plurality of clock phases of a multiphase clock group.

13. A circuit comprising: a detector circuit for monitoring a supply voltage of a transient voltage; after detecting the transient voltage, an input phase circuit configured to generate two or more clock phases; a phase selector configured to generate an output clock signal from at least one of the two or more clock phases; and a speed controller circuit configured to change a phase speed of the output clock signal to correspond to a phase speed of an input clock signal, wherein the speed controller circuit comprises: an OR gate, a NOR gate, an AND gate, and a multiplexer.

14. The circuit of claim 13 further comprises: a phase-locked loop circuit configured to provide a basic clock signal to the input phase circuit.

15. The circuit of claim 13, wherein the speed controller circuit is configured to determine whether an input signal from the detector circuit contains a voltage level higher than a voltage threshold, and whether the phase speed is higher than a phase speed threshold.

16. The circuit of claim 13, wherein changing the phase velocity includes shifting from a first clock phase to a second clock phase, wherein the second clock phase includes noise at a level lower than the first clock phase.

17. The circuit of claim 16, wherein the second clock phase includes a minimum noise clock phase.

18. A speed controller circuit comprising: an OR logic gate; a NOR logic gate; an AND logic gate; and a multiplexer, wherein the speed controller circuit is configured to determine whether an input signal from a detector circuit contains a voltage level higher than a voltage threshold, and whether a selected phase speed is higher than a phase speed threshold.

19. The speed controller circuit of claim 18, wherein the speed controller circuit is configured to receive the input signal corresponding to a detection signal and a phase selection signal, and is configured to transmit an output signal to verify a minimum noise output clock.

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