Semiconductor module and manufacturing method thereof, electroic device, electroic module and manufacturing method of electroic module

Abstract

A method for manufacturing a semiconductor module involves sealing a first bare die having a first bare die electrode, a second bare die having a second bare die electrode, a first connection portion connected to the first bare die electrode, and a second connection portion connected to the second bare die electrode with a sealing body, and then mounting a bridge circuit having a first bridge electrode and a second bridge electrode onto a structure sealed with the sealing body. The first bare die and the second bare die are electrically connected via the bridge circuit.

Description

[Technical Field]

[0001] This invention relates to a semiconductor module and its manufacturing method. [Previous Technology]

[0002] There are technologies for connecting multiple IC (Integrated Circuit) chips. For example, Patent Document 1 describes a semiconductor package in which two IC chips are connected together with an inserter using a molded bridge (nested component). Patent Document 2 describes a semiconductor package in which two IC chips are electrically connected by a bridge integrally formed with an inserter via an underfill material.

[0003] Existing Technical Documents

[0004] Patent Documents

[0005] Patent Document 1: U.S. Patent Application Publication No. 2021 / 0005542

[0006] Patent Document 2: U.S. Patent Application Publication No. 2020 / 0395313 [Summary of the Invention]

[0007] The problem the invention aims to solve

[0008] The inventors of this application have studied semiconductor packages having multiple IC chips connected via a bridge, and semiconductor modules using such semiconductor packages, and ultimately realized that there is room for improvement in the aforementioned semiconductor packages and semiconductor modules. For example, when two IC chips are electrically connected via a bridge integrated with an inserter, it is difficult to align the terminals of each of the two IC chips with the terminals of the bridge with high precision. In this case, the high density of the terminal portion that electrically connects the IC chips to the bridge is limited.

[0009] The present invention was made under the above-described conditions, and one of the exemplary objects of a certain form of it is to provide a technology that can combine IC chips and bridges with higher density.

[0010] Technical solution for solving the problem

[0011] A method for manufacturing a semiconductor module according to one embodiment includes the following processes: process (a), forming a first connection portion and a second connection portion on a first surface of a first support, the first connection portion including a first columnar connection portion extending in an outward direction from the first surface, and the second connection portion including a second columnar connection portion extending in an outward direction from the first surface; process (b), preparing a first semiconductor die and a second semiconductor die, the first semiconductor die having a first IC wafer and a first die electrode connected to the first IC wafer, the second semiconductor die having a second IC wafer and a second die electrode connected to the second IC wafer, and mounting the first semiconductor die and the second semiconductor die on the first support respectively, such that the first die electrode is disposed on the first connection portion and The second bare die electrode is disposed on the second connection portion; in process (c), after process (b), the first semiconductor bare die, the second semiconductor bare die, the first connection portion, and the second connection portion are sealed with a first sealing body; in process (d), after process (c), the first support is removed, and a portion of the first columnar connection portion and a portion of the second columnar connection portion are exposed from the first sealing body; and in process (e), a bridge is prepared, the bridge including a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion, and after process (d), the bridge is mounted on the structure sealed by the first sealing body, such that the first bridge electrode is disposed on the first columnar connection portion and the second bridge electrode is disposed on the second columnar connection portion.

[0012] As another embodiment, a method for manufacturing a semiconductor module includes the following processes: process (a), forming a first insulating layer on a first surface of a first support, and then forming a first opening and a second opening in the first insulating layer; process (b), forming a first connecting portion and a second connecting portion, the first connecting portion including a first columnar connecting portion formed in the first opening, and the second connecting portion including a second columnar connecting portion formed in the second opening; process (c), preparing a first semiconductor die and a second semiconductor die, the first semiconductor die having a first IC wafer, a first die electrode connected to the first IC wafer, and a second insulating layer sealing the first die electrode, the second semiconductor die having a second IC wafer, a second die electrode connected to the second IC wafer, and a third insulating layer sealing the second die electrode, and then preparing the first semiconductor die and the second semiconductor die. Two semiconductor dies are respectively mounted on the first support, such that the first die electrode is disposed on the first connection portion and the second die electrode is disposed on the second connection portion; process (d), after process (c), the first semiconductor die and the second semiconductor die are sealed with a first sealing body; process (e), after process (d), the first support is removed, and a portion of the first columnar connection portion and a portion of the second columnar connection portion are exposed from the first insulating layer; and process (f), a bridge is prepared, the bridge including a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion, after process (e), the bridge is mounted on the structure sealed by the first sealing body, such that the first bridge electrode is disposed on the first columnar connection portion and the second bridge electrode is disposed on the second columnar connection portion. In process (c), the first insulating layer and the second insulating layer are bonded to each other, and the first bare die electrode is sealed by the first insulating layer and the second insulating layer. In process (c), the first insulating layer and the third insulating layer are bonded to each other, and the second bare die electrode is sealed by the first insulating layer and the third insulating layer.

[0013] As another embodiment of the semiconductor module, it includes: a first semiconductor die having a first IC wafer and a first die electrode connected to the first IC wafer; a second semiconductor die having a second IC wafer and a second die electrode connected to the second IC wafer; a first connection portion electrically connected to the first die electrode; a second connection portion electrically connected to the second die electrode; a bridge having a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion; and a first sealing body sealing the first semiconductor die and the second semiconductor die. The first connection portion includes a first columnar connection portion disposed between the first semiconductor die and the bridge and extending in a direction from one of the first semiconductor die and the bridge towards the other. The first connection portion includes a second columnar connection portion disposed between the first semiconductor die and the bridge and extending in a direction from one of the first semiconductor die and the bridge towards the other. The first bridge electrode and the second bridge electrode are exposed from the first sealing body. The first columnar connecting part and the second columnar connecting part are respectively sealed by the first sealing body.

[0014] Another aspect of the present invention is an electronic device. The electronic device includes: a first die having a first electrode; a second die having a second electrode; a first connection portion electrically connected to the first electrode; a second connection portion electrically connected to the second electrode; and a bridge electrically connected to the first and second connection portions. The first connection portion has a columnar connection portion extending from the bridge toward the first die.

[0015] Another aspect of the present invention is an electronic module. The electronic module includes: the above-described electronic device; a wiring layer having wiring disposed therein; and a connection portion for electrically connecting the wiring to the electronic device.

[0016] Another aspect of the present invention is a method for manufacturing an electronic device. The method for manufacturing an electronic device includes the following processes: a forming process, forming a first connecting portion and a second connecting portion on a support body, each including a columnar connecting portion protruding from the support body; a die bonding process, bonding a first electrode of a first die to the first connecting portion, and bonding a second electrode of a second die to the second connecting portion; a sealing process, sealing the first die, the second die, and the first connecting portion with resin; and a bridge bonding process, bonding a bridge to the lower portion of the first connecting portion and the lower portion of the second connecting portion.

[0017] Furthermore, any combination of the above-mentioned constituent elements and any scheme in which the description of the present invention is transformed between methods, apparatus, systems, storage media, computer programs, etc., are also valid forms of the present invention.

[0018] Invention Effects

[0019] According to the above embodiments, IC chips and bridges can be combined at a higher density.

Implementation Method

[0021] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, a structure on which circuit elements such as transistors and wiring are formed on a semiconductor substrate is called an IC chip. IC chips include superconducting integrated circuits (quantum computers), etc. A structure on the main surface of an IC chip having stacked wiring layers is called a semiconductor die. Sometimes a rewiring layer is further formed on the IC chip, in which case the rewiring layer is included in the wiring layer. A structure in which multiple semiconductor dies are sealed together by a sealing body and thus integrated is called a chip integration module. A chip integration module also includes a bridge that electrically connects multiple semiconductor dies to each other. A structure in which multiple modules, including a chip integration module, are integrated is called a chip conglomerate. A chip conglomerate sometimes includes modules such as optical modules in addition to the chip integration module. A chip conglomerate sometimes includes multiple chip integration modules. In addition, a chip conglomerate sometimes includes a wide-area wiring layer that electrically connects multiple modules, and a heat dissipation mechanism or heat dissipation member that has the function of dissipating heat generated in each module to the outside. The portion of a chip assembly excluding heat dissipation components is called the integration layer. In the following explanation, a chip integration module is given as an example of a semiconductor module. Additionally, an integration layer is given as an example of a semiconductor package.

[0022] However, the scope of semiconductor modules and semiconductor packages is not limited to the definitions described above. For example, as shown in FIG1 described later, the wafer integration 10 is an electronic component (module) integrated within the wafer integration system 1. In this case, the wafer integration 10 can be regarded as a semiconductor module integrated within the wafer integration system 1. Furthermore, the wafer integration modules, integration layers, and wafer integrations described below may each include IC chips and be distributed as packaged semiconductor packages. Therefore, the forms of the wafer integration modules, integration layers, and wafer integrations can each be regarded as semiconductor packages.

[0023] <Chip Integration System>

[0024] FIG1 is a schematic diagram of a chip integration system according to an embodiment of the present invention. The chip integration system 1 of this embodiment includes a plurality of chip assemblies 10. These chip assemblies 10 are connected to each other by optical wiring 110. Optical wiring sometimes connects different chip assemblies, for example, but when the chip assemblies are large, it is sometimes used to connect different parts within the chip assemblies. The chip integration system 1 can be used, for example, in artificial intelligence systems that highly integrate various processors and memory. Furthermore, FIG1 shows two chip assemblies 10a and 10b, but the chip integration system 1 sometimes has three or more chip assemblies 10, or the chip integration system 1 is sometimes composed of only one chip assembly 10.

[0025] The chip integration assembly 10 is an assembly that internally includes multiple chip integration modules. The size of the chip integration modules is not particularly limited, but may range from approximately 50mm x 50mm to a maximum of approximately 300mm x 300mm. Here, the chip integration module is a semiconductor module that includes multiple IC chips. Figure 1 shows the area in the chip integration assembly 10 where the chip integration modules are arranged in dashed lines. In the example shown in Figure 1, there are 8 chip integration modules arranged vertically and 8 arranged horizontally, and the chip integration assembly 10 has a total of 64 chip integration modules. However, the number of chip modules included in the chip integration assembly 10 is not limited to this; there may be cases with fewer than 63 or more than 65.

[0026] The wafer integration 10 of this embodiment includes, for example, six optical modules. In the example shown in FIG1, the wafer integration 10 of this embodiment also includes an optical transceiver module (hereinafter referred to as "optical module"). 10a includes optical modules 11a, 12a, 13a, 14a, 15a, and 16a. The wafer integration 10b includes optical modules 11b, 12b, 13b, 14b, 15b, and 16b. The optical modules 11a-16a and 11b-16b shown in FIG1 correspond to the optical modules 11-16 shown in FIG2, which will be described later. These optical modules are connected to optical modules disposed in the same wafer integration 10 or optical modules disposed in other wafer integration 10 via optical wiring 110. As a representative example of optical wiring, optical fiber can be cited, but it is not limited to this. For example, a plate or sheet material on a plane with an optical waveguide can be used, or optical wiring utilizing free space can be used. In the chip integration system 1 of this embodiment, the signal in the chip integration body 10 is transmitted by light, so the signal transmission speed is higher than that of the case where only electrical signals are transmitted.

[0027] <Chip Integration>

[0028] FIG2 is a perspective view showing a structural example of the wafer integrated assembly shown in FIG1. ​​The wafer integrated assembly 10 of this embodiment includes an integration layer (also called a semiconductor package or electronic module) 100, optical modules 11-16 disposed on the upper surface of the integration layer 100, a heat dissipation mechanism 20 disposed on the upper surface of the integration layer 100, and external terminals 30 disposed on the lower surface of the integration layer 100.

[0029] Integration layer 100 is a layer with a stacked structure and multiple chip integration modules (also known as semiconductor modules or electronic devices). For a detailed description of the structure of integration layer 100, please refer to FIG3.

[0030] The heat dissipation mechanism 20 is a mechanism for dissipating heat generated in the chip integration 10. The heat dissipation mechanism 20 has the function of dissipating heat generated during operation, for example, by the multiple IC chips built into the integration layer 100 and the IC chips of the optical modules 11-16. In other words, the heat dissipation mechanism 20 can dissipate heat generated during operation, for example, by the integrated circuit chips of the integration layer 100 and the integrated circuit chips of the optical modules 11-16 (see Figure 2).

[0031] External terminal 30 is a terminal electrically connected to any one of the optical modules 11-16 or the chip integration module 40 (see FIG. 3 described later). In the example shown in FIG. 2, external terminal 30 is a solder ball and forms part of the electrical signal transmission path. In this embodiment, external terminal 30 can be used to supply power to the optical module or the chip integration module, or to input / output electrical signals to external devices. The shape of external terminal can be spherical as shown in FIG. 2, or it can be various shapes such as pin shape or pad shape.

[0032] Figure 3 is an explanatory diagram showing a structural example of the wafer integration shown in Figure 2. Figure 3 is a cross-sectional view of the wafer integration, but the cross-sectional lines are omitted for ease of observation. In addition, two of the 64 wafer integration modules shown in Figure 1 are illustrated in Figure 3.

[0033] The multiple optical modules 11-16 shown in FIG2 each have an optical transceiver, a connector, and a heat dissipation component. For example, the optical module 13 shown in FIG3 has an optical transceiver 130, a connector 132, and a heat dissipation component 136. The heat dissipation component 136 has a support plate (vaporizer) fixed on the optical transceiver 130 and multiple heat sinks fixed on the support plate and protruding in a direction away from the optical transceiver 130.

[0034] The optical transceiver 130 is an optoelectronic conversion component that performs the following functions: converting optical signals received via optical cable 110 (see Figure 1) into electrical signals; and converting electrical signals into optical signals and transmitting them to the outside via optical cable 110. A connector 132 is connected to the lower surface of the optical transceiver 130. Furthermore, the connector 132 is connected to an electrode 140 formed on the surface of the integration layer 100 via solder 138. The optical transceiver 130 can transmit and receive electrical signals with the integration layer 100 via the connector 132. Using the connector makes the optical transceiver easy to install and remove, and allows for rapid replacement in case of, for example, optical transceiver failure.

[0035] Furthermore, a heat dissipation member 136 is disposed on the upper surface of the optical transceiver 130. The heat dissipation member 136 is capable of dissipating heat from, for example, the optical transceiver 130. The heat dissipation member 136 includes a heat sink, on the upper surface of which a heat sink with a large surface area is disposed, achieving this with a small volume. The heat sink is capable of dissipating heat from, for example, the optical transceiver 130.

[0036] The heat dissipation mechanism 20 is supported on a support member 210 disposed on the surface of the integration layer 100. The heat dissipation mechanism 20 includes a support plate fixed to the support member 210 and a plurality of heat sinks fixed to the support plate and protruding in a direction away from the chip integration module 40. The heat dissipation mechanism 20 is thermally connected to the chip integration module 40 (in other words, a plurality of IC chips) disposed inside the integration layer 100 (specifically, inside the chip layer 104) via the support member 210. The support member 210 is, for example, a thermal interface material (TIM) and is thermally connected to the IC chips disposed inside the integration layer 100.

[0037] The integration layer 100 shown in Figure 3 includes a wide area wiring layer 102, a chip layer 104 and a connection layer 106.

[0038] The wide-area wiring layer 102 is a layer having a stacked structure composed of multiple layers. Each of the multiple layers in the wide-area wiring layer 102 has a conductor pattern such as wiring and an insulating layer covering the conductor pattern. The insulating layer is, for example, made of an insulating resin. The conductor pattern such as wiring is formed on the insulating layer of the substrate. Two wirings disposed in layers adjacent to each other in the thickness direction are electrically connected by vias. In the example shown in FIG3, the wide-area wiring layer 102 has four layers, and external terminals 30 are formed on the wirings disposed in the bottommost layer (the layer farthest from the wafer layer 104). Furthermore, the wirings disposed in the topmost layer of the wide-area wiring layer 102 (the layer closest to the wafer layer 104) are electrically connected to electrodes disposed in the wafer layer 104.

[0039] The wafer layer 104 is a layer that includes an insulating seal 105 and various conductors and functional elements embedded in the seal 105. For example, conductor pillars 146 and multiple wafer integration modules 40 are embedded in the seal 105. In the example shown in FIG3, an electrode 148 is provided on the lower surface of the conductor pillar 146, and the conductor pillar 146 is electrically connected to the wiring disposed on the uppermost layer of the wide-area wiring layer 102 via the electrode 148.

[0040] In the example shown in FIG3, the chip integration module 40 is electrically connected to the wiring disposed on the uppermost layer of the wide area wiring layer 102 via the conductor tall pillar 401 and electrode 403. Details of the structure of the chip integration module 40 will be described later with reference to FIG4.

[0041] The interconnect layer 106 is a layer that connects structural components disposed on the surface of the integration layer 100 to the wafer layer 104. For example, the interconnect layer 106 has a via 142 and an electrode 144 that connect the conductor pillar 146 of the wafer layer 104 to the electrode 140 electrically connected to the optical transceiver 130.

[0042] In addition, the connection layer 106 has metal contact portions 222 that are thermally connected to the plurality of chip integration modules 40 respectively, and the contact portions 222 are connected to the connecting portions 220 disposed inside the support member 210 of the heat dissipation mechanism 20. In this way, the chip integration module 40 of this embodiment is thermally connected to the heat dissipation mechanism 20 via the contact portions 222 and the connecting portions 220.

[0043] <Chip Integration Module>

[0044] FIG4 is an enlarged cross-sectional view showing a structural example of a portion of the wafer integration module shown in FIG3. As shown in FIG4, the wafer integration module 40 of this embodiment includes a semiconductor die 41, a semiconductor die 42, and a sealing body 45 for sealing the semiconductor die 41 and the semiconductor die 42. In addition, the wafer integration module 40 includes a bridge 43 that electrically connects the semiconductor die 41 and the semiconductor die 42. Furthermore, the wafer integration module 40 includes a connection portion 47 that electrically connects the semiconductor die 41 to the bridge 43 and a connection portion 48 that electrically connects the semiconductor die 42 to the bridge 43. The connection portion 47 and the connection portion 48 are each sealed by the sealing body 45. In addition, the semiconductor die 41 is electrically connected to the outside of the wafer integration module 40 (for example, the external terminal 30 shown in FIG3) via the connection portion 49.

[0045] The semiconductor die 41 includes an IC wafer 411 having a main surface 411t, and insulating layers 412 and 413 stacked on the main surface 411t of the IC wafer 411. The semiconductor die 41 has wiring 414 and wiring 415 electrically connected to the IC wafer 411. In addition, the semiconductor die 41 has a die electrode 416 connected to wiring 414 and a die electrode 417 connected to wiring 415. In the example shown in FIG4, the semiconductor die 41 has two insulating layers 412 and 413. However, the total number of insulating layers having the semiconductor die 41 is not limited to two layers, and sometimes, for example, there are three or more insulating layers.

[0046] The IC chip 411 includes a semiconductor substrate such as silicon and circuit elements such as transistors or diodes. As the integration form of the circuit elements within the IC chip 411, various forms can be adopted. For example, it is conceivable that the circuit elements are formed in two or three dimensions on the main surface 411t of the IC chip, or that the circuit elements are formed on each layer after the semiconductor substrate itself is stacked in multiple layers and connected by through-silicon vias (TSVs) that pass through the semiconductor substrate.

[0047] The semiconductor die 42 includes an IC wafer 421 having a main surface 421t and insulating layers 422 and 423 stacked on the main surface 421t of the IC wafer 421. The semiconductor die 42 has wiring 425 electrically connected to the IC wafer 421. In addition, the semiconductor die 42 has die electrodes 427 connected to the wiring 425. In the example shown in FIG4, the semiconductor die 42 has two insulating layers 422 and 423. However, the total number of insulating layers in the semiconductor die 42 is not limited to two layers, and sometimes it has, for example, three or more insulating layers and two or more wiring layers. In addition, the structure of the semiconductor die 42 is, for example, the same as the structure of the semiconductor die 41 described above.

[0048] The bridge 43 includes a wafer 431 having a main surface 431t and insulating layers 432 and 433 stacked on the main surface 431t of the wafer 431. The bridge 43 has wiring 434 formed on the insulating layer 432. The wafer 431 is formed, for example, from a semiconductor substrate such as a silicon wafer, but sometimes it is also formed from an inorganic material such as glass as a variation. However, the total number of insulating layers in the bridge 43 is not limited to two layers, and sometimes it has, for example, three or more insulating layers and two or more wiring layers. In addition, when the wafer 431 has a circuit, it is sometimes electrically connected to the wiring 434. The bridge 43 has bridge electrodes 436 connected to the connection portion 47 and bridge electrodes 437 connected to the connection portion 48. The bridge electrodes 436 and 437 are electrically connected to each other via the wiring 434.

[0049] The bridge 43 in this embodiment is a pillar-suspended bridge. In this embodiment, the wiring 434 is electrically connected to the wafer 431, and the wiring 434 and the wafer 431 are integrated to function as a bridge. However, as described later, the bridge 43 can function as a bridge circuit as long as it has the function of electrically connecting the semiconductor die 41 and the semiconductor die 42. Therefore, as a variation, there are cases where the wafer 431 is not present, or the wafer 431 and the wiring 434 are not electrically connected. Furthermore, in the example shown in FIG4, the bridge 43 has two insulating layers 432 and 433. However, the total number of insulating layers in the bridge 43 is not limited to two; sometimes, for example, it has three or more insulating layers.

[0050] The connection portion 47 includes a columnar connection portion 472. In the example shown in FIG4, the connection portion 47 has a columnar connection portion 472, a solder layer 473 connecting the columnar connection portion 472 and the bare die electrode 417, and a solder layer 474 connecting the columnar connection portion 472 and the bridge electrode 436.

[0051] The connection portion 48 includes a columnar connection portion 482. In the example shown in FIG4, the connection portion 48 has a columnar connection portion 482, a solder layer 483 connecting the columnar connection portion 482 and the bare die electrode 427, and a solder layer 484 connecting the columnar connection portion 482 and the bridge electrode 437.

[0052] In this embodiment, the columnar connector 472 and the columnar connector 482 are both columnar conductors with a μm dimension (also called "micropillars"). The main body of each of the columnar connectors 472 and 482 is made of a metal material, for example, with copper as the main component. At the interface between the columnar connector 472 and the solder layer 473 and the interface between the columnar connector 472 and the solder layer 474, an alloy layer is formed between a metal material, such as gold, which has higher oxidation resistance than the main body and in other words, a metal with a higher free energy for oxide formation, and a solder, such as tin as the main component. The alloy layer is formed by a eutectic reaction between the metal film formed at the interface between the columnar connector and the solder layer when the columnar connector 472 is joined to the solder layers 473 and 474. Details of the alloy layer will be described later.

[0053] Similarly, at each interface of the bonding interface between the columnar connector 482 and the solder layer 483 and the bonding interface between the columnar connector 482 and the solder layer 484, a bonding film with higher oxidation resistance than the main body and made of a metallic material such as gold is formed. However, there is also a situation where, when the columnar connector 482 is bonded to the solder layers 483 and 484, an alloy layer with the solder layers 483 and 484 is formed near the bonding film, and the original structural components of the bonding film diffuse within the solder layer.

[0054] In the example shown in FIG. 4, the connection portion 49 has an electrode 492 connected to the pillar 401 and a solder layer 493 connecting the electrode 492 to the bare die electrode 426. In the example shown in FIG. 4, the pillar 401 connected to the electrode 492 is not included in the wafer integration module 40, and is therefore shown as a dashed line. However, as a variation, the pillar 401 can also be considered as part of the wafer integration module 40.

[0055] In this embodiment, in the example shown in FIG4, the bridge electrode 436 and the bridge electrode 437 are each sealed by a separately formed sealing body 44 other than the sealing body 45. The sealing body 44 is, for example, bottom-filled resin. However, as a variation, a sealing body that seals the wafer 431 and the bridge electrodes 436 and 437 together can also be used. Alternatively, as another variation, there is a case where part of the sealing body 44 is replaced with the sealing body 105 shown in FIG3. As shown in FIG4, the structure in which the connecting portion 47 and the connecting portion 48 are sealed by the sealing body 45 and the bridge 43 is exposed from the sealing body 45 is a structure obtained by the manufacturing method of the wafer integration module 40 described below. The reasons why the structure shown in FIG4 can be obtained will be described in detail later.

[0056] Furthermore, in this embodiment, an example of a semiconductor bare die including a wafer 431 is described for the bridge 43. However, there are cases where the bridge does not include the wafer 431 and is mainly composed of wiring 434, insulating layers 432 and 433 embedded in the wiring, and bridge electrodes 436 and 437. Additionally, in this embodiment, the connecting portion 47 and the connecting portion 48 each have a columnar connecting portion 472 and 482, respectively. However, depending on the separation distance between the semiconductor bare die 41 and the bridge 43, there are also cases where the connecting portion 47 and the connecting portion 48 each have two or more stacked columnar connecting portions. There are also cases where the cross-sectional shape and cross-sectional area of ​​the stacked columnar connecting portions are different.

[0057] <Optical Module>

[0058] FIG5 is an explanatory diagram schematically showing a structural example of the optical module shown in FIG3. The optical module 13 of this embodiment mainly includes an optical system mechanism 131, an optical transceiver 130, and a connector 132. In addition, the optical module 13 has a mechanism for transmitting optical signals to the outside (hereinafter also referred to as "transmitting mechanism 13T") and a mechanism for receiving optical signals from the outside (hereinafter also referred to as "receiving mechanism 13R"). In FIG5, the transmitting mechanism 13T is shown on the left side relative to the plane of the drawing, and the receiving mechanism 13R is shown on the right side, but there are various variations in the positional relationship between the transmitting mechanism 13T and the receiving mechanism 13R other than the configuration shown in FIG5. In addition, the structure of the transmitting mechanism 13T will be described below, and sometimes the parts of the structure of the receiving mechanism 13R that are common to the structure of the transmitting mechanism 13T will be omitted from the description.

[0059] The optical system mechanism 131 of the transmitting mechanism 13T includes an optical fiber 600, a lens 601, a reflecting mechanism (mirror in FIG. 5) 602, and a lens 603. Light incident from the optical transceiver 130 onto the lens 603 passes through the lens 603 and is reflected at the reflecting mechanism 602. The reflected light passes through the lens 601 and is incident on the optical fiber 600. Thus, the optical signal is transmitted to the outside via the optical fiber 600.

[0060] The optical system mechanism 131 of the receiving mechanism 13R includes an optical fiber 610, a lens 611, a reflecting mechanism (mirror in FIG. 5) 612, and a lens 613. Light emitted from the optical fiber 610 passes through the lens 611 and is reflected by the reflecting mechanism 612. The reflected light passes through the lens 613 and is incident on the optical transceiver 130. Thus, the optical signal received by the optical fiber 610 is converted into an electrical signal and subjected to various processing. The lens and reflecting mechanism constituting the optical system mechanism 131 can be appropriately added or removed based on design requirements. For example, the optical fiber can be directly combined with the optical element chip of the optical transceiver without passing through the lens and reflecting mechanism, and depending on the situation, it can also be directly combined with the light-emitting element or the light-receiving element.

[0061] The optical transceiver 130 mainly includes a wafer layer 620, a wiring layer 630, two optical element wafers 605 and 615 disposed on the wiring layer 630, a light-emitting element 606, and a light-receiving element 616. In this embodiment, the two optical element wafers 605 and 615, the light-emitting element 606, and the light-receiving element 616 are electrically connected to the wiring layer 630, and the connection is sealed by a bottom-filled resin 607 or the like. In other words, in this embodiment, the two optical element wafers 605 and 615, the light-emitting element 606, and the light-receiving element 616 are fixed by a fixing member (bottom-filled resin 607) made of resin or the like.

[0062] The wiring layer 630 in this embodiment is, for example, composed of a two-layer structure. Conductor patterns such as wiring and electrodes are formed in each layer of the wiring layer 630. In addition, the wafer layer 620 includes an optical element driver wafer 621 and an optical element driver wafer 622. The optical element driver wafers 621 and 622 are wafers that control the driving of the optical element wafers 605 and 615, respectively. The optical element driver wafers 621 and 622 may also include functions such as converting the electrical signal level (voltage, current) required for appropriate optical-to-electrical conversion of the optical element and the electrical signal level entering and exiting from outside the optical transceiver.

[0063] The light-emitting element 606 of the transmitting mechanism is an element disposed on the surface of the light element chip 605 and emitting a light signal in response to the electrical signal transmitted from the light element chip 605. The light signal emitted by the light-emitting element 606 is incident on the lens 603 of the optical system mechanism 131.

[0064] The optical element chip 605 is connected to the electrode 631 formed on the upper layer of the wiring layer 630 via the electrode terminal 608 and the solder layer 609, and the optical element driver chip 621 is connected to the electrode 633 formed on the lower layer of the wiring layer 630 via the electrode terminal 623 and the solder layer 634. Therefore, the optical element chip 605 and the optical driver chip 621 are electrically connected via the wiring layer 630. This structure enables multiple parallel and short-distance connections with a substantially vertical electrical connection within the wiring layer 630 between the optical element chip and the optical driver chip. This enables broadband signal transmission between the optical element group and the optical driver chip arranged in a two-dimensional array. Furthermore, the solder layer 634 is not necessary according to the manufacturing method of the optical transceiver. In addition, by arranging the electrode terminal 608, the via 632, and the electrode terminal 623 in a substantially straight line, the electrical connection path length between the optical element chip and the optical driver chip can be minimized, and excellent electrical connections with low parasitic impedance can be achieved.

[0065] A metal layer 629 made of metal is formed on the underside of the optical element driver chip 621. The metal layer 629 is thermally connected to a via 641 provided on the connector 132 via a bonding member 640. Thus, the heat generated by the optical element driver chip 621 during operation is dissipated via the bonding member 640 in the direction of the arrow schematically shown in FIG. 5 (from the metal layer 629 toward the connector 132). Furthermore, the presence of the metal layer 629 is preferable for heat dissipation, but its presence is not necessary to achieve the desired effect.

[0066] The via 641 of connector 132 is connected to an electrode 140 formed on the surface of connection layer 106 via solder layer 642. Additionally, as shown in FIG3, electrode 140 is connected to electrode 148 via via 142, and electrode 148 is connected to a conductor post 146 formed in wafer layer 104. Thus, heat dissipated by connector 132 is cooled by conductor post 146.

[0067] An electrode terminal 624 is formed on the upper surface of the optical element driver chip 621. The electrode terminal 624 is connected to an electrode 626 formed on the lower side of the wiring layer 630 via a solder layer or a conductor connection portion 625. Additionally, a wiring 635 is formed on the wiring layer 630. The wiring 635 is connected to the electrode 626 electrically connected to the optical element driver chip 621 via a via 636. Furthermore, the wiring 635 is connected to an electrode 627, which is coupled to a conductor post 628 formed in the chip layer 620, via a via 637.

[0068] The conductor post 628 is electrically connected to the guide hole 644 of the connector 132 via the connecting member 643. In the example shown in FIG. 5, electrical signals are transmitted between the optical transceiver 130 and the connector 132, for example, through the connecting member 643. However, as a variation, sometimes the direction of transmission of electrical signals between the optical transceiver 130 and the connector 132 is either in one direction. That is, in the case of the transmitting mechanism 13T, electrical signals are transmitted from the connector 132 toward the optical transceiver 130, and in the case of the receiving mechanism 13R, electrical signals are transmitted from the optical transceiver 130 toward the connector 132.

[0069] <Manufacturing Method of Chip Integration Module>

[0070] Next, the manufacturing method of the chip integration module 40 shown in FIGS. 3 and 4 will be described. Before describing the manufacturing method of the chip integration module of this embodiment, a brief overview of the manufacturing method researched by the inventors of this application will be given. FIG. 6 is an explanatory diagram showing an overview of the manufacturing method of the chip integration module as a research example for this embodiment.

[0071] In the manufacturing method of the wafer integration module shown in FIG6, firstly, as shown in the upper part of FIG6, multiple semiconductor dies 51 and a bridge structure 52 are prepared. The bridge structure 52 is a structure in which multiple bridges 520 and multiple connecting portions 521 are sealed together by a sealing body 523. In the example shown in FIG6, multiple pillars 401 are sealed together with multiple bridges 520 by the sealing body 523.

[0072] Next, as shown in the middle part of FIG6, a plurality of semiconductor bare dies 51 are mounted on the bridge structure 52. At this time, the plurality of bare die electrodes 511 of the semiconductor bare dies 51 are respectively connected to the plurality of connection portions 521 of the bridge structure 52.

[0073] Next, as shown in the lower part of FIG6, a plurality of semiconductor dies 51 are sealed with a sealing body 512, thereby integrating the plurality of semiconductor dies 51 and the bridge structure 52 to obtain a wafer integration module 50.

[0074] In the case of the research example shown in FIG6, by pre-integrating multiple bridge structures 52, the operation of electrically connecting multiple semiconductor dies 51 and multiple bridges 520 can be made efficient.

[0075] However, it is understood that the manufacturing method shown in FIG. 6 presents the following concerns. Specifically, due to the shrinkage or expansion of the sealing body 523 constituting the bridge structure 52, it is difficult to improve the positional accuracy of each of the plurality of connecting portions 521. As a countermeasure to this problem, it is possible to increase the area of ​​the joint interface of each of the plurality of connecting portions 521 and increase the allowable margin for misalignment. However, in this case, it is also necessary to increase the spacing between adjacent connecting portions 521, thus hindering the high density of the connecting portions 521. That is, it limits the high density of the terminal portions that electrically connect the semiconductor die 51 to the bridge 520.

[0076] As described above, the reason why it is difficult to improve the positional accuracy of the multiple connecting parts 521 can be attributed to the large volume of the sealing body 523. Although it is also considered to reduce the linear expansion coefficient of the sealing body 523 by mixing inorganic filler particles as described later into the sealing body 523, this countermeasure also has limitations.

[0077] In view of the above research results, the inventors of this application have discovered a method for manufacturing a chip integration module according to this embodiment. The manufacturing method will be described in detail later, but the method for manufacturing a chip integration module according to this embodiment involves preparing a structure in which multiple semiconductor dies and multiple interconnects are integrated by a sealing body, and mounting multiple bridges onto this structure. The volume of the sealing body in the structure integrating multiple semiconductor dies and multiple interconnects can be reduced compared to the volume of the sealing body 523 in the bridge structure 52 shown in FIG. 6. In particular, by reducing the gap between adjacent IC chips, the effects of thermal shrinkage and thermal expansion can be reduced. As a result, according to the method for manufacturing a chip integration module according to this embodiment, the positional accuracy of each of the multiple interconnects can be improved, thus enabling high-density terminal portions that electrically connect semiconductor dies and bridges.

[0078] Hereinafter, a method for manufacturing a chip integration module according to this embodiment will be described in detail. FIG7 is an explanatory diagram showing an outline of the manufacturing process of the chip integration module shown in FIG4. As shown in FIG7, the method for manufacturing a chip integration module according to this embodiment includes a connector forming process, a semiconductor die mounting process, a first sealing process, a support removal process, a connector exposure process, a bridge mounting process, and a second sealing process.

[0079] The connection forming process shown in FIG7 includes the processes shown in FIG8 to FIG12. FIG8 to FIG12 are enlarged cross-sectional views showing details of the connection forming process shown in FIG7. In the connection forming process, as shown in FIG11, a connection 47 and a connection 48 are formed on the upper surface 70t of the support 70. The connection 47 includes a columnar connection 472 extending in the out-of-plane direction to the upper surface 70t, and the connection 48 includes a columnar connection 482 extending in the out-of-plane direction to the upper surface 70t.

[0080] In detail, firstly, as shown in FIG8, a support 70 having an upper surface 70t is prepared. A release layer 71 and a seed layer 72 are pre-formed on the upper surface 70t of the support 70. The support 70 can be any rigid plate material that does not impair workability in the various processes prior to the support removal process shown in FIG7, and the material is not particularly limited. For example, semiconductor substrates such as silicon wafers, plates made of inorganic materials such as glass or sapphire substrates, resin plates, etc. However, considering the expansion caused by heating during connection, it is preferable that the linear expansion coefficient of the support is close to the linear expansion coefficient of the semiconductor bare die.

[0081] The release layer 71 is a functional layer capable of peeling off the support 70 during the support removal process shown in FIG. 7. Various materials are selected to correspond to various methods such as peeling by energy beams such as lasers or mechanical peeling. The seed layer 72 is a seed film used as a substrate for forming conductor components such as connectors 47, 48, and 49 by electroplating. The seed layer 72 can be formed, for example, by sputtering copper onto the release layer 71.

[0082] Next, as shown in FIG9, a resist mask 73 is formed on the upper surface 70t of the support 70, specifically on the seed layer 72. For example, multiple openings 73H are formed on the resist mask 73 using photolithography.

[0083] Next, as shown in FIG10, a metal film is deposited in the opening 73H of the resist mask 73 by electroplating or the like, thereby forming the connecting portion 47, connecting portion 48, and connecting portion 49. Since a seed layer 72 is pre-formed on the upper surface 70t of the support 70, a portion of the connecting portion 47 (i.e., columnar connecting portion 472), a portion of the connecting portion 48 (i.e., columnar connecting portion 482), and a portion of the connecting portion 49 (i.e., electrode 492) can be formed by, for example, electroplating. In the example shown in FIG10, the columnar connecting portion 472 includes a main body portion 472A and a metal film 472B. The columnar connecting portion 482 includes a main body portion 482A and a metal film 482B. The electrode 492 includes a main body portion 492A and a metal film 492B. The main bodies 472A, 482A, and 492A are, for example, made of copper, and the metal films 472B, 482B, and 492B are, for example, made of a metal material with higher oxidation resistance than copper, such as gold. The metal films 472B, 482B, and 492B respectively prevent oxidation of the bonding surfaces of the copper main bodies 472A, 482A, and 492A, and enable flux-free soldering in the semiconductor die mounting process described later.

[0084] Next, as shown in FIG11, the resist mask 73 is removed (see FIG10). Removing the resist mask 73 exposes the side surfaces of the connectors 47, 48, and 49, as well as a portion of the upper surface of the seed layer 72. The semiconductor die mounting process shown in FIG7 can also be performed in the state shown in FIG11, but as shown in FIG12, it is preferable to include a process that forms an oxide film 72A on the side surfaces of the connectors 47, 48, and 49, as well as the exposed surfaces of the seed layer 72. By forming the oxide film 72A before the semiconductor die mounting process, it is possible to prevent solder from wetting and spreading to the side surfaces of the connectors during the semiconductor die mounting process, thus preventing unstable bonding shapes. When the process includes forming the oxide film 72A on the side surfaces of the connectors 47, 48, and 49, as well as the exposed surfaces of the seed layer 72, as shown in FIG4, the side surfaces of the connectors 47, 48, and 49 are covered by the oxide film 72A. In this process, even without forming an oxide film 72A, there are cases where the oxide film 72A shown in FIG4 is not formed, such as FIG24 described later.

[0085] Methods for forming the oxide film 72A can be exemplified by the following methods. For example, one method is to expose the oxide film 72A to an oxygen-containing atmosphere while the resist mask 73 shown in FIG10 is removed. Alternatively, as a method to form the oxide film 72A in a shorter time, one method is to heat the sides of the connecting portions 47, 48, and 49 and the exposed surface of the seed layer 72 in an oxygen-containing atmosphere. Furthermore, in FIG12, the oxide film 72A is shown as thicker for easier observation, but the oxide film 72A only needs to be formed thinly on the sides of the connecting portions 47, 48, and 49 and the exposed surface of the seed layer 72.

[0086] The semiconductor die mounting process shown in FIG7 includes the processes shown in FIG13 to FIG15. FIG13 to FIG15 are enlarged cross-sectional views showing details of the semiconductor die mounting process shown in FIG7. As shown in FIG15, in the semiconductor die mounting process, a semiconductor die 41 having an IC wafer 411 and a die electrode 417 connected to the IC wafer 411, and a semiconductor die 42 having an IC wafer 421 and a die electrode 427 connected to the IC wafer 421 are prepared. In addition, in the semiconductor die mounting process, the semiconductor die 41 and the semiconductor die 42 are respectively mounted on the support 70, such that the die electrode 417 is disposed on the connection portion 47 and the die electrode 427 is disposed on the connection portion 48.

[0087] In detail, firstly, semiconductor bare die 41 and semiconductor bare die 42 are prepared as shown in FIG. 13. The detailed structure of semiconductor bare die 41 and semiconductor bare die 42 has been explained using FIG. 4, so repeated explanation is omitted. Next, as shown in FIG. 13, semiconductor bare die 41 and semiconductor bare die 42 are respectively aligned with the support body 70 so that bare die electrode 417 is disposed on the connecting portion 47 and bare die electrode 427 is disposed on the connecting portion 48. Solder layer 473 is formed on the bare die electrode 417 of semiconductor bare die 41. Solder layer 493 is formed on the bare die electrode 416 of semiconductor bare die 41. Solder layer 483 is formed on the bare die electrode 427 of semiconductor bare die 42.

[0088] Next, as shown in FIG14, the bare die electrode 417 of the semiconductor bare die 41 is pressed onto the connection portion 47 via the solder layer 473. At this time, the bare die electrode 416 of the semiconductor bare die 41 is pressed onto the connection portion 49 via the solder layer 493. Similarly, the bare die electrode 427 of the semiconductor bare die 42 is pressed onto the connection portion 48 via the solder layer 483. In this process, the solder layer 473 and the columnar connection portion 472 of the connection portion 47 are temporarily bonded by solid-state diffusion bonding. Similarly, the solder layer 493 and the electrode 492 of the connection portion 49 are temporarily bonded by solid-state diffusion bonding. Similarly, the solder layer 483 and the columnar connection portion 482 of the connection portion 48 are temporarily bonded by solid-state diffusion bonding.

[0089] Next, the bonding interfaces between the solder layer 473 and the metal film 472B of the columnar connection portion 472, the solder layer 493 and the metal film 492B of the electrode 492, and the solder layer 483 and the metal film 482B of the columnar connection portion 482, as shown in FIG. 14, are heated to the melting temperature of the solder and maintained at that temperature. This generates a liquid phase at each bonding interface. As shown in FIG. 15, alloy layers 472D, 482D, and 492D are formed at each bonding interface. While maintaining the temperature at which the liquid phase is generated, elements in the liquid phase diffuse toward the alloy layer side, thereby increasing the melting point of the liquid phase. As a result, the liquid phase partially solidifies. This bonding method is called liquid phase diffusion bonding. As in this embodiment, when a temporary bonding based on solid phase diffusion bonding is combined with a bonding phase based on liquid phase diffusion bonding, a thermally stable bonding state can be firmly achieved without flux during the solder bonding process. In the case of reflow bonding using flux, flux residue is more likely to remain around the joint in such a fine joint as in this embodiment. On the other hand, in this embodiment, since no flux residue remains, the cleaning process can be omitted. Furthermore, the process of cleaning and removing flux residue becomes difficult due to the miniaturization and high density of the joint. In this embodiment, since cleaning flux residue is not required, miniaturization and high density of the joint can be achieved. In addition, depending on the size and arrangement of the joint, as options for the bonding process, besides the above, conventional soldering (tin soldering), flux soldering, and solid-phase diffusion bonding of metals to each other are sometimes used.

[0090] During soldering, it is preferable to suppress the wetting and diffusion of solder components in each solder layer on the sides of the columnar connection. This is because if solder components wet and diffuse on the sides of the columnar connection or the upper surface of the seed layer 72, the shape of the joint will be unstable, or the solder is more likely to have an adverse effect on the seed layer or the release layer. In this embodiment, as described above, an oxide film 72A is formed on the sides of the columnar connection and the exposed surface of the seed layer 72. In this case, the wetting and diffusion of solder components can be suppressed, and therefore the bare die electrode can be bonded to the connection with a small amount of solder.

[0091] In the first sealing process shown in FIG. 7, after the semiconductor die mounting process, as shown in FIG. 16, the semiconductor die 41, semiconductor die 42, connector 47, and connector 48 are sealed with a sealing body 45. FIG. 16 is an enlarged cross-sectional view showing details of the first sealing process shown in FIG. 7. In this process, the semiconductor die 41, semiconductor die 42, connector 47, and connector 48 are integrated with the sealing body 45. In addition, in the example shown in FIG. 16, the connector 49 is also sealed with the sealing body 45. The sealing body 45 includes a resin material such as a thermosetting resin. As a variation of the sealing body 45, as described later, the resin sometimes contains a large number of inorganic filler particles.

[0092] In the wafer integration module 40 shown in FIG. 4, the separation distance between semiconductor die 41 and semiconductor die 42 is relatively narrow. For example, in the example shown in FIG. 16, the separation distance G1 between semiconductor die 41 and semiconductor die 42 is shorter than the shortest distance G2 from the upper surface 70t of the support 70 to the portion of semiconductor die 41 excluding die electrodes 416 and 417. In addition, the IC wafer occupying most of semiconductor die 41 and semiconductor die 42 is made of a semiconductor material with a very low coefficient of linear expansion compared to the sealing body 45. Therefore, even if the sealing body 45 undergoes thermal expansion or contraction, the positions of the die electrodes 416, 417, and 427 are not easily affected. Furthermore, the connecting portions 47, 48, and 49 are fixed to semiconductor die 41 or semiconductor die 42 before the first sealing process. Therefore, the connecting portions 47, 48, and 49 can maintain high positional accuracy even when sealed by the sealing body 45. Therefore, in this embodiment, it is not easy to encounter the problem of difficulty in improving the positional accuracy of the multiple connection portions 521 of the bridge structure 52, as illustrated in FIG6.

[0093] In the support removal process shown in FIG. 7, after the first sealing process, as shown in FIG. 17, the support 70 is removed (refer to FIG. 16). FIG. 17 is an enlarged cross-sectional view showing details of the support removal process shown in FIG. 7. In this process, energy is applied to the release layer 71 with a laser or the like, causing the release layer 71 to decompose (ablate), significantly reducing the adhesion of the release layer 71 to the support, thereby making it easy to peel off the support 70. In addition, mechanical stress can also be used to peel off the release layer in the support removal process.

[0094] In the connection exposure process shown in FIG. 7, after the support removal process, as shown in FIG. 18, a portion (lower surface) of the columnar connection 472 and a portion (lower surface) of the columnar connection 482 are exposed from the sealing body 45. FIG. 18 is an enlarged cross-sectional view showing details of the connection exposure process shown in FIG. 7. In this process, for example, the release layer 71 and the seed layer 72 shown in FIG. 17 are removed by etching. In addition, in this process, the portion of the oxide film 72A formed on the upper surface of the seed layer 72 shown in FIG. 17 is removed. In the example shown in FIG. 18, in this process, a portion (lower surface) of the electrode 492 is also exposed from the sealing body 45.

[0095] In this process, as shown in FIG19, after the connecting portion is exposed from the sealing body 45, it is preferable to form metal films 472C, 482C, and 492C on the exposed surfaces of each connecting portion. FIG19 is an enlarged cross-sectional view showing details of the connecting portion exposure process immediately following FIG18. As shown in FIG19, in this process, metal film 472C is formed on the exposed surface of the columnar connecting portion 472 exposed from the sealing body 45. Similarly, metal film 482C is formed on the exposed surface of the columnar connecting portion 482 exposed from the sealing body 45. Metal film 492C is formed on the exposed surface of the electrode 492 exposed from the sealing body 45. Metal films 472C, 482C, and 492C respectively have the function of preventing oxidation of the bonding surfaces of the copper-based main body portions 472A, 482A, and 492A, and the function of enabling low-temperature bonding by eutectic reaction with solder, which is mainly composed of tin, in the semiconductor bare die mounting process described later. For example, metal films 472C, 482C, and 492C are made of a metal material (e.g., gold) with higher oxidation resistance than the materials of the main bodies 472A, 482A, and 492A, just like metal films 472B, 482B, and 492B. Gold is an example of a metal material possessing the aforementioned functions. By providing metal films 472C, 482C, and 492C, the aforementioned welding can be performed in the bridge mounting process shown in FIG. 7.

[0096] The bridge mounting process shown in FIG7 includes the processes shown in FIG20-22. FIG20-22 are enlarged cross-sectional views showing details of the bridge mounting process shown in FIG7. In the bridge mounting process, as shown in FIG22, a bridge 43 is prepared, which includes a bridge electrode 436 connected to the connecting portion 47 and a bridge electrode 437 connected to the connecting portion 48. In addition, in the bridge mounting process, after the connecting portion is exposed, the bridge 43 is mounted on the structure sealed by the sealing body 45, such that the bridge electrode 436 is disposed on the columnar connecting portion 472 and the bridge electrode 437 is disposed on the columnar connecting portion 482.

[0097] In detail, firstly, as shown in FIG20, a bridge 43 is prepared. The detailed structure of the bridge 43 has already been explained using FIG4, so a repeating description is omitted. Next, as shown in FIG20, the bridge 43 is aligned with the structure sealed by the sealing body 45, such that the bridge electrode 436 is disposed on the columnar connection portion 472 and the bridge electrode 437 is disposed on the columnar connection portion 482. A solder layer 474 is formed on the bridge electrode 436. A solder layer 484 is formed on the bridge electrode 437.

[0098] Next, as shown in FIG21, the bridge electrode 436 of the bridge 43 is pressed onto the columnar connection portion 472 of the connection portion 47 via the solder layer 474. At this time, the bridge electrode 437 of the bridge 43 is pressed onto the columnar connection portion 482 of the connection portion 48 via the solder layer 484. In this process, the solder layer 474 and the columnar connection portion 472 of the connection portion 47 (more specifically, the metal film 472C of the columnar connection portion 472) are temporarily bonded by solid-state diffusion bonding. Similarly, the solder layer 484 and the columnar connection portion 482 of the connection portion 48 (more specifically, the metal film 482C of the columnar connection portion 482) are temporarily bonded by solid-state diffusion bonding.

[0099] Next, the bonding interfaces between the solder layer 474 and the metal film 472C of the columnar connection portion 472 shown in FIG. 21, and the bonding interfaces between the solder layer 484 and the metal film 482C of the columnar connection portion 482, are bonded by liquid phase diffusion bonding. The liquid phase diffusion bonding method is as described above, so repeated descriptions are omitted. To perform liquid phase diffusion bonding, as shown in FIG. 22, the metal films 472C and 482C shown in FIG. 21 are respectively alloy layers 472E and 482E formed by a eutectic reaction between tin, which is the main component of the solder layer, and a metal film material (e.g., gold). In addition, including the semiconductor die mounting process described above, if flux residue can be cleaned, solder reflow processing using flux is sometimes performed instead of the combination of solid phase diffusion bonding and liquid phase diffusion bonding described above.

[0100] However, as in this embodiment, when the solder layers 473 and 483, which bond the columnar connectors 472 and 782 to the bare die electrodes 417 and 427 during the bridge mounting process, are already sealed by the sealing body 45, liquid phase diffusion bonding is particularly preferred from the viewpoint of preventing the sealed solder layers 473 and 483 from melting. If liquid phase diffusion bonding is used, the interface between the solder layer 474 and the columnar connector 472, and the interface between the solder layer 484 and the columnar connector 482, can be bonded at a temperature lower than the melting point of the solder layers 473 and 483, respectively.

[0101] In the second sealing process shown in FIG. 7, after the bridge mounting process, as shown in FIG. 23, the bridge electrodes 436 and 437 are sealed using a sealing body 44. FIG. 23 is an enlarged cross-sectional view showing details of the second sealing process shown in FIG. 7. In the example shown in FIG. 23, the sealing body 44 is a bottom-filling resin embedded between the bridge 43 and the sealing body 45. By sealing the bridge electrodes 436 and 437 using the sealing body 44, a portion of the columnar connecting portions 472 and 482 exposed from the sealing body 45 can be protected.

[0102] However, the configuration shown in FIG23 has various variations. For example, sometimes the second sealing process shown in FIG7 is omitted and the semiconductor module in the state shown in FIG22 is shipped as a product. Or, as a variation shown in FIG24, sometimes the bridge electrode 436 and bridge electrode 437 are sealed together with the conductor pillar 401 by the sealing body 105. This sealing process is usually called shaped underfill (MUF). In this variation, a process for forming the pillar 401 is required before the second sealing process. For example, it is preferable to perform the process of forming the pillar after the connection exposure process and before the bridge mounting process. As a method for forming the pillar 401, it can be performed in the same way as the connection forming process described using FIG8 to FIG12. That is, a resist mask is formed on the lower surface 45b of the sealing body 45 shown in FIG24. An opening is formed at the position where the resist mask overlaps with a part of the connection 49. A metal film is deposited inside the opening of the shield using electroplating or similar methods to form a high pillar 401. In this case, the high pillar 401 is formed directly on the electrode 492.

[0103] In the modified example shown in FIG24, the entire wafer layer 104, the entire integration layer 100, or the entire wafer integration body 10 shown in FIG3 can also be regarded as a semiconductor module.

[0104] As shown in FIG7, after integrating multiple semiconductor dies in the first sealing process, when performing the bridge mounting process, multiple die electrodes and multiple connectors can be configured with high positional accuracy, thus enabling high-density bonding of IC chips and bridges. Furthermore, as illustrated in FIG4, the structure in which a sealing body 45 seals the connectors 47, 48, semiconductor die 41, and semiconductor die 42 respectively can be obtained using the manufacturing methods described in FIGS. 7 to 24.

[0105] <Example of a modified sealing body>

[0106] Next, modified examples of the sealing bodies 45 and 44 shown in FIG4 will be described. FIG25 to FIG27 are enlarged cross-sectional views showing modified examples of the sealing bodies shown in FIG4.

[0107] In the wafer integration module 40A shown in FIG. 25, the sealing bodies 45A and 44A are different from those in the wafer integration module 40 shown in FIG. 4. The sealing body 45A contains a plurality of filler particles 451, and the sealing body 44A contains a plurality of filler particles 441. The average particle size of the plurality of filler particles 451 is larger than the average particle size of the plurality of filler particles 441. By including a plurality of filler particles 451 with a larger average particle size in the sealing body 45A as in this modified example, the linear expansion coefficient of the sealing body 45A as a whole can be reduced. As a result, the positional accuracy of the connector 47 and the connector 48 can be further improved in the bridge mounting process described in FIG. 7 and FIG. 20-22. In addition, the plurality of filler particles 451 are premixed in the sealing resin used in the first sealing process of FIG. 7. Similarly, the plurality of filler particles 441 are premixed in the sealing resin used in the second sealing process shown in FIG. 7.

[0108] In the chip integration module 40B shown in FIG. 26, the sealing bodies 45B and 44B are different from those in the chip integration module 40 shown in FIG. 4. The sealing body 45B contains a plurality of filler particles 452, and the sealing body 44B contains a plurality of filler particles 442. The filling rate of the plurality of filler particles 452 in the sealing body 45B is greater than the filling rate of the plurality of filler particles 442 in the sealing body 44B. The "filling rate of filler particles 452" is defined as the total volume of the plurality of filler particles 452 contained in the total volume of the sealing body 45B, which contains resin 453 and the plurality of filler particles 452. The "filling rate of filler particles 442" is defined as the total volume of the plurality of filler particles 442 contained in the total volume of the sealing body 44B, which contains insulating resin 443 and the plurality of filler particles 442.

[0109] However, when calculating the fill rate, for example, images are taken of cross-sections of two or more randomly selected regions in the seal 45A, and the ratio of the cross-sectional area of ​​the filler particles 452 to the cross-sectional area of ​​the seal 45A is measured in each imaging range. The average value of each region is taken as the "fill rate of filler particles 452", and the "fill rate of filler particles 442" is calculated in the same way. By increasing the fill rate of multiple filler particles 452 in the seal 45B as in this modified example, the linear expansion coefficient of the seal 45B as a whole can be reduced. As a result, the positional accuracy of the connecting part 47 and the connecting part 48 can be further improved in the bridge mounting process described using FIG. 7 and FIGS. 20-22. In addition, multiple filler particles 452 are pre-mixed in the sealing resin used in the first sealing process of FIG. 7. Similarly, multiple filler particles 442 are pre-mixed in the sealing resin used in the second sealing process shown in FIG. 7.

[0110] In the wafer integration module 40C shown in FIG. 27, the sealing body 45B is different from that in the wafer integration module 40 shown in FIG. 4. The sealing body 45B contains a plurality of filler particles 452, while the sealing body 44 is an insulating resin 443 without filler particles. As in this modified example, regardless of whether the sealing body 44 contains filler particles, as long as the sealing body 45B contains filler particles, the overall linear expansion coefficient of the sealing body 45B can be reduced. As a result, the positional accuracy of the connecting part 47 and the connecting part 48 can be further improved in the bridge mounting process described in FIG. 7 and FIG. 20-22.

[0111] <Example of a variation of the manufacturing method>

[0112] Next, a modified example of the manufacturing method of the wafer integration module 40 described using FIGS. 7 to 23 will be described. FIG. 28 is an enlarged cross-sectional view of a wafer integration module as another modified example of FIG. 4. The wafer integration module 40D shown in FIG. 28 differs from the wafer integration module 40 shown in FIG. 4 in the following two points: the connecting portion 47 and the connecting portion 48 are sealed by the insulating layer 81, and the bare die electrodes 416 and 417 of the semiconductor bare die 41 and the bare die electrode 427 of the semiconductor bare die 42 are respectively sealed by the insulating layer 82 which is in close contact with the insulating layer 81. In addition, the wafer integration module 40D differs from the wafer integration module 40 shown in FIG. 4 in that the bridge electrodes 436 and 437 of the bridge 43 are respectively sealed by the insulating layer 84 which is in close contact with the insulating layer 81.

[0113] Hereinafter, the manufacturing method of the chip integration module 40D shown in FIG28 will be described. In the following description, the focus will be on the differences from the manufacturing method of the chip integration module 40 described using FIG7 to FIG23, and common processes will sometimes be omitted. FIG29 is an explanatory diagram showing an outline of the manufacturing process of the chip integration module shown in FIG28. As shown in FIG29, the manufacturing method of the chip integration module of this modified example includes an insulating layer formation process, a connector formation process, a semiconductor die mounting process, a sealing process, a support removal process, a connector exposure process, and a bridge mounting process.

[0114] The insulating layer formation process shown in FIG29 includes the processes shown in FIG30 and FIG31. FIG30 and FIG31 are enlarged cross-sectional views showing details of the insulating layer formation process shown in FIG29. In the insulating layer formation process, as shown in FIG30, after the insulating layer 81 is formed on the upper surface 70t of the support 70, as shown in FIG31, openings 81H1 and 81H2 are formed on the insulating layer 81. In the example shown in FIG31, opening 81H3 for forming the connection portion 49 shown in FIG28 is formed accordingly. The insulating layer 81 is bonded to the insulating layer 82 shown in FIG28 in the semiconductor bare die mounting process described later. Therefore, the insulating material used for the insulating layer 82 is preferably a material with high heat resistance in addition to electrical insulation properties. Such materials include, for example, organic insulating materials such as polyimide and PBO (polybenzoxazole). The support 70, peeling layer 71 and seed layer 72 shown in Figures 30 and 31 are described as they have been described using Figure 8, so repeated descriptions are omitted.

[0115] In the connection forming process shown in FIG29, connection portions 47 and 48 are formed as shown in FIG32. Connection portion 47 includes a columnar connection portion 472 formed within an opening 81H1, and connection portion 48 includes a columnar connection portion 482 formed within an opening 81H2. FIG32 is an enlarged cross-sectional view showing details of the connection forming process shown in FIG29. In the example shown in FIG32, an electrode 492 constituting connection portion 49 is formed within an opening 81H3. In this modified example, the insulating layer 81 is used as a mask instead of the resist mask 73 described using FIG10, which differs from the manufacturing method described using FIG10. The structures of the columnar connection portions 472, 482 and the electrode 492 are as described using FIG10, and therefore repeated descriptions are omitted.

[0116] As described above, in this modified example, the insulating layer 81 is used as a mask to form the connecting portions 47, 48, and 49. Therefore, this modified example is not applicable to the process of removing the resist mask 73 as illustrated in FIG11, nor to the process of forming the oxide film 72A as illustrated in FIG12.

[0117] The semiconductor die mounting process shown in FIG29 includes the processes shown in FIG33 to FIG35. FIG33 to FIG35 are enlarged cross-sectional views showing details of the semiconductor die mounting process shown in FIG29. In the semiconductor die mounting process, as shown in FIG35, semiconductor die 41 and semiconductor die 42 are prepared. Semiconductor die 41 has an IC wafer 411 and a die electrode 417 connected to the IC wafer 411. Semiconductor die 42 has an IC wafer 421 and a die electrode 427 connected to the IC wafer 421. In addition, in the semiconductor die mounting process, semiconductor die 41 and semiconductor die 42 are respectively mounted on the support 70, such that die electrode 417 is disposed on the connection portion 47 and die electrode 427 is disposed on the connection portion 48.

[0118] In detail, firstly, semiconductor die 41 and semiconductor die 42 are prepared as shown in FIG33. In this modified example, the semiconductor die mounting process described using FIGS. 13-15 differs in the following two aspects: an insulating layer 82 is formed on the upper surface (die electrode forming surface) of semiconductor die 41, and an insulating layer 83 is formed on the upper surface (die electrode forming surface) of semiconductor die 42. The insulating layer 82 is an insulating layer bonded to the insulating layer 81 in this process. Considering the bonding with the insulating layer 81, the materials of the insulating layers 82 and 83 are particularly preferably made of the same material as the insulating layer 81. The detailed structures of semiconductor die 41 and semiconductor die 42 other than the above-mentioned differences are as described using FIG4, and therefore, repeated descriptions are omitted.

[0119] Next, as shown in FIG33, semiconductor bare die 41 and semiconductor bare die 42 are respectively aligned with the support body 70 so that bare die electrode 417 is disposed on the connection portion 47 and bare die electrode 427 is disposed on the connection portion 48. Solder layer 473 is formed on the bare die electrode 417 of semiconductor bare die 41. Solder layer 483 is formed on the bare die electrode 427 of semiconductor bare die 42. Furthermore, in this modified example, in the sealing process shown in FIG29, the sealing body 45 does not contact the connection portion 47, the connection portion 48, and the connection portion 49, respectively. Therefore, it is preferable to form solder layer 493 on the bonding surface of electrode 492, which has a relatively larger area than bare die electrode 416. As a result, the volume of the void around solder layer 493 can be reduced after the semiconductor bare die mounting process. On the other hand, from the viewpoint of preventing oxidation of the bonding surface of bare die electrode 416, it is preferable to also form solder layer on bare die electrode 416.

[0120] Next, as shown in FIG34, the bare die electrode 417 of the semiconductor bare die 41 is pressed onto the connection portion 47 via the solder layer 473. At this time, the bare die electrode 416 of the semiconductor bare die 41 is pressed onto the solder layer 493. Similarly, the bare die electrode 427 of the semiconductor bare die 42 is pressed onto the connection portion 48 via the solder layer 483. In this process, the solder layer 473 and the columnar connection portion 472 of the connection portion 47 are temporarily bonded by solid-state diffusion bonding. Similarly, the solder layer 493 and the electrode 492 of the connection portion 49 are temporarily bonded by solid-state diffusion bonding. Similarly, the solder layer 483 and the columnar connection portion 482 of the connection portion 48 are temporarily bonded by solid-state diffusion bonding. At this point in time, the insulating layer 81 is in contact with the insulating layers 82 and 83 respectively, but they are not yet bonded.

[0121] Next, the bonding interfaces between the solder layer 473 and the metal film 472B of the columnar connection portion 472, as shown in FIG. 34, the bonding interfaces between the solder layer 493 and the metal film 492B of the electrode 492, and the bonding interfaces between the solder layer 483 and the metal film 482B of the columnar connection portion 482 are respectively bonded by the liquid phase diffusion bonding described above. In this case, as shown in FIG. 35, alloy layers 472D, 482D, and 492D formed by eutectic reaction are formed at each bonding interface. The details of liquid phase diffusion bonding have already been explained, so repeated explanations are omitted.

[0122] In addition, in this modified example, during the semiconductor die mounting process, insulating layer 81 and insulating layer 82 are bonded to each other, and the die electrode 417 is sealed with insulating layer 81 and insulating layer 82. Furthermore, during the semiconductor die mounting process, insulating layer 81 and insulating layer 83 are bonded to each other, and the die electrode 427 is sealed with insulating layer 81 and insulating layer 83. The timing of bonding insulating layer 81 with insulating layer 82 and insulating layer 83 can be almost the same as the timing of liquid phase diffusion bonding. That is, when the solder layer 473 and metal film 472B shown in FIG. 34 are heated to the temperature at which a eutectic reaction occurs, each insulating layer 81, 82, and 83 is also heated together. As a result, the materials constituting insulating layers 81, 82, and 83 soften, and their contact interfaces bond. As a principle for bonding the insulating layers, in addition to bonding based on the dehydration polymerization of hydroxyl groups on the surface of the insulating layers (fusion, bonding), bonding based on softening and melting can also be used depending on the material. When using fusion and bonding methods, it is preferable to activate the surface of the insulating layers with plasma before the insulating layers bond to each other.

[0123] In this modified example, the connecting portions 47, 48, and 49 are surrounded by an insulating layer 81. Therefore, during liquid phase diffusion bonding, the wetting and diffusion of solder components can be suppressed. Thus, even in this modified example, the bare die electrode and the connecting portion can be bonded with a small amount of solder.

[0124] In the sealing process shown in FIG29, after the semiconductor die mounting process, as shown in FIG36, the semiconductor die 41 and semiconductor die 42 are sealed with a sealing body 45. FIG36 is an enlarged cross-sectional view showing details of the sealing process shown in FIG29. In this process, the semiconductor die 41 and semiconductor die 42 are integrated with the sealing body 45. In this modified example, the connecting portions 47, 48, and 49 have been sealed, so strictly speaking, the semiconductor die 41 and semiconductor die 42 are integrated via the insulating layer 81. In this process, sealing with the sealing body 45 improves the rigidity of the structure that integrates the semiconductor die 41 and semiconductor die 42.

[0125] In this modified example, the volume of the sealing body 45 is further reduced compared to the volume of the sealing body 45 shown in FIG4. Therefore, even if the sealing body 45 undergoes thermal expansion or contraction, the various connecting parts 47, 48, and 49 can maintain high positional accuracy even when sealed by the sealing body 45.

[0126] In the support removal process shown in FIG29, the support 70 shown in FIG36 is removed after the sealing process. The method for removing the support 70 is the same as the support removal process described using FIG17, so repeated description is omitted.

[0127] In the connection exposure process shown in FIG29, after the support removal process, as shown in FIG37, a portion (lower surface) of the columnar connection 472 and a portion (lower surface) of the columnar connection 482 are exposed from the insulating layer 81. FIG37 is an enlarged cross-sectional view showing details of the connection exposure process shown in FIG29. In this process, for example, the release layer 71 and seed layer 72 shown in FIG36 are removed by etching. In the example shown in FIG37, in this process, a portion (lower surface) of the electrode 492 is also exposed from the insulating layer 81.

[0128] In this process, as shown in FIG38, after the connection portion is exposed from the insulating layer 81, it is preferable to form metal films 472C, 482C, and 492C on the exposed surfaces of each connection portion. FIG38 is an enlarged cross-sectional view showing details of the connection portion exposure process immediately following FIG37. As shown in FIG38, in this process, metal film 472C is formed on the exposed surface of the columnar connection portion 472 exposed from the sealing body 45. Similarly, metal film 482C is formed on the exposed surface of the columnar connection portion 482 exposed from the sealing body 45. Metal film 492C is formed on the exposed surface of the electrode 492 exposed from the sealing body 45. Details of metal films 472C, 482C, and 492C have already been explained using FIG19, therefore, repeated explanations are omitted.

[0129] The bridge mounting process shown in FIG29 includes the processes shown in FIG39 to FIG41. FIG39 to FIG41 are enlarged cross-sectional views showing details of the bridge mounting process shown in FIG29. In the bridge mounting process, as shown in FIG41, a bridge 43 is prepared, which includes a bridge electrode 436 connected to a connecting portion 47 and a bridge electrode 437 connected to a connecting portion 48. In addition, in the bridge mounting process, after the connecting portion is exposed, the bridge 43 is mounted on a structure sealed by a sealing body 45, such that the bridge electrode 436 is disposed on the columnar connecting portion 472 and the bridge electrode 437 is disposed on the columnar connecting portion 482.

[0130] In detail, firstly, as shown in FIG39, a bridge 43 is prepared. In this modified example, the following two points differ from the semiconductor die mounting process described using FIGS13-15: an insulating layer 84 is formed on the upper surface (bridge electrode forming surface) of the bridge 43, and bridge electrodes 436 and 437 are respectively sealed by the insulating layer 84. The detailed structure of the bridge 43, apart from the above differences, is as described using FIG4, and therefore a repeated description is omitted.

[0131] Next, as shown in FIG39, the bridge 43 is aligned with the structure sealed by the sealing body 45, such that the bridge electrode 436 is disposed on the columnar connection portion 472 and the bridge electrode 437 is disposed on the columnar connection portion 482. A solder layer 474 is formed on the bridge electrode 436. A solder layer 484 is formed on the bridge electrode 437.

[0132] Next, as shown in FIG40, the bridge electrode 436 of the bridge 43 is pressed onto the columnar connection portion 472 of the connection portion 47 via the solder layer 474. At this time, the bridge electrode 437 of the bridge 43 is pressed onto the columnar connection portion 482 of the connection portion 48 via the solder layer 484. In this process, the solder layer 474 and the columnar connection portion 472 of the connection portion 47 (more specifically, the metal film 472C of the columnar connection portion 472) are temporarily bonded by solid-state diffusion bonding. Similarly, the solder layer 484 and the columnar connection portion 482 of the connection portion 48 (more specifically, the metal film 482C of the columnar connection portion 482) are temporarily bonded by solid-state diffusion bonding.

[0133] In this modified example, at this time, insulating layer 81 and insulating layer 84 are in contact with each other. However, at this point in time, insulating layer 81 and insulating layer 84 have not yet bonded together.

[0134] Next, the bonding interface between the solder layer 474 and the metal film 472C of the columnar connection portion 472 shown in FIG. 40, and the bonding interface between the solder layer 484 and the metal film 482C of the columnar connection portion 482, are bonded by liquid phase diffusion bonding. The liquid phase diffusion bonding method is as described above, so repeated descriptions are omitted. To perform liquid phase diffusion bonding, the metal films 472C and 482C shown in FIG. 40 become alloy layers 472E and 482E respectively formed by a eutectic reaction between tin, which is the main component of the solder layer, and the material of the metal film (e.g., gold) (see FIG. 41).

[0135] Furthermore, in this modified example, during the bridge mounting process, insulating layer 81 and insulating layer 84 are bonded to each other. The bonding of insulating layer 81 and insulating layer 84 occurs during liquid-phase diffusion bonding. That is, when the solder layer 474 and metal film 472C shown in FIG. 40 are heated to the temperature at which a eutectic reaction occurs, each insulating layer 81 and insulating layer 84 are also heated together. As a result, the materials constituting insulating layer 81 and insulating layer 84 soften, and their contact interfaces bond. As a principle for bonding the insulating layers, the above-described bonding based on the dehydration polymerization of hydroxyl groups on the surface of the insulating layers (fusion, bonding, etc.) can also be used.

[0136] Furthermore, this modified example illustrates an example using insulating layers 81 to 84 shown in FIG. 28, but sometimes the structure shown in FIG. 4 or the structure of the modified example illustrated in FIG. 24 is partially applicable. For example, sometimes the bridge electrode 436 and bridge electrode 437 are sealed instead of the insulating layer 84 shown in FIG. 28 by the sealing body 44 shown in FIG. 4 or the sealing body 105 shown in FIG. 24.

[0137] In addition, in this modified example, an example was described where the upper surface of the bridge 43 was covered by an insulating layer 84, but there are also cases where the insulating layer 84 is not formed. For example, when a functional insulating film called NCF (Non-Conductive Film) is used instead of the insulating layer 84, the NCF covers the insulating layer 81, the connector 47, and the connector 48 after the process shown in FIG38. In this case, during the bridge mounting process, by pressing the bridge 43 of the structure shown in FIG20 toward the NCF, the solid-phase diffusion bonding and liquid-phase diffusion bonding described above are performed while the bridge electrodes 436 and 437 penetrate through the NCF and are in contact with the connector 47 or the connector 48, respectively, thereby obtaining the same structure as the wafer integration module 40D shown in FIG28.

[0138] <Manufacturing Method of Wafer Integration>

[0139] Next, the manufacturing method of the wafer integrated assembly will be described using FIG3. First, a wide-area wiring layer 102 is formed on a support (not shown). The method for forming the wide-area wiring layer 102 is not particularly limited, and a lamination process, for example, can be used. Next, a plurality of electrodes 403 and pillars 401 are formed on the wide-area wiring layer 102. The method for forming the electrodes 403 and pillars 401 can be applied using the connection forming process described in FIGS. 8 to 12. In addition, electrodes 148 and conductor pillars 146 are also formed in this process. If the electrodes 148 and 403 have the same thickness, they can be formed together at the same time. On the other hand, since the conductor pillars 146 and pillars 401 have different thicknesses, they are formed separately.

[0140] Next, the chip integration module 40 is mounted on the pillar 401. The pillar 401 is connected to the connection portion 49 shown in FIG. 4. The connection method between the pillar 401 and the connection portion 49 is not particularly limited, but for example, it can be connected via a solder layer (not shown). At this time, from the viewpoint of preventing the solder layer in the chip integration module 40 from remelting, liquid phase diffusion bonding is preferred.

[0141] Next, the various components formed on the wafer layer 104 are sealed using the sealing body 105. In the example shown in FIG3, the conductor pillar 146, electrode 148, wafer integration module 40, high pillar 401, and electrode 403 are each sealed by the sealing body 105. Afterward, the support (not shown) is removed from the wide-area wiring layer 102. Furthermore, the upper part of the sealing body 105 is ground to expose the conductor pillar 146 and the wafer integration module 40.

[0142] Next, a connection layer 106 is formed on the sealing body 105. More specifically, the connection layer 106 is formed on the sealing body 105 such that the wiring included in the connection layer 106 is connected to the exposed portion of the conductor post 146 or the exposed portion of the chip integration module 40. For example, the electrode 140 formed on the connection layer 106 is connected to the conductor post 146 via a via 142.

[0143] Next, a heat dissipation mechanism 20 is mounted on the contact portion 222. Then, the optical module 13, to which the optical fiber 600 (see Figure 5) and optical fiber 610 (see Figure 5) are connected, is connected to the electrode 140. The heat dissipation member 136 is pre-connected to the optical module 13. Next, if a plurality of external terminals 30 are mounted on the wide area wiring layer 102, the chip integration assembly 10 shown in FIG3 is obtained.

[0144]

[0145] Next, a modified example of the wafer integrated assembly shown in FIG3 will be described. FIG42 and FIG43 are explanatory diagrams showing the modified example of the wafer integrated assembly shown in FIG3. The wafer integrated assembly 10A shown in FIG42 differs from the wafer integrated assembly 10 shown in FIG3 in that a portion of the optical module 13 is embedded within the wafer layer 104 of the integration layer 100. Specifically, a portion of the connector 132 in the optical module 13 is sealed by the sealing body 105. The connector 132 is connected to the electrode 148 via the via 142. With the connector 132 portion embedded in the wafer layer 104, the overall height of the wafer integrated assembly 10A can be reduced, and compared to FIG3, the signal transmission characteristics can be improved by shortening the distance from the wafer integrated module to the optical transceiver. In addition, since the optical transceiver 130 is exposed from the wafer layer 104 and the connection layer 106, the optical transceiver 130 is easy to install and remove.

[0146] The chip integration 10B shown in FIG. 43 differs from the chip integration 10 shown in FIG. 3 in that the optical module 13 is disposed on the back side 100b of the integration layer 100. The integration layer 100 has a front surface 100f on which the heat dissipation mechanism 20 is mounted and a back side 100b opposite to the front surface 100f. The optical module 13 is mounted on the back side 100b. By disposing the optical module 13 on the back side 100b, the separation distance between the heat dissipation mechanism 20 and the optical module 13 is increased, thereby reducing the thermal impact from the heat dissipation mechanism 20. In addition, in the example shown in FIG. 43, the optical module 13 is disposed at a position overlapping the chip integration module 40 in the thickness direction of the integration layer 100. In this case, the distance between the chip integration module 40 and the optical module 13 becomes closer, thereby improving the transmission efficiency of electrical signals.

[0147]

[0148] In the signal transmission path via bridge 43 shown in FIG. 4, the signal is transmitted at ultra-high speed. In the case of a high-speed signal transmission path, it is preferable to reduce the electrical parasitic capacitance imparted to the transmission path. Hereinafter, a variation of the technique for reducing the parasitic capacitance generated between the chip 431 and the wiring 434 shown in FIG. 4 will be described. FIG. 44 is a cross-sectional view showing a variation of the bridge shown in FIG. 4.

[0149] The bridge 43A shown in FIG44 differs from the bridge 43 shown in FIG4 in that it also has an insulating layer 438 between the insulating layer 432 and the wafer 431. Otherwise, it is the same as the bridge 43 shown in FIG4. The bridge 43A has a wafer 431, insulating layers 438, 432, and 433 sequentially stacked on the wafer 431, and wiring 434 sandwiched between the insulating layers 432 and 438 and connected to the bridge electrodes 436 and 437 respectively. The insulating layer 438 is a thick-film insulating layer. The thickness of the insulating layer 438 is greater than the thickness of the insulating layers 432 and 433. The insulating layer 438 has a surface 438t bonded to the insulating layer 432 and a surface 438b bonded to the wafer 431. Surfaces 438t and 438b each have an adhesive function, and the insulating layer 438 is bonded and fixed to the insulating layer 432 and the wafer 431 through the adhesive function of surfaces 438t and 438b. Alternatively, the insulating layer 438 can be an adhesive layer as a whole.

[0150] When an insulating layer 438 is sandwiched between the insulating layer 432 and the wafer 431, as in bridge 43A, the separation distance between the wiring 434 and the wafer 431 can be increased. As a result, the parasitic capacitance generated between the wafer 431 and the wiring 434 can be reduced compared to bridge 43 shown in FIG4.

[0151] When the bridge 43A is provided with the insulating layer 438, it is more prone to warping deformation compared to the bridge 43 shown in FIG. 4. The warping deformation of the bridge is caused by the film formation stress (curing shrinkage or thermal shrinkage of the resin) generated during the formation of the insulating layer 438. From the viewpoint of reducing this warping deformation, the insulating layer 438 is preferably made of a material with a lower elastic modulus. In addition, from the same viewpoint, it is preferable to use a resin material with a lower curing temperature and thermal decomposition temperature compared to the insulating layers 432 and 433. For example, when the insulating layers 432 and 433 are made of polyimide resin and the insulating layer 438 is made of epoxy resin, the insulating layer 438 is made of a resin material with a lower curing temperature and thermal decomposition temperature compared to the insulating layers 432 and 433, thus suppressing the warping deformation of the bridge 43A.

[0152] The bridge 43A shown in FIG44 is manufactured, for example, in the following manner. FIG45-47 are cross-sectional views showing a general outline of the manufacturing process of the bridge shown in FIG44. The manufacturing method of the bridge 43A includes the wiring layer formation process shown in FIG45, the wiring layer transfer process shown in FIG46, the support removal process shown in FIG47, and the bridge electrode formation process shown in FIG44.

[0153] First, in the wiring layer formation process, an insulating layer 433, wiring 434, and insulating layer 432 are sequentially formed on the support 80 shown in FIG. 45 in a stacked manner. Specifically, in the wiring layer formation process, the support 80 shown in FIG. 45 is prepared. A release layer 81A and a seed layer 82A are pre-formed on the upper surface 80t of the support 80. The support 80 is not particularly limited in material as long as it is a rigid board material that does not impair workability in each process up to the support removal process described later. For example, semiconductor substrates such as silicon wafers, boards made of inorganic materials such as glass or sapphire substrates, and resin boards. The release layer 81A is the same as the release layer 71 described using FIG. 8, and the seed layer 82A is the same as the seed layer 72 described using FIG. 8, so repeated descriptions are omitted.

[0154] Furthermore, in the wiring layer formation process, after the support 80 is prepared, the insulating layer 433 is deposited on the seed layer 82A. Next, an opening is formed in a portion of the insulating layer 433, and a wiring 434 is formed within the opening. Although repeated descriptions are omitted, the method for forming the opening and the method for forming the wiring 434 within the opening can be formed using the photolithography technique described in Figures 9 and 10. Next, an insulating layer 432 is formed to cover the insulating layer 433 and the wiring 434, resulting in the structure shown in Figure 45.

[0155] Next, in the wiring layer transfer process, as shown in FIG46, the insulating layer 432 on the support 80 is bonded to the wafer 431 via the insulating layer 438. FIG46 also illustrates an example of bonding a monolithic wafer 431. However, as a variation, sometimes a silicon wafer, a glass substrate, or a sapphire substrate before monolithization is bonded instead of the wafer 431 in this process. When a substrate in its pre-monolithic state is bonded in this process, a monolithic process is performed after the bridge electrode formation process to cut the substrate to obtain multiple bridges 43A (see FIG44). In this variation, it is preferable from the viewpoint of improving manufacturing efficiency since multiple bridges 43A can be manufactured at the same time. If these variations are included, this process can be performed in the following manner. That is, in the wiring layer transfer process, the insulating layer 432 on the support 80 is bonded to the substrate via the insulating layer 438. The term "substrate" as used here includes not only the wafer shown in FIG46, but also semiconductor substrates such as silicon wafers before monolithization, glass substrates before monolithization, or sapphire substrates before monolithization. As illustrated using FIG44, surfaces 438t and 438b of the insulating layer 438 have adhesive functions, thus the insulating layer 432 on the support 80 is bonded and fixed to the wafer 431 via the insulating layer 438. Furthermore, in this modified example, the wafer 431 is not electrically connected to the wiring 434. When a portion of the wafer 431 is not connected to other circuits, sometimes the portion of the wafer 431 shown in FIG44 can be replaced with a substrate (e.g., a semiconductor substrate or a glass substrate) without integrated circuits. Alternatively, as described later, sometimes a bridge is formed by removing a portion of the wafer 431.

[0156] Next, in the support removal process, as shown in FIG47, for example, the release layer 81A is decomposed by applying energy to the release layer 81A (refer to FIG46). After the support removal process, conductor portions (conductor portion 437A connected to bridge electrode 437 and conductor portion 436A connected to bridge electrode 436) connected to bridge electrode 437 and bridge electrode 436 are exposed. Conductor portion 436A and conductor portion 437A function as contactors for electrically connecting the wiring board to the bridge electrodes, respectively. In this process, for example, the release layer 81A and seed layer 82A shown in FIG46 are removed by etching.

[0157] Next, in the bridge electrode forming process, as shown in FIG44, a bridge electrode 437 is formed on the conductor portion 437A connected to the wiring 434, and a bridge electrode 436 is formed on the conductor portion 436A connected to the wiring 434. In addition, in this process, a solder layer 474 is formed on the front end surface of the bridge electrode 436, and a solder layer 484 is formed on the front end of the bridge electrode 437.

[0158] By performing the above process on a large size such as a wafer or panel and then dividing it into bridges of predetermined sizes, the bridge 43A shown in FIG44 can be formed. The bridge 43A can be used interchangeably with, for example, the bridge 43 shown in FIG4. When the bridge 43 is replaced by the bridge 43A, the parasitic capacitance between the chip 431 and the wiring 434 is reduced, which is particularly preferred when transmitting high-speed signals. In addition, in this modified example, as a modified example of the bridge 43 shown in FIG4, the bridge 43A shown in FIG44 and the bridge 43B shown in FIG48 will be described. However, the bridges 43A and 43B can be replaced with any of the bridges 43 shown in the chip integration module 40A shown in FIG25, the chip integration module 40B shown in FIG26, the chip integration module 40C shown in FIG27, and the chip integration module 40D shown in FIG28.

[0159] FIG48 is a cross-sectional view showing another variation of the bridge shown in FIG4. The bridge 43B shown in FIG48 differs from the bridge 43 shown in FIG4 in that the portion corresponding to the wafer 431 is removed. In the case of bridge 43B, since the wafer 431 is not placed near the wiring 434, the effect of parasitic capacitance on wiring 434 can be further reduced.

[0160] However, in the case of bridge 43B, the rigidity is lower compared to bridge 43 shown in FIG. 4 or bridge 43A shown in FIG. 44. Therefore, it is preferable that, in the manufacturing process of the wafer integration module 40E, semiconductor die 41 and semiconductor die 42 are bonded to bridge 43B respectively until bridge electrodes 436 and 437 are sealed, so that the insulating layer 433 is maintained on the wafer 431, and each process is performed in the same manner as the manufacturing method described in FIG. 20 to FIG. 23. Afterwards, it is preferable to remove the wafer 431 in the state shown in FIG. 23. As a method for removing the wafer 431, for example, when the wafer 431 is formed of silicon, it can be removed by dry etching or the like; when it is formed of an inorganic material such as glass, it is possible to use a method in which a release layer is sandwiched between the wafer 431 and the insulating layer 433 and the release layer is decomposed (ablated) by an energy beam such as a laser to remove the wafer 431. In addition, as a variation of the manufacturing method of bridge 43B, the manufacturing method illustrated in Figures 44 to 47 is sometimes used.

[0161] <Other variations of chip integration modules>

[0162] FIG49 is a diagram showing a partial structure of the chip integration module as a variant of FIG4. As shown in FIG49, the chip integration module 40E of this embodiment includes a first die 41E, a second die 42E, a bridge 43E, and sealing members 45E and 46E that seal them. The first die 41E is connected to the bridge 43E via a first connection portion 47E. In addition, the bridge 43E is connected to the second die 42E via a second connection portion 48E. Furthermore, the first die 41E is externally connected to the chip integration module 40E via a third connection portion 49E.

[0163] The first bare die 41E includes a first integrated circuit chip 402E, bare die electrodes 408E and 410E, wirings 404E and 406E connected to the first integrated circuit chip 402E, and insulating layers 412E and 414E in which the wirings 404E and 406E are embedded. The wirings 404E and 406E are wirings other than the wiring layers included in the first integrated circuit chip 402E. More specifically, the wirings 404E and 406E can be thick-film wirings using an insulating film of organic (or inorganic) resin, referred to as so-called redistribution layers (RDL). In addition, the wirings included in the second bare die and the bridge are also referred to as redistribution layers. Furthermore, the second integrated circuit chip 420 and the third integrated circuit chip 442E, described later, may also have the same structure as the first integrated circuit chip 402E.

[0164] The second bare die 42E includes a second integrated circuit chip 420E, a bare die electrode 424E, a wiring 422E connected to the second integrated circuit chip 420E, and insulating layers 426E and 428E in which the wiring 422E is embedded.

[0165] The bridge 43E includes a third integrated circuit chip 442E, bridge electrodes 446E and 448E, a wiring 444E connected to the third integrated circuit chip 442E, and insulating layers 450E and 452E embedded in the wiring 444E. In this embodiment, the wiring 444E forms part of the bridge that is electrically connected to the first connection portion 47E and the second connection portion 48E. The bridge in this embodiment is a pillar-suspended bridge. In this embodiment, the wiring 444E is electrically connected to the third integrated circuit chip 442E, and the wiring 444E and the third integrated circuit chip 442E are integrated and function as a bridge.

[0166] The first connection portion 47E includes columnar connection portions 474E and 472E. In this embodiment, the columnar connection portions are columnar conductors with a μm dimension (also called micropillars). The columnar connection portions 472E and 474E are columnar conductors formed from the bridge 43E toward the first bare die 41E. In this embodiment, the cross-sectional area of ​​the portion of the columnar connection portion 472E connected to the columnar connection portion 474E is larger than the cross-sectional area of ​​the portion of the columnar connection portion 474E connected to the columnar connection portion 472E. In this modified example, the columnar connection portion 474E is connected to the bare die electrode 408E via solder 478E. In addition, the columnar connection portion 472E is connected to the bridge electrode 446E via solder 476E.

[0167] The second connection portion 48E includes columnar connection portions 480E and 482E. The columnar connection portions 480E and 482E are columnar conductors formed from the bridge electrode 43E toward the second bare die 42E. In this modified example, the cross-sectional area of ​​the portion of the columnar connection portion 480E connected to the columnar connection portion 482E is larger than the cross-sectional area of ​​the portion of the columnar connection portion 482E connected to the columnar connection portion 480E. In this modified example, the columnar connection portion 482E is connected to the bare die electrode 424E via solder 486E. Furthermore, the columnar connection portion 480E is connected to the bridge electrode 448E via solder 484E.

[0168] The third connection portion 49E includes a columnar connection portion 492E. The columnar connection portion 492E is a columnar conductor formed from the first bare die 41E outwards. The columnar connection portion 492E is connected to the bare die electrode 410E via solder 490E. In addition, the columnar connection portion 492E is connected to an external electrode pad 494E (e.g., the wide area wiring layer 102). Furthermore, the third connection portion 49E may have various structures other than (or instead of) the structure shown in FIG. 49. For example, the third connection portion 49E may include various structures such as a deep via, a tall pillar, or a columnar connection portion provided below the electrode pad 494E, which can be connected to the wide area wiring layer 102 (see FIG. 3).

[0169] Furthermore, in this modified example, an example is described where the bridge includes a bare die with an integrated circuit chip. However, the bridge may also not include an integrated circuit chip and may mainly consist of wiring and an insulating layer in which the wiring is embedded. Additionally, in this embodiment, an example is described where the bare die and the bridge are connected by two columnar connectors of different diameters. However, this is not a limitation; the bare die and the bridge may be connected by one columnar connector, or by three or more columnar connectors.

[0170] (First variation)

[0171] FIG50 is a diagram showing the structure of a first variant of the chip integration module shown in FIG49. Structures in the chip integration module 40F shown in FIG50 that are substantially the same as those in the chip integration module 40E shown in FIG49 are labeled with the same reference numerals, and descriptions are omitted as appropriate.

[0172] The first modified wafer integration module 40F differs from the wafer integration module 40E described above (see FIG49) in the structure of the first connection portion, the second connection portion, and the third connection portion. Specifically, in the first modified example, the columnar connection portion or electrode pad is directly connected to other electrodes or wiring without solder. More specifically, in the first connection portion involved in the first modified example, the columnar connection portion 502F is connected to the die electrode 408E and the bridge electrode 446E. In addition, in the second connection portion, the columnar connection portion 504 is connected to the die electrode 424E and the bridge electrode 448E. Furthermore, in the third connection portion, an electrode pad 494E is connected to the die electrode 410E. Here, the columnar connection portion and the die electrode or the bridge electrode, or the die electrode and the electrode pad, can be connected by various conventional techniques related to hybrid bonding.

[0173] In the first modified example, various conductors are embedded in an insulator. Specifically, the bare die electrodes 408E, 410E, and 424E are embedded in an insulating film 510F. Additionally, the electrode pads 494E and the columnar connections 502F and 504F are embedded in an insulating layer 512F. Furthermore, the bridge electrodes 446E and 448E are embedded in an insulating film 514F. Moreover, the first bare die 41E and the second bare die 42E are sealed with an insulating resin 506F. By selecting an appropriate material system and processing conditions from various conventional techniques related to hybrid bonding, the bare die electrode 408E can be connected and bonded to the columnar connection 502F, the insulating film 510F, and the insulating layer 512F. Similarly, for the bridge electrodes, the bridge electrodes 446E and 448E can be connected and bonded to the insulating layer 512F, the insulating film 514F, and the insulating layer 512F.

[0174] Furthermore, in the first variation, an example of the bridge including an integrated circuit chip was described, but it is not limited thereto; the bridge may also not include an integrated circuit chip. For example, the bridge may also include a solid chip made of various materials such as silicon and glass instead of an integrated circuit chip.

[0175] (Second variation)

[0176] FIG51 is a diagram showing the structure of a second modified example of the wafer integration module shown in FIG49. In the second modified example of the wafer integration module 40G, a deep via 520G is formed in the insulating resin 524G of the sealing bridge 43E, and the first bare die 41E is electrically connected to an external conductor through the deep via 520G. More specifically, the electrode pad 494E connected to the bridge 43E may also be connected to the deep via 520G, and solder 522G connected to an external conductor may be formed at the end of the deep via 520G. Here, the deep via 520G may be formed such that its diameter increases from the electrode pad 494E toward the solder 522G. In addition, in the second modified example, the lower surface of the third integrated circuit wafer 442E may be exposed.

[0177] In the second modification, the bridge including bridge 43E is sealed with insulating resin 524G. Therefore, in the second modification, the bridge is protected by insulating resin 524G. In addition, the connection portion (bottom filling) between the bridge and other components can also be sealed while sealing the bridge. Furthermore, by planarizing the portion of the bare die where terminals are formed, the spacing between the connection portion and the wide-area wiring layer can be further shortened.

[0178] (Third variation)

[0179] FIG52 is a diagram illustrating a third variant of the wafer integration module shown in FIG49. FIG52 shows a variant of the wafer integration module 40G shown in FIG51, namely, near a portion of the deep via 520G and the third integrated circuit chip 442E of the wafer integration module H. In the third variant, the differences from the wafer integration module 40G of the second variant are mainly explained. In addition, the wafer integration module of the third variant may also have the structure of the wafer integration module 40G of the second variant. That is, the structure not shown in FIG52 may be substantially the same as the structure shown in FIG51. In the wafer integration module 40H of the third variant, unlike the second variant, the lower surface of the third integrated circuit chip 442E is not exposed. More specifically, the lower surface of the third integrated circuit chip 442E is covered by insulating resin 525G.

[0180] (Fourth variation)

[0181] FIG53 is a diagram showing a fourth modified example of the chip integration module shown in FIG49. In the fourth modified example of the chip integration module 40K, a wiring layer 570 is formed below the insulating resin 524 in which the bridge 43E is embedded. The wiring formed in this wiring layer 570K connects the first bare die 41E and the bridge 43E.

[0182] The wiring layer 570K of the fourth modification has various conductors embedded in the insulation layer, specifically, wiring 578K and electrodes 576 embedded in the insulation layers 572K and 574K. These wirings 578K and electrodes 576K can be electrically connected to external conductors. According to the fourth modification, terminals can be configured in the bridge, for example. In addition, power can be supplied directly to the bridge from the outside, for example.

[0183] In the fourth variation, the third integrated circuit chip 564K has functional elements 566K with various functions in the area circled by the dashed circle. These functional elements 566K are connected to electrodes 576K formed on the wiring layer 570K via vias 568K formed inside the third integrated circuit chip 564K. Furthermore, in this embodiment, bridge electrodes 446E are connected to wiring 443K, and bridge electrodes 448E are connected to wiring 444E. Thus, in the fourth variation, the first die 41E and the second die 42E are connected via functional elements 566K.

[0184] In addition, the electrode pad 494E electrically connected to the first bare die 41E is connected to the wiring 578K of the wiring layer 570K by a pillar 560K. The pillar 560K is different from the deep via 520G described in the second modified example (see Figure 51), and its cross-sectional area can be approximately constant within the range from the electrode pad 494E to the wiring 578K.

[0185] (Fifth variation)

[0186] Figure 54 is a diagram showing a fifth modification of the chip integration module shown in Figure 49. In the chip integration module 40M of the fifth modification, the bridge mainly includes wiring. Specifically, the bridge 580M of the fifth modification has various wirings and an insulating layer embedded in the wirings, but does not have an integrated circuit chip.

[0187] The bridge 580M has a wiring 588M embedded in the insulating layer 582M, which is connected to the bridge electrodes 446E and 448E. Additionally, wirings 589M and 590M are embedded in the insulating layers 582M, 584M, and 586M. These wirings 589M and 590M are connected to the electrodes 576 of the wiring layer 570K via contact vias 592M.

[0188] <Other variations of the manufacturing method for chip integration modules>

[0189] Other variations of the manufacturing method of the chip integration module will be described with reference to Figures 55 to 60.

[0190] First, a support 800 with a release film 802 formed on its surface, as shown in FIG. 55, is prepared. Various conductors are formed on the release film 802 (forming process). Various materials such as glass, silicon, and metal can be used as the support. For example, columnar connecting portions 806 and 808 protruding from the surface of the support 800 are formed on the release film 802. In addition, electrode pads 804 and 809 may also be formed on the release film 802.

[0191] Next, as shown in FIG56, a plurality of bare dies, including a first bare die 81E and a second bare die 82E, are bonded to various conductors formed on the release film 802. The first bare die 81E has a first integrated circuit wafer 810, a wiring layer 812 formed on its surface, and various electrodes including bare die electrodes 814 and 816 formed on its surface. In addition, the second bare die 82E has a second integrated circuit wafer 820, a wiring layer 822 formed on its surface, and various electrodes including bare die electrodes 824 and 826 formed on its surface.

[0192] In this embodiment, the die electrode formed on the die is bonded to various conductors (die bonding process). For example, the die electrode 814 and die electrode 816 of the first die 81E are bonded to the electrode pad 804 and the columnar connection portion 806, respectively. Furthermore, the die electrode 824 and die electrode 826 of the second die 82E are bonded to the electrode pad 809 and the columnar connection portion 808, respectively. The die electrode can be bonded to the electrode pad or the columnar connection portion via solder, or it can be bonded using a hybrid bonding method without solder.

[0193] Next, as shown in FIG57, the various conductors and multiple bare crystals formed on the release film 802 are sealed with resin 818 (sealing member) (sealing process). The first bare crystal 81E and the second bare crystal 82E can be pre-sealed with an insulating resin such as capillary underfill or NCF (Non-Conductive Film) before the sealing process of resin 818, or they can be sealed simultaneously during the sealing process of resin 818 (mold underfill). Thus, the multiple bare crystals are fixed in a state of being bonded to the columnar connector and the metal pad.

[0194] Next, as shown in FIG. 58, a process is performed to remove the release film 802 and the support 800, and to remove any remaining release film such as electrode pads. Various methods can be used to remove the support, including mechanically peeling the support, irradiating the release film with a laser to peel it off, and, depending on the situation, removing the support by grinding or etching. In the case of grinding or etching, sometimes the release film is not required. Then, the resin 818 on the bare die surface is ground. This exposes the bare die. Hereinafter, the intermediate 84E, in which various conductors and multiple bare dies are embedded and the resin is ground, will be described using the method shown in FIG. 58.

[0195] Next, as shown in FIG59, the bridge is bonded to the plurality of columnar connections (bridge bonding process). In this embodiment, the plurality of bare dies including the bridge 83E are used as bridges, and the bridges are bonded to the lower part of each of the plurality of columnar connections. In this embodiment, the bridge 83E has a third integrated circuit wafer 830, a wiring layer 832 formed on its surface, and bridge electrodes (including bridge electrodes 834 and 836) further formed thereon.

[0196] The bridge electrode 834 of the bridge 83E is bonded to the columnar connection portion 806 connected to the first die 81E. Furthermore, the bridge electrode 836 of the bridge 83E is bonded to the columnar connection portion 808 connected to the second die 82E. Thus, the bridge 83E serves as a bridge for electrical connection with the first die 81E and the second die 82E, forming a structure characterized by a columnar floating bridge. In addition, the bridge electrode can be bonded to the columnar connection portion via solder, or it can be bonded to the columnar connection portion via a hybrid bonding without solder.

[0197] Next, as shown in FIG60, the resin 818 is cut in such a way that it is divided into each chip integration module 80. Thus, each chip integration module is formed individually.

[0198] According to the manufacturing method of the chip integration module of this embodiment, as described with reference to FIG57, subsequent processes are performed after the first bare die, the second bare die, and the columnar connecting portion are fixed with resin. Therefore, in subsequent processes, the positional relationship of the multiple bare dies will not shift, and the integrated circuit chips can be connected to each other with higher precision. Furthermore, a simpler process and operation can be achieved. Moreover, external terminals can be formed directly below the integrated circuit chip, and excellent characteristics in terms of power integrity (PI) and signal integrity (SI) can be expected. In addition, since stable relative positional accuracy of the bare dies can be ensured regardless of the module size, according to this embodiment, large-scale chip integration, such as panel-scale, is easily implemented.

[0199] (Sixth variation)

[0200] Figures 61 to 64 are diagrams illustrating a sixth variation of the manufacturing method of the wafer integration module shown in Figures 55 to 60. In the sixth variation, a manufacturing method for a wafer integration module having the same structure as the wafer integration module 40F of the second variation described with reference to FIG50 will be described.

[0201] First, a plurality of intermediates 84E are prepared to be embedded in the resin 818 in the same manner as described above with reference to Figures 55 to 58.

[0202] Referring to FIG61, the following process will be described. First, the bridge is connected to the columnar connection portion. The bridge in the sixth modification has a wiring layer 946 and an integrated circuit chip 948. The wiring layer 946 has wiring (not shown in FIG61) that is connected to a plurality of bridge electrodes. The bridge electrodes are connected to the columnar connection portion. For example, bridge electrode 942 is connected to columnar connection portion 806, and bridge electrode 944 is connected to columnar connection portion 808. Thus, bridge electrodes 942 and 944, wiring layer 946, and integrated circuit chip function as a bridge.

[0203] Then, resin sealing is performed to cover the bare die electrode, wiring layer and integrated circuit chip (Fig. 61). Then, the integrated circuit chip is exposed by grinding or the like (Fig. 62).

[0204] The following process will be described with reference to FIG62. In FIG61, the lower surface of the integrated circuit chip is covered with resin 940. The lower surface of the integrated circuit chip and the resin 940 on the lower surface are ground. As a result, as shown in FIG62, the lower surface of the integrated circuit chip is exposed.

[0205] The following process will be described with reference to FIG63. In this process, an opening 950 for a via is formed in the resin 940 in which the integrated circuit chip is embedded. For example, the resin 940 can be irradiated with a laser to form the opening 950 in the resin. The opening 950 can be formed, for example, such that the electrode pad 809 to which the integrated circuit chip is connected is exposed. In addition, the opening 950 of the formed via can be formed such that its diameter increases as it moves downward from the electrode pad 809.

[0206] The following process will be described with reference to FIG64. In this process, metal is formed in the opening of the resin 940 by means of processes such as plating, and solder is provided at its end. Thus, as shown in FIG64, a deep via 952 with solder 954 provided at its end is formed in the resin 940. Furthermore, a chip integration module of the desired size can be formed individually by cutting the resin 818 and 940.

[0207] Furthermore, in the sixth modification, an example was described in which the lower surface of the integrated circuit chip and the resin 940 on the lower surface were ground. However, this is not a limitation. An opening 950 can be formed without grinding the resin 940, and a deep via with solder provided at the end can be formed therein. Thus, the chip integration module described in the third modification can be manufactured.

[0208] (Seventh variation)

[0209] Referring to Figures 65 and 66, the manufacturing method of the chip integration module of the seventh variation will be described. In the seventh variation, firstly, intermediate body 84E is manufactured as described with reference to Figures 55 to 58.

[0210] The following process will be described with reference to FIG65. In this process, a pillar 962 is formed on the electrode pad 809 embedded in the resin 818, or a bridge is bonded to the connection portion. The bridge in the seventh modification has a wiring layer 964 and an integrated circuit chip 966. The wiring layer 964 has wiring, and the bridge electrodes provided on the surface of the wiring function as a bridge, for example, by connecting to the pillar-shaped connection portions 806, 808.

[0211] Then, resin sealing is performed to cover the formed pillars and the electrical bridges connected to the pillar-shaped connection (Fig. 64). Then, grinding or the like is used to expose the pillars and electrical bridges (Fig. 65).

[0212] The following process will be described with reference to FIG66. In this process, the resin 960 sealing the pillars and bridge, the pillars, and the integrated circuit chip are ground. As a result, as shown in FIG66, the surfaces of the pillars and the integrated circuit chip are exposed on the surface of the resin 960. Furthermore, a chip integration module of the desired size can be manufactured by cutting the resin 818 and 960.

[0213] (Eighth variation)

[0214] The manufacturing method of the wafer integration module of the eighth variation will be described with reference to Figures 67 to 69. In the eighth variation, firstly, intermediate body 84E is prepared as described with reference to Figures 55 to 58.

[0215] The following process will be described with reference to FIG67. In this process, a bridge is joined at the connection portion embedded in the resin 818. The bridge in the eighth modification has a wiring layer 986 and an integrated circuit chip 988. The wiring layer 986 has wiring. The bridge electrodes provided on the wiring surface are connected to the columnar connection portions 806, 808, and the bridge electrodes and the wiring layer 986 function as a bridge.

[0216] Furthermore, resin sealing is performed to cover the wiring layer 986 and the bridge electrode formed on the wiring layer 986. Thus, as shown in FIG67, the bridge is connected to the columnar connection portion while the bare die electrode and the wiring layer 986 are fixed by the resin 980.

[0217] The following process will be described with reference to FIG68. In this process, the integrated circuit chip 988 is removed from the wiring layer 986. Then, the chip integration module of the desired size can be fabricated by cutting the resin 818.

[0218] The process of removing the integrated circuit chip 988 from the wiring layer 986 will be described in detail with reference to FIG69. In the eighth modification, a release layer 996 is provided between the integrated circuit chip 988 and the insulating layer 994 of the wiring layer. By irradiating the release layer 996 with energy particles 981 (e.g., laser), at least a portion of the release layer 996 can be decomposed (degraded). By moving the area irradiated with energy particles along the scanning direction indicated by the arrow, the release layer 996 can be decomposed entirely. Thus, the integrated circuit chip 988 can be removed from the insulating layer 994.

[0219] In addition, an example of decomposing the stripping layer 996 by scanning the area irradiated with energy particles has been described here, but it is not limited to this. It is also possible to irradiate the entire stripping layer 996 with energy particles at once without scanning.

[0220] <Manufacturing Method of Optical Module>

[0221] A method for manufacturing an optical module according to an embodiment of the present invention will be described with reference to Figures 70 to 74.

[0222] First, a support 850 with a release layer 852 formed on its surface is prepared. Next, as shown in FIG70, a wiring layer 860 is formed on the surface of the release layer 852. This wiring layer 860 may have a two-layer structure, and more specifically, it may have a structure substantially the same as that of the wiring layer 630 described with reference to FIG5. In this embodiment, a plurality of vias are formed on the upper layer of the wiring layer 630, and electrodes are bonded to each via. For example, an electrode 862 connected to a conductor post is bonded to via 861, and an electrode 864 connected to an optical element driver chip is bonded to via 863.

[0223] Next, as shown in FIG71, the conductor post 870 and the optical element driver chip 880 are bonded to electrodes. For example, the conductor post 870 is bonded to electrode 862. In addition, the optical element driver chip 880 has a plurality of electrode terminals 874. The electrode terminals 874 are connected to the electrodes 872 formed on the surface of the wiring layer 860 via solder 782.

[0224] Next, as shown in FIG72, the plurality of conductor posts 870 and the optical element driver chip 880 are sealed with resin 882. Thus, the plurality of conductor posts 870 and the optical element driver chip 880 are fixed.

[0225] Next, the release layer 852 and the support 850 are removed, and the release layer 852 remaining on the lower surface of the wiring layer 860 is removed. Then, the upper surface of the resin 882 is ground, and as shown in FIG73, a metal layer 884 is formed on the upper surface of the optical element driver chip 880.

[0226] Next, as shown in FIG74, the entire assembly is flipped over so that the metal layer 884 becomes the lower surface, and the optical element chip 890 is bonded to the upper surface of the wiring layer 860. The optical element chip 890 is provided with a light-emitting element 892, a light-receiving element 894, and multiple electrode terminals 896. The optical element chip 890 is bonded to the wiring layer 860 by bonding the multiple electrode terminals 896 to the electrodes 866 of the wiring layer 860 via solder 868. Then, the lower side of the optical element chip 890, the light-emitting element 892, the light-receiving element 894, and the multiple electrode terminals 896 are sealed with resin 898. This forms the optical module 89.

[0227]

[0228] A method for manufacturing a wafer integration according to other embodiments will be described with reference to Figures 75 to 79.

[0229] First, as shown in FIG75, a support 900 on which a release layer 902 is formed is prepared, and various conductors are formed on the surface of the release layer 902. Specifically, electrodes 906 connected to conductor pillars and columnar connection portions 908 (high pillars) connected to the wafer integration module are formed.

[0230] Next, as shown in FIG76, various components are formed on the various conductors formed on the release layer 902. For example, conductor pillars 907 may be formed on the electrode 906, or a chip integration module 909 may be connected to the pillar-shaped connection portion 908. The chip integration module 909 may be connected to the pillar-shaped connection portion 908 by solder provided on the pillar-shaped connection portion 908. If the thickness of the bridge of the chip integration module is thin enough, the pillar-shaped connection portion 908 may also be replaced by solder bumps with a relatively low height.

[0231] Next, as shown in FIG77, various components formed are sealed with resin. Specifically, the conductor post 907, the columnar connector 908, and the chip integration module 909 can be sealed with resin 914. Thereafter, the support 900 and the release layer 902 are removed from the wiring layer 904. Then, the resin 914 is ground to expose the conductor post 907 and the chip integration module 909.

[0232] Next, as shown in FIG. 78, a wiring layer 912 is formed on the resin 914. More specifically, the wiring layer 912 is formed on the resin 914 so that the wiring included in the wiring layer 912 is connected to the exposed portion of the conductor post 907 or the exposed portion of the chip integration module 909. For example, the electrode 916 formed on the wiring layer 912 can be connected to the conductor post 907 via a via. In addition, the contact metal 918 can be connected to the chip integration module 909 via a via.

[0233] Next, as shown in FIG79, a heat dissipation mechanism 922 is mounted on the contact metal 918. Then, the optical module 917, to which the optical wiring 920 is connected, is connected to the electrode 916. Thus, the chip integration of this embodiment is manufactured.

[0234] <Integrated Circuit Chip>

[0235] FIG80 is a diagram showing an example of the structure of an integrated circuit chip as an embodiment. The integrated circuit chip 35 includes a wiring layer 350, a transistor 370, and a connection layer 390 connecting the wiring layer 350 and the transistor 370.

[0236] The wiring layer 350 has a five-layer stacked structure, each layer having a film for interlayer insulation, wiring embedded in the film, and vias connecting the wiring of adjacent layers. For example, wiring 352 of the second layer and wiring 354 of the third layer are connected via vias 353, with wiring 354 embedded in the insulating film 356. The film of each layer may be made of, for example, BPSG (Boron-Phosphorous Silicate Glass). The wiring of each layer may be made of, for example, a metal such as copper. Furthermore, the wiring of the upper layers (e.g., the fifth and fourth layers) serves as power or ground, and therefore may not be as fine as the wiring of the other layers.

[0237] Several representative embodiments have been described above with reference to the accompanying drawings, but various modifications exist to the embodiments and variations described above. Appropriate changes can be made to a portion of the embodiments without contradicting the above description. Furthermore, for example, a portion of the embodiments and variations described above can be combined with a portion of other embodiments.

[0238] In the above embodiments, examples of various columnar connectors oriented in a direction substantially perpendicular to the surface of the bare die have been mainly described. However, this is not a limitation; various columnar connectors can be formed in any orientation as long as they extend in a direction toward other bare dies. Furthermore, the various dimensions, cross-sectional shapes, and aspect ratios (the ratio of the dimension in the cross-sectional direction to the dimension in the direction perpendicular to it) of the columnar connectors can be appropriately set according to performance, reliability, and optional manufacturing processes.

[0239] In the above embodiments, when the bridge includes a chip, an example was mainly described in which the bridge includes wiring and the chip is connected to the bridge electrodes via the wiring. However, this is not a limitation; the bridge may not include wiring, and the chip may be directly connected to the bridge electrodes.

[0240] Furthermore, in the above embodiments, examples of various bare dies (e.g., first bare dies and second bare dies) including wiring have been mainly described. However, it is not limited to this; a bare die may also not include wiring. In this case, the integrated circuit chip of the bare die can be directly connected to the bare die electrode.

[0241] In the above embodiment, a thin film wiring layer formed on the support 900 is used as wiring 904, but wiring 904 is not limited to this, and various conventional intermediates and wiring substrates can also be used.

[0242] Potential for industrial use

[0243] This invention can be widely applied to semiconductor modules, etc. [Simplified Explanation of the Diagram]

[0020] FIG1 is a schematic diagram of a wafer integration system according to one embodiment; FIG2 is a perspective view showing a structural example of the wafer integration shown in FIG1; FIG3 is an explanatory diagram showing a structural example of the wafer integration shown in FIG2; FIG4 is an enlarged cross-sectional view showing a structural example of a portion of the wafer integration module shown in FIG3; FIG5 is an explanatory diagram schematically showing a structural example of the optical module shown in FIG3; FIG6 is an explanatory diagram showing an outline of a manufacturing method of a wafer integration module as an embodiment; FIG7 is an explanatory diagram showing an outline of the manufacturing process of the wafer integration module shown in FIG4; FIG8 is an enlarged cross-sectional view showing details of the connection forming process shown in FIG7; FIG9 is an enlarged cross-sectional view showing details of the connection forming process immediately following FIG8; FIG10 is an enlarged cross-sectional view showing details of the connection forming process immediately following FIG9; FIG11 is an enlarged cross-sectional view showing details of the connection forming process immediately following FIG10; FIG12 is an enlarged cross-sectional view showing details of the connection forming process immediately following FIG11. Figure 13 is an enlarged cross-sectional view showing details of the semiconductor die mounting process shown in Figure 7; Figure 14 is an enlarged cross-sectional view showing details of the semiconductor die mounting process immediately following Figure 13; Figure 15 is an enlarged cross-sectional view showing details of the semiconductor die mounting process immediately following Figure 14; Figure 16 is an enlarged cross-sectional view showing details of the first sealing process shown in Figure 7; Figure 17 is an enlarged cross-sectional view showing details of the support removal process shown in Figure 7; Figure 18 is an enlarged cross-sectional view showing details of the connector exposure process shown in Figure 7; Figure 19 is an enlarged cross-sectional view showing details of the connector exposure process immediately following Figure 18; Figure 20 is an enlarged cross-sectional view showing details of the bridge mounting process shown in Figure 7; Figure 21 is an enlarged cross-sectional view showing details of the bridge mounting process immediately following Figure 20; Figure 22 is an enlarged cross-sectional view showing details of the bridge mounting process immediately following Figure 21; Figure 23 is an enlarged cross-sectional view showing details of the second sealing process shown in Figure 7. Figure 24 is an enlarged cross-sectional view showing a modified example of Figure 23; Figure 25 is an enlarged cross-sectional view showing a modified example of the sealing body shown in Figure 4; Figure 26 is an enlarged cross-sectional view showing another modified example of the sealing body shown in Figure 4; Figure 27 is an enlarged cross-sectional view showing another modified example of the sealing body shown in Figure 4; Figure 28 is an enlarged cross-sectional view of a wafer integration module as a modified example of Figure 4; Figure 29 is an explanatory diagram showing a summary of the manufacturing process of the wafer integration module shown in Figure 28; Figure 30 is an enlarged cross-sectional view showing details of the insulating layer formation process shown in Figure 29; Figure 31 is an enlarged cross-sectional view showing details of the insulating layer formation process immediately following Figure 30; Figure 32 is an enlarged cross-sectional view showing details of the connector formation process shown in Figure 29; Figure 33 is an enlarged cross-sectional view showing details of the semiconductor die mounting process shown in Figure 29; Figure 34 is an enlarged cross-sectional view showing details of the semiconductor die mounting process immediately following Figure 33.Figure 35 is an enlarged cross-sectional view showing details of the semiconductor die mounting process immediately following Figure 34; Figure 36 is an enlarged cross-sectional view showing details of the sealing process shown in Figure 29; Figure 37 is an enlarged cross-sectional view showing details of the interconnect exposure process shown in Figure 29; Figure 38 is an enlarged cross-sectional view showing details of the interconnect exposure process immediately following Figure 37; Figure 39 is an enlarged cross-sectional view showing details of the bridge mounting process shown in Figure 29; Figure 40 is an enlarged cross-sectional view showing details of the bridge mounting process immediately following Figure 39; Figure 41 is an enlarged cross-sectional view showing details of the bridge mounting process immediately following Figure 40; Figure 42 is an explanatory diagram showing a modified example of the wafer integration shown in Figure 3; Figure 43 is an explanatory diagram showing other modified examples of the wafer integration shown in Figure 3; Figure 44 is a cross-sectional view showing a modified example of the bridge shown in Figure 4; Figure 45 is a cross-sectional view showing an outline of the wiring layer formation process in the manufacturing process of the bridge shown in Figure 44; Figure 46 is a cross-sectional view showing an outline of the wiring layer transfer process in the manufacturing process of the bridge shown in Figure 44; Figure 47 is a cross-sectional view showing an outline of the support removal process in the manufacturing process of the bridge shown in Figure 44; Figure 48 is an explanatory diagram showing other variations of the bridge shown in Figure 4; Figure 49 is a diagram showing the structure of a chip integration module as part of a variation of Figure 4; Figure 50 is a diagram showing the structure of a chip integration module related to a first variation of the chip integration module shown in Figure 49; Figure 51 is a diagram showing the structure of a chip integration module related to a second variation of the chip integration module shown in Figure 49; Figure 52 is a diagram showing the structure of a chip integration module related to a third variation of the chip integration module shown in Figure 49; Figure 53 is a diagram showing the structure of a chip integration module related to a fourth variation of the chip integration module shown in Figure 49; Figure 54 is a diagram showing the structure of a chip integration module related to a fifth variation of the chip integration module shown in Figure 49; Figure 55 is a diagram used to explain the manufacturing method of a chip integration module related to other embodiments. Figure 56 is a diagram illustrating a method for manufacturing a chip integrated module related to an embodiment; Figure 57 is a diagram illustrating a method for manufacturing a chip integrated module related to an embodiment; Figure 58 is a diagram illustrating a method for manufacturing a chip integrated module related to an embodiment; Figure 59 is a diagram illustrating a method for manufacturing a chip integrated module related to an embodiment; Figure 60 is a diagram illustrating a method for manufacturing a chip integrated module related to an embodiment; Figure 61 is a diagram illustrating a method for manufacturing a chip integrated module according to a sixth variation of the method for manufacturing the chip integrated module shown in Figures 55-60; Figure 62 is a diagram illustrating a method for manufacturing a chip integrated module according to a sixth variation of the method for manufacturing the chip integrated module shown in Figures 55-60.Figure 63 is a diagram illustrating a method for manufacturing a wafer integrated module according to a sixth modification of the method for manufacturing the wafer integrated module shown in Figures 55-60; Figure 64 is a diagram illustrating a method for manufacturing a wafer integrated module according to a sixth modification of the method for manufacturing the wafer integrated module shown in Figures 55-60; Figure 65 is a diagram illustrating a method for manufacturing a wafer integrated module according to a seventh modification of the method for manufacturing the wafer integrated module shown in Figures 55-60; Figure 66 is a diagram illustrating a method for manufacturing a wafer integrated module according to a seventh modification of the method for manufacturing the wafer integrated module shown in Figures 55-60; Figure 67 is a diagram illustrating a method for manufacturing a wafer integrated module according to an eighth modification of the method for manufacturing the wafer integrated module shown in Figures 55-60; Figure 68 is a diagram illustrating a method for manufacturing a wafer integrated module according to an eighth modification of the method for manufacturing the wafer integrated module shown in Figures 55-60; Figure 69 is a diagram illustrating a method for manufacturing a wafer integrated module according to an eighth modification of the method for manufacturing the wafer integrated module shown in Figures 55-60. Figure 70 is a diagram illustrating a method for manufacturing an optical module according to one embodiment; Figure 71 is a diagram illustrating a method for manufacturing an optical module according to the same embodiment; Figure 72 is a diagram illustrating a method for manufacturing an optical module according to the same embodiment; Figure 73 is a diagram illustrating a method for manufacturing an optical module according to the same embodiment; Figure 74 is a diagram illustrating a method for manufacturing an optical module according to the same embodiment; Figure 75 is a diagram illustrating a method for manufacturing a wafer integrated circuit according to another embodiment; Figure 76 is a diagram illustrating a method for manufacturing a wafer integrated circuit according to the same embodiment; Figure 77 is a diagram illustrating a method for manufacturing a wafer integrated circuit according to the same embodiment; Figure 78 is a diagram illustrating a method for manufacturing a wafer integrated circuit according to the same embodiment; Figure 79 is a diagram illustrating a method for manufacturing a wafer integrated circuit according to the same embodiment; and Figure 80 is a diagram showing a structural example of an integrated circuit wafer according to one embodiment.

Claims

1. An electronic device comprising: a first die having a first electrode; a second die having a second electrode; a first connection portion electrically connected to the first electrode; a second connection portion electrically connected to the second electrode; and a bridge electrically connected to the first connection portion and the second connection portion, the first connection portion having a columnar connection portion extending from the bridge toward the first die; the columnar connection portion having a first columnar connection portion extending from the bridge toward the first electrode, and a second columnar connection portion directly connected to an end of the first columnar connection portion and extending from the end of the first columnar connection portion toward the first electrode, the cross-sectional area of ​​the portion of the first columnar connection portion connected to the second columnar connection portion being larger than the cross-sectional area of ​​the portion of the second columnar connection portion connected to the first columnar connection portion.

2. The electronic device as claimed in claim 1, wherein, It also includes a sealing component that integrally seals the first bare crystal and the second bare crystal.

3. The electronic device as claimed in claim 1, wherein, The bridge circuit includes a chip.

4. The electronic device as claimed in claim 1, wherein, The bridge is connected to the first columnar connection via solder.

5. The electronic device as claimed in claim 1, wherein, The first die is connected to the first connection portion by a hybrid bonding, the second die is connected to the second connection portion by a hybrid bonding, and the first die and the second die are integrally sealed by a sealing member.

6. An electronic module comprising: the electronic device described in claim 1; a wiring layer having wiring disposed therein; and a connection portion for electrically connecting the wiring to the electronic device.

7. The electronic module as described in claim 6, wherein, The first bare die has a third electrode electrically connected to the third connection portion. The first bare die, the third electrode, and the third connection portion are integrally sealed by a sealing member. The third connection portion passes through the sealing member and is connected to the wiring layer.

8. A method of manufacturing an electronic device, comprising the following processes: a forming process, forming a first connecting portion and a second connecting portion on a support body, each including a columnar connecting portion protruding from the support body; a die bonding process, bonding a first electrode of a first die to the first connecting portion, and bonding a second electrode of a second die to the second connecting portion; a sealing process, sealing the first die, the second die, and the first connecting portion with resin; and a bridge bonding process, bonding a bridge to the lower portion of the first connecting portion and the lower portion of the second connecting portion, wherein the first connecting portion has a columnar first columnar connecting portion and a columnar second columnar connecting portion, the forming process comprising: The process of forming the first connection portion on the support body is such that the first connection portion protrudes from the support body toward the first bare die; The process of directly forming the second connection portion on the first connection portion, such that the second columnar connection portion protrudes from the first columnar connection portion toward the first bare die, the cross-sectional area of ​​the portion of the first columnar connection portion connected to the second columnar connection portion is greater than the cross-sectional area of ​​the portion of the second columnar connection portion connected to the first columnar connection portion, and the bare die bonding process includes the process of bonding the first bare die to the second columnar connection portion.

Images