Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for manufacturing semiconductor devices, which mainly involves providing a first wafer and a second wafer, wherein the first wafer includes an element wafer and the second wafer includes a blank wafer, then bonding the first wafer and the second wafer, performing a thermal processing process to separate the second wafer into a first part and a second part, and then planarizing the first part.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor element, in particular to a method for bonding two wafers. Prior Art

[0002] With the continuous development and growth of electronic products such as digital cameras and scanners, the consumer market's demand for image sensors continues to increase. Generally speaking, commonly used image sensors include charge coupled devices (CCD sensors) and CMOS image sensors (CIS). CMOS image sensors are widely used due to their low operating voltage, low power consumption, high operating efficiency, on-demand random access, and their ability to be integrated into current semiconductor technology for mass production.

[0003] However, hybrid bonding, when connecting wafers carrying semiconductor devices such as CMOS image sensors, typically requires a chemical mechanical polishing (CMP) process to remove material from the wafer's backside. This step not only raises concerns about flatness but also presents another challenge: accurate wafer alignment during bonding. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, which mainly provides a first wafer and a second wafer, wherein the first wafer includes a device wafer and the second wafer includes a blank wafer, then joins the first wafer and the second wafer, performs a heat treatment process to separate the second wafer into a first part and a second part, and then flattens the first part.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a first wafer including a device wafer, a second wafer including a blank wafer, an electrode layer arranged on the second wafer, a dielectric layer surrounding the second wafer and the electrode layer, and a first metal interconnect arranged in the dielectric layer and connecting the first wafer and the electrode layer. Simple diagram description

[0006] FIG1 to FIG14 are schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG15 is a schematic diagram of a three-dimensional structure of a semiconductor device according to an embodiment of the present invention. Implementation Method

[0007] Please refer to Figures 1 to 14, which are schematic diagrams of a method for fabricating semiconductor devices according to an embodiment of the present invention. As shown in Figure 1, a first wafer 12 and a second wafer 14, such as a first silicon wafer and a second silicon wafer, are first provided. The first wafer 12 preferably comprises a device wafer, and the second wafer 14 comprises a blank wafer. More specifically, the first wafer 12 or device wafer preferably includes active components, passive components, sensors, memory components, or other semiconductor components fabricated through multiple semiconductor processes, an insulating layer covering each semiconductor component, and wires or metal patterns used to connect the semiconductor components. The second wafer 14 or blank wafer is preferably a control wafer commonly used for semiconductor process testing. None of the semiconductor components and / or metal patterns found on the first wafer 12 are present on the second wafer 14.

[0008] An ion implantation process is then used to form a doped region 16 on the second wafer 14. An insulating layer 18 composed of silicon oxide is then formed on the bottom surface of the second wafer 14 to serve as isolation between the first wafer 12 and the second wafer 14. In this embodiment, the ion implantation process preferably implants hydrogen atoms into the second wafer 14, for example, at a location approximately halfway through the thickness of the second wafer 14 or less, to form the doped region 16 indicated by the dashed line. The doped region 16 is then separated into a first portion 22 and a second portion 24, wherein neither the first portion 22 nor the second portion 24 contains any hydrogen implantation.

[0009] Then, as shown in FIG. 2 , a bonding process is performed to bond the first wafer 12 to the second wafer 14 , wherein the insulating layer 18 on the bottom surface of the second wafer 14 is preferably in direct contact with the top surface of the first wafer 12 .

[0010] As shown in FIG. 3 , a heat treatment process 20, such as an annealing process, is then performed to heat the two wafers at a temperature of approximately 300-400 degrees Celsius. According to a preferred embodiment of the present invention, after heating, the two wafers are preferably separated from the doped region 16 of the second wafer 14, where the first portion 22 and the second portion 24 are separated. The first portion 22 is preferably used for subsequent processes, while the second portion 24 is recycled.

[0011] As shown in FIG. 4 , a planarization process is then performed, such as using chemical mechanical polishing (CMP) to planarize the top surface of the first portion 22 of the second wafer 14 .

[0012] Then, as shown in FIG. 5 , a patterned mask 26 such as a patterned photoresist is formed on the first portion 22 , wherein the patterned mask 26 includes an opening 28 exposing a portion of the surface of the first portion 22 of the second wafer 14 .

[0013] Then, as shown in FIG6 , a deposition process is performed to form an active layer 30 on the exposed surface of the first portion 22 of the second wafer 14 and the patterned mask 26. The sidewalls of the active layer 30 are preferably aligned with the sidewalls of the patterned mask 26. In this embodiment, the active layer 30 preferably comprises indium gallium zinc oxide (IGZO), but is not limited thereto.

[0014] 7 , another deposition process is then performed to form an electrode layer 32 on the active layer 30. In this embodiment, the electrode layer 32 preferably comprises indium tin oxide (ITO), but is not limited thereto.

[0015] As shown in FIG8 , a lift-off process is then performed to remove the patterned mask 26 and simultaneously form a patterned active layer 30 and electrode layer 32 on the surface of the first portion 22 of the second wafer 14. It should be noted that the lift-off process performed at this stage not only completely removes the patterned mask 26 but also removes the portion of the active layer 30 and electrode layer 32 located directly above the patterned mask 26, leaving the remaining or patterned active layer 30 and electrode layer 32 located approximately in the center of the first portion 22 of the second wafer 14. It should also be noted that although the patterned active layer 30 and the electrode layer 32 formed in this stage are exemplified by a single patterned active layer 30 and a single patterned electrode layer 32, they are not limited thereto. According to other embodiments of the present invention, a plurality of patterned active layers 30 and a plurality of patterned electrode layers 32 can be formed on the second wafer 14 in this stage, thereby being used to prepare a plurality of light sensing elements or light sensing units in subsequent processes. This variation also falls within the scope of the present invention.

[0016] Then, as shown in FIG. 9 , another patterned mask 34 such as a patterned photoresist or a patterned dielectric layer is formed on the first portion 22 of the second wafer 14 and the electrode layer 32 to expose a portion of the surface of the first wafer 14 .

[0017] As shown in Figure 10 , an etching process is then performed using a patterned mask 34 as a mask to remove a portion of the first portion 22 of the second wafer 14 and expose the surface of the insulating layer 18. The patterned mask 34 is then removed. At this stage, the width of the second wafer 14 is smaller than that of the first wafer 12, and one side of the electrode layer 32, such as the left sidewall, is preferably flush with the active layer 30 and the sidewall of the second wafer 14. It should be noted that while this embodiment preferably does not remove any of the insulating layer 18 when removing a portion of the first portion 22, this is not limiting. According to other embodiments of the present invention, a portion of the insulating layer 18 may be removed simultaneously with the removal of a portion of the first portion 22, exposing the top surface of the first wafer 12. This variation is also within the scope of the present invention.

[0018] As shown in FIG. 11 , a dielectric layer 36 , such as an interlayer dielectric layer made of silicon oxide, is then formed on the first wafer 12 and the electrode layer 32 and surrounds the first portion 22 of the second wafer 14 , the active layer 30 , and the electrode layer 32 , wherein the sidewalls of the dielectric layer 36 are preferably aligned with the sidewalls of the first wafer 12 .

[0019] 12 , a lithography and etching process is performed to remove a portion of the dielectric layer 36 , a portion of the insulating layer 18 , and a portion of the first wafer 12 to form a contact hole 38 , exposing a portion of the electrode layer 32 and portions of the first wafer 12 on both sides of the electrode layer 32 .

[0020] As shown in FIG. 13 , contact plugs or metal interconnects 40 are then formed within contact holes 38 to connect the first wafer 12 and the electrode layer 32. The metal interconnects 40 on the left side of the electrode layer 32 preferably connect and contact the electrode layer 32 and the first wafer 12, while the metal interconnects 42 on the right side of the electrode layer 32 connect from the side of the second wafer 14 to the underlying first wafer 12. From a cross-sectional view, the metal interconnects 40 on the left side of the electrode layer 32 are L-shaped, while the metal interconnects 42 on the right side of the electrode layer 32 are I-shaped.

[0021] According to one embodiment of the present invention, contact holes 38 may be filled with a desired conductive material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof. A planarization process, such as chemical mechanical polishing (CMP), is then performed to remove a portion of the conductive material to form contact plugs or metal interconnects 40 and 42.

[0022] Finally, as shown in FIG14 , another lithography and etching process may be performed to remove a portion of the dielectric layer 36 directly above the electrode layer 32 and expose the top surface of the electrode layer 32. Thus, the fabrication of a semiconductor device according to an embodiment of the present invention is completed.

[0023] Please continue to refer to Figure 15, which is a partial three-dimensional schematic diagram of the structure of Figure 14. As shown in Figure 15, compared to the previous embodiment in which only a single photosensitive element comprising an active layer 30 and an electrode layer 32 is fabricated on the second wafer 14, the present invention can form a plurality of photosensitive elements or units arranged in an array on the second wafer 14 when patterning the electrode layer 32 and the active layer 30. Each photosensitive element can be defined by a fence-like metal interconnect 40 above, and each photosensitive element can include a patterned or unpatterned electrode layer 32 and active layer 30. Furthermore, the metal interconnect 40 on the left side of Figure 14 is preferably provided in the form of a fence-like patterned metal interconnect above the electrode layer 32 and the active layer 30 in Figure 15 and connected to the first wafer 12 (not shown). The metal interconnect 42 on the right side of Figure 14 is also connected to a specific circuit in the underlying first wafer 12 via the sidewall of the second wafer 14 in Figure 15.

[0024] In summary, the present invention primarily discloses a method for integrating component wafers and blank wafers. The method involves first providing a first wafer, such as a component wafer, and a second wafer, such as a blank wafer. A portion of the second wafer is preferably doped with hydrogen ions. A heat treatment process is then performed to separate the doped regions from the undoped regions of the second wafer, thereby creating a substrate for subsequent formation of various electrode patterns and / or conductive lines. Subsequently, various conductive patterns, such as an active layer composed of IGZO and an electrode layer composed of ITO, can be formed on the two wafers, depending on process or product requirements. A dielectric layer is then formed to cover the conductive patterns, and metal interconnects are then formed to connect the conductive patterns to the upper and lower wafers. In a preferred embodiment of the present invention, combining the two wafers in this manner not only improves backside flatness but also minimizes interference between the two silicon wafers at low temperatures, such as less than 300 degrees Celsius. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0025] 12: First Wafer 14: Second wafer 16: Doping area 18: Insulation layer 20:Heat treatment process 22: Part 1 24: Part 2 26: Patterned Mask 28: Opening 30: Active layer 32: Electrode layer 34: Patterned Mask 36: Dielectric layer 38:Contact hole 40:Metal interconnect 42: Metal interconnects

Claims

1. A method for fabricating a semiconductor device, characterized in that it comprises: providing a first wafer and a second wafer, wherein the first wafer includes a device wafer and the second wafer includes a blank wafer; bonding the first wafer and the second wafer; performing a thermal processing step to separate the second wafer into a first portion and a second portion; planarizing the first portion; and forming an active layer and an electrode layer on the first portion, wherein the electrode layer includes indium tin oxide (ITO).

2. The method as described in claim 1 further comprises: forming a doped region in the second wafer; forming an insulating layer on the bottom of the second wafer; bonding the first wafer and the second wafer; performing a heat treatment process to remove the second portion; and planarizing the first portion.

3. The method as described in claim 2, wherein the doped region comprises hydrogen.

4. The method as described in claim 2, further comprising: forming a first patterned mask on the first portion; forming an active layer on the first portion and the first patterned mask; forming an electrode layer on the active layer; removing the first patterned mask; patterning the first portion; forming a dielectric layer surrounding the first portion, the active layer, and the electrode layer; forming a first metal interconnect in the dielectric layer connecting the first wafer and the electrode layer; and forming a second metal interconnect in the dielectric layer connecting the first portion.

5. The method as described in claim 4 further includes simultaneously peeling off the first patterned mask and the electrode layer and the active layer above the first patterned mask.

6. The method as described in claim 4, wherein patterning the first portion comprises: forming a second patterned mask on the first portion and the electrode layer; and removing a portion of the first portion.

7. The method as described in claim 4, wherein the active layer comprises indium gallium zinc oxide (IGZO).

8. The method as described in claim 4, wherein the first metal interconnect comprises an L-shape.

9. The method as described in claim 4, wherein the second metal interconnect includes an I-shape.

10. A semiconductor device, characterized in that it comprises: a first wafer including a device wafer; a second wafer including a blank wafer; an electrode layer disposed on the second wafer, wherein the electrode layer includes indium tin oxide (ITO); a dielectric layer surrounding the second wafer and the electrode layer; and a first metal interconnect disposed within the dielectric layer and connecting the first wafer and the electrode layer.

11. The semiconductor device as described in claim 10 further comprises: an insulating layer disposed between the first wafer and the second wafer; and an active layer disposed between the first wafer and the electrode layer.

12. The semiconductor device as described in claim 11, wherein the active layer comprises indium gallium zinc oxide (IGZO).

13. The semiconductor element as described in claim 10, wherein the width of the second wafer is smaller than the width of the first wafer.

14. The semiconductor device as described in claim 10, wherein the thickness of the second wafer is less than the thickness of the first wafer.

15. The semiconductor device as described in claim 10, wherein the sidewall of the electrode layer is flush with the sidewall of the second wafer.

16. The semiconductor element as described in claim 10, wherein the first metal interconnect comprises an L-shape.

17. The semiconductor device as described in claim 10 further includes a second metal interconnect disposed within the dielectric layer to connect the second wafer.

18. The semiconductor element as described in claim 17, wherein the second metal interconnect comprises an I-shape.

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