Photonic-electronic integrated circuit chip, semiconductor-on-insulator substrate for forming said chip, and manufacturing methods thereof

Abstract

The present invention relates to an optoelectronic integrated circuit wafer formed on a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a buried dielectric layer (11) and an active layer (12) of semiconductor material, the wafer comprising an electronic circuit portion (CE1, CE2) and a photonic interconnect interface (IPI) of the electronic circuit portion, characterized in that the electronic circuit portion (CE1, CE2) is formed in an active layer region (RE1, RE2) and its thickness is greater than the thickness of the active layer region (RP) in which the photonic interconnect interface (IPI) is formed.

Description

[Technical Field]

[0001] This invention belongs to the field of integrated circuits, and more specifically, this invention relates to the field of optoelectronic integrated circuits that include electronic and photonic components on the same chip. [Previous Technology]

[0002] Heterogeneous computing involves various electronic circuits, such as central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), neural network accelerators, and shared memory resources.

[0003] These electronic circuits are typically connected together using metal wires / connectors to form a multi-core processing unit that achieves the required computing power. However, this assembly method limits bandwidth and power density.

[0004] Photonics is a promising technology that provides optical communication on or between chips, overcoming the limitations of electrical interconnects.

[0005] 2.5D or 3D integration allows electronic circuitry to be combined with photonic interconnect interfaces. However, since this type of integration requires photonic interposers and copper vertical interconnects, it still cannot completely overcome the aforementioned limitations.

[0006] For this reason, it is necessary to combine electrons and photons on the same chip, even though this combination is quite difficult due to the conflicting requirements of the two technologies, especially in terms of manufacturing.

[0007] For example, the article "Single-chip microprocessor that communicates directly using light" by Sun C., Wade M., Lee Y. et al., Nature 528, 534-538 (2015), describes a solution for integrating an electronic circuit and an optical device on the same silicon-on-insulator (SOI) substrate, so as to provide the interconnection function of the electronic circuit through an optical path.

[0008] This solution relates to providing an SOI substrate comprising a thin silicon surface layer separated from a support substrate by a buried oxide layer, and structuring the thin silicon surface layer to form both the body of an electronic transistor and the core of an optical waveguide. However, because the buried oxide layer of the SOI substrate is very thin (< 200 nm), light propagating in the waveguide easily and rapidly dissipates into the support substrate, resulting in high loss in the waveguide. To address this issue, this solution proposes selective removal of the substrate after electro-packaging the wafer, by etching away the support substrate beneath the region containing the optical devices.

[0009] However, selective removal after encapsulation is difficult to achieve, making this solution difficult to industrialize. [Summary of the Invention]

[0010] The objective of this invention is to provide a simpler monolithic integration solution to integrate an electronic circuit section with a photonic interconnect interface on the same substrate, thereby providing the electronic circuit section with intra-chip or inter-chip optical communication with minimal metal interconnects.

[0011] Accordingly, according to a first aspect, the present invention provides an optoelectronic integrated circuit wafer formed on a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a buried dielectric layer and an active layer of semiconductor material. The wafer includes an electronic circuit portion and a photonic interconnect interface of the electronic circuit portion co-integrated in the active layer. The electronic circuit portion is fabricated in an active layer region, the thickness of which is greater than the thickness of the active layer region in which the photonic interconnect interface is fabricated.

[0012] Some preferred but non-limiting aspects of this chip are as follows: the active layer region formed therein in the photonic interconnect interface is sandwiched between the buried dielectric layer and a surface dielectric region, and the active layer region formed therein in the electronic circuit portion has no surface dielectric layer; the thickness of the active layer region formed therein in the electronic circuit portion is greater than 0.2 µm, preferably greater than 0.5 µm; the thickness of the active layer region formed therein in the photonic interconnect interface is in the range of 0.2 µm and 0.5 µm; the thickness of the buried dielectric layer is greater than 1 µm, preferably greater than 2 µm; the photonic interconnect interface includes at least one waveguide; the photonic interconnect interface further includes an active photonic circuit portion; the electronic circuit portion includes a transistor logic module; the transistor is a FinFET or GAAFET type.

[0013] According to a second aspect, the present invention relates to a semiconductor-on-insulator substrate comprising a supporting substrate, a buried dielectric layer, and an active layer of semiconductor material spaced apart from the supporting substrate by the buried oxide layer. The thickness of an active layer region for forming an electronic circuit portion is greater than the thickness of an active layer region for forming a photonic interconnect interface of the electronic circuit portion.

[0014] According to a third aspect, the present invention relates to a method for fabricating a semiconductor-on-insulator substrate according to the second aspect, comprising transferring an active layer from a donor substrate to a support substrate, the transfer comprising bonding the donor substrate and the support substrate through an oxide layer at a bonding interface.

[0015] Some preferred but non-limiting embodiments of the method are as follows: It further includes locally etching the transferred active layer to form the active layer region for fabricating the photonic interconnect interface; It further includes forming a dielectric layer on the surface of the active layer region for fabricating the photonic interconnect interface; It further includes forming the active layer region for fabricating the electronic circuit portion by local epitaxial growth; Before forming the active layer region for fabricating the electronic circuit portion, oxidizing the transferred active layer to form a dielectric layer, and locally removing the dielectric layer so that the remaining dielectric layer after local removal serves as a photomask for the local epitaxial growth; It includes forming a dielectric layer on the surface of an active layer region that has not undergone local epitaxial growth.

[0016] According to a fourth aspect, the present invention relates to a method for fabricating an optoelectronic integrated circuit wafer, comprising the steps of: fabricating a semiconductor-on-insulator substrate according to the third aspect; forming an electronic circuit portion in the active layer region for fabricating an electronic circuit portion; and forming a photonic interconnect interface in the active layer region for fabricating a photonic interconnect interface of the electronic circuit portion.

[0017] Fabricating the semiconductor-on-insulator substrate includes forming a dielectric layer on the surface of the active layer region used to fabricate the photonic interconnect interface before or after forming all or part of the photonic interconnect interface.

Implementation Method

[0019] Referring to FIG1, the present invention relates to an optoelectronic integrated circuit chip formed on a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a buried dielectric layer 11 and an active layer 12 of a semiconductor material (e.g., single crystal silicon). The buried dielectric layer 11 typically separates the active layer 12 of the semiconductor material from a supporting substrate 20.

[0020] The chip according to the present invention includes electronic circuit portions CE1 and CE2 jointly integrated in the active layer 12, and a photonic interconnect interface (IPI) of the electronic circuit portions. In the example of FIG1, the photonic interconnect interface (IPI) serves as an intra-chip interface connecting the two electronic circuit portions CE1 and CE2. The present invention also extends to a photonic interconnect interface (IPI) that serves as an inter-chip interface, interconnecting an electronic circuit portion integrated in one chip with an electronic circuit portion integrated in another chip.

[0021] Each electronic circuit section CE1, CE2 may include a transistor logic module, for example, based on FinFET ("Fin Field-Effect Transistor") or GAAFET ("Gate Field-Effect Transistor").

[0022] The photonic interconnect interface (IPI) typically includes at least one waveguide. It may also include an active photonic circuit section, such as an electro-optical modulator or even a laser transferred to the IPI interface.

[0023] According to the present invention, the electronic circuit portions CE1 and CE2 are formed in an active layer region RE1 and RE2, and their thickness is greater than the thickness of the photonic interconnect interface IPI in one of the active layer regions RP.

[0024] The thickness of the active layer regions RE1 and RE2 formed therein in the electronic circuit CE1 and CE2 may be greater than 0.2 µm, and preferably greater than 0.5 µm.

[0025] The thickness of the active layer region RP formed in the photonic interconnect interface IPI can be between 0.2 µm and 0.5 µm.

[0026] The thickness of the buried dielectric layer may be greater than 200 nm, for example, greater than 1 µm, and preferably greater than 2 µm.

[0027] In a preferred embodiment, the active layer region RP formed therein in the photonic interconnect interface IPI is sandwiched between the buried dielectric layer 11 and a surface dielectric region 21, and the active layer regions RE1 and RE2 formed therein in the electronic circuit portions CE1 and CE2 do not contain a surface dielectric layer. The thickness of the surface dielectric region 21 typically corresponds to the thickness difference between the active layer region RP formed therein in the photonic interconnect interface IPI and the active layer regions RE1 and RE2 formed therein in the electronic circuit portions CE1 and CE2.

[0028] The wafer according to the present invention is therefore fabricated on an insulator-on-semiconductor substrate having a thick buried oxide layer. The active layer region used to fabricate the electronic circuit portion is thick enough to prevent the operation of this portion from being adversely affected by the buried oxide layer. Furthermore, the thickness and optical confinement of the active layer region used to fabricate the photonic interconnect interface are optimized to form a high-quality optical interconnect in a horizontal plane.

[0029] According to another aspect, the present invention relates to a semiconductor-on-insulator substrate comprising an embedded dielectric layer 11 and an active layer 12 of a semiconductor material. In this substrate, the thickness of one of the active layer regions RE1, RE2 used to fabricate electronic circuit portions CE1, CE2 is greater than the thickness of one of the active layer regions RP used to fabricate one of the photonic interconnect interfaces IPI of the electronic circuit portion.

[0030] The present invention also relates to a method for fabricating the aforementioned semiconductor-on-insulator substrate, the method comprising transferring the active layer from a donor substrate to a support substrate. This transfer typically includes bonding the donor substrate and the support substrate by an oxide layer at a bonding interface, and may be performed by thinning the back side of the donor substrate according to BESOI technology, or by separation near a fragile plane formed in the donor substrate through ion species implantation according to Smart Cut™ technology.

[0031] Various examples of fabrication methods using Smart Cut™ technology will be described below. Referring to FIG2, the method may begin by providing a donor substrate 10, at least one surface portion of which is made of a semiconductor material. A bulk substrate 10 of single-crystal Si is illustrated in the figure. Referring to FIG3, the method includes the step of forming an oxide layer 11 on the donor substrate 10, the oxide layer being intended for forming all or part of the aforementioned buried dielectric layer 11.

[0032] According to another embodiment, the method includes the step of forming the oxide layer 11 on the support substrate 20.

[0033] Referring to Figure 4, the method further includes implanting ionic species into the donor substrate 10 to form a fragile plane 13 defining the single-crystal Si active layer 12 to be transferred. The implanted species typically contain hydrogen and / or helium. Those skilled in the art will be able to determine the required implantation dose and energy.

[0034] When the oxide layer is formed on the support substrate 20, the vulnerable plane 13 can be formed deeper in the donor substrate because the donor substrate lacks this oxide layer, which ultimately causes the thicker active layer 12 to be transferred.

[0035] Referring to Figure 5, the method includes bonding the donor substrate 10 and a support substrate 20 after implantation. This bonding involves direct bonding obtained through molecular adhesion at surface contact. Referring to Figure 6, the method then includes separating the donor substrate 10 along the vulnerable plane 13 to transfer the single-crystal Si active layer 12 onto the support substrate 20. In a known manner, this separation can be induced by heat treatment, mechanical action, or a combination of these methods. The remaining portion 10' of the donor substrate can be recycled for another purpose if necessary.

[0036] Next, one or more finishing operations may be applied to the transferred single-crystal Si active layer 12. For example, smoothing, cleaning or even polishing (e.g., chemical mechanical polishing (CMP)) may be performed to remove defects associated with ion species implantation and reduce the roughness of the transferred single-crystal Si active layer 12.

[0037] In one possible embodiment, the implantation energy is such that the thickness of the transferred active layer 12 is suitable for fabricating an electronic circuit portion, for example, greater than 0.2 µm, preferably greater than 0.5 µm. In this example, as shown in FIG7, the method may include locally etching the transferred active layer 12 to form an active layer region RP for fabricating a photonic interconnect interface. The unetched area may form active layer regions RE1, RE2 for fabricating an electronic circuit portion. Next, the method may form a dielectric layer 21 on the surface of the active layer region for fabricating the photonic interconnect interface. This formation may include thermal oxidation of the active layer 12, followed by local removal of the oxide layer formed by thermal oxidation in one or more regions of the active layer for fabricating the electronic circuit portion (as shown in FIG8 and 9). In an alternative embodiment, this formation may include locally oxidizing the active layer in one or more regions of the active layer for fabricating the photonic interconnect interface by using a photomask (e.g., a nitride-based photomask) to cover other regions of the active layer.

[0038] In another alternative embodiment, after the partial etching shown in FIG7, the method may include forming all or part of the photonic interconnect interface before forming the dielectric layer 21. For example, the method may include shaping a waveguide in the etched region RP and then forming the dielectric layer 21 on the waveguide. Thus, the waveguide system is completely confined within the dielectric layer, thereby further minimizing optical losses.

[0039] In another possible embodiment, the implanted energy system is such that the thickness of the transferred active layer 12 is not directly suitable for creating an electronic circuit portion. In this example, the method includes forming an active layer region for fabricating the electronic circuit portion by epitaxial growth.

[0040] In a first variation of this other embodiment, the method includes, after the separation shown in FIG. 6, a step of forming a dielectric layer 14 on the transferred active layer 12 by thermal oxidation, as shown in FIG. 10, and subsequently, as shown in FIG. 11, a step of partially removing the dielectric layer 14 in one or more regions of the active layer used to fabricate an electronic circuit portion, with the remaining dielectric forming the surface layer 21, which covers the active layer region used to fabricate a photonic interconnect interface. As shown in FIG. 12, then local epitaxial growth is performed to thicken one or more regions of the active layer used to fabricate an electronic circuit portion, and the dielectric layer 21 remaining after the aforementioned local removal can serve as a photomask for the local epitaxial growth.

[0041] In a second alternative embodiment, forming the active layer region for fabricating the electronic circuit portion involves local epitaxial growth immediately after separation as shown in FIG. 6. This local epitaxial growth is followed by oxidation to form the surface layer 21, which covers the active layer region for fabricating a photonic interconnect interface. This oxidation may be a local oxidation of the surface of an active layer region that has not undergone local epitaxial growth to form a dielectric layer. Alternatively, it may involve full wafer oxidation, followed by local removal, so that only the surface layer 21 covering the active layer region for fabricating a photonic interconnect interface remains.

[0042] In the third alternative embodiment, full-wafer epitaxial growth is performed after the separation shown in FIG. 6. This epitaxial growth is followed by local etching and oxidation to form the surface layer 21 covering the active layer region for fabricating a photonic interconnect interface.

[0043] As described above, the present invention also relates to a method for fabricating an optoelectronic integrated circuit wafer as shown in FIG1. ​​The method comprises the following steps: fabricating a semiconductor-on-insulator substrate according to the method of the present invention, various alternative embodiments of which have been disclosed above; forming an electronic circuit portion in the active layer region for fabricating an electronic circuit portion; and forming a photonic interconnect interface in the active layer region for fabricating a photonic interconnect interface of the electronic circuit portion.

[0044] In this method, fabricating the semiconductor-on-insulator substrate may include forming the dielectric layer 21 on the surface of the active layer region used to fabricate the photonic interconnect interface before or after forming all or part of the photonic interconnect interface. [Simplified Explanation of the Diagram]

[0018] Further aspects, objectives, advantages, and features of the present invention will become more apparent from reading the following preferred embodiments (non-limiting examples) and referring to the accompanying drawings, in which: FIG1 illustrates an optoelectronic integrated circuit chip of the present invention; FIG2 illustrates a schematic cross-sectional view of a single-crystal Si donor substrate; FIG3 illustrates a schematic cross-sectional view of a dielectric layer formed on the surface of the single-crystal Si donor substrate; FIG4 illustrates a schematic cross-sectional view of a fragile plane formed in the donor substrate of FIG2 by implanting ion species to define the single-crystal Si active layer to be transferred; FIG5 illustrates a schematic cross-sectional view of the assembly of the donor substrate and a support substrate of FIG3; FIG6 illustrates a schematic cross-sectional view of separating the donor substrate along the fragile plane to transfer the single-crystal Si active layer onto the support substrate; FIG7 illustrates a schematic cross-sectional view of partially etching the single-crystal Si active layer after separation in FIG6; FIG8 illustrates a schematic cross-sectional view of oxidizing the single-crystal Si active layer after partial etching in FIG7; Figure 9 shows a schematic cross-sectional view of the oxide layer formed by partial removal of the oxide in Figure 8; Figure 10 shows a schematic cross-sectional view of the single-crystal Si active layer after separation in Figure 6; Figure 11 shows a schematic cross-sectional view of the oxide layer formed by partial removal of the oxide in Figure 10; Figure 12 shows a schematic cross-sectional view of the remaining oxide layer used as a photomask for local epitaxial growth after partial removal in Figure 11.

Claims

1. An optoelectronic integrated circuit chip formed on a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate including a buried dielectric layer (11) and an active layer (12) of semiconductor material, the chip including an electronic circuit portion (CE1, CE2) and a photonic interconnect interface (IPI) of the electronic circuit portion integrated in the active layer (12), characterized in that the electronic circuit portion (CE1, CE2) is fabricated in an active layer region (RE1, RE2), the thickness of the active layer region (RE1, RE2) is greater than the thickness of an active layer region (RP) in which the photonic interconnect interface (IPI) is fabricated.

2. The chip of claim 1, wherein the active layer region (RP) where the photonic interconnect interface (IPI) is located is sandwiched between the buried dielectric layer (11) and a surface dielectric region (21), and the active layer region (RE1, RE2) where the electronic circuit portion (CE1, CE2) is located does not have a surface dielectric layer.

3. For the wafer of claim 1 or 2, the thickness of the active layer region (RE1, RE2) where the electronic circuit portion (CE1, CE2) is located is greater than 0.2 µm, preferably greater than 0.5 µm.

4. The wafer of claim 1, wherein the thickness of the active layer region (RP) where the photonic interconnect interface (IPI) is located is between 0.2 µm and 0.5 µm.

5. The wafer of claim 1, wherein the thickness of the buried dielectric layer (11) is greater than 1 µm, preferably greater than 2 µm.

6. The chip of claim 1, wherein the photonic interconnect interface (IPI) includes at least one waveguide and preferably includes an active photonic circuit portion.

7. The chip of claim 1, wherein the electronic circuit portion includes a transistor logic module, the transistor being, for example, a FinFET or GAAFET type.

8. A method for fabricating a semiconductor-on-insulator substrate, comprising transferring an active layer (12) from a donor substrate (10) to a support substrate (20), said transfer comprising bonding the donor substrate and the support substrate through an oxide layer at a bonding interface.

9. The method of claim 8 further includes partially etching the transferred active layer to form an active layer region for fabricating a photonic interconnect interface.

10. The method of claim 9, further comprising forming a dielectric layer on the surface of the active layer region used to fabricate the photonic interconnect interface.

11. The method of claim 8 further includes forming an active layer region for fabricating an electronic circuit portion by means of local epitaxial growth.

12. The method of claim 11, wherein before forming the active layer region for fabricating the electronic circuit portion, the transferred active layer is oxidized to form a dielectric layer (14), and the dielectric layer is partially removed so that the remaining dielectric layer (21) after partial removal serves as the photomask for the local epitaxial growth.

13. The method of claim 11, comprising forming a dielectric layer (21) on the surface of an active layer region that has not undergone local epitaxial growth.

14. A method for fabricating an optoelectronic integrated circuit wafer, the method comprising the steps of: fabricating a semiconductor-on-insulator substrate according to any one of claims 8 to 13; forming an electronic circuit portion in an active layer region for fabricating an electronic circuit portion; and forming a photonic interconnect interface in an active layer region for fabricating a photonic interconnect interface of the electronic circuit portion.

15. The method of claim 14, wherein fabricating the semiconductor-on-insulator substrate includes forming a dielectric layer on the surface of an active layer region for fabricating the photonic interconnect interface before or after forming all or part of the photonic interconnect interface.

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