Clock data recovery circuit, digital loop filter and device including the same

Abstract

A clock data recovery circuit includes: a binary phase detector that receives data and a clock signal and determines whether the phase of the clock signal leads or lags the phase of the data; a digital loop filter that receives the output of the binary phase detector and filters input jitter; an accumulator that accumulates the output from the digital loop filter; an encoder that encodes the output of the accumulator to generate a phase interpolation code; and a phase interpolator configured to generate a clock signal with an output phase based on the phase interpolation code. The digital loop filter includes a first integral triangular modulation (SDM) arithmetic block circuit connected to the binary phase detector.

Description

Technical Field

[0001] The present invention concept relates to a digital loop filter (DLF), and more particularly, to a digital loop filter with low latency and less operation and a clock data recovery circuit including the same. [Cross-reference to Related Applications]

[0002] This application is based on Korean Patent Application Nos. 10-2021-0155148 and 10-2022-0093462 filed with the Korean Intellectual Property Office on November 11, 2021 and July 27, 2022, respectively, and claims the priority thereof under 35 U.S.C. § 119. The entire disclosures of the Korean patent applications are incorporated herein by reference. Prior Art

[0003] With the recent technological leap, the demand for high-speed data transmission has been increasing day by day. For this purpose, a serial communication method for transmitting data at high speed is used. The serial communication method can be used for various applications, such as communication between components included in a system, data movement in an integrated circuit, and communication between independent devices via a detachable port. For example, as a fourth generation of the peripheral component interconnect express (PCIe) memory interface, which is a high-speed serial computer expansion bus standard using an expansion card, operates at a speed of 16 gigabits per second (Gbps) per lane, and the fifth gear of the M-PHY interface operates at a speed of about 24 gigabits per second per lane.

[0004] A clock data recovery circuit that generates a recovered clock signal from serial data by detecting the phase of a clock signal embedded in the serial data and generates recovered data from the serial data using the recovered clock signal can be used in various devices and applications for transmitting and receiving data by a serial communication method. Summary of the Invention

[0005] The present invention concept relates to a clock data recovery circuit, the clock data recovery circuit including a low-latency and low-operation digital loop filter for increasing jitter tolerance.

[0006] According to an aspect of the present invention concept, a clock data recovery circuit includes: a bang bang phase detector (BBPD) that receives a data and a clock signal and determines whether the phase of the clock signal is ahead of or behind the phase of the data; a digital loop filter that receives the output of the bang bang phase detector and filters the input jitter; an accumulator that accumulates the output from the digital loop filter; an encoder that encodes the output of the accumulator to generate a phase interpolation code; and a phase interpolator that is configured to generate a clock signal having an output phase according to the phase interpolation code. The digital loop filter includes a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.

[0007] According to an aspect of the present invention concept, a digital loop filter includes: a proportional path that includes a first sigma delta modulation (SDM) arithmetic block circuit; and an integral path that includes a second SDM arithmetic block circuit and an integrator. The integral path is arranged in parallel with the proportional path. The first SDM arithmetic block circuit performs a division operation on the input of the digital loop filter using a first SDM coefficient as a divisor. The second SDM arithmetic block circuit performs a division operation on the output of the first SDM arithmetic block circuit using a second SDM coefficient as a divisor.

[0008] According to another aspect of the inventive concept, a device includes: a receiving circuit; and a transmitting circuit that transmits data to the receiving circuit via a channel. The receiving circuit includes a clock data recovery circuit. The clock data recovery circuit includes: a binary phase detector that receives data and a clock signal and determines whether the phase of the clock signal is ahead of or lagging behind the phase of the data; a digital loop filter that receives the output from the binary phase detector and filters input jitter; an accumulator that accumulates the output from the digital loop filter; an encoder that encodes the output of the accumulator to generate a phase interpolation code; and a phase interpolator that generates a clock signal having an output phase based on the phase interpolation code. The digital loop filter includes: a proportional path that includes a first sigma-delta modulation (SDM) arithmetic block circuit; and an integral path that is parallel to the proportional path and includes a second SDM arithmetic block circuit and an integrator. Brief Description of the Drawings

[0009] Embodiments will be understood more clearly by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram illustrating a data transmission and reception system according to an embodiment. FIG. 2 is a block diagram illustrating a clock data recovery circuit according to an embodiment. FIG. 3 is a diagram illustrating the binary phase detector of FIG. 2. FIG. 4 is a block diagram illustrating a digital loop filter according to a comparative example. FIG. 5A is a graph illustrating a recovered clock and sinusoidal jitter according to a comparative example, and FIG. 5B is a graph illustrating the variation of jitter tolerance according to frequency. FIG. 6 illustrates an equivalent digital loop filter according to an embodiment. FIG. 7 is a graph illustrating the jitter tolerance of a clock data recovery circuit including a digital loop filter according to an embodiment. FIG. 8 is a graph illustrating a recovered clock signal of a clock data recovery circuit including an equivalent digital loop filter according to an embodiment. FIG. 9 is a block diagram of a digital clock data recovery circuit according to an embodiment. FIG. 10 is a block diagram of a digital clock data recovery circuit according to an embodiment. FIG. 11 is a block diagram illustrating a device including a clock data recovery circuit according to an embodiment. FIG. 12 is a block diagram illustrating a system including a clock data recovery circuit according to an embodiment. Embodiments

[0010] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0011] FIG. 1 is a block diagram showing a data transmission and reception system 100 according to an embodiment.

[0012] Referring to FIG. 1, the data transmission and reception system 100 may include a first device 101, a second device 102, and a transmission line 105. The first device 101 for transmitting data may transmit data to the second device 102 via the transmission line 105 through a transmission circuit 103. In an embodiment, the first device 101 may only transmit data to the second device 102, may encode the data alone to transmit the encoded data, or may transmit the data together with a clock signal.

[0013] According to an embodiment, the first device 101 may further include a serializer 110. The serializer 110 may divide the data to be transmitted to the second device 102 according to a predetermined unit, and may transmit the data as burst data according to a high-speed serial interface.

[0014] The second device 102 may receive the data transmitted by the first device 101 via the transmission line 105 and a reception circuit 104. In an embodiment, the second device 102 may further include a decoder for decrypting the encoded data. In various embodiments, the first device 101 may be referred to as a transmitting device, and the second device 102 may be referred to as a receiving device.

[0015] According to an embodiment, the second device 102 may further include a deserializer 120. The deserializer 120 may receive an input data signal including a bit sequence to generate an output data signal including parallel data.

[0016] According to an embodiment, the second device 102 may further include a clock data recovery circuit 130. The clock data recovery circuit 130 may receive an input data signal transmitted by the first device 101 in a serial communication method, and may generate an output data signal from the input data signal. The output data signal may be referred to as a recovered data signal. The input data signal may include a series of bits, i.e., a bit sequence. For example, the input data signal may include a packet composed of m bits listed in sequence. The clock data recovery circuit 130 may identify the serial data included in the input data signal by sampling the bit sequence included in the input data signal, and may generate an output data signal including parallel data from the serial data.

[0017] According to an embodiment, the input data signal may include a clock signal and serial data. The data signal including the serial data may be received from the first device 101 via the transmission line 105, and the clock signal may be received via a clock line (not shown) separated from the transmission line 105. In an embodiment, the first device 101 may have a clock signal included in the data signal, and the second device 102 may recover the clock signal included in the data signal to identify the serial data. The second device 102 may sample the bit sequence by recovering the clock signal including the change of the data signal, so that the data transfer rate may be increased. The clock signal included in the input data signal may be referred to as an embedded clock.

[0018] In various embodiments, the transmission line 105 may be referred to as one of various terms including a transmission channel and a data channel. Additionally, as shown in FIG. 1, the transmission line 105 is used for physical connection or electrical connection. However, the inventive concept is not limited thereto. According to various embodiments, the transmission line 105 may refer to a channel for wirelessly transmitting data.

[0019] FIG. 2 is a block diagram showing a clock data recovery circuit 200 according to an embodiment.

[0020] Referring to FIG. 2, the clock data recovery circuit 200 may include a binary phase detector 210 (i.e., a binary phase detector), a digital loop filter 220, an integrator 230, an encoder 240, and a phase interpolator 250.

[0021] According to an embodiment, the binary phase detector 210 may receive a signal from a comparative sampler (not shown) to determine whether the input data signal DATA_IN (i.e., data) matches the clock signal CLK (i.e., is in phase with the clock signal CLK) or to determine whether the clock signal CLK leads / lags the input data signal DATA_IN. The binary phase detector 210 may determine whether the clock signal CLK is locked together with the input data signal DATA_IN (i.e., in phase with the input data signal DATA_IN) or leads / lags the input data signal DATA_IN based on changes in the output values received by the comparative sampler (not shown) during a predefined unit interval (UI). For example, as described in detail with reference to FIG. 3, the binary phase detector 210 may compare the transitions of the clock signal CLK output from the phase interpolator 250 with the transitions of the input data signal DATA_IN to determine whether the phase of the clock signal CLK leads or lags the phase of the input data signal DATA_IN. In an embodiment, the binary phase detector 210 may extract the sign of the phase error between the phase of the input data signal DATA_IN and the phase of the clock signal CLK. For example, the sign of the phase error may indicate whether the phase of the clock signal CLK leads or lags the phase of the input data signal DATA_IN.

[0022] According to an embodiment, the digital loop filter 220 may receive the phase error signal Δpi obtained from the binary phase detector 210 to control the phase of the clock signal CLK, so that the input data signal DATA_IN and the clock signal CLK are locked together (i.e., in phase with each other). In an embodiment, the phase error signal Δpi may represent the accumulation of the clock lead amount and the clock lag amount within a predetermined clock duration. For example, the sign of the value of the clock lead amount is positive, and the sign of the value of the clock lag amount is negative. When the clock signal continuously leads the input data signal DATA_IN, the phase error signal Δpi will increase. When the clock signal continuously lags behind the input data signal DATA_IN, the phase error signal Δpi will decrease. Although not illustrated in FIG. 2, the phase error signal Δpi will be calculated via a serializer and adder circuit between the BBPD 210 and the DLF filter 220. When the value of the phase error signal Δpi dithers around "0", the digital loop filter 220 may determine that the input data signal DATA_IN and the clock signal CLK are locked together. For example, as detailed with reference to FIG. 4, when the phase of the clock signal CLK received by the binary phase detector 210 is represented by a lead value or a lag value, and when the received lead value or lag value meets or is greater than a predetermined value, the digital loop filter 220 may notify the phase interpolator 250 of the changed value of the phase interpolation code to control the phase of the clock signal CLK. In an embodiment, the phase interpolation code changes in response to the phase error signal Δpi being greater than a first threshold value that is a positive value or in response to the phase error signal Δpi being less than a second threshold value that is a negative value.

[0023] According to an embodiment, the integrator 230 may sum its output and input to provide the sum as an input thereto. For example, the integrator 230 may be implemented using an adder and a flip-flop. The flip-flop provides an output to the encoder 240 and provides feedback to the adder. The adder sums the input from the DLF 220 and the output from the flip-flop. The adder provides the sum to the flip-flop. That is, since the integrator 230 adds the input to the output, the integrator 230 may be referred to as an accumulator. In an embodiment, the integrator 230 may sum the output of the digital loop filter 220. According to an embodiment, the integrator 230 may be arranged between the digital loop filter 220 and the phase interpolator 250. When a frequency offset is provided between the input data signal DATA_IN and the clock signal CLK, in order to track the phase of the clock, in the clock data recovery circuit 200 using the phase interpolator 250, the integrator 230 may be arranged at the lower end of the digital loop filter 220 and at the front end of the phase interpolator 250.

[0024] According to an embodiment, the encoder 240 may encode an accumulated signal via the integrator 230. The encoded output of the encoder 240 may correspond to a phase interpolation code.

[0025] According to an embodiment, the phase interpolator 250 may receive a phase interpolation code from the encoder 240 to control the phase of the output clock. For example, the phase interpolator 250 may receive a source clock signal including a plurality of phase clock signals from a phase locked loop (PLL). The phase interpolator 250 may generate a clock signal CLK with a new phase by setting the weights of the plurality of phase clock signals to be different from each other based on the phase interpolation code.

[0026] FIG. 3 is a diagram showing the binary phase detector 210 of FIG. 2.

[0027] Referring to FIGS. 2 and 3, the binary phase detector 210 may include a first exclusive-OR (XOR) gate 310 and a second exclusive-OR gate 320. The output of the first exclusive-OR gate 310 may be a signal indicating whether the clock signal CLK is ahead of the input data signal DATA_IN (i.e., a signal indicating whether the phase of the clock signal CLK is ahead of the phase of the input data signal DATA_IN). The output of the second exclusive-OR gate 320 may be a signal indicating whether the clock signal CLK lags behind the input data signal DATA_IN (i.e., a signal indicating whether the phase of the clock signal CLK lags behind the phase of the input data signal DATA_IN). The first exclusive-OR gate 310 and the second exclusive-OR gate 320 may compare the logical value of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK with the logical values of the input data signal DATA_IN at each of the rising edges Ex-1 and Ex of the clock signal CLK to generate an output indicating whether the clock signal CLK is ahead of the input data signal DATA_IN or whether the clock signal CLK lags behind the input data signal DATA_IN. For example, the inputs of the first exclusive-OR gate 310 may be the logical level of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and the logical level of the input data signal DATA_IN at the previous rising edge Ex-1 of the clock signal CLK. When the inputs of the first exclusive-OR gate 310 are different from each other, the output of the first exclusive-OR gate 310 is a logical level of "logical high", and when the inputs of the first exclusive-OR gate 310 are the same as each other, the output of the first exclusive-OR gate 310 is a logical level of "logical low". For example, the inputs of the second exclusive-OR gate 320 may be the logical level of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and the logical level of the input data signal DATA_IN at the subsequent rising edge Ex of the clock signal CLK. When the inputs of the second exclusive-OR gate 320 are different from each other, the output of the second exclusive-OR gate 320 is a logical level of "logical high", and when the inputs of the second exclusive-OR gate 320 are the same as each other, the output of the second exclusive-OR gate 320 is a logical level of "logical low".

[0028] According to an embodiment, in the first scenario, Case 1, the clock signal CLK leads the input data signal DATA_IN. For example, the input data signal DATA_IN is a differential signal of two complementary signals, and one of the two complementary signals of the input data signal DATA_IN (e.g., the complementary signal that is "logic high") is an input to the first exclusive-OR gate 310. The first exclusive-OR gate 310 can perform an exclusive-OR operation on the logic level of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and the logic level of the input data signal DATA_IN at the previous rising edge Ex-1 (i.e., the prior rising edge) of the clock signal CLK. For example, the input to the first exclusive-OR gate 310 is "logic high" of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and "logic low" of the input data signal DATA_IN at the previous rising edge Ex-1 of the clock signal CLK, and the output of the first exclusive-OR gate 310 can be "logic high". The input to the second exclusive-OR gate 320 is "logic high" of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and "logic high" of the input data signal DATA_IN at the subsequent rising edge Ex of the clock signal CLK, and the output of the second exclusive-OR gate 320 can be "logic low". In an example, when the input data signal DATA_IN is a differential signal of two complementary signals and one of the two complementary signals of the input data signal DATA_IN (e.g., the complementary signal that is "logic low") is an input to the first exclusive-OR gate 310, an exclusive-OR operation can be performed on the logic level of the input data signal DATA_IN at the falling edge Dx and the logic level of the input data signal DATA_IN at the previous rising edge Ex-1 (i.e., the prior rising edge) (both of which are inputs to the first exclusive-OR gate 310). The input to the first exclusive-OR gate 310 is "logic low" of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and "logic high" of the input data signal DATA_IN at the previous rising edge Ex-1, and the output of the first exclusive-OR gate 310 can be "logic high". The input to the second exclusive-OR gate 320 is "logic low" of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and "logic low" of the input data signal DATA_IN at the subsequent rising edge Ex of the clock signal CLK, and the output of the second exclusive-OR gate 320 can be "logic low". That is, it can be noted that when the clock signal CLK leads the input data signal DATA_IN, the first exclusive-OR gate 310 outputs a "logic high" signal, and the second exclusive-OR gate 320 outputs a "logic low" signal.

[0029] According to an embodiment, in the second case (Case 2), the clock signal CLK lags behind the input data signal DATA_IN. For example, the input data signal DATA_IN is a differential signal of two complementary signals, and one of the two complementary signals of the input data signal DATA_IN (for example, the complementary signal that is "logic high") is the input of the first exclusive-OR gate 310. The first exclusive-OR gate 310 can perform an exclusive-OR operation on the logic level of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and the logic level of the input data signal DATA_IN at the previous rising edge Ex-1 of the clock signal CLK. The input of the first exclusive-OR gate 310 is the "logic high" of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and the "logic high" of the input data signal DATA_IN at the previous rising edge Ex-1, and the output of the first exclusive-OR gate 310 can be "logic low". The input of the second exclusive-OR gate 320 is the "logic high" of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and the "logic low" of the input data signal DATA_IN at the subsequent rising edge Ex of the clock signal CLK, and the output of the second exclusive-OR gate 320 can be "logic high". In an example, the input data signal DATA_IN is a differential signal of two complementary signals, and one of the two complementary signals of the input data signal DATA_IN (for example, the complementary signal that is "logic low") is the input of the first exclusive-OR gate 310. The first exclusive-OR gate 310 can perform an exclusive-OR operation on the logic level of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and the logic level of the input data signal DATA_IN at the previous rising edge Ex-1 of the clock signal CLK. The input of the first exclusive-OR gate 310 is the "logic low" of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and the "logic low" of the input data signal DATA_IN at the previous rising edge Ex-1, and the output of the first exclusive-OR gate 310 can be "logic low". The input of the second exclusive-OR gate 320 is the "logic low" of the input data signal DATA_IN at the falling edge Dx of the clock signal CLK and the "logic high" of the input data signal DATA_IN at the subsequent rising edge Ex of the clock signal CLK, and the output of the second exclusive-OR gate 320 can be "logic high". That is, it can be noted that when the clock signal CLK lags behind the input data signal DATA_IN, the first exclusive-OR gate 310 outputs a "logic low" signal, and the second exclusive-OR gate 320 outputs a "logic high" signal.

[0030] FIG. 4 is a block diagram showing a digital loop filter 400 according to a comparative example.

[0031] Referring to FIG. 4, the digital loop filter 400 may include a proportional path 401 and an integral path 403.

[0032] According to an embodiment, the proportional path 401 may include a first arithmetic block 410, a summer 420 (i.e., an adder circuit), a third arithmetic block 430, and a fourth arithmetic block 440. The proportional path 401 can quickly track the phase difference between the clock signal and the data (i.e., the input data signal) as the input. For example, the proportional path 401 can track jitter that is a high frequency. The jitter may be included in the input data signal DATA_IN. Tracking of the jitter indicates that the phase difference between the jitter and the input data signal DATA_IN is reduced. The first arithmetic block 410 may multiply the input DLF in received from the binary phase detector 210 of the digital loop filter 400 by a coefficient Kp. The summer 420 may sum the input DLF in multiplied by the coefficient Kp via the first arithmetic block 410 of the digital loop filter 400 and the input DLF in converted via the integral path 403 of the digital loop filter 400. The third arithmetic block 430 may perform integral delta modulation. For example, the third arithmetic block 430 may divide the value received from the summer 420 by a coefficient SDM. The fourth arithmetic block 440 may multiply the input received from the third arithmetic block 430 by K to generate the output DLF out of the digital loop filter 400. According to an embodiment, the gain of the proportional path 401 including the first arithmetic block 410 to the fourth arithmetic block 440 with respect to the output may be "K P*SDM*K".

[0033] According to an embodiment, the integral path 403 may include a fifth arithmetic block 450 and an integrator 460. The integral path 403 can track the phase difference between the clock signal and the data as the input. For example, the integral path 403 can track jitter that is a low frequency. The fifth arithmetic block 450 may divide the input DLF in of the digital loop filter 400 by a coefficient Ki*SDM. The integrator 460 may sum its output and the output of the fifth arithmetic block 450 to accumulate the sum. According to an embodiment, the gain of the integral path 403 including the fifth arithmetic block 450 and the integrator 460 may be "Ki*SDM*1 / (1-Z -1)*SDM*K". The gain of the integral path 403 can be a small value that is about 1 / 1000 of the gain of the proportional path 401.

[0034] According to the comparative example described above, the proportional path 401 of the digital loop filter 400 converts the input DLF in into the output DLF out via the first arithmetic block 410, the summer 420, the third arithmetic block 430, and the fourth arithmetic block 440. However, since a delay occurs due to the time spent on the operations each time the operations are performed by the first arithmetic block 410, the third arithmetic block 430, and the fourth arithmetic block 440, and since retiming occurs each time the operations are performed, the delay occurring via the proportional path 401 may be large enough. Since the integration path 403 tracks the jitter that is at a low frequency, in an environment where data is transmitted at a high frequency via a high-speed serial interface, the delay of the proportional path 401 may reduce the bit error rate (BER) of transmitting and receiving data, and may deteriorate the jitter performance.

[0035] FIG. 5A is a graph showing the recovered clock and sinusoidal jitter according to the comparative example, and FIG. 5B is a graph showing the variation of the jitter tolerance according to the frequency.

[0036] Referring to FIG. 5A, in order to measure the jitter tolerance of the clock data recovery circuit including the digital loop filter 400 according to the comparative example shown in FIG. 4, a sinusoidal jitter signal 510 may be input. For example, the sinusoidal jitter signal 510 may have a period of 2 UI.

[0037] According to an embodiment, the total delay of the clock data recovery circuit including the digital loop filter 400 may be 0.5 UI. For example, the section from the time point when the input data signal DATA_IN (see FIGS. 2 and 3) is input to the binary phase detector 210 to the time point when the clock signal CLK (see FIGS. 2 and 3) output from the phase interpolator 250 is input to the binary phase detector 210 may be the total delay. When the total delay is approximately 1 / 4 of the period of the sinusoidal jitter signal 510 (for example, 0.5 UI), the clock signal 520 recovered by the phase interpolator 250 may lag behind the sinusoidal jitter signal 510 by 1 / 2 of the period of the sinusoidal jitter signal 510 (for example, 1 UI). That is, the sinusoidal jitter signal 510 and the recovered clock signal 520 may have opposite phases. That is, the clock data recovery circuit including the digital loop filter 400 may not be able to perform normal data sampling only by receiving the sinusoidal jitter signal 510 with a small amplitude as an input.

[0038] Referring to FIG. 5B, the variation of the jitter tolerance according to the frequency of the sinusoidal jitter signal 510 is shown. For example, the first graph 530 shows the jitter tolerance varying according to the frequency change of the sinusoidal jitter signal 510 when the total delay is small enough. The second graph 540 shows the jitter tolerance varying according to the frequency change of the sinusoidal jitter signal 510 when the total delay increases. Referring to the second graph 540, when the total delay increases such that the total delay is approximately 1 / 4 of the period of the sinusoidal jitter signal 510 (e.g., 0.5 UI), underdamping occurs, causing the jitter tolerance to deteriorate rapidly. At this time, since the delay occurring in the digital loop filter 400 has the highest percentage in the total delay, it is desirable to minimize the delay occurring in the digital loop filter 400.

[0039] FIG. 6 shows an equivalent digital loop filter 600 according to an embodiment.

[0040] Referring to FIG. 6, the equivalent digital loop filter 600 may include a proportional path 601 and an integral path 603.

[0041] According to an embodiment, the proportional path 601 may include a first equivalent arithmetic block 610 and a summator 620. The proportional path 601 can quickly track the phase difference between the clock signal as the input and the data (e.g., the clock signal CLK and the input data signal DATA_IN described with reference to FIG. 3). The first equivalent arithmetic block 610 may divide the input DLF in received by the equivalent digital loop filter 600 from the binary phase detector 210 by a coefficient K p.

[0042] Referring to the comparative example of FIG. 4, the gain DLF out / DLF in of the digital loop filter 400 can have a very small value (<1). Therefore, since the final output of the equivalent digital loop filter 600 must have a small value, the equivalent digital loop filter 600 can include a first equivalent arithmetic block 610 such that the equivalent digital loop filter 600 has the same gain as the transfer function of the proportional path 401 of the digital loop filter 400 in FIG. 4. At this time, from the perspective of the proportional path 601, the equivalent digital loop filter 600 does not need to repeatedly perform a multiplication operation on the input DLF in of the equivalent digital loop filter 600 using the coefficient K p, does not need to perform a division operation using the coefficient SDM, and does not need to perform a multiplication operation using the coefficient K p again. As described above with reference to FIGS. 5A and 5B, in the proportional path 401, a delay occurs every time passing through multiple arithmetic blocks (for example, the first arithmetic block 410, the third arithmetic block 430, and the fourth arithmetic block 440), and the delay dominates in the total delay. For example, the proportional path 601 of the equivalent digital loop filter 600 according to an embodiment can perform only one division operation on the result of the operations performed by the multiple arithmetic blocks (for example, the first arithmetic block 410, the third arithmetic block 430, and the fourth arithmetic block 440) of the proportional path 401 of the digital loop filter 400 by an equivalent coefficient. Since the gain of the proportional path 601 is less than 1, the first equivalent arithmetic block 610 can equivalently perform only one division operation. In an embodiment, the proportional path 601 of the equivalent digital loop filter 600 according to an embodiment can use the coefficient K p*SDM as a divisor to perform a division operation on the output of the binary phase detector. Using the coefficient K p*SDM as a divisor can have the effect of performing a division operation on the result of the operations performed by the multiple arithmetic blocks (for example, the first arithmetic block 410, the third arithmetic block 430, and the fourth arithmetic block 440) of the proportional path 401 of the digital loop filter 400. Since the gain of the proportional path 601 is less than 1, the first equivalent arithmetic block 610 can equivalently perform only one division operation using the coefficient K p*SDM.

[0043] The summer 420 can sum the input DLF in of the equivalent digital loop filter 600 multiplied by K p*SDM via the first equivalent arithmetic block 610 and the input DLF in of the equivalent digital loop filter 600 converted via the integration path 603. According to an embodiment, the input-to-output gain of the proportional path 601 including the first equivalent arithmetic block 610 can be "K p*SDM".

[0044] According to an embodiment, the integration path 603 may include a third equivalent arithmetic block 630 and an integrator 640. The integration path 603 may track the phase difference between a clock signal and data as an input. The third equivalent arithmetic block 630 may divide the input DLF in of the equivalent digital loop filter 600 by K i*SDM. For example, the third equivalent arithmetic block 630 may perform a division operation on the output of the first equivalent arithmetic block 610. The integrator 640 may sum its output and the output of the third equivalent arithmetic block 630 to accumulate the sum. For example, the integration path 603 may perform a division operation on a value obtained by using the coefficient K p*SDM to divide the input DLF in of the equivalent digital loop filter 600 by the first equivalent arithmetic block 610 using the coefficient K i / K p*SDM as a divisor. Therefore, when the coefficients "K p*SDM" and "K i / K p*SDM" are controlled, the equivalent digital loop filter 600 may have the same gain as the gain of the digital loop filter 400 in FIG. 4, and may operate with less delay and fewer operations compared to the digital loop filter 400 in FIG. 4.

[0045] FIG. 7 is a graph showing the jitter tolerance of a clock data recovery circuit including an equivalent digital loop filter 600 according to an embodiment.

[0046] Referring to FIG. 7, the first curve 710 shows the standard specification of the M-PHY fifth gear. In other words, although the jitter tolerance deteriorates according to the frequency change, a jitter tolerance larger than the jitter tolerance of the first curve 710 must be provided.

[0047] The second curve 720 shows the result of measuring the jitter tolerance of a clock data recovery circuit including the digital loop filter 400. For example, the second curve 720 may show the result of measuring the jitter performance of a clock data recovery circuit including the digital loop filter 400 in FIG. 4. At this time, it can be noted from the second curve 720 that underdamping occurs, so that the jitter tolerance deteriorates rapidly in the bandwidth (e.g., 10 8 Hz) of the clock data recovery circuit. It can be noted that the jitter tolerance when underdamping occurs has a margin of 0.046 UI from the jitter tolerance of the first curve 710.

[0048] The third curve 730 shows the result of measuring the jitter tolerance of a clock data recovery circuit including the equivalent digital loop filter 600 according to an embodiment. For example, the third curve 730 may show the result of measuring the jitter performance of a clock data recovery circuit including the equivalent digital loop filter 600 of FIG. 6. At this time, it can be noted from the third curve 730 that underdamping occurs, such that the jitter tolerance rapidly deteriorates in the bandwidth (e.g., 10 8 Hz) of the clock data recovery circuit. It can be noted that the jitter tolerance when underdamping occurs has a margin of 0.107 UI compared to the jitter tolerance of the first curve 710. That is, the clock data recovery circuit including the equivalent digital loop filter 600 of FIG. 6 (where the delay is reduced) can ensure that the jitter tolerance margin is approximately 2.3 times the jitter tolerance margin of a conventional clock data recovery circuit.

[0049] FIG. 8 is a graph showing a recovered clock signal of a clock data recovery circuit including an equivalent digital loop filter 600 according to an embodiment.

[0050] Referring to FIG. 8, clock signals recovered by a clock data recovery circuit including a digital loop filter 400 according to a comparative example of FIG. 4 and a clock data recovery circuit including the equivalent digital loop filter 600 of FIG. 6 are shown, respectively.

[0051] To measure the jitter tolerance, a first signal 810, which is a sinusoidal jitter signal, may be input. At this time, the frequency of the first signal 810 may be 100 megahertz. A second signal 820 shows the clock signal recovered by a clock data recovery circuit including the digital loop filter 400 according to the comparative example of FIG. 4. It can be noted that the second signal 820 is recovered to have a phase opposite to that of the first signal 810.

[0052] A third signal 830 shows the clock signal recovered by a clock data recovery circuit including the equivalent digital loop filter 600 of FIG. 6. Different from the second signal 820 whose phase is opposite to that of the first signal 810, it can be noted that the third signal 830 is recovered to be delayed from the first signal 810 by about 0.005 microseconds. That is, the third signal 830 can be recovered to have a smaller phase difference than the phase difference of the second signal 820.

[0053] FIG. 9 is a block diagram of a digital clock data recovery circuit 1000 according to an embodiment.

[0054] Referring to FIG. 9, the digital clock data recovery circuit 1000 may include a binary phase detector 1010, a digital loop filter 1020, and a digitally controlled oscillator (DCO) 1030.

[0055] According to an embodiment, the binary phase detector 1010 may receive a signal from a comparison sampler to determine whether the data matches the clock signal or whether the clock signal is ahead of / lagging behind the input data signal DATA_IN. The binary phase detector 1010 may determine whether the clock signal is locked together with the input data signal DATA_IN or is ahead of / lagging behind the input data signal DATA_IN based on the change in the output value received by a comparison sampler (not shown) during a predefined UI period. For example, the binary phase detector 1010 may compare the transition of the clock signal to be divided output from the DCO 1030 with the transition of the input data signal DATA_IN to determine whether the phase of the clock signal is ahead of or lagging behind the phase of the input data signal DATA_IN.

[0056] According to an embodiment, the digital loop filter 1020 may receive a phase error signal Δpi from the binary phase detector 1010 to control the phase of the clock signal such that the input data signal DATA_IN and the clock signal CLK are locked together with each other. When the value of the phase error signal Δpi fluctuates near "0", the digital loop filter 1020 may determine that the input data signal DATA_IN and the clock signal are locked together with each other. For example, the digital loop filter 1020 may receive the ahead value or lag value of the phase of the clock signal received from the binary phase detector 1010, and may generate a DCO control code to provide the generated DCO control code to the DCO 1030. According to an embodiment, the DCO 1030 may generate a signal with a variable frequency based on the DCO control code received from the digital loop filter 1020.

[0057] FIG. 10 is a block diagram of a digital clock data recovery circuit 1100 according to an embodiment.

[0058] Referring to FIG. 10, the digital clock data recovery circuit 1100 may include a time to digital converter (TDC) 1110, a digital loop filter 1120, and a DCO 1130.

[0059] According to an embodiment, the TDC 1110 may receive a reference clock signal Ref CLK and a clock signal divided by the DCO 1130. The TDC 1110 may compare the time point when the reference clock signal Ref CLK is received with the time point when the divided clock signal is received to detect the time difference. For example, the TDC 1110 may generate skew information representing the time difference. For example, the TDC 1110 may receive the reference clock signal Ref CLK at a first time point and may receive the clock signal divided by the DCO 1130 at a second time point later than the first time point. At this time, the TDC 1110 may determine how many clock signals have elapsed between the first time point and the second time point according to the reference clock signal and may generate skew information.

[0060] According to an embodiment, the digital loop filter 1120 may receive skew information from the TDC 1110 to control the phase of the clock signal so that the clock signal divided by the DCO 1130 and the reference clock signal Ref CLK are locked to each other. When the value of the phase error signal ∆pi fluctuates near "0", the digital loop filter 1120 may determine that the data and the clock signal are locked to each other. For example, the digital loop filter 1120 may receive the leading value or the lagging value of the phase of the clock signal received from the TDC 1110 and may generate a DCO control code to provide the generated DCO control code to the DCO 1130. According to an embodiment, the DCO 1130 may generate a signal with a variable frequency based on the DCO control code received from the digital loop filter 1120.

[0061] FIG. 11 is a block diagram showing a device including a clock data recovery circuit according to an embodiment.

[0062] The clock data recovery circuit according to an embodiment may be included in the receiving circuit 1422. The device may be a computing system including a display panel 1400, and as a non-limiting example, may be a stationary system such as a desktop computer, a server, a television (TV) set, or a billboard, or a mobile system such as a laptop computer, a mobile phone, a tablet personal computer (PC), or a wearable device. As shown in FIG. 11, the device may include a motherboard 1300 and a display panel 1400, and the input data signal DATA_IN may be transmitted from the motherboard 1300 to the display panel 1400 via the data line 1500.

[0063] The motherboard 1300 may include a processor 1320, and the processor 1320 may include a transmission circuit 1322. The processor 1320 may refer to a processing unit that performs computing operations, such as a microprocessor, a microcontroller, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In some embodiments, the processor 1320 may be a video graphics processor, such as a graphics processing unit (GPU). The processor 1320 may generate image data corresponding to an image output via a display 1440 included in the display panel 1400, and the image data may be provided to the transmission circuit 1322.

[0064] The transmission circuit 1322 may output an input data signal DATA_IN to the receiving circuit 1422 for the clock data recovery operation of the receiving circuit 1422. The display panel 1400 may include a display controller 1420 and a display 1440. The display controller 1420 may receive the input data signal DATA_IN from the motherboard 1300 and may perform a clock data recovery operation using the input data signal DATA_IN. In some embodiments, the display controller 1420 may provide a display signal SIG for controlling pixels included in the display 1440 and may be referred to as a display driver integrated circuit (DDI).

[0065] The display controller 1420 may include a receiving circuit 1422, and the receiving circuit 1422 may receive the input data signal DATA_IN. The receiving circuit 1422 may include a clock data recovery circuit according to an embodiment and may generate a recovered clock signal and recovered data from the input data signal DATA_IN. The clock data recovery circuit included in the receiving circuit 1422 may include a digital loop filter for minimizing the phase difference between the recovered clock signal and the input data.

[0066] The display 1440 may include any type of display, as non-limiting examples, including, for example, a liquid crystal display (LCD), a light emitting diode (LED) display, an electroluminescent display (ELD), a cathode ray tube (CRT) display, a plasma display panel (PDP) display, or a liquid crystal on silicon (LCoS) display. In FIG. 11, the device is shown as including a display panel 1400. However, in some embodiments, the device may include two or more display panels, i.e., two or more displays.

[0067] FIG. 12 is a block diagram showing a system 2000 including clock data recovery circuits 2240 and 2464 according to an embodiment.

[0068] Referring to FIG. 12, the system 2000 may include a host 2200 and a storage device 2400. The storage device 2400 may be referred to as a memory system or a storage system, and may include a signal connector 2001, a plurality of non-volatile memories 2420_1 to 2420_n, a buffer memory 2440, and a controller 2460. For example, the controller 2460 may be referred to as a memory controller or a storage controller.

[0069] The storage device 2400 can transmit signals to the host 2200 via the signal connector 2001 and receive signals from the host 2200. The host 2200 and the storage device 2400 can communicate with each other via electrical signals and / or optical signals, and as a non-limiting example, can communicate with each other via a universal flash storage (UFS) interface, a serial advanced technology attachment (SATA) interface, a SATA express (SATAe) interface, a small computer small interface (SCSI) interface, a serial attached SCSI (SAS) interface, a peripheral component interconnect express (PCIe) interface, a non-volatile memory express (NVMe) interface, an advanced host controller interface (AHCI) interface, or a combination of the above communication interfaces.

[0070] The controller 2460 can control the plurality of non-volatile memories 2420_1 to 2420_n in response to signals received from the host 2200. The controller 2460 can include a serial communication interface circuit 2462 for transmitting and receiving data, and can include a clock data recovery circuit 2464 for applying the embodiments to recover the clock signal and data of the received serial data signal. The serial communication interface circuit 2462 can provide a communication interface, such as a UFS interface, a SATA interface, a SATAe interface, a SCSI interface, a SAS interface, a PCIe interface, an NVMe interface, and an AHCI interface. The buffer memory 2440 can operate for the storage device 2400. On the other hand, the host 2200 can include a serial communication interface circuit 2220 for transmitting and receiving data and a clock data recovery circuit 2240 for applying the embodiments.

[0071] Each of the plurality of non-volatile memories 2420_1 to 2420_n can include a memory cell array, the memory cell array can include memory blocks, each of the memory blocks can be divided into pages, and each of the pages can include non-volatile memory cells, such as at least one NAND flash memory cell.

[0072] Although the present inventive concept has been particularly shown and described with reference to embodiments of the present inventive concept, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the following claims.

[0073] 100: Data transmission and reception system 101: First device 102: Second device 103, 1322: Transmission circuit 104, 1422: Reception circuit 105: Transmission line 110: Serializer 120: Deserializer 130, 200, 2240, 2464: Clock data recovery circuit 210, 1010: Binary phase detector (BBPD) 220, 400, 1020, 1120: Digital loop filter (DLF) 230, 460, 640: Integrator 240: Encoder 250: Phase interpolator 310: First exclusive OR (XOR) gate 320: Second exclusive OR gate 401, 601: Proportional path 403, 603: Integral path 410: First arithmetic block 420, 620: Summing device 430: Third arithmetic block 440: Fourth arithmetic block 450: Fifth arithmetic block 510, T SJ: Sine dither signal 520, CLK: Clock signal 530: First pattern 540: Second pattern 600: Equivalent digital loop filter 610: First equivalent arithmetic block 630: Third equivalent arithmetic block 710: First curve 720: Second curve 730: Third curve 810: First signal 820: Second signal 830: Third signal 1000, 1100: Digital clock data recovery circuit 1030, 1130: Digital controlled oscillator (DCO) 1110: Time-to-digital converter (TDC) 1200: Device 1300: Motherboard 1320: Processor 1400: Display panel 1420: Display controller 1440: Display 1500: Data line 2000: System 2001: Signal connector 2200: Host 2220, 2462: Serial communication interface circuit 2400: Storage device 2420_1, 2420_2~2420_n: Non-volatile memory 2440: Buffer memory 2460: Controller clk_lead, clk_lag: Signals DATA_IN: Input data signal DLF in: Input DLF out: Output D x: Falling edge E x-1: Previous rising edge / Rising edge E x: Rising edge K i*SDM, K i / K p*SDM, K p, K p*SDM, SDM: Coefficients Ref CLK: Reference clock signal SIG: Display signal Δpi: Phase error signal

Claims

1. A clock data recovery circuit, comprising: A binary phase detector is configured to receive data and a clock signal, and to determine whether the phase of the clock signal leads or lags the phase of the data. A digital loop filter is configured to receive the output of the binary phase detector and filter input jitter; an accumulator is configured to accumulate the output from the digital loop filter; an encoder is configured to encode the output of the accumulator to generate a phase interpolation code; and a phase interpolator is configured to generate the clock signal having an output phase based on the phase interpolation code, wherein the digital loop filter includes a first integral trigonometric modulation (SDM) arithmetic block circuit connected to the binary phase detector, wherein the digital loop filter further includes a second integral trigonometric modulation arithmetic block circuit connected to the first integral trigonometric modulation arithmetic block circuit, wherein the first integral trigonometric modulation arithmetic block circuit performs division on the output of the binary phase detector using a first integral trigonometric modulation coefficient as a divisor, and wherein the second integral trigonometric modulation arithmetic block circuit performs division on the output of the first integral trigonometric modulation arithmetic block circuit using a second integral trigonometric modulation coefficient as a divisor.

2. The clock data recovery circuit as claimed in claim 1, wherein the first integral triangular modulation coefficient is different from the second integral triangular modulation coefficient.

3. The clock data recovery circuit as described in claim 1, wherein the digital loop filter further comprises: The integrator is connected to the second integral trigonometric modulation arithmetic block circuit; And an adder circuit, connected to the first integral trigonometric modulation arithmetic block circuit and the integrator, and configured to sum the output of the first integral trigonometric modulation arithmetic block circuit and the output of the integrator.

4. The clock data recovery circuit as claimed in claim 3, wherein the first integral trigonometric modulation arithmetic block circuit is included in the proportional path of the digital loop filter, the proportional path tracking jitter input at a high frequency, and wherein the second integral trigonometric modulation arithmetic block circuit and the integrator are included in the integral path of the digital loop filter, the integral path tracking jitter input at a low frequency.

5. The clock data recovery circuit as claimed in claim 4, wherein the first gain of the proportional path is less than 1, and wherein the second gain of the integral path is less than the first gain of the proportional path.

6. The clock data recovery circuit as claimed in claim 1, wherein the binary phase detector comprises: A first OR gate is configured to perform an OR operation on the data at the falling edge of the clock signal and the data at the first rising edge of the clock signal to produce a first output indicating whether the phase of the clock signal leads the phase of the data; and a second OR gate is configured to perform an OR operation on the data at the falling edge of the clock signal and the data at the second rising edge of the clock signal to produce a second output indicating whether the phase of the clock signal lags the phase of the data, wherein the first rising edge precedes the falling edge, and wherein the second rising edge follows the falling edge.

7. The clock data recovery circuit of claim 1, wherein the phase interpolator controls the output phase in response to a change in the phase interpolation code, and wherein the phase interpolation code is changed in response to a value greater than a predefined value in which the phase representing the clock signal received from the binary phase detector leads the phase of the data, or in response to a value greater than the predefined value in which the phase representing the clock signal received from the binary phase detector lags the phase of the data.

8. A digital loop filter, comprising: The proportional path includes a first integral trigonometric modulation (SDM) arithmetic block circuit; and the integral path includes a second integral trigonometric modulation arithmetic block circuit and an integrator, the integral path being configured in parallel with the proportional path, wherein the first integral trigonometric modulation arithmetic block circuit uses a first integral trigonometric modulation coefficient as a divisor to perform a division operation on the input of the digital loop filter, and wherein the second integral trigonometric modulation arithmetic block circuit uses a second integral trigonometric modulation coefficient as a divisor to perform a division operation on the output of the first integral trigonometric modulation arithmetic block circuit.

9. The digital loop filter of claim 8, wherein the first gain of the proportional path is less than 1, and wherein the second gain of the integral path is less than the first gain of the proportional path.

10. The digital loop filter as claimed in claim 8, wherein the first integral triangular modulation coefficient is different from the second integral triangular modulation coefficient.

11. The digital loop filter of claim 8, wherein the integrator is connected to the second integral trigonometric modulation arithmetic block circuit, and wherein the proportional path further includes an adder circuit connected to the first integral trigonometric modulation arithmetic block circuit and the integrator of the integral path, and configured to sum the output of the first integral trigonometric modulation arithmetic block circuit and the output of the integrator of the integral path.

12. The digital loop filter as claimed in claim 8, wherein the proportional path tracking is at a high-frequency jitter input and wherein the integral path tracking is at a low-frequency jitter input.

13. An apparatus for transmitting and receiving data, comprising: Receiver circuit; The system includes a transmission circuit configured to transmit the data to the receiving circuit via a channel. The receiving circuit includes a clock data recovery circuit comprising: a binary phase detector configured to receive the data and a clock signal, and determine whether the phase of the clock signal leads or lags the phase of the data; a digital loop filter configured to receive the output from the binary phase detector and filter input jitter; an accumulator configured to accumulate the output from the digital loop filter; an encoder configured to encode the output of the accumulator to generate a phase interpolation code; and a phase interpolator configured to generate the clock signal having an output phase based on the phase interpolation code. The digital loop filter includes: a proportional path including a first integral trigonometric modulation (SDM) arithmetic block circuit; and an integral path parallel to the proportional path and including a second integral trigonometric modulation arithmetic block circuit and an integrator. The first integral triangular modulation arithmetic block circuit uses the first integral triangular modulation coefficient as the divisor to perform a division operation on the output of the binary phase detector, and the second integral triangular modulation arithmetic block circuit uses the second integral triangular modulation coefficient as the divisor to perform a division operation on the output of the first integral triangular modulation arithmetic block circuit.

14. The apparatus of claim 13, wherein the first integral triangular modulation coefficient is different from the second integral triangular modulation coefficient.

15. The apparatus of claim 13, wherein the integrator is connected to the second integral trigonometric modulation arithmetic block circuit, and wherein the proportional path further includes an adder circuit connected to the first integral trigonometric modulation arithmetic block circuit and the integrator of the integral path, and configured to sum the output of the first integral trigonometric modulation arithmetic block circuit and the output of the integrator of the integral path.

16. The apparatus of claim 13, wherein the first gain of the proportional path is less than 1, and wherein the second gain of the integral path is less than the first gain of the proportional path.

17. The apparatus of claim 13, wherein the binary phase detector comprises: A first mutually exclusive OR gate is configured to perform a mutually exclusive OR operation on the data at the falling edge of the clock signal and the data at the first rising edge of the clock signal to generate a first output indicating whether the phase of the clock signal leads the phase of the data; and a second mutually exclusive OR gate is configured to perform a mutually exclusive OR operation on the data at the falling edge of the clock signal and the data at the second rising edge of the clock signal to generate a second output indicating whether the phase of the clock signal lags the phase of the data, wherein the first rising edge precedes the falling edge, and wherein the second rising edge follows the falling edge, wherein the phase interpolator controls the output phase in response to a change in the phase interpolation code, and wherein the phase interpolation code changes in response to a value received from the binary phase detector indicating that the phase of the clock signal leads the phase of the data is greater than a predefined value, or in response to a value received from the binary phase detector indicating that the phase of the clock signal lags the phase of the data is greater than the predefined value.

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