Image sensor and method performed by image sensor

Abstract

An image sensor includes: a pixel including a first floating diffuser and a second floating diffuser, generating a first pixel signal based on the charge amount of the first floating diffuser, and generating a second pixel signal based on the charge amount of the first floating diffuser and the charge amount of the second floating diffuser; a row line connected to the pixel and transmitting the first pixel signal or the second pixel signal; and a readout circuit connected to the row line and generating an image signal based on a plurality of comparison results, the plurality of comparison results including a first comparison result obtained by comparing the first pixel signal with the first reference signal, a second comparison result obtained by comparing the second pixel signal with the first reference signal, and a third comparison result obtained by comparing the second pixel signal with the second reference signal.

Description

Technical Field

[0001] The present invention relates to an image sensor. [Cross-reference to related applications]

[0002] This application claims priority and benefits to Korean Patent Application No. 10-2021-0164972 filed with the Korean Intellectual Property Office on November 25, 2021, and Korean Patent Application No. 10-2022-0106204 filed with the Korean Intellectual Property Office on August 24, 2022, the entire contents of which are incorporated herein by reference. Prior Technology

[0003] An image sensor is a device for capturing two-dimensional or three-dimensional images of an object. The image sensor uses a photoelectric transducer to generate an image of the object, the transducer responding to the intensity of light reflected from the object.

[0004] Recently, there has been an increasing demand for image sensors with improved performance across various fields. Complementary metal-oxide semiconductor (CMOS) image sensors are image acquisition devices manufactured using CMOS processes. Compared to charge-coupled device (CCD) image sensors, CMOS image sensors offer advantages such as lower manufacturing costs, lower power consumption, and higher integration.

[0005] However, there is a problem that images acquired by CMOS image sensors are greatly affected by the signal-to-noise ratio (SNR) of the CMOS image sensor. Specifically, the sharp decrease in SNR when synthesizing low-light and high-light images is one of the main factors that degrade image quality. Summary of the Invention

[0006] Some embodiments of the present invention can provide an image sensor with the advantage of a reduced signal-to-noise ratio.

[0007] Some embodiments of the present invention can provide an image sensor with the advantage of improved signal-to-noise ratio reduction.

[0008] According to some embodiments of the present invention, an image sensor may be provided, comprising: a pixel, including a first floating diffuser and a second floating diffuser including a lateral overflow integration capacitor (LOFIC), generating a first pixel signal based on the charge amount of the first floating diffuser and generating a second pixel signal based on the charge amount of the first floating diffuser and the charge amount of the second floating diffuser; a row line, connected to the pixel and transmitting the first pixel signal or the second pixel signal; a ramp signal generator, generating a first reference signal and a second reference signal; and a readout circuit, connected to the row line and generating an image signal based on a plurality of comparison results, the plurality of comparison results including a first comparison result obtained by comparing the first pixel signal with the first reference signal, a second comparison result obtained by comparing the second pixel signal with the first reference signal, and a third comparison result obtained by comparing the second pixel signal with the second reference signal.

[0009] In some embodiments of the present invention, the first reference signal may include a plurality of ramp signals having a first slope, the second reference signal may include a plurality of ramp signals having a second slope different from the first slope, and the plurality of comparison results may further include a fourth comparison result obtained by comparing the first pixel signal with the second reference signal.

[0010] In some embodiments of the present invention, a pixel may further include a third floating diffusion, a second pixel signal may be generated based on the charge amount of the third floating diffusion, and the pixel may further generate a third pixel signal based on the charge amount of the first floating diffusion and the charge amount of the third floating diffusion.

[0011] In some embodiments of the present invention, the first reference signal may include a plurality of ramp signals having a first slope, the second reference signal may include a plurality of ramp signals having a second slope different from the first slope, and the plurality of comparison results may further include a fourth comparison result obtained by comparing a third pixel signal with the second reference signal.

[0012] In some embodiments of the present invention, the image sensor may further include: a first comparator that receives a first pixel signal, a second pixel signal, and a first reference signal and outputs a first comparison result and a second comparison result; and a second comparator that receives a second pixel signal, a third pixel signal, and a second reference signal and outputs a third comparison result and a fourth comparison result.

[0013] In some embodiments of the present invention, the first reference signal may include a plurality of ramp signals having a first slope, the second reference signal may include a plurality of ramp signals having a second slope different from the first slope, and the plurality of comparison results may further include a fourth comparison result obtained by comparing the first pixel signal with the second reference signal.

[0014] In some embodiments of the present invention, the ramp signal generator may further generate a third reference signal with a third slope, and the multiple comparison results may further include a fifth comparison result obtained by comparing the third pixel signal with the third reference signal.

[0015] In some embodiments of the present invention, the ramp signal generator can maintain a third slope as the analog gain of the image sensor increases.

[0016] In some embodiments of the present invention, the readout circuit may include: a first comparator that receives a first pixel signal, a second pixel signal, and a first reference signal and outputs a second comparison result and a fourth comparison result; a second comparator that receives the first pixel signal, the second pixel signal, and the second reference signal and outputs a third comparison result and a fourth comparison result; and a third comparator that receives a third pixel signal and a third reference signal and outputs a fifth comparison result.

[0017] In some embodiments of the present invention, the ramp signal generator may further generate a fourth reference signal having a fourth slope different from the third slope, and the multiple comparison results further include a sixth comparison result obtained by comparing the third pixel signal with the fourth reference signal.

[0018] In some embodiments of the present invention, the ramp signal generator can maintain a fourth slope as the analog gain of the image sensor increases.

[0019] In some embodiments, the readout circuit may further include a fourth comparator that receives a third pixel signal and a fourth reference signal and outputs a sixth comparison result.

[0020] In some embodiments of the present invention, a pixel may include a first floating diffuser, a second floating diffuser, and a third floating diffuser as a first sub-pixel, and a second sub-pixel including a fourth floating diffuser having the same capacitance as the first floating diffuser, a fifth floating diffuser having the same capacitance as the second floating diffuser, and a sixth floating diffuser having the same capacitance as the third floating diffuser. A fourth pixel signal is generated based on the charge of the fourth floating diffuser, a fifth pixel signal is generated based on the charge of the fourth floating diffuser and the fifth floating diffuser, and a sixth pixel signal is generated based on the charge of the fourth floating diffuser, the fifth floating diffuser, and the sixth floating diffuser. A row line may include a first row line connected to the first sub-pixel and a row line connected to... The second row line of the second sub-pixel, and the readout circuit can generate a first comparison result by comparing the average of the first pixel signal and the fourth pixel signal with the first reference signal when comparing the first pixel signal and the first reference signal, generate a second comparison result by comparing the average of the second pixel signal and the fifth pixel signal with the first reference signal when comparing the second pixel signal and the second reference signal, generate a third comparison result by comparing the average of the second pixel signal and the fifth pixel signal with the second reference signal when comparing the second pixel signal and the second reference signal, and generate a fourth comparison result by comparing the average of the third pixel signal and the sixth pixel signal with the second reference signal when comparing the second pixel signal and the second reference signal.

[0021] According to some embodiments of the present invention, an image sensor may be provided, comprising: an optoelectronic device; a transfer transistor connected between a first node and the optoelectronic device; a first floating diffuser connected to the first node; a first switching transistor connected between the first node and a second node; a second floating diffuser connected to the second node; a second switching transistor connected between a power supply voltage line and the second node; a driving transistor that generates a pixel signal in response to a voltage at the first node and outputs the pixel signal to a row line; a readout circuit connected to the row line that compares the pixel signal with a first reference signal comprising a ramp signal having a first slope and compares the pixel signal with a second reference signal comprising a ramp signal having a second slope different from the first slope to generate an image signal; and a ramp signal generator that generates a plurality of reference signals comprising a plurality of ramp signals and transmits the plurality of reference signals to the readout circuit.

[0022] In some embodiments of the present invention, the pixel signal may include a first pixel signal generated by the driving transistor when the first switching transistor is off, and a second pixel signal generated by the driving transistor when the first switching transistor is on and the second switching transistor is off.

[0023] In some embodiments of the present invention, the image sensor may further include: a third switching transistor connected between the first node and the third node; and a third floating diffuser connected to the third node, wherein the pixel signal may further include a third pixel signal generated by a driving transistor when the first switching transistor and the third switching transistor are turned on.

[0024] In some embodiments, the image sensor may further include a third floating diffuser connected in series with the second switching transistor, wherein the pixel signal may further include a third pixel signal generated by the driving transistor when the first switching transistor and the second switching transistor are turned on.

[0025] In some embodiments of the present invention, the readout circuit can compare the first pixel signal and the third pixel signal with the first reference signal, and compare the second pixel signal and the third pixel signal with the second reference signal to generate an image signal.

[0026] In some embodiments of the present invention, the plurality of reference signals may further include a third reference signal containing a ramp signal with a third slope, generated synchronously by a ramp signal generator and a third pixel signal, and the readout circuit may compare the first pixel signal and the second pixel signal with the first reference signal, compare the first pixel signal and the second pixel signal with the second reference signal, and compare the third pixel signal with the third reference signal to generate an image signal.

[0027] In some embodiments of the present invention, the ramp signal generator can maintain the slope of the ramp signal in the third reference signal as the analog gain of the image sensor increases.

[0028] In some embodiments of the present invention, the plurality of reference signals may further include a fourth reference signal having a fourth slope, generated synchronously by a ramp signal generator and a third pixel signal, and the readout circuit may further include a fourth comparator that compares the third pixel signal with the fourth reference signal.

[0029] In some embodiments of the present invention, the ramp signal generator can maintain the slope of the ramp signal in the fourth reference signal as the analog gain of the image sensor increases.

[0030] According to some embodiments of the present invention, a method performed by an image sensor can be provided, comprising: generating a first pixel signal based on the charge amount of the first floating diffusion and generating a second pixel signal based on the charge amount of the first floating diffusion and the charge amount of the second floating diffusion in a pixel comprising a first floating diffusion and a second floating diffusion; generating a first reference signal comprising a ramp signal having a first slope and a second reference signal comprising a ramp signal having a second slope different from the first slope; and generating an image signal based on a plurality of comparison results, the plurality of comparison results including a first comparison result obtained by comparing the first pixel signal and the first reference signal, a second comparison result obtained by comparing the second pixel signal and the first reference signal, and a third comparison result obtained by comparing the second pixel signal and the second reference signal. Simple Explanation of the Diagram

[0031] Figure 1 is an example block diagram of an image sensor according to one embodiment. Figures 2A and 2B are example circuit diagrams illustrating pixels according to one embodiment. Figure 3 is an example block diagram illustrating a pixel array and readout circuit according to one embodiment. Figure 4 is an example diagram illustrating the operation timing of an image sensor according to an embodiment. Figure 5 is an example diagram illustrating the operation timing of an image sensor according to an embodiment. Figure 6 is an example block diagram illustrating a pixel array and readout circuit according to another embodiment. Figure 7 is an example diagram illustrating the operating timing of the image sensor shown in Figure 6. Figure 8 is an example graph illustrating the signal-to-noise ratio according to one embodiment. Figure 9 is an example block diagram illustrating a pixel array and readout circuit according to another embodiment. Figure 10 is an example circuit diagram illustrating a pixel according to one embodiment. Figures 11A and 11B are example circuit diagrams illustrating pixels according to another embodiment. Figure 12 is an example diagram illustrating the operation timing of an image sensor according to an embodiment. Figure 13 is an example diagram illustrating another operating timing of an image sensor according to one embodiment. Figure 14 is an example curve illustrating the signal-to-noise ratio according to an embodiment of the present invention. Figures 15 and 16 are example diagrams illustrating the operation timing of an image sensor. Figures 17 and 18 are example graphs illustrating the signal-to-noise ratio according to another embodiment of the present invention. Figure 19 is an example block diagram illustrating a pixel array and readout circuit according to another embodiment. Figures 20 and 21 are example diagrams illustrating the operating timing of the image sensor shown in Figure 19. Figures 22 and 23 are example graphs illustrating the signal-to-noise ratio according to one embodiment. Figures 24 and 25 are example graphs illustrating the signal-to-noise ratio according to one embodiment. Figure 26 is an example block diagram illustrating a pixel array and readout circuit according to another embodiment. Figures 27 and 28 are example diagrams illustrating the operating timing of the image sensor shown in Figure 26. Figure 29 is an example block diagram illustrating a pixel array and readout circuit according to another embodiment. Figure 30 is an example diagram illustrating the operating timing of the image sensor shown in Figure 29. Figure 31 is an example graph illustrating the signal-to-noise ratio according to an embodiment. Figure 32 is an example circuit diagram illustrating a pixel according to one embodiment. Figure 33 is an example block diagram of a computer device according to an embodiment. Implementation

[0032] In the following embodiments, certain embodiments of the invention are shown and described by way of illustration only. As will be appreciated by those skilled in the art, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention.

[0033] Therefore, the diagrams and descriptions are to be considered illustrative rather than restrictive in nature. Throughout this specification, the same reference numerals designate the same elements. In the flowcharts described with reference to the diagrams, the order of operations may be changed, some operations may be combined, some operations may be divided, and certain operations may not be performed.

[0034] Furthermore, unless explicitly stated as "a" or "single," expressions written in the singular can be interpreted in either the singular or plural form. Terms containing ordinal numbers such as first, second, etc., may be used to describe various components, but the components are not limited to these terms. These terms may be used for the purpose of distinguishing one component from others.

[0035] Figure 1 is an example block diagram of an image sensor according to one embodiment.

[0036] Referring to FIG1, an image sensor 100 according to an embodiment of the present invention includes a controller 110, a timing generator 120, a column driver 130, a pixel array 140, a readout circuit 150, a ramp signal generator 160, a data buffer 170, and an image signal processor 180. In some embodiments, the image signal processor 180 may be located outside the image sensor 100.

[0037] The image sensor 100 can generate an image signal by converting light received from the outside into an electrical signal. The image signal IMS can be provided to the image signal processor 180.

[0038] The image sensor 100 can be installed in an electronic device that has image sensing or light sensing capabilities. For example, the image sensor 100 can be installed in electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, home appliances, personal computers (PCs), personal digital assistants (PDAs) or portable multimedia players (PMPs), navigation systems, drones, and advanced driver assistance systems (ADAS). Alternatively, the image sensor 100 can be installed in electronic devices provided as components in vehicles, furniture, manufacturing facilities, doors, various measuring devices, and the like.

[0039] The controller 110 can control all of the components 120, 130, 150, 160, and 170 included in the image sensor 100. The controller 110 can use control signals to control the operating timing of each of the components 120, 130, 150, 160, and 170. According to one embodiment, the controller 110 can control the ramp signal generator 160 to adjust the reference signal RAMP generated by the ramp signal generator 160, and control the timing generator 120 to adjust the floating diffusion (FD) capacitance of the pixel circuitry in the pixel array 140 via the column decoder 130.

[0040] In some embodiments, the controller 110 may receive a mode signal indicating an imaging mode from an application processor and control the image sensor 100 as a whole based on the received mode signal. For example, the application processor may determine the imaging mode of the image sensor 100 based on various situations (such as the illumination of the imaging environment, the user's resolution settings, detected or trained states, and the like) and provide the determination result as a mode signal to the controller 110. The controller 110 may control a plurality of pixels in the pixel array 140 to output pixel signals according to the imaging mode. The pixel array 140 may output pixel signals for each of the plurality of pixels or for a portion of the plurality of pixels, and the readout circuit 150 may sample and process the pixel signals received from the pixel array 140. The timing generator 120 may generate signals that serve as a reference for the operating timing of the components of the image sensor 100. The timing generator 120 may control the timing of the column driver 130, the readout circuit 150, and the ramp signal generator 160. Timing generator 120 can provide control signals for controlling the timing of column driver 130, readout circuit 150 and ramp signal generator 160.

[0041] Pixel array 140 may include a plurality of pixels PX, and a plurality of column lines RL and a plurality of row lines CL respectively connected to the plurality of pixels PX. In some embodiments, each pixel PX may include at least one photoelectric device (or photosensitive device). The photoelectric device can detect incident light and convert the incident light into an electrical signal, i.e., a plurality of analog pixel signals, according to the amount of light. The level of the analog pixel signal output from the photoelectric device may be proportional to the amount of charge output from the photoelectric device. That is, the level of the analog pixel signal output from the photoelectric device may be proportional to the amount of light received in pixel array 140.

[0042] The pixel array 140 can adjust the conversion gain when generating multiple analog pixel signals. The conversion gain is the magnitude of the analog pixel signal output from the pixel array 140 per unit photocharge generated by photoelectric conversion. Here, the conversion gain can be adjusted by changing the capacitance of the floating diffusion (FD) using multiple transistors contained in one pixel of the pixel array 140.

[0043] Column lines RL can extend in a first direction and can be connected to pixels PX arranged along the first direction. For example, column lines RL can transmit control signals output from column driver 130 to devices, such as transistors, contained in the pixel PX. In addition to column lines RL, other signal lines can also be arranged in the first direction. Row lines CL can extend in a second direction intersecting the first direction and can be connected to pixels PX arranged along the second direction. Row lines CL can transmit pixel signals output from the pixel PX to readout circuit 150.

[0044] In some embodiments, a pixel PX may comprise multiple subpixel groups. Subpixel groups can be configured in the form M*N (where M and N are integers greater than or equal to 2). In the M*N form, M subpixel groups can be configured in the direction of the row line CL, and N subpixel groups can be configured in the direction of the column line RL.

[0045] For example, a pixel 1400 may contain multiple subpixel groups 1401 and 1402, each configured in a 1*2 configuration. In Figure 1, a pixel 1400 is illustrated as containing two subpixel groups 1401 and 1402, but is not limited thereto. A pixel may contain any number of subpixel groups configured in an M*N configuration.

[0046] Pixel array 140 can operate on a subpixel group basis. A subpixel group may contain multiple subpixels. Specifically, subpixel group 1401 may contain subpixels 1401_1 and 1401_2. Subpixel group 1402 may contain subpixels 1402_1 and 1402_2. Each of the multiple subpixels 1401_1, 1401_2, 1402_1, and 1402_2 may contain one or more photoelectric devices (or photosensitive devices).

[0047] Each of the multiple sub-pixel groups 1401 and 1402 can output an analog pixel signal. In this case, the voltage level of the analog pixel signal output from a sub-pixel group 1401 or 1402 can be the sum of the voltage levels output from each of the sub-pixels 1401_1, 1401_2, 1402_1, and 1402_2 within sub-pixel groups 1401 and 1402. The sub-pixels included in a sub-pixel group 1401 or 1402 can have the same color filter.

[0048] In one embodiment, the pixel array 140 may output analog signals from each of sub-pixels 1401_1, 1401_2, 1402_1, and 1402_2. For example, in a high-illuminance environment, the application processor may provide a mode signal indicating a full mode to the image sensor 100. A high-illuminance environment may be an environment with a higher light intensity than a low-illuminance environment. A full mode may refer to performing a readout operation on the voltages detected by all sub-pixels constituting the pixel array 140. Upon receiving the mode signal indicating a full mode, the image sensor 100 may control the pixel array 140 to output pixel signals generated by each of the sub-pixels in the pixel array 140, and process the output pixel signals individually. Because the number of output analog signals is large, the shape, contrast, etc., of the external environment of the image sensor 100 can be clearly displayed in the full mode.

[0049] In one embodiment, pixel array 140 may output pixel signals from sub-pixel groups 1401 and 1402, rather than outputting analog signals from each of sub-pixels 1401_1, 1401_2, 1402_1, and 1402_2. The amount of light received by a sub-pixel group may be the sum of the amounts of light received by each sub-pixel in the sub-pixel group. For example, in a low-light environment, the application processor may provide a mode signal indicating a binning mode to image sensor 100. A low-light environment may be an environment with insufficient light, such as indoors or at night. A binning mode may refer to a mode in which the sum (or average) of the output values ​​of sub-pixels contained in a set is output as an analog pixel signal. Upon receiving a mode signal indicating a binning mode, image sensor 100 controls pixel array 140 to output pixel signals generated in units of sub-pixels located adjacent to a sub-pixel group or in units of a predetermined number of pixels of the same color. Upon receiving a mode signal indicating a parallel imaging mode, the image sensor 100 can output a single sub-pixel signal 1401, which is the sum of the voltages detected by each of the multiple sub-pixels 1401_1 and 1401_2 in a sub-pixel group 1401. Furthermore, the image sensor 100 can output a single pixel signal, which is the sum of the voltages detected by each of the multiple sub-pixels 1402_1 and 1402_2 in a sub-pixel group 1402. Therefore, the pixel signal output in parallel imaging mode can contain sufficient light information even in low-light environments, and thus, can adequately display the colors of the external environment of the image sensor 100.

[0050] In the following description, it is assumed that the image sensor 100 operates in parallel mode.

[0051] Column driver 130 may generate control signals for driving pixel array 140 in response to control signals from timing generator 120, and provide the control signals to a plurality of pixels PX in pixel array 140 via a plurality of column lines RL. In some embodiments, column driver 130 may control the plurality of pixels PX to detect incident light in column line units. A column line unit may include at least one column line RL. For example, column driver 130 transmits transfer signal TG, reset signal RG, select signal SEL, gain control signal DCG, and similar signals to pixel array 140, as described later.

[0052] The readout circuit 150 can convert pixel signals (or electrical signals) from a plurality of pixels PX connected to column lines RL into pixel values ​​indicating light intensity in response to a control signal from the timing generator 120. The readout circuit 150 can also convert pixel signals output via corresponding row lines CL into pixel values. For example, the readout circuit 150 can convert pixel signals into pixel values ​​by comparing a ramp signal with a pixel signal. Pixel values ​​can be image data having multiple bits. Specifically, the readout circuit 150 may include selectors, multiple comparators, multiple counter circuits, and the like.

[0053] The ramp signal generator 160 can generate a reference signal and transmit the generated reference signal to the readout circuit 150.

[0054] The ramp signal generator 160 may include a current source, a resistor, and a capacitor. The ramp signal generator 160 can adjust the ramp voltage, which is the voltage applied to the ramp resistor, by adjusting the current value of the variable current source or the resistance value of the variable resistor, thereby generating multiple ramp signals with a slope decrease or increase determined according to the current value of the variable current source or the resistance value of the variable resistor.

[0055] Similarly, the ramp signal generator 160 can adjust the gain of the ramp voltage by adjusting the clock frequency. The "gain" of the ramp voltage can refer to the degree of signal amplification, and can also be defined as analog gain.

[0056] Here, the gain of the ramp voltage can be based on the magnitude of the absolute value of the ramp signal's slope. For example, the ramp signal can have a waveform that maintains a constant voltage, reduces the voltage to a determined slope, and returns to a constant voltage. As the absolute value of the slope of the voltage-reducing portion of the ramp signal increases, the number of signals that can be detected simultaneously can decrease. Therefore, the steeper the slope of the voltage-reducing portion of the ramp signal, the smaller the analog gain. Conversely, the gentler the slope of the voltage-reducing portion of the ramp signal, the larger the analog gain.

[0057] The data buffer 170 can store pixel values ​​transferred from the readout circuit 150 to a plurality of pixels PX connected to the selected row line CL, and outputs the stored pixel values ​​in response to an enable signal from the controller 110.

[0058] The image signal processor 180 can perform image signal processing on the image signals received from the data buffer 170. For example, the image signal processor 180 can receive multiple image signals from the data buffer 170 and synthesize the received image signals to generate an image.

[0059] Figure 2A is an example circuit diagram illustrating pixels according to one embodiment.

[0060] According to one embodiment, a pixel PX1 may include a pixel circuit PC1 that processes the charge generated by photoelectric devices PD11, PD12, PD13, and PD14 in response to light to output an electrical signal. In FIG. 2A, a pixel PX1 is illustrated as comprising four photoelectric devices PD11, PD12, PD13, and PD14, but the present invention is not limited thereto, and a pixel PX1 may contain fewer or more photoelectric devices. Photoelectric devices PD11, PD12, PD13, and PD14 can detect external light to generate charge.

[0061] The cathodes of photoelectric devices PD11, PD12, PD13 and PD14 can be connected to the floating node FN11 via transfer transistors TX11, TX12, TX13 and TX14, and the anodes of photoelectric devices PD11, PD12, PD13 and PD14 can be grounded.

[0062] Pixel circuit PC1 may include multiple transistors, such as transfer transistors TX11, TX12, TX13, and TX14, drive transistor DX1, select transistor SX1, reset transistor RX1, and switch transistor SW1. The transistors TX11, TX12, TX13, TX14, SX1, RX1, and SW1 in pixel circuit PC1 can operate in response to control signals provided by the auto-driver 130, such as transfer control signals TG11, TG12, TG13, and TG14, select signal SEL1, reset control signal RG1, and first gain control signal DCG1.

[0063] In some embodiments, the pixel circuit PC1 may include a plurality of floating diffusers FD11 and FD12. Each of the plurality of floating diffusers FD11 and FD12 may have a predetermined capacitance and may store the charge generated by the optoelectronic devices PD11 and PD12. Although two floating diffusers FD11 and FD12 are shown in FIG2A, the pixel circuit PC1 may have three or more floating diffusers.

[0064] The transfer transistor TX11 can be connected between the photoelectric device PD11 and the floating node FN11, and can be controlled by the transfer signal TG11. When the transfer transistor TX11 is turned on, the charge generated by the photoelectric device PD11 can be transferred to the floating diffuser FD11.

[0065] The transfer transistor TX12 can be connected between the photoelectric device PD12 and the floating node FN11, and can be controlled by the transfer signal TG12. When the transfer transistor TX12 is turned on, the charge generated by the photoelectric device PD12 can be transferred to the floating diffuser FD11. The transfer transistors TX11 and TX12 are connected in parallel.

[0066] The transfer transistor TX13 can be connected between the photoelectric device PD13 and the floating node FN11, and can be controlled by the transfer signal TG13. When the transfer transistor TX13 is turned on, the charge generated by the photoelectric device PD13 can be transferred to the floating diffuser FD11.

[0067] The transfer transistor TX14 can be connected between the photoelectric device PD14 and the floating node FN11, and can be controlled by the transfer signal TG14. When the transfer transistor TX14 is turned on, the charge generated by the photoelectric device PD14 can be transferred to the floating diffuser FD11.

[0068] The voltage of the floating node FN11 can be determined based on the charge accumulated in the floating diffuser FD11. The conversion gain is inversely proportional to the capacitance of the floating diffuser FD11, which is the ratio of charge to voltage. For example, the conversion gain decreases as the capacitance of the floating diffuser FD11 increases, and increases as the capacitance decreases.

[0069] The gate of the driver transistor DX1 is connected to the floating node FN11. The driver transistor DX1 can operate as a source follower amplifier for the voltage of the floating node FN11. The driver transistor DX1 can output the pixel signal VS to the row line CL via the select transistor SX1 in response to the voltage of the floating node FN11.

[0070] The select transistor SX1 can be connected between the drive transistor DX1 and the row line CL, and can be controlled by the select signal SEL1. When the select transistor SX1 is turned on, the pixel voltage VS output from the drive transistor DX1 can be output to the readout circuit (150 in Figure 1) via the row line CL connected to the select transistor SX1.

[0071] The reset transistor RX1 can be connected between the power supply voltage line (VDD) and the floating node FN12, and can be controlled by the reset control signal RG1. When the reset transistor RX1 is turned on by the reset signal RG1, the power supply voltage VDD can be applied to the floating node FN12 to reset the floating node FN12. When the switching transistor SW1 is turned on and the reset transistor RX1 is turned on, both the floating nodes FN11 and FN12 can be reset to the power supply voltage VDD.

[0072] The switching transistor SW1 can be connected between floating node FN11 and floating node FN12, and can be controlled by the first gain control signal DCG1.

[0073] When the switching transistor SW1 is off, the floating node FN11 has a capacitance that allows the floating diffuser FD11 to move. In this case, because the amount of capacitance connected to the floating node FN11 is reduced, the image sensor 100 can generate an image signal in a high conversion gain (HCG) mode. When operating in HCG mode, the gain of the circuitry (e.g., readout circuitry 150) used to process the pixel signal VS can be relatively smaller than the gain of the readout circuitry 150 when operating in low conversion gain (LCG) mode. Therefore, the SNR of the image sensor 100 can be increased to reduce the minimum detectable light intensity and improve the low light intensity detection performance of the image sensor 100.

[0074] When the switching transistor SW1 is turned on, the floating diffuser FD12 can be connected to the floating node FN11. Since the floating diffusers FD11 and FD12 are connected in parallel to the floating node FN11, the capacitance of the floating node FN11 is increased by the capacitance of the floating diffuser FD12 before the switching transistor SW1 is turned on. In this case, because the capacitance connected to the floating node FN11 is greater than before the switching transistor SW1 is turned on, the image sensor 100 can operate in LCG mode, in which a larger amount of charge can be processed in the pixel to generate an image signal compared to HCG mode. Therefore, the high light intensity detection performance of the image sensor 100 can be improved.

[0075] In some embodiments, the floating diffuser FD12 may include a lateral overflow integration capacitor (LOFIC). When the floating diffuser FD12 includes a LOFIC, the overflow charge from the charge transferred from photoelectric devices PD11 and PD12 to the floating node FD11 can be shared by the floating diffuser FD12. In this case, since the amount of capacitance connected to the floating node FN11 increases, the image sensor 100 can generate an image signal in the LOFIC conversion gain mode. Similarly, even in the LOFIC conversion gain mode, the full well capacity (FWC) can be increased. Therefore, the high light intensity detection performance of the image sensor 100 can be improved. That is, the large amount of charge overflowing from photoelectric devices PD11 and PD12 can be integrated instead of being wasted by the floating diffuser FD12, so the image sensor 100 can generate an image signal detected under relatively high light intensity.

[0076] In general, pixel PX1 can operate in LCG mode when the switching transistor SW1 is on, and in HCG mode when the switching transistor SW1 is off. Alternatively, pixel PX1 can operate in LOFIC mode when the switching transistor SW1 is on, and in HCG mode when the switching transistor SW1 is off. On the other hand, since the floating diffusion FD12 containing LOFIC is generally used to store a large amount of signal in a floating diffusion, the floating diffusion FD12 can be mainly used for parallel imaging modes that should store the charge generated by multiple sub-pixels, rather than complete modes that should store the charge generated by a single sub-pixel.

[0077] In some embodiments, since the pixel array 140 operates in two modes (HCG mode and LCG mode; or HCG mode and LOFIC mode) during a frame time period, the image signal processor 180 can generate a composite image signal with high dynamic range by synthesizing the image signal according to each mode.

[0078] However, when the image signal processor 180 combines image signals generated under different conditions, a decrease in signal-to-noise ratio (SNR) may occur. SNR decrease refers to the phenomenon where the SNR rapidly decreases at the boundaries between image signals when the image signal processor 180 combines image signals generated in two modes where pixels operate with different capacitances.

[0079] For example, when pixel array 140 operates in both HCG and LCG modes within a frame time period, a decrease in SNR may occur at the boundary between the HCG and LCG mode image signals when synthesizing them. Alternatively, when pixel array 140 operates in both HCG and LCG modes within a frame time period, a decrease in SNR may occur at the boundary between the HCG and LCG mode image signals when synthesizing them. In both LCG and LCG modes, a first floating diffuser FD11 and a second floating diffuser FD12 connected in parallel are used, and in HCG mode, only the first floating diffuser FD11 is used. Therefore, since the capacitance difference between the first floating diffuser FD11 and the second floating diffuser FD12 can be increased, the magnitude of the SNR decrease in a synthesized image signal can be further increased. A decrease in SNR can be clearly seen in areas of illumination variation within a synthetic image signal and can degrade image quality.

[0080] Figure 2B is an example circuit diagram illustrating pixels according to another embodiment.

[0081] The optoelectronic devices PD21, PD22, PD23, and PD24, transfer transistors TX21, TX22, TX23, and TX24, drive transistor DX2, select transistor SX2, and reset transistor RX2 of pixel PX2 shown in Figure 2B can have the same configuration as the optoelectronic devices PD11, PD12, PD13, and PD14, transfer transistors TX11, TX12, TX13, and TX14, drive transistor DX1, select transistor SX1, and reset transistor RX1 of pixel PX1 shown in Figure 2A.

[0082] In some embodiments, in addition to the multiple transistors listed above, the pixel circuit PC2 may also include multiple floating diffusers FD21 and FD22. The floating diffusers FD21 and FD22 may have predetermined capacitances and store charges generated by the photoelectric devices PD21, PD22, PD23, and PD24. Although two floating diffusers FD21 and FD22 are shown in Figure 2B, the pixel circuit PC2 may have three or more floating diffusers.

[0083] The switching transistor SW2 can be connected between floating node FN21 and floating node FN22, and can be controlled by the first gain control signal DCG1.

[0084] When the switching transistor SW2 is off, the floating node FN21 has a capacitance that is a floating diffuser FD21. In this case, since the amount of capacitance connected to the floating node FN21 decreases, the image sensor 100 can generate an image signal in HCG mode.

[0085] When the switching transistor SW2 is turned on, the floating diffuser FD22 is connected to the floating node FN21, and the capacitance of the floating node FN21 is increased by the capacitance of the floating diffuser FD22. In this case, depending on the capacitance of the floating diffuser FD22, the image sensor 100 can generate an image signal in LCG mode or in LOFIC conversion gain mode.

[0086] In general, pixel PX2 can operate in LCG mode when transistor SW2 is on, and in HCG mode when transistor SW2 is off. Alternatively, pixel PX2 can operate in LOFIC mode when transistor SW2 is on, and in HCG mode when transistor SW2 is off.

[0087] The connection relationships between the multiple floating diffusers included in the pixel PX of the present invention are not limited to the specific pixel circuit structures shown in Figures 2A and 2B, and the pixel circuits can have arbitrary connection relationships and may have structures including connected floating diffusers. In the following description, for ease of explanation, it is assumed that the pixel PX of the present invention has the structure shown in Figure 2A.

[0088] Figure 3 is an example block diagram illustrating the pixel array and readout circuit according to an embodiment.

[0089] Referring to Figure 3, the pixel array 140 may include multiple pixels PXa, PXb, and PXc. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding transfer signal from transfer signals TTi, TTi+1, and TTi+2, and a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2 to output a pixel signal VS. Here, it is assumed that each of the multiple pixels PXa, PXb, and PXc includes a sub-pixel.

[0090] The readout circuit 150 may include a selector 151, a comparator 153, a counter 155, and a CDS circuit 157 connected to each row line CL of the pixel array 140.

[0091] Selector 151 may be implemented as, for example, a demultiplexer, but is not limited thereto. Selector 151 may be connected to a corresponding row line CL and may receive a pixel signal VS from the connected row line CL. Selector 151 may receive a DEMUX selection signal SEL_M from controller 110 and output the pixel signal VS to comparator 153 based on the DEMUX selection signal SEL_M. In one embodiment, selector 151 may include two output terminals. Selector 151 may output the pixel signal VS to either of the two output terminals based on the DEMUX selection signal SEL_M.

[0092] Comparator 153 compares the pixel signal VS with the reference signal RAMP and outputs the result to counter 155. In one embodiment, comparator 153 may include a first comparator 153_1 and a second comparator 153_2. Each of the first comparator 153_1 and the second comparator 153_2 may have two input terminals and one output terminal. One of the two input terminals of the first comparator 153_1 may be connected to one of the two output terminals of the selector 151, and the other of the two input terminals may be connected to the ramp signal generator 160. The output terminal of the first comparator 153_1 may be connected to counter 155_1. One of the two input terminals of the second comparator 153_2 may be connected to the other of the two output terminals of the selector 151, and the other of the two input terminals may be connected to the ramp signal generator 160. The output terminal of the second comparator 153_2 may be connected to counter 155_2.

[0093] Ramp signal generator 160 can generate a reference signal RAMP in response to a ramp enable signal R_EN input from controller 110. In some embodiments, the reference signal RAMP may include a ramp signal whose voltage level increases or decreases over time. In some embodiments, when the ramp signal included in the reference signal RAMP is a signal with a waveform that decreases at a predetermined slope, the timing may occur where the magnitude of the signal input to comparator 153_1 via selector 151 is the same as the magnitude of the ramp signal of the reference signal RAMP. Furthermore, the timing may occur where the magnitude of the signal input to comparator 153_2 via selector 151 is the same as the magnitude of the ramp signal of the reference signal RAMP. Since the magnitudes of the signals input to comparators 153_1 and 153_2 and the magnitude of the ramp signal of the reference signal RAMP are synchronized in the same timing, the level of the signal output from comparators 153_1 and 153_2 can be shifted.

[0094] Counter 155 counts the duration for which a specific level of the signal output from comparator 153 is maintained. Specifically, counter 155 may receive a clock signal from timing generator 120. Counter 155 may use the rising or falling edge of the clock signal to count the duration for which a specific level of the signal received from comparator 153 is maintained. In one embodiment, counter 155 may include a first comparator 155_1 and a second comparator 155_2. Counter 155_1 may be connected to the output terminal of comparator 153_1. Similarly, counter 155_2 may be connected to the output terminal of comparator 153_2. Counter 155_1 counts the time corresponding to the high level of logic level "1" output from comparator 153_1. Counter 155_2 counts the time corresponding to the high level of logic level "1" output from comparator 153_2. Counters 155_1 and 155_2 may include up / down counters or bit-by-bit counters.

[0095] CDS circuit 157 can generate an image signal by performing a correlated double sampling (CDS) method on the counting signal received from counter 155. The CDS method measures a desired value by removing unwanted offsets based on two inputs (i.e., the output under known conditions and the output under unknown conditions). In an image sensor, CDS can be performed based on the difference between the reset voltage and the signal voltage. In one embodiment, CDS circuit 157 may include CDS circuit 157_1 and CDS circuit 157_2. CDS circuit 157_1 can be connected to the output terminal of counter 155_1 to perform the CDS method on the counting signal received from counter 155_1. Furthermore, CDS circuit 157_2 can be connected to the output terminal of counter 155_2 to perform the CDS method on the counting signal received from counter 155_2.

[0096] Figure 4 is an example diagram illustrating the operation timing of an image sensor according to an embodiment.

[0097] Figure 4 illustrates a scan period used to drive multiple pixels in column-line units. A scan period may sequentially include a Reset period, an Exposure period, and a Readout period.

[0098] Figure 4 is a diagram illustrating the operation of the floating diffusion FD12 of the image sensor 100 in the RST-RST-SIG-SIG (RRSS) readout method when the floating diffusion FD12 does not contain LOFIC.

[0099] The operation of the image sensor will be described with reference to Figures 2A, 3 and 4.

[0100] During the Reset period, the charges stored in the first floating diffuser FD11 and the second floating diffuser FD12 are reset.

[0101] In detail, the high-level first gain control signal DCG1 is applied to the gate of the first switching transistor SW1 to turn on the first switching transistor SW1. Floating diffusers FD11 and FD12 are connected to the floating node FN11.

[0102] The transfer signals TG11, TG12, TG13, and TG14 applied to transfer transistors TX11, TX12, TX13, and TX14 can all have the same waveform, which is represented as transfer signal TG in Figures 4 and 5. The high-level transfer signal TG is applied to the gates of transfer transistors TX11, TX12, TX13, and TX14 to turn them on. The charge generated by photoelectric devices PD11, PD12, PD13, and PD14 can be provided to floating diffusers FD11 and FD12. However, the high-level reset signal RG1 is applied to the gate of reset transistor RX1 to turn it on. Next, the power supply voltage VDD is supplied to the floating node FN11, thus resetting floating diffusers FD11 and FD12. In this embodiment, the reset voltage can be, for example, the power supply voltage VDD. In this case, the low-level selection signal SEL1 is applied to the selection transistor SX1, thus turning off the selection transistor SX1.

[0103] The exposure period is the time during which photoelectric devices PD11, PD12, PD13, and PD14 are exposed to light to generate charge. During the exposure period, the transfer signal TG shifts from a high level to a low level, and transfer transistors TX11, TX12, TX13, and TX14 are disconnected. Similarly, the reset control signal RG1 shifts to a low level and then becomes high again to supply the power supply voltage VDD to the floating node FN12.

[0104] The readout period is the time during which the pixel signal VS generated in pixel PX1 is transferred to the readout circuit 150. Each of the LCG reset signal RST_L, HCG reset signal RST_H, HCG signal SIG_H, and LCG signal SIG_L can be output as the pixel signal VS.

[0105] The conversion gain can be adjusted depending on whether the switching transistor SW1 is driven according to the first gain control signal DCG1. For example, when the switching transistor SW1 is off, the pixel PX can operate in HCG mode, which generates the pixel signal VS based on the charge stored in the floating diffusion FD11, and when the switching transistor SW1 is on, the pixel PX can operate in LCG mode, which generates the pixel signal VS based on the charge stored in the floating diffusion FD11 and the floating diffusion FD12.

[0106] First, a high-level selection signal SEL1 is applied to the gate of the selection transistor SX1 to turn it on. Next, the first gain control signal DCG1 is shifted to a high level, thus connecting floating diffusers FD11 and FD12 to the floating node FN11. Therefore, during time period 401, the voltage of the floating node FN11, based on the charge stored in floating diffusers FD11 and FD12, can be output as the pixel signal VS (i.e., the LCG reset signal RST_L) via the driving transistor DX1 to the row line CL.

[0107] Next, when the first gain control signal DCG1 is shifted to the low bit, the switching transistor SW1 is turned off. During time period 402, the voltage of the floating node FN11, based on the charge stored in the floating diffuser FD11, can be output to the row line CL via the driving transistor DX1 as the pixel signal VS (i.e., the HCG reset signal RST_H).

[0108] Subsequently, the high-level transfer signal TG can be applied to the gates of transfer transistors TX11, TX12, TX13, and TX14, so that the charge generated by photoelectric devices PD11, PD12, PD13, and PD14 can be supplied to the floating diffuser FD11. Therefore, the amount of charge stored in the floating diffuser FD11 can be changed. During time period 403, the voltage of the floating node FN11 based on the charge stored in the floating diffuser FD11 can be output as the pixel signal VS (i.e., the HCG signal SIG_H) via the driving transistor DX1 to the row line CL.

[0109] Furthermore, a high-level first gain control signal DCG1 is applied to the switching transistor SW1, causing floating diffusers FD11 and FD12 to connect to the floating node FN11. Additionally, a high-level transfer signal TG can be applied to the gates of transfer transistors TX11, TX12, TX13, and TX14, allowing the charge generated by photoelectric devices PD11, PD12, PD13, and PD14 to be supplied to floating diffusers FD11 and FD12, and altering the charge stored in floating diffusers FD11 and FD12. Therefore, during time period 404, the voltage of the floating node FN11, based on the charge stored in floating diffusers FD11 and FD12, can be output as a pixel signal VS (i.e., LCG signal SIG_L) via the driving transistor DX1 to the row line CL.

[0110] During time period 401, the DEMUX selection signal SEL_M can be at a low level, and therefore, the LCG reset signal RST_L can be output to the first comparator 153_1. During time period 402, the DEMUX selection signal SEL_M can be at a high level, and therefore, the HCG reset signal RST_H can be output to the second comparator 153_2. During time period 403, the DEMUX selection signal SEL_M can be at a high level, and therefore, the HCG signal SIG_H can be output to the second comparator 153_2. During time period 404, the DEMUX selection signal SEL_M can be at a low level, and therefore, the LCG signal SIG_L can be output to the first comparator 153_1. However, selector 151 can output the input pixel signal VS to the second comparator 153_2 when the DEMUX selection signal SEL_M is in the low bit position, and can output the input pixel signal VS to the first comparator 153_1 when the DEMUX selection signal SEL_M is in the high bit position.

[0111] Meanwhile, the reference signal RAMP shown in Figure 4 is a signal provided to the comparator 153 in the readout circuit 150 during the readout period.

[0112] The waveform of the reference signal RAMP shown in Figure 4 can be determined based on the type of pixel signal VS generated during the time period shown in Figure 4.

[0113] A first ramp signal R41 having a first period and a fourth ramp signal R44 having a second period greater than the first period can be provided to the first comparator 153_1 synchronously with a comparison target signal (e.g., pixel signal VS). Specifically, the first ramp signal R41 can be provided to the first comparator 153_1 during time period 401, and the fourth ramp signal R44 can be provided to the first comparator 153_1 during time period 404.

[0114] Furthermore, a second ramp signal R42 having a first period and a third ramp signal R43 having a second period can be provided to the second comparator 153_2 synchronously with a comparison target signal (e.g., pixel signal VS). Specifically, the second ramp signal R42 can be provided to the second comparator 153_2 during time period 402, and the third ramp signal R43 can be provided to the second comparator 153_2 during time period 403. In the following, in this specification, the period of the ramp signal means the time period during which the ramp signal decreases at a predetermined slope. Ordinal numbers such as "first," "second," and "third" can be simply used as markers for certain elements, steps, etc., to distinguish such elements, steps, etc. from one another. Terms described in this specification that are not used as "first," "second," etc., may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in this specification or another claim).

[0115] Comparator 153 compares the pixel signal VS output from pixel PX1 with a reference signal. Specifically, the first comparator 153_1 outputs the result of comparing the LCG reset signal RST_L input via selector 151 with a first ramp signal R41 having a first period. Furthermore, the first comparator 153_1 outputs the result of comparing the LCG signal SIG_L input via selector 151 with a fourth ramp signal R44 having a second period greater than the first period. The second comparator 153_2 outputs the result of comparing the HCG reset signal RST_H input via selector 151 with a second ramp signal R42 having a first period. Furthermore, the second comparator 153_2 outputs the result of comparing the HCG signal SIG_H input via selector 151 with a third ramp signal R43 having a second period. However, the embodiment is not limited to this, and the ramp signal generator 160 can also generate a reference signal having another waveform including the first ramp signal R41 to the fourth ramp signal R44.

[0116] Since the changes in the LCG reset signal RST_L and the HCG reset signal RST_H are relatively small, while the changes in the HCG signal SIG_H and the LCG signal SIG_L are relatively large, the first cycle can be shorter than the second cycle.

[0117] Generally, since the analog gain is adjusted to be the same in all modes, the first ramp signal R41 to the fourth ramp signal R44 can all have the same slope. When adjusting the analog gain, the slopes of the first ramp signal R41 to the fourth ramp signal R44 can be changed.

[0118] Meanwhile, as described above, CDS circuit 157_1 can generate an image signal IMS by performing a correlated double sampling (CDS) method on the count signal of the pixel signal VS received by self-counter 155_1, and CDS circuit 157_2 can generate an image signal IMS by performing a correlated double sampling (CDS) method on the count signal of the pixel signal VS received by self-counter 155_2. For example, CDS circuit 157_1 can generate an image signal by performing a CDS method on the LCG reset signal RST_L and the LCG signal SIG_L. In addition, CDS circuit 157_2 can generate an image signal by performing a CDS method on the HCG reset signal RST_H and the HCG signal SIG_H. Since the pixel signal VS readout method is RRSS, the LCG reset signal RST_L, the LCG signal SIG_L, the HCG reset signal RST_H, and the HCG signal SIG_H should be input to individual comparators to remove reset noise (kTC noise).

[0119] Figure 5 is an example diagram illustrating the operation timing of an image sensor according to an embodiment.

[0120] Figure 5 illustrates a scan period used to drive multiple pixels in column-line units. A scan period may sequentially include a Reset period, an Exposure period, and a Readout period.

[0121] Figure 5 is a diagram illustrating the operation of the floating diffusion FD12 of the image sensor 100 in the RST-SIG-SIG-RST (RRSS) readout method when the floating diffusion FD12 of the image sensor 100 includes LOFIC.

[0122] The operation of the image sensor will be described with reference to Figures 2A, 3 and 5.

[0123] The operation for resetting the time period in Figure 5 is the same as the operation for resetting the time period in Figure 4.

[0124] The exposure period is the time during which photoelectric devices PD11, PD12, PD13, and PD14 are exposed to light to generate charge. During the exposure period, the reset control signal RG1 and the transfer signal TG are shifted to a low level, thus disconnecting the reset transistor RX1 and the transfer transistors TX11, TX12, TX13, and TX14. Furthermore, the first gain control signal DCG1 is shifted to a low level followed by a high level, thus connecting the floating diffusers FD11 and FD12 to the floating node FN11.

[0125] The readout period is the time during which the pixel signal VS generated in pixel PX1 is transferred to the readout circuit 150. Each of the HCG reset signal RST_H, HCG reset signal SIG_H, LOFIC signal SIG_LOFIC, and LOFIC reset signal RST_LOFIC can be output as the pixel signal VS.

[0126] The conversion gain can be adjusted depending on whether the switching transistor SW1 is driven according to the first gain control signal DCG1. For example, when the switching transistor SW1 is off, pixel PX1 can operate in HCG mode, which generates pixel signal VS based on the charge stored in the floating diffuser FD11, and when the switching transistor SW1 is on, pixel PX can operate in LOFIC mode, which generates pixel signal VS based on the charge stored in the floating diffuser FD12 containing LOFIC.

[0127] First, the high-level selection signal SEL1 is applied to the gate of the selection transistor SX1 to turn on the selection transistor SX1. Additionally, the first gain control signal DCG1 is shifted to a low level. Therefore, during time period 501, the voltage of the floating node FN11, based on the charge stored in the floating diffuser FD11, can be output as the pixel signal VS (i.e., the HCG reset signal RST_H) via the driving transistor DX1 to the row line CL.

[0128] Subsequently, the high-level transfer signal TG can be applied to the gates of transfer transistors TX11, TX12, TX13, and TX14, so that the charge generated by photoelectric devices PD11, PD12, PD13, and PD14 can be supplied to the floating diffuser FD11. Therefore, the amount of charge stored in the floating diffuser FD11 can be changed. During time period 502, the voltage of the floating node FN11 based on the charge stored in the floating diffuser FD11 can be output as the pixel signal VS (i.e., the HCG signal SIG_H) via the driving transistor DX1 to the row line CL.

[0129] Next, the high-level first gain control signal DCG1 is applied to the switching transistor SW1, causing floating diffusers FD11 and FD12 to connect to the floating node FN11. Furthermore, the high-level transfer signal TG can be applied to the gates of transfer transistors TX11, TX12, TX13, and TX14, allowing the charge generated by photoelectric devices PD11, PD12, PD13, and PD14 to be supplied to floating diffusers FD11 and FD12. During time period 503, the voltage of the floating node FN11, based on the charge stored in floating diffusers FD11 and FD12, can be output as a pixel signal (i.e., the LOFIC signal SIG_LOFIC) via the driving transistor DX1 to the row line CL.

[0130] Next, the high-level reset signal RG1 is applied to the reset transistor RX1, causing the floating diffusers FD11 and FD12 to be reset by the power supply voltage VDD. Therefore, during time period 504, the voltage of the floating node FN11, based on the charge stored in the reset floating diffusers FD11 and FD12, can be output to the row line CL via the driving transistor DX1 as the pixel signal VS (i.e., the LOFIC reset signal RST_LOFIC).

[0131] During time periods 501, 502, 503 and 504, the DEMUX selection signal SEL_M is at a low level, and therefore, the HCG reset signal RST_H, the HCG signal SIG_H, the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC can all be output to the first comparator 153_1.

[0132] The reference signal RAMP shown in Figure 5 is the signal provided to comparator 153 in readout circuit 150 during the readout period. The waveform of the reference signal RAMP shown in Figure 5 can be determined based on the type of pixel signal VS generated during the period shown in Figure 5. For example, in the case of RSSR readout method, pixel PX may sequentially output HCG reset signal RST_H, HCG signal SIG_H, LOFIC signal SIG_LOFIC, and LOFIC reset signal RST_LOFIC.

[0133] Meanwhile, as described above, the CDS circuit 157 can generate the image signal IMS by performing a correlated double sampling (CDS) method on the count signal of the pixel signal VS received from the corresponding counter 155. However, when the floating diffuser FD12 includes LOFIC, the overflow charge in the charge transferred to the floating node FN12 is stored in the floating diffuser FD12. Therefore, the LOFIC signal SIG_LOFIC is not output after the LOFIC reset signal RST_LOFIC, but the LOFIC reset signal RST_LOFIC can be output as the pixel signal VS after the LOFIC signal SIG_LOFIC. Therefore, even using a single comparator, it is possible to read out all pixel signals VS.

[0134] Considering this situation, a first ramp signal R51 with a first period, a second ramp signal R52 with a second period greater than the first period, a third ramp signal R53 with a second period, and a fourth ramp signal R54 with a first period can be provided to the first comparator 153_1 or the second comparator 153_2 synchronously with the comparison target signal (e.g., pixel signal VS). In the following, it is assumed that the pixel signal VS is provided to the first comparator 153_1. Specifically, the first ramp signal R51 can be provided to the first comparator 153_1 during time period 501, and the second ramp signal R52 can be provided to the first comparator 153_1 during time period 502. Furthermore, the third ramp signal R53 can be provided to the first comparator 153_1 during time period 503, and the fourth ramp signal R54 can be provided to the first comparator 153_1 during time period 504.

[0135] The first comparator 153_1 can output the result of comparing the HCG reset signal RST_H input via selector 151 with the first ramp signal R51 having a first period, and also output the result of comparing the HCG signal SIG_H input via selector 151 with the second ramp signal R52 having a second period greater than the first period. Next, the first comparator 153_1 can output the result of comparing the LOFIC signal SIG_LOFIC input via selector 151 with the third ramp signal R53 having a second period, and also output the result of comparing the LOFIC reset signal RST_LOFIC input via selector 151 with the fourth ramp signal R54 having a first period.

[0136] Since the changes in the HCG reset signal RST_H and the LOFIC reset signal RST_LOFIC are relatively small, while the changes in the HCG signal SIG_H and the LOFIC signal SIG_LOFIC are relatively large, the first cycle can be shorter than the second cycle.

[0137] Generally, since the analog gain is adjusted to be the same in all modes, the first ramp signal R51 to the fourth ramp signal R54 can all have the same slope. When adjusting the analog gain, the slopes of the first ramp signal R51 to the fourth ramp signal R54 can be changed.

[0138] Figure 6 is an example block diagram illustrating a pixel array and readout circuit according to another embodiment.

[0139] Referring to Figure 6, the pixel array 640 may include multiple pixels PXa, PXb, and PXc. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding transfer signal from transfer signals TGi, TGi+1, and TGi+2, and a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2 to output a pixel signal VS. Here, it is assumed that each of the multiple pixels PXa, PXb, and PXc includes a sub-pixel.

[0140] Referring to FIG6, an image sensor 600 according to another embodiment may include a pixel array 640 and a readout circuit 650.

[0141] The readout circuit 650 may include a selector 651, a comparator 653, a counter 655, and a CDS circuit 657 connected to each row line CL of the pixel array 640. The selector 651 may be implemented as, for example, a demultiplexer, but is not limited thereto.

[0142] Selector 651 can receive pixel signal VS from the corresponding row line CL. Selector 651 can receive DEMUX selection signal SEL_M from controller 610, and output pixel signal VS to comparator 653 based on DEMUX selection signal SEL_M.

[0143] Comparator 653 includes a first comparator 653_1 and a second comparator 653_2. One of the two input terminals of each of the first comparator 653_1 and the second comparator 653_2 can be connected to the output terminal of selector 651, and the other of the two input terminals can be connected to ramp signal generator 660. The first comparator 653_1 compares the pixel signal VS with a first reference signal RAMP1 (which is input synchronously with the timing of the pixel signal VS input to the first comparator 653_1), and outputs the result to counter 655_1. The second comparator 653_2 compares the pixel signal VS with a second reference signal RAMP2 (which is input synchronously with the timing of the pixel signal VS input to the second comparator 653_2), and outputs the result to counter 655_2.

[0144] Ramp signal generator 660 can generate reference signals RAMP1 and RAMP2 in response to a ramp enable signal R_EN input from controller 610. Each of reference signals RAMP1 and RAMP2 may contain multiple ramp signals. The multiple ramp signals may be signals in which voltage levels increase or decrease over time. In some embodiments, when the ramp signal included in reference signal RAMP1 is a signal with a waveform that decreases at a predetermined slope, a timing sequence may occur where the magnitude of the signal input to comparator 653_1 via selector 651 is the same as the magnitude of the ramp signal of reference signal RAMP1. Furthermore, when the ramp signal included in reference signal RAMP2 has a waveform that decreases at a predetermined slope, a timing sequence may occur where the magnitude of the signal input to comparator 653_1 via selector 653 is the same as the magnitude of the ramp signal of reference signal RAMP2. The levels of the signals output from comparators 653_1 and 653_2 can be synchronously shifted with the same timing as the values ​​of the signals input to comparator 653_1 and the reference signal RAMP1, and with the same timing as the values ​​of the signals input to comparator 653_2 and the reference signal RAMP2.

[0145] Counter 655 includes a first counter 655_1 and a second counter 655_2. Counter 655_1 can be connected to the output terminal of comparator 653_1, and counter 655_2 can be connected to the output terminal of comparator 653_2. Each of counters 655_1 and counter 655_2 may be an up / down counter or a bit-by-bit counter.

[0146] For example, counter 655 can receive a clock from a timing generator (120 in Figure 1). Counter 655 can use the rising or falling edge of the clock signal to count how long a specific level of the signal output from comparator 153 has been maintained. For example, counter 655_1 can count the time corresponding to the high level of logic level "1" output from comparator 653_1.

[0147] CDS circuit 657 includes a first CDS circuit 657_1 and a second CDS circuit 657_2. CDS circuit 657_1 can be connected to the output terminal of counter 655_1 and can perform a correlated double sampling (CDS) method on the output of the pixel signal VS received from counter 655_1 to generate an image signal IMS. CDS circuit 657_2 can be connected to the output terminal of counter 655_2 and can perform a correlated double sampling (CDS) method on the output of the pixel signal VS received from counter 655_2 to generate an image signal IMS.

[0148] Figure 7 is an example diagram illustrating the operating timing of the image sensor shown in Figure 6.

[0149] Figure 7 illustrates a scan period used to drive multiple pixels in column-line units. A scan period may sequentially include a Reset period, an Exposure period, and a Readout period.

[0150] Figure 7 illustrates the operation of the image sensor 600 in the RST-SIG-SIG-RST (RSSR) readout method. First, the waveforms of the selection signal SEL1, DEMUX selection signal SEL_M, DEMUX selection signal SEL_M, reset signal RG1, first gain control signal DCG1, and transfer signal TG during the Reset, Exposure, and Readout periods are similar to those in Figure 5. Therefore, the description in Figure 5 can be applied to Figure 7.

[0151] Similar to Figure 5, pixel PX can sequentially output the HCG reset signal RST_H, the HCG signal SIG_H, the LOFIC signal SIG_LOFIC, and the LOFIC reset signal RST_LOFIC. During time period 701, the HCG reset signal RST_H can be output to the row line CL. During time period 702, the HCG reset signal SIG_H can be output to the row line CL. During time period 703, the LOFIC signal SIG_LOFIC can be output to the row line CL. During time period 704, the LOFIC reset signal RST_LOFIC can be output to the row line CL.

[0152] Meanwhile, the reference signals RAMP1 and RAMP2 shown in Figure 7 are signals provided to the comparator 653 in the readout circuit 650 during the readout period. The shapes of the reference signals RAMP1 and RAMP2 can be attributed to the shape of the pixel signal VS.

[0153] The ramp signal generator 660 can generate a first reference signal RAMP1 and a second reference signal RAMP2 in response to the ramp enable signal R_EN during the readout period.

[0154] The ramp signal generator 660 can generate a reference signal containing multiple ramp signals with different slopes. For example, the slope of the ramp signal in the first reference signal RAMP1 can be different from the slope of the ramp signal in the second reference signal RAMP2. The ramp signal generator 660 can generate a first reference signal RAMP1 containing multiple ramp signals with a first slope s1 and a second reference signal RAMP2 containing multiple ramp signals with a second slope s2. For example, as illustrated in FIG7, the absolute value of the first slope s1 can be twice the second slope s2, but the embodiment is not limited thereto. As described above, the method of reading an image with two analog gains for a pixel signal VS via two reference signals RAMP containing ramp signals with different slopes is called the dual slope gain (DSG) method. By applying the DSG method, the SNR can be reduced and the dynamic range can be increased by reducing the quantization noise (QN) of the image signal.

[0155] Meanwhile, the first reference signal RAMP1 is a signal provided to the first comparator 653_1 during the Readout period, and the second reference signal RAMP2 is a signal provided to the second comparator 653_2 during the Readout period.

[0156] The first reference signal RAMP1 may include a first ramp signal R71 output during time period 701, a second ramp signal R72 output during time period 702, a third ramp signal R73 output during time period 703, and a fourth ramp signal R74 output during time period 704.

[0157] Furthermore, the second reference signal RAMP2 may include a first ramp signal R71 output during time period 701, a second ramp signal R72 output during time period 702, a third ramp signal R73 output during time period 703, and a fourth ramp signal R73 output during time period 704.

[0158] The first comparator 653_1 compares the pixel signal VS output from pixel PX with a first reference signal RAMP1 (which is input to the first comparator 653_1 in a timing synchronized manner with the pixel signal VS), and generates an output based on the comparison result. Furthermore, the second comparator 653_2 compares the pixel signal VS output from pixel PX with a second reference signal RAMP2 (which is input to the comparator 653_2 in a timing synchronized manner with the pixel signal VS), and generates an output based on the comparison result.

[0159] The embodiments are not limited to this, and each of the LOFIC reset signal RST_LOFIC, LOFIC signal SIG_LOFIC, HCG reset signal RST_H, and HCG signal SIG_H can be read out with different analog gains via ramp signals with different slopes.

[0160] Figure 8 is an example graph illustrating the signal-to-noise ratio according to one embodiment.

[0161] Specifically, Figure 8 illustrates a first curve 801 and a second curve 803. The first curve 801 is a graph showing the signal-to-noise ratio (SNR) in decibels (dB) of the signal obtained by synthesizing the HCG and LOFIC image signals read from the timing diagram shown in Figure 5. The second curve 803 is a graph showing the SNR in decibels (dB) of the signal obtained by synthesizing the HCG and LOFIC image signals read from the timing diagram shown in Figure 7. In this case, it is assumed that the absolute value of the slope s1 of the ramp signal in the first reference signal RAMP1 of Figure 7 is set to the absolute value of the slope s2 of the ramp signal in the second reference signal RAMP2 as 4:1.

[0162] That is, the first curve 801 is the SNR curve when the pixel signal VS is read out with the first analog gain without applying the DSG method, and the second curve 803 is the SNR curve when the pixel signal VS is read out while applying the DSG method. In other words, the second curve 803 shows the SNR of the composite image signal when the pixel signal VS is read out by applying the DSG method using two analog gains (that is, the first analog gain and a second analog gain that is four times the first analog gain).

[0163] The SNR decrease d8011 between the HCG and LOFIC image signals in the first curve 801 is greater than the SNR decrease d8031 between the HCG and LOFIC image signals in the second curve 803. Similarly, the dynamic range DR803 in the second curve 803 is wider than the dynamic range DR801 in the first curve 801.

[0164] Figure 9 is an example block diagram illustrating a pixel array and readout circuit according to another embodiment.

[0165] Referring to FIG9, an image sensor 900 according to another embodiment may include a pixel array 940 and a readout circuit 950.

[0166] Pixel array 940 may include multiple pixels PXa, PXb, and PXc. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding transfer signal from transfer signals TGi, TGi+1, TGi+2, TGi+3, TGi+4, and TGi+5, and a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2 to output pixel signals VS1 and VS2.

[0167] Assume that each of the multiple pixels PXa, PXb, and PXc contains two sub-pixels. For example, a pixel PXa may contain multiple sub-pixels 9401 and 9402. Each of the multiple sub-pixels 9401 and 9402 can be selected by transfer signals TTi and TTi+1 and selection signal SELi to output pixel signals VS1 and VS2.

[0168] As the number of photoelectric devices contained in a pixel PXa increases, the total amount of charge generated by the photoelectric devices can increase. Therefore, the magnitude of the pixel signal generated by processing the charge generated by all the photoelectric devices can also increase. When a large amount of charge is stored in a single floating diffuser (i.e., read out via a single row line), the conversion gain decreases when operating in HCG mode, and therefore, random noise (RN) can increase. Therefore, a method can be used to store the pixel signal generated by the photoelectric devices contained in a pixel in multiple floating diffusers and read the pixel signal via row lines corresponding to each floating diffuser.

[0169] The pixel array 940 will be described in detail with reference to FIG10. FIG10 is an example circuit diagram illustrating one pixel according to this embodiment.

[0170] Sub-pixel 9401 may include photoelectric devices PD11, PD12, PD13, and PD14 that generate charge in response to light, and pixel circuitry that processes the charge generated by photoelectric devices PD11, PD12, PD13, and PD14 to output an electrical signal. Sub-pixel 9402 may include photoelectric devices PD21, PD22, PD23, and PD24, and pixel circuitry that processes the charge generated by photoelectric devices PD21, PD22, PD23, and PD24 to output an electrical signal. Figure 10 illustrates that each of the plurality of sub-pixels 9401 and 9402 includes four photoelectric devices, but the present invention is not limited thereto, and each of the plurality of sub-pixels 9401 and 9402 may include fewer or more photoelectric devices.

[0171] In some embodiments, the charge generated by photoelectric devices PD11, PD12, PD13 and PD14 in sub-pixel 9401 can be output to readout circuit 950 via row line CL1, and the charge generated by photoelectric devices PD21, PD22, PD23 and PD24 in sub-pixel 9402 can be output to readout circuit 950 via row line CL2.

[0172] The cathodes of photoelectric devices PD11, PD12, PD13, and PD14 can be connected to the floating node FN11 via transfer transistors TX11, TX12, TX13, and TX14, and the anodes of photoelectric devices PD11, PD12, PD13, and PD14 can be grounded. Similarly, the cathodes of photoelectric devices PD21, PD22, PD23, and PD24 can be connected to the floating node FN21 via transfer transistors TX21, TX22, TX23, and TX24, and the anodes of photoelectric devices PD21, PD22, PD23, and PD24 can be grounded.

[0173] The pixel circuit may include transfer transistors TX11, TX12, TX13, TX14, TX21, TX22, TX23, and TX24, drive transistors DX1 and DX2, select transistors SX1 and SX2, reset transistors RX1 and RX2, and switch transistors SW1 and SW2. Transistors TX11, TX12, TX13, TX14, TX21, TX22, TX23, TX24, DX1, DX2, SX1, SX2, RX1, RX2, SW1, and SW2 in the pixel circuit can operate in response to control signals provided by the auto-driver 130, such as transfer control signals TG11, TG12, TG13, and TG14, selection signal SEL1, reset control signal RG1, and first gain control signal DCG1.

[0174] In some embodiments, sub-pixel 9401 may include a plurality of floating diffusers FD11 and FD12. Floating diffusers FD11 and FD12 may have a predetermined capacitance and store charges generated by photoelectric devices PD21, PD22, PD23, and PD24. Sub-pixel 9402 may include a plurality of floating diffusers FD21 and FD22. Floating diffusers FD21 and FD22 may have a predetermined capacitance and store charges generated by photoelectric devices PD21, PD22, PD23, and PD24. Floating diffusers FD11 and FD21 may have the same capacitance, and floating diffusers FD12 and FD22 may have the same capacitance.

[0175] Transfer transistor TX11 can be connected between photoelectric device PD11 and floating node FN11, and transfer transistor TX21 can be connected between photoelectric device PD21 and floating node FN21 and is controlled by transfer signal TG11. When transfer transistor TX11 is turned on, the charge generated by photoelectric device PD11 can be transferred to floating diffuser FD11. When transfer transistor TX21 is turned on, the charge generated by photoelectric device PD21 can be transferred to floating diffuser FD21.

[0176] Furthermore, transfer transistor TX12 can be connected between photoelectric device PD12 and floating node FN11, and transfer transistor TX22 can be connected between photoelectric device PD22 and floating node FN21 and is controlled by transfer signal TG12. When transfer transistor TX12 is turned on, the charge generated by photoelectric device PD12 can be transferred to floating diffusion FD11. When transfer transistor TX22 is turned on, the charge generated by photoelectric device PD22 can be transferred to floating diffusion FD21.

[0177] Furthermore, transfer transistor TX13 can be connected between photoelectric device PD12 and floating node FN11, and transfer transistor TX23 can be connected between photoelectric device PD23 and floating node FN21 and is controlled by transfer signal TG13. When transfer transistor TX13 is turned on, the charge generated by photoelectric device PD13 can be transferred to floating diffusion FD11. When transfer transistor TX23 is turned on, the charge generated by photoelectric device PD23 can be transferred to floating diffusion FD21.

[0178] Transfer transistor TX14 can be connected between photoelectric device PD14 and floating node FN11, and transfer transistor TX24 can be connected between photoelectric device PD24 and floating node FN21 and is controlled by transfer signal TG14. When transfer transistor TX14 is turned on, the charge generated by photoelectric device PD14 can be transferred to floating diffuser FD11. When transfer transistor TX24 is turned on, the charge generated by photoelectric device PD24 can be transferred to floating diffuser FD21.

[0179] The voltage of the floating node FN11 can be determined based on the charge accumulated in the floating diffuser FD11. The gate of the driving transistor DX1 is connected to the floating node FN11. The driving transistor DX1 can operate as a source follower amplifier for the voltage of the floating node FN11. The driving transistor DX1 can output the pixel signal VS1 to the row line CL1 via the selection transistor SX1 in response to the voltage of the floating node FN11.

[0180] Furthermore, the voltage of the floating node FN21 can be determined based on the charge accumulated in the floating diffuser FD11. The gate of the driving transistor DX2 is connected to the floating node FN21. The driving transistor DX2 can operate as a source follower amplifier for the voltage of the floating node FN21. The driving transistor DX2 can output the pixel signal VS2 to the row line CL2 via the selection transistor SX2 in response to the voltage of the floating node FN21.

[0181] Selector transistor SX1 can be connected between driver transistor DX1 and the corresponding row line CL1, and selector transistor SX2 can be connected between driver transistor DX2 and the corresponding row line CL2. Therefore, both selector transistors SX1 and SX2 can be controlled by select signal SEL1. For example, sub-pixels 9401 and 9402 can be selected simultaneously. When selector transistor SX1 is turned on, the pixel voltage VS1 output from driver transistor DX1 can be output to readout circuit 950 via row line CL1 connected to selector transistor SX1. Furthermore, when selector transistor SX2 is turned on, the pixel voltage VS2 output from driver transistor DX2 can be output to readout circuit 950 via row line CL2 connected to selector transistor SX2.

[0182] Reset transistors RX1 and RX2 can be connected between the power supply voltage line supplying the power supply voltage VDD and each of the floating nodes FN12 and FN22, and can be controlled by the reset control signal RG1. When reset transistors RX1 and RX2 are turned on by the reset signal RG1, the power supply voltage VDD can be applied to floating nodes FN12 and FN22 to reset them. When switching transistors SW1 and SW2 are turned on and reset transistors RX1 and RX2 are turned on, floating nodes FN11, FN12, FN21, and FN22 can all be reset to the power supply voltage VDD.

[0183] Switching transistor SW1 can be connected between floating node FN11 and floating node FN12, and switching transistor SW2 can be connected between floating node FN21 and floating node FN22 and is controlled by the first gain control signal DCG1.

[0184] Each of sub-pixels 9401 and 9402 can operate in the same manner as pixel PX1 described with reference to Figures 2A, 4 and 5.

[0185] Referring back to Figure 9, the readout circuit 950 may include a selector 951, a comparator 953, a counter 955, and a CDS circuit 957 connected to the pixel array 940.

[0186] Selector 951 may be implemented as, for example, a demultiplexer, but is not limited thereto. Selector 951 may generate an average value by averaging two pixel signals VS1 and VS2 received from pixel array 940. Selector 951 may receive a DEMUX selection signal SEL_M from controller 910 and output the generated average value to one of comparators 953_1 and 953_2 selected based on the DEMUX selection signal SEL_M.

[0187] Comparator 953 includes a first comparator 953_1 and a second comparator 953_2. One of the two input terminals of each of the first comparator 953_1 and the second comparator 953_2 can be connected to the output terminal of selector 951, and the other of the two input terminals can be connected to ramp signal generator 960. The first comparator 953_1 compares the pixel signal VS, corresponding to the average of the two pixel signals VS1 and VS2, with a first reference signal RAMP1 (which is input synchronously with the timing of the pixel signal VS input to the first comparator 953_1), and outputs the result to counter 955_1. The second comparator 953_2 compares the pixel signal VS, corresponding to the average of the two pixel signals VS1 and VS2, with a second reference signal RAMP2 (which is input synchronously with the timing of the pixel signal VS input to the second comparator 953_2), and outputs the result to counter 955_2.

[0188] Ramp signal generator 960 can generate reference signals RAMP1 and RAMP2 in response to a ramp enable signal R_EN input from controller 910. The ramp signal in each of reference signals RAMP1 and RAMP2 can be a signal in which the voltage level increases or decreases over time. In some embodiments, when the ramp signal included in reference signal RAMP1 has a waveform that decreases with a predetermined slope, a timing sequence may occur where the magnitude of the signal input to comparator 953_1 via selector 953 is the same as the magnitude of the ramp signal in reference signal RAMP1. Furthermore, in some embodiments, when the ramp signal included in reference signal RAMP2 has a waveform that decreases with a predetermined slope, a timing sequence may occur where the magnitude of the signal input to comparator 953_2 via selector 951 is the same as the magnitude of the ramp signal in reference signal RAMP2. The levels of the signals output from comparator 953_1 and comparator 953_2 can be synchronously shifted with the same timing as the magnitude of the signal input to comparator 953_1 and the magnitude of the ramp signal of reference signal RAMP1, and with the same timing as the magnitude of the signal input to comparator 953_2 and the magnitude of the ramp signal of reference signal RAMP2.

[0189] Counter 955 includes a first counter 955_1 and a second counter 955_2. The first counter 955_1 can be connected to the output terminal of comparator 953_1, and the second counter 955_2 can be connected to the output terminal of comparator 953_2. Each of counters 955_1 and counter 955_2 may be an up / down counter or a bit-by-bit counter.

[0190] The CDS circuit 957 includes a first CDS circuit 957_1 and a second CDS circuit 957_2. The first CDS circuit 957_1 can be connected to the output terminal of the counter 955_1 and can perform a correlation double sampling (CDS) method on the output of the pixel signal VS received from the counter 955_1 to generate an image signal. The second CDS circuit 957_2 can be connected to the output terminal of the counter 955_2 and can perform a correlation double sampling (CDS) method on the output of the pixel signal VS received from the counter 955_2 to generate an image signal.

[0191] The image sensor 900 shown in Figures 9 and 10 can operate in a manner similar to that of the image sensor described with reference to Figures 6 and 7.

[0192] Pixels capable of operating in two modes (HCG mode and LCG mode; or HCG mode and LOFIC mode) have been described with reference to Figures 2 through 10. However, when operating in two modes, there may be a significant decrease in SNR, as described with reference to Figure 8. Therefore, pixels capable of operating in three modes will be described.

[0193] Figure 11A is an example circuit diagram illustrating pixels according to another embodiment.

[0194] According to one embodiment, a pixel PX3 may include a pixel circuit that processes the charge generated by photoelectric devices PD31, PD32, PD33, and PD34 in response to light to output an electrical signal. In FIG11A, a pixel PX3 is illustrated as including four photoelectric devices PD31, PD32, PD33, and PD34, but the present invention is not limited thereto, and a pixel PX3 may include fewer or more photoelectric devices. Photoelectric devices PD31, PD32, PD33, and PD34 can detect external light to generate charge. The cathodes of photoelectric devices PD31, PD32, PD33, and PD34 can be connected to a floating node FN31 via transfer transistors TX31, TX32, TX33, and TX34, and the anodes of photoelectric devices PD31, PD32, PD33, and PD34 can be grounded.

[0195] The pixel circuit PC3 may include transfer transistors TX31, TX32, TX33, and TX34, a drive transistor DX3, a select transistor SX3, a reset transistor RX3, a first switch transistor SW31, and a second switch transistor SW32. The transistors TX31, TX32, TX33, TX34, SX3, RX3, SW31, and SW32 in the pixel circuit PC3 can operate in response to control signals provided by the auto-driver 130, such as transfer control signals TG31, TG32, TG33, and TG34, a select signal SEL1, a reset control signal RG1, and gain control signals DCG1 and DCG2.

[0196] In some embodiments, the pixel circuit PC3 may include a plurality of floating diffusers FD31, FD32, and FD33. The plurality of floating diffusers FD31, FD32, and FD33 may have a predetermined capacitance and store the charge generated by the photoelectric devices PD31, PD32, PD33, and PD34. Although three floating diffusers FD31, FD32, and FD33 are illustrated in FIG11A, the present invention is not limited thereto.

[0197] Transfer transistor TX31 can be connected between photoelectric device PD31 and the first floating node FN31, and can be controlled by transfer signal TG31. When transfer transistor TX31 is turned on, the charge generated by photoelectric device PD31 can be transferred to the first floating diffuser FD31. Furthermore, transfer transistor TX32 can be connected between photoelectric device PD32 and the first floating node FN31, and can be controlled by transfer signal TG32. When transfer transistor TX32 is turned on, the charge generated by photoelectric device PD32 can be transferred to the first floating diffuser FD31. Transfer transistor TX33 can be connected between photoelectric device PD33 and the first floating node FN31, and can be controlled by transfer signal TG33. When transfer transistor TX33 is turned on, the charge generated by photoelectric device PD33 can be transferred to the first floating diffuser FD31. Transfer transistor TX34 can be connected between photoelectric device PD34 and the first floating node FN31, and can be controlled by transfer signal TG34. When the transfer transistor TX34 is turned on, the charge generated by the photoelectric device PD34 can be transferred to the first floating diffuser FD31.

[0198] The voltage of the floating node FN31 can be determined based on the charge accumulated in the floating diffusion FD31.

[0199] The gate of the driving transistor DX3 is connected to the first floating node FN31. The driving transistor DX3 is operable as a source follower amplifier for the voltage of the first floating node FN31. The driving transistor DX3 can output the pixel signal VS2 to the row line CL via the select transistor SX3 in response to the voltage of the first floating node FN31.

[0200] The select transistor SX3 can be connected between the driving transistor DX3 and the row line CL, and is controlled by the select signal SEL. When the select transistor SX3 is turned on, the pixel voltage VS output from the driving transistor DX3 can be output to the readout circuit 150 via the row line CL connected to the select transistor SX3.

[0201] The reset transistor RX3 can be connected between the power supply voltage line supplying the power supply voltage VDD and the second floating node FN32, and is controlled by the reset control signal RG. When the reset transistor RX3 is turned on by the reset signal RG, the power supply voltage VDD can be applied to the second floating node FN32 to reset the second floating node FN32. When the first switching transistor SW31 and the second switching transistor SW32 are turned on and the reset transistor RX3 is turned on, both the first floating node FN31 and the second floating node FN32 can be reset.

[0202] The first switching transistor SW31 can be connected between the first floating node FN31 and the second floating node FN32, and is controlled by the first gain control signal DCG1.

[0203] When the first switching transistor SW31 is off, the first floating node FN31 has capacitance to the first floating diffuser FD31. In this case, since the amount of capacitance connected to the first floating node FN31 decreases, the image sensor 100 can generate an image signal in HCG mode. When operating in HCG mode, the gain of the circuitry (e.g., readout circuitry 150) used to process the pixel signal VS can be relatively smaller than the gain of the readout circuitry 150 when operating in LCG or LOFIC mode. Therefore, the SNR of the image sensor 100 can be increased to reduce the minimum detectable light intensity and improve the low-light detection performance of the image sensor 100.

[0204] When the first switching transistor SW31 is turned on, the second floating diffuser FD32 is connected to the first floating node FN31, and the capacitance of the first floating node FN31 is increased by the capacitance of the second floating diffuser FD32. In this case, since the amount of capacitance connected to the first floating node FN31 increases, the image sensor 100 can generate an image signal in LCG mode. When operating in LCG mode, the amount of charge that can be processed within a pixel can be increased. Therefore, the high light intensity detection performance of the image sensor 100 can be improved.

[0205] Meanwhile, the pixel circuit PC3 may further include a second switching transistor SW32. The second switching transistor SW32 may be connected between the second floating node FN32 and the third floating diffuser FD33, and is controlled by the second gain control signal DCG2.

[0206] The third floating diffuser FD33 may include a lateral overflow integrating capacitor (LOFIC).

[0207] When the second switching transistor SW32 is turned on, the third floating diffuser FD33 is connected to the second floating node FN32. In this case, when the first switching transistor SW31 is also turned on, the overflow charge from the charge transferred from photoelectric devices PD31, PD32, PD33, and PD34 to the first floating node FN31 can be shared by the second floating diffuser FD32 and the third floating diffuser FD33. In this case, since the capacitance connected to the first floating node FN31 is greatly increased, the image sensor 100 can generate an image signal in the LOFIC conversion gain mode. Similarly, FWC can be increased in the LOFIC conversion gain mode. Therefore, the high light intensity detection performance of the image sensor 100 can be further improved. That is, the large amount of charge overflowing from photoelectric devices PD31, PD32, PD33, and PD34 can be accumulated without being wasted by the third floating diffuser FD33, thus enabling the image sensor 100 to be detected under relatively high light intensity.

[0208] In general, the pixel PX3 can operate in one of the following modes: HCG mode (SW31 and SW32 off), LCG mode (SW31 on only), and LOFIC mode (SW31 and SW32 on) depending on the on and off states of the first switching transistor SW31 and the second switching transistor SW32.

[0209] In some embodiments, when the pixel array 140 operates in HCG mode, LCG mode, and LOFIC mode during a frame time period, the image signal processor 180 may receive HCG image signals according to HCG mode, LCG image signals according to LCG mode, and LOFIC image signals according to LOFIC mode from the data buffer 170, and synthesize the HCG image signals, LCG image signals, and LOFIC image signals to generate a composite image signal with high dynamic range.

[0210] SNR decrease can occur at the boundary between image signals according to HCG mode and image signals according to LCG mode, and SNR decrease can also occur at the boundary between image signals according to LCG mode and image signals according to LOFIC mode. As the capacitance difference between the first floating diffusion FD31, the second floating diffusion FD32, and the third floating diffusion FD33 increases, the magnitude of the SNR decrease occurring within a composite image signal can increase.

[0211] Figure 11B is an example circuit diagram illustrating pixels according to another embodiment.

[0212] The optoelectronic devices PD41, PD42, PD43, and PD44, transfer transistors TX41, TX42, TX43, and TX44, drive transistor DX4, select transistor SX4, and reset transistor RX4 shown in Figure 11B can each have the same configuration as the optoelectronic devices PD31, PD32, PD33, and PD34, transfer transistors TX31, TX32, TX33, and TX34, drive transistor DX3, select transistor SX3, and reset transistor RX3 shown in Figure 11A.

[0213] In some embodiments, the pixel circuit PC4 may include multiple floating diffusers FD41, FD42, and FD43. Floating diffusers FD41, FD42, and FD43 may have predetermined capacitances and store charges generated by photoelectric devices PD41, PD42, PD43, and PD44. Although three floating diffusers FD41, FD42, and FD43 are illustrated in FIG11B, the present invention is not limited thereto.

[0214] The first switching transistor SW41 can be connected between the first floating node FN41 and the second floating node FN42, and is controlled by the first gain control signal DCG1.

[0215] When the second switching transistor SW42 is turned off, the first floating node FN41 has a capacitance of the first floating diffuser FD41. In this case, since the amount of capacitance connected to the first floating node FN41 decreases, the image sensor 100 can generate an image signal in HCG mode.

[0216] When the first switching transistor SW41 is turned on, the second floating diffuser FD42 is connected to the first floating node FN41, and the capacitance of the first floating node FN41 is increased by the capacitance of the second floating diffuser FD42. In this case, since the amount of capacitance connected to the first floating node FN41 increases, the image sensor 100 can generate an image signal in LCG mode.

[0217] Meanwhile, the pixel circuit PC4 may further include a second switching transistor SW42. The second switching transistor SW42 may be connected between the first floating node FD41 and the third floating diffuser FD43, and is controlled by the second gain control signal DCG2.

[0218] The third floating diffusion FD43 may contain LOFIC.

[0219] When the second switching transistor SW42 is turned on, the third floating diffuser FD43 is connected to the first floating node FN41. In this case, when the first switching transistor SW41 is also turned on, the overflow charge from the charge transferred from photoelectric devices PD41, PD42, PD43, and PD44 to the first floating node FN41 can be shared by the second floating diffuser FD42 and the third floating diffuser FD43. In this case, since the capacitance connected to the first floating node FN41 is greatly increased, the image sensor 100 can generate an image signal in LOFIC conversion gain mode. Similarly, FWC can be increased in LOFIC conversion gain mode. Therefore, the high light intensity detection performance of the image sensor 100 can be further improved. That is, the large amount of charge overflowing from photoelectric devices PD41, PD42, PD43, and PD44 can be accumulated without being wasted by the third floating diffuser FD43, thus enabling the image sensor 100 to be detected under relatively high light intensity.

[0220] In general, the pixel PX4 can operate in one of the following modes depending on whether the first switching transistor SW41 and the second switching transistor SW42 are turned on or off: HCG mode (SW41 and SW42 are off), LCG mode (SW41 is on only), and LOFIC mode (SW41 and SW42 are on).

[0221] Figures 11A and 11B, as described above, are circuit diagrams illustrating an optoelectronic device and a pixel circuit according to an embodiment. However, the connection relationships between the plurality of floating diffusers included in the pixel according to the present invention are not limited to the specific structure of the pixel circuit shown in Figures 11A and 11B, and the pixel circuit may have a structure with arbitrary connection relationships and including connected floating diffusers. In the following, for ease of explanation, it is assumed that the pixel according to the present invention has the structure shown in Figure 11A.

[0222] Figure 12 is an example diagram illustrating the operation timing of an image sensor according to an embodiment.

[0223] Figure 12 illustrates a scan period used to drive multiple pixels in column-line units. A scan period may sequentially include a Reset period, an Exposure period, and a Readout period.

[0224] Figure 12 is a diagram illustrating the operation of the image sensor 100 in the RST-RST-SIG-SIG-SIG-RST (RRSS-SR) readout method.

[0225] The operation of the image sensor shown in Figure 12 will be described with reference to Figures 3 and 11A described above.

[0226] During the Reset period, the charges stored in the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33 are reset.

[0227] Specifically, a high-level first gain control signal DCG1 is applied to the gate of the first switching transistor SW31, and a second gain control signal DCG2 is applied to the gate of the second switching transistor SW32 to turn on both the first switching transistor SW31 and the second switching transistor SW32. The first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33 are connected to the first floating node FN31.

[0228] The transfer signal TG31 applied to the transfer transistor TX31, the transfer signal TG32 applied to the transfer transistor TX32, the transfer signal TG33 applied to the transfer transistor TX33, and the transfer signal TG34 applied to the transfer transistor TX34 can all have the same waveform, which is illustrated as the transfer signal TG in Figures 12 and 13, 15 and 16, 20 and 21, and 27 to 31.

[0229] The high-level quasi-transfer signal TG is applied to the gates of transfer transistors TX31, TX32, TX33 and TX34 to turn on transfer transistors TX31, TX32, TX33 and TX34.

[0230] The charges generated by photoelectric devices PD31, PD32, PD33, and PD34 can be supplied to the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33. Similarly, a high-level reset signal RG1 is applied to the gate of the reset transistor RX3 to turn it on. Then, the power supply voltage VDD is supplied to the first floating node FN31 to reset the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33. In this embodiment, the reset voltage can be, for example, the power supply voltage VDD. In this case, the selector transistor SX3 is turned off.

[0231] The exposure period is the time during which photoelectric devices PD31, PD32, PD33, and PD34 are exposed to light to generate charge. During the exposure period, the reset signal RG1 and the transfer signal TG shift from a high level to a low level, thus disconnecting the reset transistor RX3 and the transfer transistors TX31, TX32, TX33, and TX34. Furthermore, since both the first gain control signal DCG1 and the second gain control signal DCG2 remain at a high level, the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33 are all connected to the first floating node FN31 and the second floating node FN32.

[0232] The readout period is the time during which the pixel signal VS generated in pixel PX3 is transferred to the readout circuit 150. Each of the following signals can be output as the pixel signal VS: LCG reset signal RST_L, HCG reset signal RST_H, HCG signal SIG_H, LCG signal SIG_L, LOFIC signal SIG_LOFIC, and LOFIC reset signal RST_LOFIC.

[0233] The conversion gain can be adjusted depending on whether the first switching transistor SW31 and the second switching transistor SW32 are driven according to the first gain control signal DCG1 and the second gain control signal DCG2. For example, when the switching transistor SW31 is off, pixel PX3 can operate in HCG mode, which generates pixel signal VS based on the charge stored in the first floating diffusion FD31; when the switching transistor SW31 is on and the switching transistor SW32 is off, pixel PX3 can operate in LCG mode, which generates pixel signal VS based on the charge stored in the first floating diffusion FD31 and the second floating diffusion FD32; and when the switching transistors SW31 and SW32 are on, pixel PX3 can operate in LOFIC mode, which generates pixel signal based on the charge stored in the first floating diffusion FD31, the second floating diffusion FD32, and the third floating diffusion FD33.

[0234] First, a high-level selection signal SEL1 is applied to the gate of the selection transistor SX3 to turn it on. Furthermore, since the first gain control signal DCG1 is maintained at a high level, the first floating diffuser FD31 and the second floating diffuser FD32 are connected to the first floating node FN31. Therefore, during time period 101, the voltage of the first floating node FN31, based on the charge stored in the first floating diffuser FD31 and the second floating diffuser FD32, can be output as the pixel signal VS (i.e., the LCG reset signal RST_L) via the driving transistor DX3 to the row line CL.

[0235] Next, when the first gain control signal DCG1 is shifted to the low bit, the first switching transistor SW31 is turned off. Therefore, during time period 102, the voltage of the first floating node FN31, based on the charge stored in the first floating diffuser FD31, can be output to the row line CL via the driving transistor DX3 as the pixel signal VS (i.e., the HCG reset signal RST_H).

[0236] Subsequently, a high-level transfer signal TG is applied to the gates of transfer transistors TX31, TX32, TX33, and TX34, thus transferring the charge generated by photoelectric devices PD31, PD32, PD33, and PD34 to the first floating diffuser FD31. Therefore, the amount of charge stored in the first floating diffuser FD31 can be changed. Thus, during time period 103, the voltage of the first floating node FN31, based on the changed charge stored in the first floating diffuser FD31, can be output as a pixel signal VS (i.e., HCG signal SIG_H) to the row line CL via the driving transistor DX3.

[0237] Furthermore, a high-level first gain control signal DCG1 is applied to the first switching transistor SW31, thus connecting the first floating diffuser FD31 and the second floating diffuser FD32 to the first floating node FN31. Additionally, a high-level transfer signal TG is applied to the gates of transfer transistors TX31, TX32, TX33, and TX34, thus providing the charge generated by photoelectric devices PD31, PD32, PD33, and PD34 to the first floating diffuser FD31 and the second floating diffuser FD32, and the charge stored in the first floating diffuser FD31 and the second floating diffuser FD32 can be changed. Therefore, during time period 104, the voltage of the first floating node FN31, based on the charge stored in the first floating diffuser FD31 and the second floating diffuser FD32, can be output as a pixel signal VS (i.e., LCG signal SIG_L) via the driving transistor DX3 to the row line CL.

[0238] Subsequently, the high-level second gain control signal DCG2 is applied to the second switching transistor SW32, thus connecting the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33 to the first floating node FN31. Furthermore, the high-level transfer signal TG is applied to the gates of the transfer transistors TX31, TX32, TX33, and TX34, thus transferring the charge generated by the photoelectric devices PD31, PD32, PD33, and PD34 to the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33. Therefore, during time period 105, the voltage of the first floating node FN31, based on the charge stored in the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33, can be output as the pixel signal VS (i.e., the LOFIC signal SIG_LOFIC) to the row line CL via the driving transistor DX3.

[0239] Next, the high-level reset signal RG1 is applied to the reset transistor RX3, so the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33 are reset by the power supply voltage VDD. Therefore, during time period 106, the voltage of the first floating node FN31 based on the charge stored in the reset first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33 can be output to the row line CL as the pixel signal VS (i.e., the LOFIC reset signal RST_LOFIC) via the driving transistor DX3.

[0240] During time period 101, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG reset signal RST_L can be output to the first comparator 153_1. During time periods 102 and 103, the DEMUX selection signal SEL_M is at a high level, and therefore, the HCG reset signal RST_H and the HCG signal SIG_H can be output to the second comparator 153_2. During time period 104, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG signal SIG_L can be output to the first comparator 153_1. During time periods 105 and 106, the DEMUX selection signal SEL_M is at a high level, and therefore, the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC can be output to the second comparator 153_2.

[0241] Meanwhile, the reference signal RAMP shown in Figure 12 is a signal provided to the comparator 653 in the readout circuit 150 during the readout period.

[0242] The waveform of the reference signal RAMP shown in Figure 12 can be determined based on the type of pixel signal VS generated during the time period shown in Figure 12.

[0243] Comparators 153_1 and 153_2 can compare the pixel signal VS with the reference signal RAMP (which is input to each of the pixel signal VS in comparators 153_1 and 153_2 in a timing synchronized manner), and output the result to counters 155_1 and 155_2.

[0244] A first ramp signal R1 having a first period and a fourth ramp signal R4 having a second period greater than the first period can be provided to the first comparator 153_1 synchronously with the comparison target signal. Specifically, the first ramp signal R1 can be provided to the first comparator 153_1 during time period 101, and the fourth ramp signal R4 can be provided to the first comparator 153_1 during time period 104.

[0245] The first comparator 153_1 can output the result of comparing the LCG reset signal RST_L input via selector 151 with the first ramp signal R1 having a first period, and output the result of comparing the LCG signal SIG_L input via selector 151 with the fourth ramp signal R4 having a second period greater than the first period.

[0246] A second ramp signal R2 with a first period, a third ramp signal R3 with a second period, a fifth ramp signal R5 with a first period, and a sixth ramp signal R6 with a first period can be sequentially provided to the second comparator 153_2 synchronously with the comparison target signal. Specifically, the second ramp signal R2 can be provided to the second comparator 153_2 during time period 102, the third ramp signal R3 can be provided to the second comparator 153_2 during time period 103, the fifth ramp signal R5 can be provided to the second comparator 153_2 during time period 105, and the sixth ramp signal R6 can be provided to the second comparator 153_2 during time period 106.

[0247] The second comparator 153_2 can output the result of comparing the HCG reset signal RST_H input via selector 151 with the second ramp signal R2 having a first period, the result of comparing the HCG signal SIG_H input via selector 151 with the third ramp signal R3 having a second period, the result of comparing the LOFIC signal SIG_LOFIC input via selector 151 with the fifth ramp signal R5 having a second period, and the result of comparing the LOFIC reset signal RST_LOFIC input via selector 151 with the sixth ramp signal R6 having a second period.

[0248] However, the embodiments are not limited to this, and the ramp signal generator 160 may also generate a reference signal RAMP having another waveform that includes the first ramp signal R1 to the sixth ramp signal R6.

[0249] Here, since the changes in the LCG reset signal RST_L, HCG reset signal RST_H, and LOFIC reset signal RST_LOFIC are relatively small, while the changes in the HCG signal SIG_H, LCG signal SIG_L, and LOFIC signal SIG_LOFIC are relatively large, the first cycle can be shorter than the second cycle.

[0250] Typically, since the analog gain is adjusted to be the same in all modes, the first ramp signal R1 to the sixth ramp signal R6 can all have the same slope. When adjusting the analog gain, the slopes of the first ramp signal R1 to the sixth ramp signal R6 can be changed.

[0251] Figure 13 is an example diagram illustrating another operating timing of an image sensor according to one embodiment.

[0252] Figure 13 illustrates a scan period used to drive multiple pixels in column-line units. A scan period may sequentially include a Reset period, an Exposure period, and a Readout period.

[0253] Figure 13 is a diagram illustrating the operation of the image sensor 100 in the SIG-RST-RST-RST-SIG-SIG (SR-RRSS) readout method.

[0254] The operation of the image sensor illustrated in FIG13 will be described with reference to FIG3 and FIG11A described above. First, since the waveforms of the reset signal RG1, the first gain control signal DCG1, the second gain control signal DCG2, and the transfer signal TG in the Reset and Exposure periods of FIG13 are similar to those in the Reset and Exposure periods of FIG12, the description of FIG12 can also be applied to FIG13. The Readout period is the period during which the pixel signal VS generated in pixel PX3 is transferred to the readout circuit 150.

[0255] During the readout period, each of the following signals can be output as pixel signal VS: LOFIC signal SIG_LOFIC, LOFIC reset signal RST_LOFIC, LCG reset signal RST_L, HCG reset signal RST_H, HCG signal SIG_H, and LCG signal SIG_L.

[0256] First, a high-level selection signal SEL1 is applied to the gate of the selection transistor SX3 to turn on the selection transistor SX3. Furthermore, since the first gain control signal DCG1 and the second gain control signal DCG2 are maintained at a high level, the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33 are applied to the first floating node FN31. During the exposure period, the charge overflowing from photoelectric devices PD31, PD32, PD33, and PD34 can be shared by the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33. Therefore, during period 111, the voltage of the first floating node FN31, based on the charge stored in the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33, can be output as the pixel signal VS (i.e., the LOFIC signal SIG_LOFIC) to the row line CL via the driving transistor DX3.

[0257] Next, the high-level reset signal RG1 is applied to the reset transistor RX3, thus resetting the first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33 by the power supply voltage. Therefore, during time period 112, the voltage of the first floating node FN31, based on the charge stored in the reset first floating diffuser FD31, the second floating diffuser FD32, and the third floating diffuser FD33, can be output to the row line CL via the driving transistor DX3 as the pixel signal VS (i.e., the LOFIC reset signal RST_LOFIC).

[0258] Subsequently, since the first gain control signal DCG1 is maintained at a high level, the first floating diffuser FD31 and the second floating diffuser FD32 are connected to the first floating node FN31. Therefore, during time period 113, the voltage of the first floating node FN31, based on the charge stored in the first floating diffuser FD31 and the second floating diffuser FD32, can be output to the row line CL via the driving transistor DX3 as the pixel signal VS (i.e., the LCG reset signal RST_L).

[0259] Next, when the first gain control signal DCG1 is shifted to the low bit, the first switching transistor SW31 is turned off. Therefore, during time period 114, the voltage of the first floating node FN31, based on the charge stored in the first floating diffusion FD31, can be output to the row line CL via the driving transistor DX3 as the pixel signal VS (i.e., the HCG reset signal RST_H).

[0260] Next, a high-level transfer signal TG is applied to the gates of transfer transistors TX31, TX32, TX33, and TX34, thus transferring the charge generated by photoelectric devices PD31, PD32, PD33, and PD34 to the first floating diffuser FD31. Therefore, the amount of charge stored in the first floating diffuser FD31 can be changed. Thus, during time period 115, the voltage of the first floating node FN31, based on the changed charge stored in the first floating diffuser FD31 due to photoelectric devices PD31, PD32, PD33, and PD34, can be output as a pixel signal (i.e., HCG signal SIG_H) to the row line CL via the driving transistor DX3.

[0261] Furthermore, a high-level first gain control signal DCG1 is applied to the first switching transistor SW31, thus connecting the first floating diffuser FD31 and the second floating diffuser FD32 to the first floating node FN31. Additionally, a high-level transfer signal TG is applied to the gates of transfer transistors TX31, TX32, TX33, and TX34, thus transferring the charge generated by photoelectric devices PD31, PD32, PD33, and PD34 to the first floating diffuser FD31 and the second floating diffuser FD32. Therefore, during time period 116, the voltage of the first floating node FN31, based on the charge stored in the first floating diffuser FD31 and the second floating diffuser FD32, can be output as a pixel signal (i.e., LCG signal SIG_L) via the driving transistor DX3 to the row line CL. During time periods 111 and 112, the DEMUX selection signal SEL_M is at a high level, and therefore, the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC can be output to the second comparator 153_2. During time period 113, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG reset signal RST_L can be output to the first comparator 153_1. During time periods 114 and 115, the DEMUX selection signal SEL_M is at a high level, and therefore, the HCG reset signal RST_H and the HCG signal SIG_H can be output to the second comparator 153_2. During time period 116, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG signal SIG_L can be output to the first comparator 153_1.

[0262] Meanwhile, the reference signal RAMP shown in Figure 13 is a signal provided to the comparator 653 in the readout circuit 150 during the readout period.

[0263] The waveform of the reference signal RAMP can be determined based on the type of pixel signal VS generated during the time period shown in Figure 13.

[0264] Comparators 153_1 and 153_2 can compare the pixel signal VS with the reference signal RAMP (which is input to each of the pixel signal VS in comparators 153_1 and 153_2 in a timing synchronized manner), and output the result to counters 155_1 and 155_2.

[0265] A third ramp signal R13 having a first period and a sixth ramp signal R16 having a second period greater than the first period can be sequentially provided to the first comparator 153_1 synchronously with the comparison target signal. Specifically, the third ramp signal R13 can be provided to the first comparator 153_1 within a time period 113, and the sixth ramp signal R16 can be provided to the first comparator 153_1 within a time period 116.

[0266] Furthermore, a first ramp signal R11 with a second period, a second ramp signal R12 and a fourth ramp signal R14 with a first period shorter than the second period, and a fifth ramp signal R15 with a second period can be sequentially provided to the second comparator 153_2 synchronously with the comparison target signal. Specifically, the first ramp signal R11 can be provided to the second comparator 153_2 within time period 111, the second ramp signal R12 can be provided to the second comparator 153_2 within time period 112, the fourth ramp signal R14 can be provided to the second comparator 153_2 within time period 114, and the fifth ramp signal R15 can be provided to the second comparator 153_2 within time period 115.

[0267] However, the embodiments are not limited to this, and the ramp signal generator 160 may also generate a reference signal RAMP having another waveform that includes the first ramp signal R11 to the sixth ramp signal R16.

[0268] Comparator 153 compares the pixel signal VS output from pixel PX3 with a reference signal RAMP (which is input to comparator 153 in a timing synchronized manner with the pixel signal VS), and generates an output based on the comparison result. This has been described in detail with reference to FIG12, and the corresponding description can also be applied to the embodiment illustrated in FIG13.

[0269] Figure 14 is an example curve illustrating the signal-to-noise ratio according to an embodiment of the present invention.

[0270] In Figure 14, the x-axis represents the amount of charge generated by photoelectric devices PD31, PD32, PD33 and PD34, and the y-axis represents the signal-to-noise ratio of the signal obtained by the image signal processor 180 synthesizing HCG image signal, LCG image signal and LOFIC image signal in decibels (dB).

[0271] The first graph 1401 is a graph showing the SNR of the composite signal output from the image signal processor 180 when the pixel signal VS is read out at an analog gain of twice the predetermined analog gain. In this case, as shown in the first graph 1401, the FWC is proportional to the amount of the maximum detectable incident light f1. Furthermore, the first graph 1401 shows the SNR decrease d1411 between the HCG image signal and the LCG image signal, and the SNR decrease d1412 between the LCG image signal and the LOFIC image signal.

[0272] The second graph 1403 is a graph showing the SNR of the composite signal output from the image signal processor 180 when the pixel signal VS is read out at an analog gain of four times the predetermined analog gain. In this case, as shown in the first graph 1403, the FWC is proportional to the amount of the maximum detectable incident light f2. Furthermore, the second graph 1403 shows the SNR decrease d1421 between the HCG image signal and the LCG image signal, and the SNR decrease d1422 between the LCG image signal and the LOFIC image signal.

[0273] As shown in Figure 14, the SNR curve changes with increasing analog gain. The dynamic range decreases as analog gain increases. Furthermore, it can be seen that increasing analog gain shifts the signal-to-noise ratio (SNR) curve of the LOFIC image signal to the left, and therefore, the SNR drop can further increase. Specifically, with increasing analog gain, the increase in the magnitude of the SNR drop between the LCG and LOFIC image signals from SNR drop d1412 to SNR drop d1422 is greater than the increase in the magnitude of the SNR drop between the HCG and LCG image signals from SNR drop d1411 to SNR drop d1421.

[0274] Figures 15 and 16 are example diagrams illustrating the operation timing of an image sensor.

[0275] The operation of the image sensor illustrated in Figures 15 and 16 will be described with reference to Figures 6 and 11A.

[0276] Figure 15 illustrates a scan period used to drive multiple pixels in column-line units. A scan period may sequentially include a Reset period, an Exposure period, and a Readout period.

[0277] Figure 15 illustrates the operation of the image sensor 600 in the SIG-RST-RST-RST-SIG-SIG (SR-RRSS) readout method. Firstly, since the waveforms of the reset signal RG1, the first gain control signal DCG1, the second gain control signal DCG2, and the transfer signal TG in the Reset, Exposure, and Readout periods of Figure 15 are similar to those in Figure 13, the description in Figure 13 can also be applied to Figure 15.

[0278] The readout period is the time during which the pixel signal VS generated in pixel PX is transferred to the readout circuit 650.

[0279] During time period 121, the voltage of the first floating node FN31, based on the charge stored in the first floating diffusion FD31, the second floating diffusion FD32, and the third floating diffusion FD33, can be output to the horizontal line CL as a pixel signal VS (i.e., the LOFIC signal SIG_LOFIC) via the driving transistor DX3. During time period 122, the pixel signal VS can be output to the horizontal line CL as a LOFIC reset signal RST_LOFIC. During time period 123, the pixel signal VS can be output to the horizontal line CL as an LCG reset signal RST_L. During time period 124, the pixel signal VS can be output to the horizontal line CL as an HCG reset signal RST_H. During time period 125, the voltage of the first floating node FN31, based on the charge stored in the first floating diffusion FD31 as changed due to photoelectric devices PD31, PD32, PD33, and PD34, can be output to the horizontal line CL as a pixel signal VS (i.e., the HCG signal SIG_H) via the driving transistor DX3. During time period 126, the voltage of the first floating node FN31, based on the charge stored in the first floating diffuser FD31 and the second floating diffuser FD32, can be output as a pixel signal VS (i.e., LCG signal SIG_L) to the row line CL via the driving transistor DX3.

[0280] During time periods 121 and 122, the DEMUX selection signal SEL_M is at a high level, and therefore, the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC can be output to the second comparator 653_2. During time period 123, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG reset signal RST_L can be output to the first comparator 653_1. During time periods 124 and 125, the DEMUX selection signal SEL_M is at a high level, and therefore, the HCG reset signal RST_H and the HCG signal SIG_H can be output to the second comparator 653_2. Finally, during time period 126, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG signal SIG_L can be output to the first comparator 653_1.

[0281] The reference signals RAMP1 and RAMP2 shown in Figure 15 are signals provided to comparator 653 in readout circuit 650 during the readout period. The shapes of reference signals RAMP1 and RAMP2 can be attributed to the shape of pixel signal VS.

[0282] Simultaneously, the first reference signal RAMP1 is a signal provided to the first comparator 653_1 during the Readout period, and the second reference signal RAMP2 is a signal provided to the second comparator 653_2 during the Readout period. The ramp signal generator 660 can generate the first reference signal RAMP1 and the second reference signal RAMP2 in response to the ramp enable signal R_EN during the Readout period.

[0283] A third ramp signal R23 having a first period and a sixth ramp signal R26 having a second period greater than the first period can be sequentially provided to the first comparator 653_1 synchronously with the comparison target signal. Specifically, the third ramp signal R23 can be provided to the first comparator 653_1 within time period 123, and the sixth ramp signal R26 can be provided to the first comparator 653_1 within time period 126.

[0284] Furthermore, a first ramp signal R21 with a second period, a second ramp signal R22 and a fourth ramp signal R24 with a first period, and a fifth ramp signal R25 with a second period can be sequentially provided to the second comparator 653_2 synchronously with the comparison target signal. Specifically, the first ramp signal R21 can be provided to the second comparator 653_2 during time period 121, the second ramp signal R22 can be provided to the second comparator 653_2 during time period 122, the fourth ramp signal R24 can be provided to the second comparator 653_2 during time period 124, and the fifth ramp signal R25 can be provided to the second comparator 653_2 during time period 125.

[0285] However, the embodiments are not limited to this, and the ramp signal generator 660 may also generate a reference signal having another waveform including the first ramp signal R21 to the sixth ramp signal R26.

[0286] The first ramp signal R21 to the sixth ramp signal R26 can all have the same slope s1.

[0287] The first comparator 653_1 compares the pixel signal VS output from pixel PX with a first reference signal RAMP1 (which is input to the first comparator 653_1 in a timing synchronized manner with the pixel signal VS), and generates an output based on the comparison result. Furthermore, the second comparator 653_2 compares the pixel signal VS output from pixel PX with a second reference signal RAMP2 (which is input to the comparator 653_2 in a timing synchronized manner with the pixel signal VS), and generates an output based on the comparison result.

[0288] Specifically, Figure 16 is a diagram illustrating the operating timing of the image sensor when the slope of the ramp signal in the first reference signal RAMP1 shown in Figure 15 is different from the slope of the ramp signal in the second reference signal RAMP2.

[0289] Similar to Figure 15, during time period 131, the pixel signal VS can be output to the horizontal line CL as the LOFIC signal SIG_LOFIC. During time period 132, the pixel signal VS can be output to the horizontal line CL as the LOFIC reset signal RST_LOFIC. During time period 133, the pixel signal VS can be output to the horizontal line CL as the LCG reset signal RST_L. During time period 134, the pixel signal VS can be output to the horizontal line CL as the HCG reset signal RST_H. During time period 135, the pixel signal VS can be output to the horizontal line CL as the HCG signal SIG_H. During time period 136, the pixel signal VS can be output to the horizontal line CL as the LCG signal SIG_L.

[0290] During time periods 131 and 132, the DEMUX selection signal SEL_M is at a high level, and therefore, the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC can be output to the second comparator 653_2. During time period 133, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG reset signal RST_L can be output to the first comparator 653_1. During time periods 134 and 132, the DEMUX selection signal SEL_M is at a high level, and therefore, the HCG reset signal RST_H and the HCG signal SIG_H can be output to the second comparator 653_2. Finally, during time period 136, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG signal SIG_L can be output to the first comparator 653_1.

[0291] The first reference signal RAMP1 is a signal provided to the first comparator 653_1 during the readout period, and the second reference signal RAMP2 is a signal provided to the second comparator 653_2 during the readout period. The ramp signal generator 660 can generate the first reference signal RAMP1 and the second reference signal RAMP2 in response to the ramp enable signal R_EN during the readout period. For example, the first reference signal RAMP1 may contain multiple ramp signals with a first slope s1, and the second reference signal RAMP2 may contain multiple ramp signals with a second slope s2. When the ramp signal generator 660 adjusts the slope of the ramp signals in the second reference signal RAMP2, the analog gain can be changed when the readout LOFIC signal SIG_LOFIC, the LOFIC reset signal RST_LOFIC, the HCG reset signal RST_H, and the HCG signal SIG_H are output.

[0292] A third ramp signal R33 having a first period and a sixth ramp signal R36 having a second period greater than the first period can be sequentially provided to the first comparator 653_1 synchronously with the comparison target signal. Specifically, the third ramp signal R33 can be provided to the first comparator 653_1 within time period 133, and the sixth ramp signal R26 can be provided to the first comparator 653_1 within time period 136.

[0293] Furthermore, a first ramp signal R31 with a second period, a second ramp signal R32 and a fourth ramp signal R34 with a first period, and a fifth ramp signal R35 with a second period can be sequentially provided to the second comparator 653_2 synchronously with the comparison target signal. Specifically, the first ramp signal R31 can be provided to the second comparator 653_2 during time period 131, the second ramp signal R32 can be provided to the second comparator 653_2 during time period 132, the fourth ramp signal R34 can be provided to the second comparator 653_2 during time period 134, and the fifth ramp signal R35 can be provided to the second comparator 653_2 during time period 135.

[0294] The embodiments are not limited to this, and each of the LOFIC reset signal RST_LOFIC, LOFIC signal SIG_LOFIC, LCG reset signal RST_L, LCG signal SIG_L, HCG reset signal RST_H and HCG signal SIG_H can be read out with different analog gains via ramp signals with different slopes.

[0295] Figures 17 and 18 are example graphs illustrating the signal-to-noise ratio according to another embodiment of the present invention. Specifically, Figures 17 and 18 illustrate the signal-to-noise ratio in decibels (dB) of the signal obtained by synthesizing the HCG image signal, LCG image signal, and LOFIC image signal according to the readout circuit 650 shown in Figure 6.

[0296] The first graph 1701 is a graph showing the SNR of the signal obtained by synthesizing the HCG image signal, LCG image signal, and LOFIC image signal when the analog gain of the HCG image signal, LCG image signal, and LOFIC image signal is twice a predetermined analog gain. In this case, the first reference signal RAMP1 and the second reference signal RAMP2 have the same slope. The first graph 1701 shows the SNR decrease d1711 between the HCG image signal and the LCG image signal, and the SNR decrease d1712 between the LCG image signal and the LOFIC image signal.

[0297] The second curve 1703 is a graph showing the SNR of the signal obtained by synthesizing the HCG image signal, LCG image signal, and LOFIC image signal when the analog gain of the HCG image signal and the LOFIC image signal is twice the predetermined analog gain, and the analog gain of the LCG image signal is the same as the predetermined analog gain. In this case, the slope of the ramp signal when reading out the HCG image signal and the LOFIC image signal can be 1 / 2 times the slope of the ramp signal when reading out the LCG image signal. The second curve 1703 shows the SNR decrease d1721 between the HCG image signal and the LCG image signal, and the SNR decrease d1722 between the LCG image signal and the LOFIC image signal.

[0298] As shown in Figure 17, the SNR decrease d1722 between the LCG image signal and the LOFIC image signal in the first curve 1703 is smaller than the SNR decrease d1712 between the LCG image signal and the LOFIC image signal in the first curve 1701. For example, when acquiring the image signal without increasing the analog gain of the LCG image signal, the SNR decrease between the LCG image signal and the LOFIC image signal may be smaller.

[0299] The third curve 1801 plots the SNR of the signal obtained by synthesizing the LCG signal SIG_H, LCG image signal, and LOFIC image signal when the analog gain of the HCG image signal, LCG image signal, and LOFIC image signal is four times the predetermined analog gain. In this case, the first reference signal RAMP1 and the second reference signal RAMP2 have the same slope. The third curve 1801 plots the SNR decrease d1811 between the HCG image signal and the LCG image signal, and the SNR decrease d1812 between the LCG image signal and the LOFIC image signal.

[0300] The fourth curve, Figure 1803, illustrates the SNR of the signal obtained by synthesizing the HCG, LCG, and LOFIC image signals when the analog gain of the HCG and LOFIC image signals is four times the predetermined analog gain, and the analog gain of the LCG image signal is the predetermined analog gain. In this case, the slope of the ramp signal when reading out the HCG and LOFIC image signals can be 1 / 4 times the slope of the ramp signal when reading out the LCG image signal. The fourth curve, Figure 1803, shows the SNR decrease d1821 between the HCG and LCG image signals and the SNR decrease d1822 between the LCG and LOFIC image signals.

[0301] As shown in Figure 18, the SNR decrease d1812 between the LCG image signal and the LOFIC image signal in the third curve 1801 is less than the SNR decrease d1822 between the LCG image signal and the LOFIC image signal in the fourth curve 1803.

[0302] Referring to Figures 17 and 18, according to an embodiment of the present invention, the analog gain of the LCG image signal is maintained, and it can be seen that as the analog gain of the HCG image signal and the LOFIC image signal increases, the degree of SNR decrease between the LCG image signal and the LOFIC image signal is further improved.

[0303] The embodiments are not limited to this, and can be applied to situations where the analog gain of the LCG image signal is lower than that of the HCG and LOFIC image signals. For example, the ratio of the analog gain of the HCG image signal, the analog gain of the LCG image signal, and the analog gain of the LOFIC image signal is 2:1:2, 4:1:4, 4:2:4, 8:2:8, 16:4:16, etc., but is not limited to this.

[0304] Figure 19 is an example block diagram illustrating a pixel array and readout circuit according to another embodiment.

[0305] Referring to FIG19, an image sensor 1900 according to another embodiment may include a pixel array 1940 and a readout circuit 1950.

[0306] Pixel array 1940 may contain multiple pixels PX. Each pixel PX can be selected by transfer signal TG and selection signal SEL1 to output pixel signal VS. Referring to Figure 19, pixel array 1940 may contain multiple pixels PXa, PXb, and PXc. Each of the multiple pixels PXa, PXb, and PXc can receive a corresponding transfer signal from transfer signals TGi, TGi+1, and TGi+2, and a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2. Each of the multiple pixels PXa, PXb, and PXc can receive a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2 to output pixel signal VS. Here, it is assumed that each of the multiple pixels PXa, PXb, and PXc contains a sub-pixel.

[0307] The readout circuit 1950 may include a selector 1951, a comparator 1953, a counter 1955, and a CDS circuit 1957 connected to each row line CL of the pixel array 1940.

[0308] Selector 1951 may be implemented as, for example, a multiplexer, but is not limited thereto. Selector 1951 may correspond to a corresponding row line CL and may receive a pixel signal VS from the row line CL. Selector 1951 may receive a DEMUX selection signal SEL_M from controller 1910 and output the pixel signal VS to comparator 1953 based on the DEMUX selection signal SEL_M. According to one embodiment, selector 1951 may include four output terminals. Selector 1951 may output the pixel signal VS to any of the four output terminals based on the DEMUX selection signal SEL_M.

[0309] The ramp signal generator 1960 can generate multiple reference signals RAMP1, RAMP2, RAMP3, and RAMP4 in response to the ramp enable signal R_EN input from the controller 1910. The ramp signal among the reference signals can be a signal in which the voltage level increases or decreases over time.

[0310] Comparator 1953 can compare the pixel signal VS with one of a plurality of reference signals RAMP1, RAMP2, RAMP3 and RAMP4.

[0311] In one embodiment, comparator 1953 may include first comparators 1953_1 through fourth comparators 1953_4. One of the two input terminals of the first comparator 1953_1 may be connected to one of the four output terminals of the selector 1951, and the other of the two input terminals may be connected to the ramp signal generator 1960. One of the two input terminals of the first comparator 1953_2 may be connected to one of the four output terminals of the selector 1951, and the other of the two input terminals may be connected to the ramp signal generator 1960. One of the two input terminals of the third comparator 1953_3 may be connected to one of the four output terminals of the selector 1951, and the other of the two input terminals may be connected to the ramp signal generator 1960. One of the two input terminals of the fourth comparator 1953_4 may be connected to one of the four output terminals of the selector 1951, and the other of the two input terminals may be connected to the ramp signal generator 1960.

[0312] Counter 1955 can count how long a specific level of the signal output from the corresponding comparator 1953 is maintained. Specifically, counter 1955 can receive a clock from a timing generator (120 in Figure 1).

[0313] Counter 1955 can use the rising or falling edge of a clock signal to count how long a specific level of the signal received from the corresponding comparator 1953 has been maintained. In one embodiment, counter 1955 may include a first counter 1955_1 through a fourth counter 1955_4. In some embodiments, the output terminal of the first comparator 1953_1 may be connected to counter 1955_1. The output terminal of the second comparator 1953_2 may be connected to counter 1955_2. The output terminal of the third comparator 1953_3 may be connected to counter 1955_3. The output terminal of the fourth comparator 1953_4 may be connected to counter 1955_4.

[0314] In general, the first comparator 1953_1 compares the pixel signal VS with the first reference signal RAMP1 (which is input synchronously with the timing of the pixel signal VS input to the first comparator 1953_1), and outputs the comparison result to the first counter 1955_1. The second comparator 1953_2 compares the pixel signal VS with the second reference signal RAMP2 (which is input synchronously with the timing of the pixel signal VS input to the second comparator 1953_2), and outputs the comparison result to the second counter 1955_2. The third comparator 1953_3 compares the pixel signal VS with the third reference signal RAMP3 (which is input synchronously with the timing of the pixel signal VS input to the third comparator 1953_3), and outputs the comparison result to the third counter 1955_3. The fourth comparator 1953_4 compares the pixel signal VS with the fourth reference signal RAMP4 (which is input synchronously with the timing of the pixel signal VS input to the fourth comparator 1953_4), and outputs the comparison result to the fourth counter 1955_4.

[0315] In some embodiments, the ramp signal included in the reference signal may include a ramp signal where the voltage level increases or decreases over time. In some embodiments, when the ramp signal included in the first reference signal RAMP1 is a signal with a waveform that decreases at a predetermined slope, the timing sequence in which the value of the signal input to comparator 1953_1 via selector 1951 is the same as the value of the ramp signal of the first reference signal RAMP1 may occur. Furthermore, when the ramp signal included in the second reference signal RAMP2 is a signal with a waveform that decreases at a predetermined slope, the timing sequence in which the value of the signal input to comparator 1953_2 via selector 1951 is the same as the value of the ramp signal of the second reference signal RAMP2 may occur. When the ramp signal included in the third reference signal RAMP3 is a signal with a waveform that decreases at a predetermined slope, the timing sequence in which the value of the signal input to comparator 1953_3 via selector 1951 is the same as the value of the ramp signal of the third reference signal RAMP3 may occur. When the ramp signal included in the fourth reference signal RAMP4 is a signal with a waveform that decreases at a predetermined slope, the timing can occur where the magnitude of the signal input to comparator 1953_4 via selector 1951 is the same as the magnitude of the ramp signal of the fourth reference signal RAMP4. The level of the signals output from comparators 1953_1, 1953_2, 1953_3, and 1953_4 can be shifted synchronously with the timing of the pixel signal VS and the reference signal.

[0316] CDS circuit 1957 can generate an image signal IMS by performing a correlated double sampling (CDS) method on the counting signal received from the corresponding counter 1955. In some embodiments, CDS circuit 1957 may include a first CDS circuit 1957_1 to a fourth CDS circuit 1957_4. CDS circuit 1957_1 can be connected to the output terminal of counter 1955_1 and can generate an image signal IMS by performing a CDS method on the counting signal received from counter 1955_1. CDS circuit 1957_2 can be connected to the output terminal of counter 1955_2 and can generate an image signal IMS by performing a CDS method on the counting signal received from counter 1955_2. CDS circuit 1957_3 can be connected to the output terminal of counter 1955_3 and can generate an image signal IMS by performing a CDS method on the counting signal received from counter 1955_3. The CDS circuit 1957_4 can be connected to the output terminal of the counter 1955_4, and can generate an image signal IMS by performing the CDS method on the counting signal received from the counter 1955_4.

[0317] However, in order to reduce the number of comparators 1953, counters 1955 and CDS circuits 1957 required to read out the pixel signal VS, according to the embodiment, the HCG signal SIG_H, the HCG reset signal (RST_H), the LOCIC signal SIG_LOFIC and the LOCIC reset signal RST_LOFIC can be read out as the same reference signal, and the LCG signal SIG_L and the LOCIC reset signal RST_L, whose slope of the reference signal remains unchanged even when the analog gain increases, can be read out as separate reference signals.

[0318] Figure 20 is an example diagram illustrating the operating timing of the image sensor shown in Figure 19.

[0319] Figure 20 illustrates a scan period used to drive multiple pixels in column-line units. A scan period may sequentially include a Reset period, an Exposure period, and a Readout period.

[0320] Figure 20 illustrates the operation of the image sensor 1900 in the RST-RST-SIG-SIG-SIG-RST (RRSS-SR) readout method.

[0321] The operation of the image sensor shown in Figure 20 will be described with reference to Figure 11A described above.

[0322] Since the waveforms of the reset signal RG1, the first gain control signal DCG1, the second gain control signal DCG2, and the transfer signal TG in the Reset and Exposure periods of Figure 20 are similar to those in Figure 12, the description in Figure 12 can also be applied to Figure 20. In this case, the readout circuit 1950 can use the correlated double sampling (CDS) method to read out the received pixel signal VS. Here, the pixel signal VS can be a signal output from the pixel circuit PX3 via the row line CL within a frame.

[0323] During period 141, the pixel signal VS can be output to the horizontal line CL as the LCG reset signal RST_L. During period 142, the pixel signal VS can be output to the horizontal line CL as the HCG reset signal RST_H. During period 143, the pixel signal VS can be output to the horizontal line CL as the HCG signal SIG_H. During period 144, the pixel signal VS can be output to the horizontal line CL as the LCG signal SIG_L. During period 145, the pixel signal VS can be output to the horizontal line CL as the LOFIC signal SIG_LOFIC. During period 146, the pixel signal VS can be output to the horizontal line CL as the LOFIC reset signal RST_LOFIC.

[0324] During time period 141, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG reset signal RST_L can be output to the first comparator 1953_1 and the second comparator 1953_2. During time periods 142 and 143, the DEMUX selection signal SEL_M is at a high level, and therefore, the HCG reset signal RST_H and the HCG signal SIG_H can be output to the third comparator 1953_3 and the fourth comparator 1953_4. During time period 144, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG signal SIG_L can be output to the first comparator 1953_1 and the second comparator 1953_2. During periods 145 and 146, the DEMUX selection signal SEL_M is at a high level, and therefore, the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC can be output to the third comparator 1953_3 and the fourth comparator 1953_4.

[0325] Simultaneously, the ramp signal generator 1960 can generate first to fourth reference signals RAMP1, RAMP2, RAMP3, and RAMP4 in response to the ramp enable signal R_EN. The reference signals RAMP1, RAMP2, RAMP3, and RAMP4 illustrated in Figure 20 are signals provided to the comparator 1953 in the readout circuit 1950 during the readout period.

[0326] Specifically, the first reference signal RAMP1 is a signal provided to the first comparator 1953_1 during the Readout period, the second reference signal RAMP2 is a signal provided to the second comparator 1953_2 during the Readout period, the third reference signal RAMP3 is a signal provided to the third comparator 1953_3 during the Readout period, and the fourth reference signal RAMP4 is a signal provided to the fourth comparator 1953_4 during the Readout period.

[0327] A first ramp signal R41 having a first period and a fourth ramp signal R44 having a second period greater than the first period can be sequentially provided to the first comparator 1953_1 synchronously with the comparison target signal. Specifically, the first ramp signal R41 can be provided to the first comparator 1953_1 during time period 141, and the fourth ramp signal R44 can be provided to the first comparator 1953_1 during time period 144.

[0328] A first 'ramp signal R41' with a third period and a fourth 'ramp signal R44' with a fourth period greater than the third period can be sequentially provided to the second comparator 1953_2 synchronously with the comparison target signal. Specifically, the first 'ramp signal R41' can be provided to the second comparator 1953_2 during time period 141, and the fourth 'ramp signal R44' can be provided to the second comparator 1953_2 during time period 144.

[0329] A second ramp signal R42 with a first period, a third ramp signal R43 with a second period, a fifth ramp signal R45 with a second period, and a sixth ramp signal R46 with a first period can be sequentially provided to the third comparator 1953_3 synchronously with the comparison target signal. Specifically, the second ramp signal R42 can be provided to the third comparator 1953_3 during time period 142, the third ramp signal R43 can be provided to the third comparator 1953_3 during time period 143, the fifth ramp signal R45 can be provided to the third comparator 1953_3 during time period 145, and the sixth ramp signal R46 can be provided to the third comparator 1953_3 during time period 146.

[0330] A second 'ramp signal R42' with a third cycle, a third 'ramp signal R43' and a fifth 'ramp signal R45' with a fourth cycle, and a sixth 'ramp signal R46' with a third cycle can be sequentially provided to the fourth comparator 1953_4 synchronously with the comparison target signal. Specifically, the second 'ramp signal R42' can be provided to the fourth comparator 1953_4 during time period 142, the third 'ramp signal R43' can be provided to the fourth comparator 1953_4 during time period 143, the fifth 'ramp signal R45' can be provided to the fourth comparator 1953_4 during time period 145, and the sixth 'ramp signal R46' can be provided to the fourth comparator 1953_4 during time period 146.

[0331] However, the embodiments are not limited thereto, and the ramp signal generator 1960 can generate reference signals with different waveforms, including the first ramp signal R41 to the sixth ramp signal R46 and the first 'ramp signal R41' to the sixth 'ramp signal R46'.

[0332] As shown in Figure 20, the first slope s1 of the ramp signal included in the first reference signal RAMP1 can be different from the second slope s2 of the ramp signal included in the second reference signal RAMP2. The absolute value of the slope of the ramp signal in the second reference signal RAMP2 can be adjusted to be less than the absolute value of the slope of the ramp signal in the first reference signal RAMP1. The ratio of the second slope s2 to the first slope s1 can be preset.

[0333] Similarly, the third slope s3 of the ramp signal included in the third reference signal RAMP3 can be different from the fourth slope s4 of the ramp signal included in the fourth reference signal RAMP4. The absolute value of the slope of the ramp signal included in the fourth reference signal RAMP4 can be adjusted to be less than the absolute value of the slope of the ramp signal included in the third reference signal RAMP3. The ratio of the fourth slope s4 to the third slope s3 can be preset. For example, as shown in FIG20, the absolute values ​​of the first slope s1 and the third slope s3 can be twice the absolute values ​​of the second slope s2 and the fourth slope s4, but the embodiment is not limited to this.

[0334] The first comparator 1953_1 compares each of the LCG reset signal RST_L and the LCG signal SIG_L with the first reference signal RAMP1 (which is input synchronously with the timing of the inputs of each signal to the first comparator 1953_1), and outputs a first comparison result. Synchronously with the operation of the first comparator 1953_1, the second comparator 1953_2 compares each of the LCG reset signal RST_L and the LCG signal SIG_L with the second reference signal RAMP2 (which is input synchronously with the timing of the inputs of each signal to the second comparator 1953_2), and outputs a second comparison result.

[0335] The third comparator 1953_3 compares each of the HCG reset signal RST_H, HCG signal SIG_H, LCG signal SIG_L, LOFIC signal SIG_LOFIC, and LOFIC reset signal RST_LOFIC with the third reference signal RAMP3 (which is input synchronously with the timing of the inputs of each signal to the third comparator 1953_3), and outputs the third comparison result. Synchronously with the operation of the third comparator 1953_3, the fourth comparator 1953_4 compares each of the HCG reset signal RST_H, HCG signal SIG_H, LCG signal SIG_L, LOFIC signal SIG_LOFIC, and LOFIC reset signal RST_LOFIC with the fourth reference signal RAMP4 (which is input synchronously with the timing of the inputs of each signal to the fourth comparator 1953_4), and outputs the fourth comparison result.

[0336] Figure 21 is an example diagram illustrating another operating timing of the image sensor shown in Figure 19.

[0337] Figure 21 is a diagram illustrating the operation of the image sensor 1900 in the SIG-RST-RST-RST-SIG-SIG (SR-RRSS) readout method. In this regard, it will be described with reference to Figure 11A.

[0338] Since the waveforms of the reset signal RG1, the first gain control signal DCG1, the second gain control signal DCG2, and the transfer signal TG in the Reset and Exposure periods of Figure 21 are similar to those in Figure 13, the description in Figure 13 can also be applied to Figure 21. In this case, the readout circuit 1950 can use the CDS method to read out the received pixel signal VS. Here, the pixel signal VS can be a signal output from the pixel circuit PX3 via the row line CL within a frame.

[0339] During period 151, the pixel signal VS can be output to the horizontal line CL as the LOFIC signal SIG_LOFIC. During period 152, the pixel signal VS can be output to the horizontal line CL as the LOFIC reset signal RST_LOFIC. During period 153, the pixel signal VS can be output to the horizontal line CL as the LCG reset signal RST_L. During period 154, the pixel signal VS can be output to the horizontal line CL as the HCG reset signal RST_H. During period 155, the pixel signal VS can be output to the horizontal line CL as the HCG signal SIG_H. During period 156, the pixel signal VS can be output to the horizontal line CL as the LCG signal SIG_L.

[0340] During periods 151 and 152, the DEMUX selection signal SEL_M is at a high level, and therefore, the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC can be output to the third comparator 1953_3 and the fourth comparator 1953_4. During period 153, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG reset signal RST_L can be output to the first comparator 1953_1 and the second comparator 1953_2. During periods 154 and 155, the DEMUX selection signal SEL_M is at a high level, and therefore, the HCG reset signal RST_H and the HCG signal SIG_H can be output to the third comparator 1953_3 and the fourth comparator 1953_4. Finally, during time period 156, the DEMUX selection signal SEL_M is at a low level, and therefore, the LCG signal SIG_L can be output to the first comparator 1953_1 and the second comparator 1953_2.

[0341] Meanwhile, the ramp signal generator 1960 can generate first to fourth reference signals RAMP1, RAMP2, RAMP3 and RAMP4 in response to the ramp enable signal R_EN.

[0342] The first reference signal RAMP1 is provided to the first comparator 1953_1 during the Readout period, the second reference signal RAMP2 is provided to the second comparator 1953_2 during the Readout period, the third reference signal RAMP3 is provided to the third comparator 1953_3 during the Readout period, and the fourth reference signal RAMP4 is provided to the fourth comparator 1953_4 during the Readout period.

[0343] A third ramp signal R53 having a first period and a sixth ramp signal R56 having a second period greater than the first period can be sequentially provided to the first comparator 1953_1 synchronously with the comparison target signal. Specifically, the third ramp signal R53 can be provided to the first comparator 1953_1 within a time period 153, and the sixth ramp signal R56 can be provided to the first comparator 1953_1 within a time period 156.

[0344] A third 'ramp signal R53' with a third period and a sixth 'ramp signal R56' with a fourth period greater than the third period can be sequentially provided to the second comparator 1953_2 synchronously with the comparison target signal. Specifically, the third 'ramp signal R53' can be provided to the second comparator 1953_2 within a time period 153, and the sixth 'ramp signal R56' can be provided to the second comparator 1953_2 within a time period 156.

[0345] A first ramp signal R51 with a second period, a second ramp signal R52 with a first period, a fourth ramp signal R54 with a second period, and a fifth ramp signal R55 with a second period can be sequentially provided to the third comparator 1953_2 synchronously with the comparison target signal. Specifically, the first ramp signal R51 can be provided to the third comparator 1953_3 during time period 151, the second ramp signal R52 can be provided to the third comparator 1953_3 during time period 152, the fourth ramp signal R54 can be provided to the third comparator 1953_3 during time period 154, and the fifth ramp signal R55 can be provided to the third comparator 1953_3 during time period 155.

[0346] A first 'ramp signal R51' with a fourth cycle, a second 'ramp signal R52' with a second cycle, a fourth 'ramp signal R54' with a fourth cycle, and a fifth 'ramp signal R55' with a fourth cycle can be sequentially provided to the fourth comparator 1953_4 synchronously with the comparison target signal. Specifically, the first 'ramp signal R51' can be provided to the fourth comparator 1953_4 during time period 151, the second 'ramp signal R52' can be provided to the fourth comparator 1953_4 during time period 152, the fourth 'ramp signal R54' can be provided to the fourth comparator 1953_4 during time period 154, and the fifth 'ramp signal R55' can be provided to the fourth comparator 1953_4 during time period 155.

[0347] However, the embodiments are not limited thereto, and the ramp signal generator 1960 can generate reference signals with different waveforms, including the first ramp signal R51 to the sixth ramp signal R56 and the first 'ramp signal R51' to the sixth 'ramp signal R56'.

[0348] The first slope s1 of the ramp signal included in the first reference signal RAMP1 may be different from the second slope s2 of the ramp signal included in the second reference signal RAMP2. The absolute value of the slope of the ramp signal included in the second reference signal RAMP2 may be adjusted to be less than the absolute value of the slope of the ramp signal included in the first reference signal RAMP1. The ratio of the second slope s2 to the first slope s1 may be preset.

[0349] Similarly, the third slope s3 of the ramp signal in the third reference signal RAMP3 can be different from the fourth slope s4 of the ramp signal in the fourth reference signal RAMP4. The absolute value of the slope of the ramp signal in the fourth reference signal RAMP4 can be adjusted to be less than the absolute value of the slope of the ramp signal in the third reference signal RAMP3. The ratio of the fourth slope s4 to the third slope s3 can be preset. For example, as shown in Figure 13, the absolute values ​​of the first slope s1 and the third slope s3 can be twice the absolute values ​​of the second slope s2 and the fourth slope s4, but the embodiment is not limited to this.

[0350] The first comparator 1953_1 compares each of the LCG reset signal RST_L and the LCG signal SIG_L with the first reference signal RAMP1 (which is input synchronously with the timing of the inputs of each signal to the first comparator 1953_1), and outputs a first comparison result. Synchronously with the operation of the first comparator 1953_1, the second comparator 1953_2 compares each of the LCG reset signal RST_L and the LCG signal SIG_L with the second reference signal RAMP2 (which is input synchronously with the timing of the inputs of each signal to the second comparator 1953_2), and outputs a second comparison result.

[0351] The third comparator 1953_3 compares each of the HCG reset signal RST_H, HCG signal SIG_H, LCG signal SIG_L, LOFIC signal SIG_LOFIC, and LOFIC reset signal RST_LOFIC with the third reference signal RAMP3 (which is input synchronously with the timing of the inputs of each signal to the third comparator 1953_3), and outputs the third comparison result. Synchronously with the operation of the third comparator 1953_3, the fourth comparator 1953_4 compares each of the HCG reset signal RST_H, HCG signal SIG_H, LCG signal SIG_L, LOFIC signal SIG_LOFIC, and LOFIC reset signal RST_LOFIC with the fourth reference signal RAMP4 (which is input synchronously with the timing of the inputs of each signal to the fourth comparator 1953_4), and outputs the fourth comparison result.

[0352] Figures 22 and 23 are example graphs illustrating the signal-to-noise ratio according to one embodiment. Specifically, Figures 22 and 23 illustrate the signal-to-noise ratio in decibels (dB) of the signal obtained by synthesizing the HCG image signal, LCG image signal, and LOFIC image signal using the readout circuit 1950 shown in Figure 19. In this case, it is assumed that the ratio of the absolute value of the slope s1 of the ramp signal in the first reference signal RAMP1 of Figure 7 to the absolute value of the slope s2 of the ramp signal in the second reference signal RAMP2 is set to 2:1.

[0353] Figure 22 illustrates the SNR of the signal obtained by synthesizing the HCG image signal, LCG image signal, and LOFIC image signal when the analog gain of both the first curve 2201 and the second curve 2203 is twice the predetermined analog gain. The first curve 2201 is the SNR curve when the pixel signal VS is read out without applying the DSG method, and the second curve 2203 is the SNR curve when the pixel signal VS is read out while applying the DSG method. That is, the second curve 2203 illustrates the SNR of the synthesized signal when the pixel signal VS is read out by applying the DSG method using double analog gain (i.e., four times the predetermined analog gain).

[0354] As shown in Figure 22, the SNR decrease d221 between the LCG image signal and the LOFIC image signal in the first curve 2201 is greater than the SNR decrease d223 between the LCG image signal and the LOFIC image signal in the second curve 2203. Similarly, the dynamic range DR3 in the first curve 2203 is wider than the dynamic range DR1 in the first curve 2201.

[0355] Figure 23 illustrates the SNR of the signal obtained by synthesizing the HCG, LCG, and LOFIC image signals when the analog gain of both the third curve 2301 and the fourth curve 2303 is four times the predetermined analog gain. The third curve 2301 shows the SNR curve when the pixel signal VS is read out without applying the DSG method, and the fourth curve 2303 shows the SNR curve when the pixel signal VS is read out while applying the DSG method. That is, the fourth curve 2303 shows the SNR of the synthesized signal when the pixel signal VS is read out using the DSG method with double analog gain (i.e., eight times the predetermined analog gain).

[0356] As shown in Figure 23, the SNR decrease d231 between the LCG image signal and the LOFIC image signal in the third curve 2301 is greater than the SNR decrease d223 between the LCG image signal and the LOFIC image signal in the fourth curve 2303.

[0357] However, as analog gain increases, QN decreases, and therefore, the SNR curve tends to increase under low light conditions. Based on this, applying DSG has a greater impact on reducing SNR drop when analog gain is low, but as analog gain increases, the ratio of QN to overall noise decreases, and therefore, the SNR reduction improvement effect that can be obtained by applying DSG can also be reduced.

[0358] Figures 24 and 25 are example graphs illustrating the signal-to-noise ratio according to one embodiment. Specifically, Figures 24 and 25 illustrate the signal-to-noise ratio in decibels (dB) of the signal obtained by synthesizing the HCG image signal, LCG image signal, and LOFIC image signal using the readout circuit 1950 shown in Figure 19. In this case, it is assumed that the ratio of the absolute value of the slope s1 of the ramp signal in the first reference signal RAMP1 of Figure 7 to the absolute value of the slope s2 of the ramp signal in the second reference signal RAMP2 is set to 2:1.

[0359] Figure 24 illustrates a first curve 2401 and a second curve 2403. The first curve 2401 shows the SNR of the signal obtained by synthesizing the HCG image signal, LCG image signal, and LOFIC image signal when the analog gain of the HCG image signal, LCG image signal, and LOFIC image signal is twice the predetermined analog gain. The second curve 2403 shows the SNR of the synthesized signal when the pixel signal VS is read out by applying the DSG method using twice the analog gain of the HCG image signal and LOFIC image signal (i.e., four times the predetermined analog gain), without applying the DSG method to the LCG image signal.

[0360] As shown in Figure 24, the SNR decrease d241 between the LCG image signal and the LOFIC image signal in the first curve 2401 is greater than the SNR decrease d243 between the LCG image signal and the LOFIC image signal in the second curve 2403.

[0361] Figure 25 illustrates the first curve 2401 and the second curve 2503. The first curve 2401 is a graph showing the SNR of the signal obtained by synthesizing the HCG image signal, LCG image signal, and LOFIC image signal when the analog gain of the HCG image signal, LCG image signal, and LOFIC image signal is four times the predetermined analog gain. The second curve 2503 is a graph showing the SNR of the synthesized signal when the pixel signal VS is read out by applying the DSG method using twice the analog gain of the HCG image signal and LOFIC image signal (i.e., eight times the predetermined analog gain), and when the pixel signal VS is read out without applying the DSG method to the LCG image signal.

[0362] Similarly, as shown in Figure 25, the SNR decrease d251 between the LCG image signal and the LOFIC image signal in the first curve 2501 is less than the SNR decrease d253 between the LCG image signal and the LOFIC image signal in the second curve 2503.

[0363] Figure 26 is an example block diagram illustrating a pixel array and readout circuit according to another embodiment.

[0364] Referring to FIG26, an image sensor 2600 according to another embodiment may include a pixel array 2640 and a readout circuit 2650.

[0365] The pixel array 2640 may contain multiple pixels PX. Each pixel PX can be selected by the transfer signal TG and the selection signal SEL1 to output a pixel signal VS.

[0366] Referring to Figure 26, pixel array 2640 may include multiple pixels PXa, PXb, and PXc. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding transfer signal from transfer signals TGi, TGi+1, and TGi+2, and a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2 to output a pixel signal VS. Here, it is assumed that each of the multiple pixels PXa, PXb, and PXc includes a sub-pixel.

[0367] The readout circuit 2650 may include a selector 2640, a comparator 2651, a counter 2653, and a CDS circuit 2655 connected to each row line CL of the pixel array 2657.

[0368] Selector 2651 may be implemented as, for example, a multiplexer, but is not limited thereto. Selector 2651 may correspond to a corresponding row line CL and may receive a pixel signal VS from the row line CL. Selector 2651 may receive a DEMUX selection signal SEL_M from controller 2610 and output the pixel signal VS to comparator 2653 based on the DEMUX selection signal SEL_M. According to one embodiment, selector 2651 may include three output terminals. Selector 2651 may output the pixel signal VS to any one of the three output terminals based on the DEMUX selection signal SEL_M.

[0369] The ramp signal generator 2660 can generate multiple reference signals RAMP1, RAMP2, and RAMP3 in response to the ramp enable signal R_EN input from the controller 2610. The ramp signal among the reference signals can be a signal in which the voltage level increases or decreases over time.

[0370] Comparator 2653 can compare the pixel signal VS with one of a plurality of reference signals RAMP1, RAMP2 and RAMP3.

[0371] In one embodiment, comparator 2653 may include first comparators 2653_1 through third comparators 2653_3. One of the two input terminals of the first comparator 2653_1 may be connected to one of the three output terminals of the selector 2651, and the other of the two input terminals may be connected to the ramp signal generator 2660. One of the two input terminals of the second comparator 2653_2 may be connected to one of the three output terminals of the selector 2651, and the other of the two input terminals may be connected to the ramp signal generator 2660. One of the two input terminals of the third comparator 2653_3 may be connected to one of the three output terminals of the selector 2651, and the other of the two input terminals may be connected to the ramp signal generator 2660.

[0372] Counter 2655 counts how long a specific level of a signal output from the corresponding comparator 2653 has been maintained. Specifically, counter 2655 receives a clock signal from a timing generator (120 in FIG. 1). Counter 2655 can use the rising or falling edge of the clock signal to count how long a specific level of a signal received from the corresponding comparator 2653 has been maintained. In one embodiment, counter 2655 may include a first counter 2655_1 through a third counter 2655_3. Counter 2655_1 may be connected to the output terminal of comparator 2653_1. Counter 2655_2 may be connected to the output terminal of comparator 2653_2. Counter 2655_3 may be connected to the output terminal of comparator 2653_3. Counter 2655 may include an up / down counter or a bit-by-bit counter.

[0373] In general, the first comparator 2653_1 compares the pixel signal VS with the first reference signal RAMP1 (which is input synchronously with the pixel signal VS to the first comparator 2653_1 in timing), and outputs the result to the counter 2655_1. The second comparator 2653_2 compares the pixel signal VS with the second reference signal RAMP2 (which is input synchronously with the pixel signal VS to the second comparator 2653_2 in timing), and outputs the result to the counter 2655_2. The third comparator 2653_3 compares the pixel signal VS with the third reference signal RAMP3 (which is input synchronously with the pixel signal VS to the third comparator 2653_3 in timing), and outputs the result to the counter 2655_3.

[0374] Ramp signal generator 2660 can generate reference signals RAMP1, RAMP2, and RAMP3 in response to a ramp enable signal R_EN input from controller 2610. The ramp signal in each of the reference signals RAMP1, RAMP2, and RAMP3 can be a signal in which the voltage level increases or decreases over time. In some embodiments, when the ramp signal included in reference signal RAMP1 has a waveform that decreases with a predetermined slope, a timing sequence may occur where the magnitude of the signal input to comparator 2653_1 via selector 2651 is the same as the magnitude of the ramp signal in reference signal RAMP1. Furthermore, in some embodiments, when the ramp signal included in reference signal RAMP2 has a waveform that decreases with a predetermined slope, a timing sequence may occur where the magnitude of the signal input to comparator 2653_2 via selector 2651 is the same as the magnitude of the ramp signal in reference signal RAMP2. In some embodiments, when the ramp signal included in the reference signal RAMP3 has a waveform that decreases with a predetermined slope, the timing may occur where the magnitude of the signal input to comparator 2653_3 via selector 2651 is the same as the magnitude of the ramp signal of the reference signal RAMP3. The magnitude of the signal input to comparator 2653_1 and the magnitude of the ramp signal of the reference signal RAMP1 are synchronized at the same timing, the magnitude of the signal input to comparator 2653_2 and the magnitude of the ramp signal of the reference signal RAMP2 are synchronized at the same timing, and the magnitude of the signal input to comparator 2653_3 and the magnitude of the ramp signal of the reference signal RAMP3 are synchronized at the same timing. Therefore, the level of the signals output from comparators 2653_1, 2653_2, and 2653_3 can be shifted.

[0375] The CDS circuit 2657 can generate an image signal IMS by performing a correlated double sampling (CDS) method on the counting signal received from the corresponding counter 2655. In some embodiments, the CDS circuit 2657 may include a first CDS circuit 2657_1 to a third CDS circuit 2657_3. The CDS circuit 2657_1 can be connected to the output terminal of the counter 2655_1 and can perform the CDS method on the output of the pixel signal VS received from the counter 2655_1 to generate the image signal IMS. The CDS circuit 2657_2 can be connected to the output terminal of the counter 2655_2 and can perform the CDS method on the output of the pixel signal VS received from the counter 2655_2 to generate the image signal IMS. The CDS circuit 2657_3 can be connected to the output terminal of the counter 2655_3 and can perform the CDS method on the output of the pixel signal VS received from the counter 2655_3 to generate the image signal IMS.

[0376] However, in order to reduce the number of comparators 2653, counters 2655 and CDS circuits 2657 required to read out the pixel signal VS, the HCG signal SIG_H, HCG reset signal (RST_H), LOFIC signal SIG_LOFIC and LOFIC reset signal RST_LOFIC can be read out as a reference signal, and the LCG signal SIG_L and LCG reset signal RST_L, whose slope remains unchanged even when the analog gain increases, can be read out as individual reference signals.

[0377] Figure 27 is an example diagram illustrating the operating timing of the image sensor shown in Figure 26.

[0378] Figure 27 illustrates the operation of the image sensor 2600 in the RST-RST-SIG-SIG-SIG-RST (RRSS-SR) readout method.

[0379] Since the waveforms of the reset signal RG1, the first gain control signal DCG1, the second gain control signal DCG2, the transfer signal TG, and the DEMUX selection signal SEL_M in the Reset and Exposure periods of Figure 27 are similar to those in Figure 20, the description in Figure 20 can also be applied to Figure 27. In this case, the readout circuit 2650 can use the correlated double sampling (CDS) method to read out the received pixel signal VS. Here, the pixel signal VS can be a signal output from the pixel circuit PX3 via the row line CL within a frame.

[0380] During period 161, the pixel signal VS can be output to the horizontal line CL as the LCG reset signal RST_L. During period 162, the pixel signal VS can be output to the horizontal line CL as the HCG reset signal RST_H. During period 163, the pixel signal VS can be output to the horizontal line CL as the HCG signal SIG_H. During period 164, the pixel signal VS can be output to the horizontal line CL as the LCG signal SIG_L. During period 165, the pixel signal VS can be output to the horizontal line CL as the LOFIC signal SIG_LOFIC. During period 166, the pixel signal VS can be output to the horizontal line CL as the LOFIC reset signal RST_LOFIC.

[0381] During period 161, the DEMUX selection signal SEL_M is at a low level, therefore the LCG reset signal RST_L can be output to the first comparator 1953_1. During periods 162 and 163, the DEMUX selection signal SEL_M is at a high level, therefore the HCG reset signal RST_H and the HCG signal SIG_H can be output to the second comparator 1953_2 and the third comparator 1953_3. During period 164, the DEMUX selection signal SEL_M is at a low level, therefore the LCG signal SIG_L can be output to the first comparator 1953_1. During periods 165 and 166, the DEMUX selection signal SEL_M is at a high level, therefore the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC can be output to the second comparator 1953_2 and the third comparator 1953_3.

[0382] Simultaneously, the ramp signal generator 2660 can generate three reference signals RAMP1, RAMP2, and RAMP3 in response to the ramp enable signal R_EN during the Readout period. The reference signals RAMP1, RAMP2, and RAMP3 illustrated in Figure 27 are signals provided to the comparator 2653 during the Readout period.

[0383] Specifically, the first reference signal RAMP1 is a signal provided to the first comparator 2653_1 during the Readout period, the second reference signal RAMP2 is a signal provided to the second comparator 2653_2 during the Readout period, and the third reference signal RAMP3 is a signal provided to the third comparator during the Readout period.

[0384] A first ramp signal R61 having a first period and a fourth ramp signal R64 having a second period greater than the first period can be sequentially provided to the first comparator 2653_1 synchronously with the comparison target signal. Specifically, the first ramp signal R61 can be provided to the first comparator 1953_1 within a time period 161, and the fourth ramp signal R64 can be provided to the first comparator 1953_1 within a time period 164.

[0385] A second ramp signal R62 with a first period, a third ramp signal R63 with a second period, a fifth ramp signal R65 with a second period, and a sixth ramp signal R66 with a first period can be sequentially provided to the second comparator 2653_2 synchronously with the comparison target signal. Specifically, the second ramp signal R62 can be provided to the second comparator 1953_2 within a time period 162, the third ramp signal R63 can be provided to the second comparator 1953_2 within a time period 163, the fifth ramp signal R65 can be provided to the second comparator 1953_2 within a time period 165, and the sixth ramp signal R66 can be provided to the second comparator 1953_2 within a time period 166.

[0386] A second 'ramp signal R62' with a third period, a third 'ramp signal R63' and a fifth 'ramp signal R65' with a fourth period greater than the third period, and a sixth 'ramp signal R66' with a third period can be sequentially provided to the third comparator 2653_3 synchronously with the comparison target signal. Specifically, the second 'ramp signal R62' can be provided to the third comparator 1953_3 within time period 162, the third 'ramp signal R63' can be provided to the third comparator 1953_3 within time period 163, the fifth 'ramp signal R65' can be provided to the third comparator 1953_3 within time period 165, and the sixth 'ramp signal R66' can be provided to the third comparator 1953_3 within time period 166.

[0387] However, the embodiments are not limited thereto, and the ramp signal generator 2660 can generate reference signals RAMP containing first ramp signals R61 to sixth ramp signals R66 and first 'ramp signals R61' to sixth 'ramp signals R66' with different waveforms.

[0388] As shown in Figure 27, the second slope s2 of the ramp signal included in the second reference signal RAMP2 may be different from the third slope s3 of the ramp signal included in the third reference signal RAMP3. The absolute value of the slope of the ramp signal included in the second reference signal RAMP3 may be adjusted to be less than the absolute value of the slopes of the ramp signals included in the first reference signal RAMP1 and the second reference signal RAMP2. The ratio of the third slope s3 to the second slope s2 may be preset. For example, as shown in Figure 27, the absolute values ​​of the first slope s1 and the second slope s2 may be twice the second slope s2, but the embodiment is not limited to this.

[0389] The first comparator 2653_1 compares each of the LCG reset signal RST_L and the LCG signal SIG_L with the first reference signal RAMP1 (which is input synchronously with the timing of each signal input to the first comparator 2653_1), and outputs a first comparison result. The second comparator 2653_2 compares each of the HCG reset signal RST_H, the HCG signal SIG_H, the LOFIC signal SIG_LOFIC, and the LOFIC reset signal RST_LOFIC with the second reference signal RAMP2 (which is input synchronously with the timing of each signal input to the second comparator 2653_2), and outputs a second comparison result. Furthermore, the third comparator 2653_3 compares each of the HCG reset signal RST_H, the HCG signal SIG_H, the LOFIC signal SIG_LOFIC, and the LOFIC reset signal RST_LOFIC with the third reference signal RAMP3 (which is input synchronously with the timing of each signal input to the third comparator 2653_3), and outputs a third comparison result.

[0390] Figure 28 is an example diagram illustrating another operating timing of the image sensor shown in Figure 26.

[0391] Figure 28 illustrates the operation of the image sensor 2600 in the SIG-RST-RST-RST-SIG-SIG (SR-RRSS) readout method. Since the waveforms of the reset signal RG1, the first gain control signal DCG1, the second gain control signal DCG2, the transfer signal TG, and the DEMUX selection signal SEL_M in the Reset and Exposure periods of Figure 28 are similar to those in Figure 21, the description in Figure 21 can also be applied to Figure 28.

[0392] During period 171, the pixel signal VS can be output to the horizontal line CL as the LOFIC signal SIG_LOFIC. During period 172, the pixel signal VS can be output to the horizontal line CL as the LOFIC reset signal RST_LOFIC. During period 173, the pixel signal VS can be output to the horizontal line CL as the LCG reset signal RST_L. During period 174, the pixel signal VS can be output to the horizontal line CL as the HCG reset signal RST_H. During period 175, the pixel signal VS can be output to the horizontal line CL as the HCG signal SIG_H. During period 176, the pixel signal VS can be output to the horizontal line CL as the LCG signal SIG_L.

[0393] During periods 171 and 172, the DEMUX selection signal SEL_M is at a high level, therefore, the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC can be output to the second comparator 1953_2 and the third comparator 1953_3. During period 173, the DEMUX selection signal SEL_M is at a low level, therefore, the LCG reset signal RST_L can be output to the first comparator 1953_1. During periods 174 and 175, the DEMUX selection signal SEL_M is at a high level, therefore, the HCG reset signal RST_H and the HCG signal SIG_H can be output to the second comparator 1953_2 and the third comparator 1953_3. Finally, during period 176, the DEMUX selection signal SEL_M is at a low level, therefore, the LCG signal SIG_L can be output to the first comparator 1953_1.

[0394] Simultaneously, the ramp signal generator 2660 can generate first to third reference signals RAMP1, RAMP2, and RAMP3 in response to the ramp enable signal R_EN during the Readout period. The reference signals RAMP1, RAMP2, and RAMP3 illustrated in Figure 28 are signals provided to the comparator 2653 in the readout circuit 2650 during the Readout period.

[0395] The first reference signal RAMP1 is a signal provided to the first comparator 2653_1 during the Readout period, the second reference signal RAMP2 is a signal provided to the second comparator 2653_2 during the Readout period, and the third reference signal RAMP3 is a signal provided to the third comparator 2653_3 during the Readout period.

[0396] A third ramp signal R73 with a first period and a sixth ramp signal R76 with a second period greater than the first period can be sequentially provided to the first comparator 2653_1 in sync with the comparison target signal. Specifically, the third ramp signal R73 can be provided to the first comparator 1953_1 within time period 173, and the sixth ramp signal R76 can be provided to the first comparator 1953_1 within time period 176.

[0397] A first ramp signal R71 with a second period, a second ramp signal R72 with a first period, a fourth ramp signal R74 with a first period, and a fifth ramp signal R75 can be sequentially provided to the second comparator 2653_2 synchronously with the comparison target signal. Specifically, the first ramp signal R71 can be provided to the second comparator 1953_2 during time period 171, the second ramp signal R72 can be provided to the second comparator 1953_2 during time period 172, the fourth ramp signal R74 can be provided to the second comparator 1953_2 during time period 174, and the fifth ramp signal R75 can be provided to the second comparator 1953_2 during time period 175.

[0398] Furthermore, a first 'ramp signal R71' with a third period, a second 'ramp signal R72' and a fourth 'ramp signal R74' with a fourth period greater than the third period, and a fifth 'ramp signal R75' with a third period can be sequentially provided to the third comparator 2653_3 synchronously with the comparison target signal. Specifically, the first 'ramp signal R71' can be provided to the third comparator 1953_3 during time period 171, the second 'ramp signal R72' can be provided to the third comparator 1953_3 during time period 172, the fourth 'ramp signal R74' can be provided to the third comparator 1953_3 during time period 174, and the fifth 'ramp signal R75' can be provided to the third comparator 1953_3 during time period 175.

[0399] However, the embodiments are not limited thereto, and the ramp signal generator 2660 can generate reference signals RAMP containing first ramp signals R71 to sixth ramp signals R76 and first 'ramp signals R71' to sixth 'ramp signals R76' with different waveforms.

[0400] The first slope s1 of the ramp signal included in the first reference signal RAMP1 can be the same as the second slope s2 of the ramp signal included in the second reference signal RAMP2. However, the second slope s2 of the ramp signal included in the second reference signal RAMP2 can be different from the third slope s3 of the ramp signal included in the third reference signal RAMP3. The absolute value of the slope of the ramp signal included in the third reference signal RAMP3 can be adjusted to be less than the absolute value of the slopes of the ramp signals included in the first reference signal RAMP1 and the second reference signal RAMP2. The ratio of the third slope s3 to the second slope s2 can be preset. For example, as shown in FIG28, the absolute value of the first slope s1 and the second slope s2 can be twice the second slope s2, but the embodiment is not limited to this.

[0401] The first comparator 2653_1 compares each of the LCG reset signal RST_L and the LCG signal SIG_L with the first reference signal RAMP1 (which is input synchronously with the timing of each signal input to the first comparator 2653_1), and outputs a first comparison result. The second comparator 2653_2 compares each of the LOFIC signal SIG_LOFIC, the LOFIC reset signal RST_LOFIC, the HCG reset signal RST_H, and the HCG signal SIG_H with the second reference signal RAMP2 (which is input synchronously with the timing of each signal input to the second comparator 2653_2), and outputs a second comparison result. Synchronously with the second comparator 2653_2, the third comparator 2653_3 can compare each of the LOFIC signal SIG_LOFIC, the LOFIC reset signal RST_LOFIC, the HCG reset signal RST_H, and the HCG signal SIG_H with the third reference signal RAMP3 (which is input synchronously with the timing of each signal input to the third comparator 2653_3), and output the third comparison result.

[0402] Referring to Figures 27 and 28, since the DSG method is not applied to the LCG signal SIG_L and the LCG reset signal RST_L, the ramp signal generator 2660 can use a reference signal containing a ramp signal with a slope to read out the LCG signal SIG_L and the LCG reset signal RST_L. Furthermore, since the DSG method is applied to the HCG signal SIG_H, the HCG reset signal RST_H, the LOFIC signal SIG_LOFIC, and the LOFIC reset signal RST_LOFIC, the ramp signal generator 2660 can use two reference signals containing ramp signals with different slopes to read out the HCG signal SIG_H, the HCG reset signal RST_H, the LOFIC signal SIG_LOFIC, and the LOFIC reset signal RST_LOFIC. Simultaneously, the ramp signal generator 2660 uses variable analog gain for the HCG signal and the LOFIC signal, while using fixed analog gain when reading out the LCG signal, thereby reducing the SNR drop of the image signal.

[0403] Figure 29 is an example block diagram illustrating a pixel array and readout circuit according to another embodiment.

[0404] Referring to Figure 29, pixel array 2940 may include multiple pixels PXa, PXb, and PXc. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding transfer signal from transfer signals TTi, TTi+1, and TTi+2, and a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2 to output pixel signal VS. Here, it is assumed that each of the multiple pixels PXa, PXb, and PXc includes a sub-pixel.

[0405] The readout circuit 2950 may include a selector 2940, a comparator 2951, a counter 2953, and a CDS circuit 2955 connected to each row line CL of the pixel array 2957.

[0406] Selector 2951 may be implemented as, for example, a demultiplexer, but is not limited thereto. Selector 2951 may be connected to a corresponding row line CL and may receive a pixel signal VS from the connected row line CL. Selector 2951 may receive DEMUX selection signals SEL_M1 and SEL_M2 from controller 2910 and output the pixel signal VS to comparator 2953 based on DEMUX selection signals SEL_M1 and SEL_M2. In one embodiment, selector 2951 may include two output terminals. Selector 2951 may output the pixel signal VS to either of the two output terminals based on DEMUX selection signals SEL_M1 and SEL_M2.

[0407] Comparator 2953 compares the pixel signal VS with each of the reference signals RAMP1 and RAMP2, and outputs the result to counter 2955. In one embodiment, comparator 2953 may include a first comparator 2953_1 and a second comparator 2953_2. Each of the first comparator 2953_1 and the second comparator 2953_2 may have two input terminals and one output terminal. One of the two input terminals of the first comparator 2953_1 may be connected to one of the two output terminals of the selector 2951, and the other of the two input terminals may be connected to the ramp signal generator 2960. The output terminal of the first comparator 2953_1 may be connected to counter 2955_1. One of the two input terminals of the second comparator 2953_2 may be connected to the other of the two output terminals of the selector 2951, and the other of the two input terminals may be connected to the ramp signal generator 2960. The output terminal of the second comparator 2953_2 may be connected to counter 2955_2.

[0408] Ramp signal generator 2960 can generate reference signals RAMP1 and RAMP2 in response to a ramp enable signal R_EN input from controller 2910. In some embodiments, reference signals RAMP1 and RAMP2 may include ramp signals whose voltage levels increase or decrease over time. In some embodiments, when the ramp signal included in reference signal RAMP1 is a signal with a waveform that decreases at a predetermined slope, the timing when the magnitude of the signal input to comparator 2951_1 via selector 2953 is the same as the magnitude of the ramp signal of reference signal RAMP1 can occur. Furthermore, the timing point when the magnitude of the signal input to comparator 2953_2 via selector 2951 is equal to the magnitude of the ramp signal of reference signal RAMP2 can occur. Since the magnitudes of the signals input to comparators 2953_1 and 2953_2 and the magnitude of the ramp signal of reference signal RAMP1 are synchronized at the same timing, the level of the signal output from comparator 2953_1 can be shifted. Furthermore, since the magnitude of the signal input to comparator 2953_2 and the magnitude of the ramp signal of reference signal RAMP2 are synchronized at the same time, the level of the signal output from comparator 2953_2 can be shifted.

[0409] Counter 2955 counts the duration for which a specific level of the signal output from comparator 2953 is maintained. Specifically, counter 2955 receives a clock signal from timing generator 2920. Counter 2955 can use the rising or falling edge of the clock signal to count the duration for which a specific level of the signal received from comparator 2953 is maintained. In one embodiment, counter 2955 may include a first counter 2955_1 and a second counter 2955_2. Counter 2955_1 may be connected to the output terminal of comparator 2953_1. Similarly, counter 2955_2 may be connected to the output terminal of comparator 2953_2. Counter 2955_1 counts the time corresponding to the high level of logic level "1" output from comparator 2953_1. Counter 2955_2 counts the time corresponding to the high level of logic level "1" output from comparator 2953_2. Counters 2955_1 and 2955_2 may include up / down counters or bit-by-bit counters.

[0410] The CDS circuit 2957 can generate an image signal by performing a correlated double sampling (CDS) method on the counting signal received from the counter 2955. In one embodiment, the CDS circuit 2957 may include CDS circuit 2957_1 and CDS circuit 2957_2. CDS circuit 2957_1 can be connected to the output terminal of the counter 2955_1 to perform the CDS method on the counting signal received from the counter 2955_1. Furthermore, CDS circuit 2957_2 can be connected to the output terminal of the counter 2955_2 to perform the CDS method on the counting signal received from the counter 2955_2.

[0411] Figure 30 is an example diagram illustrating the operating timing of the image sensor shown in Figure 29.

[0412] Figure 30 illustrates the operation of the image sensor 2900 in the RST-RST-SIG-SIG-SIG-RST (RRSS-SR) readout method.

[0413] Since the waveforms of the reset signal RG1, the first gain control signal DCG1, the second gain control signal DCG2, and the transfer signal TG in the Reset and Exposure periods of Figure 20 are similar to those in Figure 20, the description in Figure 12 can also be applied to Figure 30.

[0414] During period 201, the pixel signal VS can be output to the horizontal line CL as the LCG reset signal RST_L. During period 202, the pixel signal VS can be output to the horizontal line CL as the HCG reset signal RST_H. During period 203, the pixel signal VS can be output to the horizontal line CL as the HCG signal SIG_H. During period 204, the pixel signal VS can be output to the horizontal line CL as the LCG signal SIG_L. During period 205, the pixel signal VS can be output to the horizontal line CL as the LOFIC signal SIG_LOFIC. During period 206, the pixel signal VS can be output to the horizontal line CL as the LOFIC reset signal RST_LOFIC.

[0415] During time period 201, the DEMUX selection signal SEL_M1 is at a low level, and the DEMUX selection signal SEL_M2 is at a high level. Therefore, the LCG reset signal RST_L can be output to the second comparator 2953_2. During time periods 202 and 203, the DEMUX selection signal SEL_M1 is at a high level, and the DEMUX selection signal SEL_M2 is at a low level. Therefore, the HCG reset signal RST_H and the HCG signal SIG_H can be output to the first comparator 2953_1. During time period 204, the DEMUX selection signal SEL_M1 is at a low level, and the DEMUX selection signal SEL_M2 is at a high level. Therefore, the LCG signal SIG_L can be output to the second comparator 2953_2. During time period 205 and time period 206, the DEMUX selection signal SEL_M1 and the DEMUX selection signal SEL_M2 are at high level, and therefore, the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC can be output to the first comparator 2953_1 and the second comparator 2953_2.

[0416] Simultaneously, the ramp signal generator 2960 can generate two reference signals RAMP1 and RAMP2 in response to the ramp enable signal R_EN during the Readout period. The reference signals RAMP1 and RAMP2 shown in Figure 31 are signals provided to the comparator 2953 in the readout circuit 2950 during the Readout period.

[0417] The first reference signal RAMP1 is provided to the first comparator 2953_1 during the Readout period, and the second reference signal RAMP2 is provided to the second comparator 2953_2 during the Readout period. A second ramp signal R102 with a first period, a third ramp signal R103 and a fifth ramp signal R105 with a second period, and a sixth ramp signal R106 with a first period can be sequentially provided to the second comparator 2953_2 synchronously with the comparison target signal. Specifically, the second ramp signal R102 can be provided to the first comparator 2953_1 during period 202, the third ramp signal R103 can be provided to the first comparator 2953_1 during period 203, the fifth ramp signal R105 can be provided to the first comparator 2953_1 during period 205, and the sixth ramp signal R106 can be provided to the first comparator 2953_1 during period 206.

[0418] A first ramp signal R101 with a first period, a fourth ramp signal R104 and a fifth ramp signal R105 with a second period greater than the first period, a fifth ramp signal R105 with a second period, and a sixth ramp signal R106 with a first period can be sequentially provided to the second comparator 2953_2 synchronously with the comparison target signal. Specifically, the first ramp signal R101 can be provided to the second comparator 2953_2 during time period 201, the fourth ramp signal R104 can be provided to the second comparator 2953_2 during time period 204, the fifth ramp signal R105 can be provided to the second comparator 2953_2 during time period 205, and the sixth ramp signal R106 can be provided to the second comparator 2953_2 during time period 206. However, the embodiments are not limited thereto, and the ramp signal generator 2960 can generate reference signals RAMP containing first ramp signals R101 to sixth ramp signals R106 and fifth ramp signals R105 to sixth ramp signals R106 with different waveforms.

[0419] The first slope s1 of the ramp signal included in the first reference signal RAMP1 may be different from the second slope s2 of the ramp signal included in the second reference signal RAMP2. The absolute value of the slope of the ramp signal included in the second reference signal RAMP2 may be adjusted to be greater than the absolute value of the slope of the ramp signal included in the first reference signal RAMP1. The ratio of the first slope s1 to the second slope s2 may be preset.

[0420] For example, as shown in Figure 30, the absolute value of the second slope s2 can be twice the absolute value of the second slope s2, but the embodiments are not limited to this.

[0421] The first comparator 2953_1 compares each of the HCG reset signal RST_H, HCG signal SIG_H, LOFIC signal SIG_LOFIC, and LOFIC reset signal RST_LOFIC with the first reference signal RAMP1 (which is input synchronously with the timing of the inputs of each signal to the first comparator 2953_2), and outputs a first comparison result. The second comparator 2953_2 compares each of the LCG reset signal RST_L, LCG signal SIG_L, LOFIC signal SIG_LOFIC, and LOFIC reset signal RST_LOFIC with the second reference signal RAMP2 (which is input synchronously with the timing of the inputs of each signal to the second comparator 2953_2), and outputs a second comparison result.

[0422] Referring to Figure 30, since the DSG method is not applied to the LCG signal SIG_L and the LCG reset signal RST_L, the ramp signal generator 2960 uses a reference signal containing a ramp signal with a predetermined slope s1 to read the DSG method to the LCG signal SIG_L and the LCG reset signal RST_L. Since the DSG method is applied to the HCG signal SIG_H and the HCG reset signal RST_H, the ramp signal generator 2960 uses a reference signal RAMP2 containing a ramp signal with a slope s2 different from the predetermined slope to read the HCG signal SIG_H and the HCG reset signal RST_H. And since the DSG method is applied to the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC, the ramp signal generator 2960 can use two reference signals RAMP1 and RAMP2 containing ramp signals with different slopes s1 and s2 to read the LOFIC signal SIG_LOFIC and the LOFIC reset signal RST_LOFIC.

[0423] Figure 31 is an example graph illustrating the signal-to-noise ratio according to one embodiment. Specifically, Figure 31 illustrates the signal-to-noise ratio in decibels (dB) of the signal obtained by synthesizing the HCG image signal, LCG image signal, and LOFIC image signal using the readout circuit 650 shown in Figure 29. In this case, it is assumed that the ratio of the absolute value of the slope s1 of the ramp signal in the first reference signal RAMP1 of Figure 7 to the absolute value of the slope s2 of the ramp signal in the second reference signal RAMP2 is set to 1:2.

[0424] Figure 31 illustrates a first curve 3101 and a second curve 3103, where each curve represents the signal's signal-to-noise ratio (SNR) obtained by synthesizing HCG, LCG, and LOFIC image signals. The first curve 3101 shows the SNR when the pixel signal VS is read out without applying the DSG method, and the second curve 3103 shows the SNR when the pixel signal VS is read out while applying the DSG method. Specifically, the second curve 3103 shows the SNR of the synthesized signal when the pixel signal VS is read out by applying the DSG method with an analog gain twice the predetermined analog gain.

[0425] As shown in Figure 31, the SNR decrease d3111 between the LCG image signal and the LOFIC image signal in the first curve 3101 is greater than the SNR decrease d3113 between the LCG image signal and the LOFIC image signal in the second curve 3103. Similarly, the dynamic range DR3 in the second curve 3103 is wider than the dynamic range DR1 in the first curve 3101.

[0426] Meanwhile, as described above, as the number of photoelectric devices contained in a pixel PX increases, the amount of charge generated by each photoelectric device can increase, and the magnitude of the pixel signal based on the generated charge can increase. To prevent an increase in random noise due to the decrease in pixel conversion gain when operating in HCG mode, a method can be used to read the pixel signal generated from a pixel via multiple row lines.

[0427] Figure 32 is an example circuit diagram illustrating a pixel according to one embodiment.

[0428] Referring to FIG9, an image sensor 900 according to another embodiment may include a pixel array 940 and a readout circuit 950.

[0429] As described above, pixel array 940 may include multiple pixels PXa, PXb, and PXc. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding transfer signal from transfer signals TGi, TGi+1, TGi+2, TGi+3, TGi+4, and TGi+5, and a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2. Each of the multiple pixels PXa, PXb, and PXc may receive a corresponding selection signal from selection signals SELi, SELi+1, and SELi+2 to output pixel signals VS1 and VS2. As shown in Figure 32, a pixel PXa may include multiple sub-pixels 9401 and 9402. Each of the multiple sub-pixels 9401 and 9402 can be selected by transfer signals TTi and TTi+1 and selection signal SELi to output pixel signal VS1 and pixel signal VS2.

[0430] According to one embodiment, a pixel PXa may include a pixel circuit that processes the charge generated by photoelectric devices PD31, PD32, PD33, PD34, PD41, PD42, PD43, and PD44, and outputs an electrical signal, as well as photoelectric devices PD31, PD32, PD33, PD34, PD41, PD42, PD43, and PD44 that generate charge in response to light. In FIG32, a pixel PXa is illustrated as comprising eight photoelectric devices PD31, PD32, PD33, PD34, PD41, PD42, PD43, and PD44, but the present invention is not limited to this, and a pixel PXa may also comprise multiple photoelectric devices.

[0431] In some embodiments, photoelectric devices PD31, PD32, PD33, PD34, PD41, PD42, PD43, and PD44 can detect external light to generate charges. The charges generated by photoelectric devices PD31, PD32, PD33, and PD34 in sub-pixel 9401 and the charges generated by photoelectric devices PD41, PD42, PD43, and PD44 in sub-pixel 9402 can each be output by being divided into two row lines CL1 and CL2. Specifically, the charges generated by photoelectric devices PD31, PD32, PD33, and PD34 can be output to the readout circuit 950 via row line CL1, and the charges generated by photoelectric devices PD41, PD42, PD43, and PD44 can be output to the readout circuit 950 via row line CL2.

[0432] The cathodes of photoelectric devices PD31, PD32, PD33, and PD34 can be connected to the floating node FN31 via transfer transistors TX31, TX32, TX33, and TX34, and the anodes of photoelectric devices PD31, PD32, PD33, and PD34 can be grounded. Similarly, the cathodes of photoelectric devices PD41, PD42, PD43, and PD44 can be connected to the floating node FN41 via transfer transistors TX41, TX42, TX43, and TX44, and the anodes of photoelectric devices PD41, PD42, PD43, and PD44 can be grounded.

[0433] The pixel circuit PX may include transfer transistors TX31, TX32, TX33, TX34, TX41, TX42, TX43, and TX44; drive transistors DX3 and DX4; select transistors SX3 and SX4; reset transistors RX3 and RX4; and switch transistors SW31, SW32, SW41, and SW42. The transistors TX31, TX32, TX33, TX34, TX41, TX42, TX43, TX44, DX3, DX4, SX3, SX4, SX1, SX2, RX3, RX4, SW31, SW32, SW41, and SW42 in the pixel circuit can operate in response to control signals provided by the auto-driver 130, such as transfer control signals TG31, TG32, TG33, and TG34, selection signal SEL1, reset control signal RG1, first gain control signal DCG1, and second gain control signal DCG2.

[0434] In some embodiments, sub-pixel 9401 may include a plurality of floating diffusers FD31, FD32, and FD33. Floating diffusers FD31, FD32, and FD33 may have a predetermined capacitance and store the charge generated by photoelectric devices PD31, PD32, PD33, and PD34. Sub-pixel 9402 may include a plurality of floating diffusers FD41, FD42, and FD43. Floating diffusers FD41, FD42, and FD43 may have a predetermined capacitance and store the charge generated by photoelectric devices PD41, PD42, PD43, and PD44. Floating diffusers FD31 and FD41 may have the same capacitance, and floating diffusers FD32 and FD42 may have the same capacitance. Third floating diffusers FD33 and FD43 may include lateral overflow integral capacitors (LOFIC) and may have the same capacitance.

[0435] Transfer transistor TX31 can be connected between photoelectric device PD31 and floating node FN31, and transfer transistor TX41 can be connected between photoelectric device PD41 and floating node FN41 and is controlled by transfer signal TG31. When transfer transistor TX31 is turned on, the charge generated by photoelectric device PD31 can be transferred to floating diffuser FD31. When transfer transistor TX41 is turned on, the charge generated by photoelectric device PD41 can be transferred to floating diffuser FD41.

[0436] Furthermore, transfer transistor TX32 can be connected between photoelectric device PD32 and floating node FN31, and transfer transistor TX42 can be connected between photoelectric device PD42 and floating node FN41 and is controlled by transfer signal TG32. When transfer transistor TX32 is turned on, the charge generated by photoelectric device PD32 can be transferred to floating diffusion FD31. When transfer transistor TX42 is turned on, the charge generated by photoelectric device PD42 can be transferred to floating diffusion FD41.

[0437] Transfer transistor TX33 can be connected between photoelectric device PD33 and floating node FN31, and transfer transistor TX43 can be connected between photoelectric device PD43 and floating node FN41 and is controlled by transfer signal TG33. When transfer transistor TX33 is turned on, the charge generated by photoelectric device PD33 can be transferred to floating diffuser FD31. When transfer transistor TX43 is turned on, the charge generated by photoelectric device PD43 can be transferred to floating diffuser FD41.

[0438] Transfer transistor TX34 can be connected between photoelectric device PD34 and floating node FN31, and transfer transistor TX44 can be connected between photoelectric device PD44 and floating node FN41 and is controlled by transfer signal TG34. When transfer transistor TX34 is turned on, the charge generated by photoelectric device PD34 can be transferred to floating diffusion FD31. When transfer transistor TX44 is turned on, the charge generated by photoelectric device PD44 can be transferred to floating diffusion FD41.

[0439] The voltage of the floating node FN31 can be determined based on the charge accumulated in the floating diffuser FD31. The gate of the driving transistor DX3 is connected to the floating node FN31. The driving transistor DX3 can operate as a source follower amplifier for the voltage of the floating node FN31. The driving transistor DX3 can output the pixel signal VS1 to the row line CL1 via the select transistor SX3 in response to the voltage of the floating node FN31.

[0440] Furthermore, the voltage of the floating node FN41 can be determined based on the charge accumulated in the floating diffuser FD41. The gate of the driving transistor DX4 is connected to the floating node FN41. The driving transistor DX4 can operate as a source follower amplifier for the voltage of the floating node FN41. The driving transistor DX4 can output the pixel signal VS2 to the row line CL2 via the selection transistor SX4 in response to the voltage of the floating node FN41.

[0441] Selector transistor SX3 can be connected between driver transistor DX3 and the corresponding row line CL1, and selector transistor SX4 can be connected between driver transistor DX4 and the corresponding row line CL2. Therefore, both selector transistors SX3 and SX4 can be controlled by the select signal SEL1. That is, sub-pixels 9401 and 9402 can be selected simultaneously. When selector transistor SX3 is turned on, the pixel voltage VS1 output from driver transistor DX3 can be output to readout circuit 950 via row line CL connected to selector transistor SX3. Furthermore, when selector transistor SX4 is turned on, the pixel voltage VS2 output from driver transistor DX4 can be output to readout circuit 950 via row line CL2 connected to selector transistor SX4.

[0442] Reset transistors RX3 and RX4 can be connected between the power supply voltage line supplying power supply voltage VDD and each of floating nodes FN32 and FN42, and can be controlled by the reset control signal RG2. When reset transistors RX3 and RX4 are turned on by the reset signal RG2, the power supply voltage VDD can be applied to floating nodes FN32 and FN42 to reset them. When switching transistors SW31 and SW32 are turned on and reset transistor RX3 is turned on, both floating nodes FN31 and FN32 can be reset to the power supply voltage VDD. Furthermore, when switching transistors SW41 and SW42 are turned on and reset transistor RX4 is turned on, both floating nodes FN41 and FN42 can be reset to the power supply voltage VDD.

[0443] Switching transistor SW31 can be connected between floating node FN31 and floating node FN32, and switching transistor SW41 can be connected between floating node FN41 and floating node FN42 and is controlled by the first gain control signal DCG1. Switching transistor SW32 can be connected between floating node FN32 and floating diffuser FN33, and switching transistor SW42 can be connected between floating node FN42 and floating diffuser FD43 and is controlled by the second gain control signal DCG2.

[0444] When switching transistors SW31 and SW41 are off, floating node FN31 has a capacitance of floating diffusion FD31, and floating node FN41 has a capacitance of floating diffusion FD41. In this case, since the capacitance values ​​connected to floating nodes FN31 and FN41 are small, pixel PX operates in HCG mode and can output the same pixel signal VS1 and pixel signal VS2 via each of row lines CL1 and CL2.

[0445] When switching transistors SW31 and SW41 are turned on and switching transistors SW32 and SW42 are turned off, the second floating diffuser FD32 is connected to the first floating node FN31 and the floating diffuser FD42 is connected to the floating node FN41. That is, the capacitance of the first floating node FN31 is increased by the capacitance of the second floating diffuser FD32, and the capacitance of the floating node FN41 is increased by the capacitance of the second floating diffuser FD42. In this case, pixel PX can operate in LCG mode and can output the same pixel signal VS1 and pixel signal VS2 via each of row lines CL1 and CL2.

[0446] When switching transistors SW31 and SW41 are turned on, and switching transistors SW32 and SW42 are also turned on, the second floating diffuser FD33 is connected to the first floating node FN31, and the floating diffuser FD43 is connected to the floating node FN41. That is, the capacitance of the first floating node FN31 is increased by the capacitance of the second and third floating diffusers FD32 and FD33, and the capacitance of the floating node FN41 is increased by the capacitance of the second and third floating diffusers FD42 and FD43. In this case, pixel PX can operate in LOFIC mode and can output the same pixel signal VS1 and pixel signal VS2 via each of row lines CL1 and CL2.

[0447] Each of sub-pixels 9401 and 9402 can operate in the same manner as pixel PX3 described with reference to FIG11A.

[0448] As described above with reference to Figure 9, selector 951 then averages pixel signals VS1 and VS2 to generate an average value VS, and outputs the generated average value to comparators 953_1 and 953_2. Comparator 953_1 compares the pixel signal VS corresponding to the average value of the two pixel signals VS1 and VS2 with a reference signal RAMP (which is timing-synchronized with the pixel signal VS input to the first comparator 953_1), and outputs the result to counter 955_1. CDS circuit 957_1 can then be connected to the output terminal of counter 955_1, and performs Correlated Double Sampling (CDS) on the output of pixel signal VS received from counter 955_1 to generate image signal IMS.

[0449] Similarly, comparator 953_2 can compare the reference signals that are synchronously input to each comparator 953_2 at the same time as the pixel signal VS, and output the result to counter 955_2. Thereafter, CDS circuit 957_2 can be connected to the output terminal of counter 955_2, and can perform a correlated double sampling (CDS) method on the output of the pixel signal VS received from counter 955_2 to generate the image signal IMS.

[0450] Figure 33 is an exemplary block diagram of a computer device according to an embodiment.

[0451] Referring to Figure 33, the computing device 3300 may include a camera 3310, a controller 3320, a memory 3330, and a display 3340.

[0452] The camera 3310 may include an image sensor 3311. The image sensor 3311 may be implemented as an image sensor described with reference to Figures 1 to 32. The camera 3310 may use the image sensor 3311 to generate an image signal, perform image signal processing on the image signal, and output the processed image signal to the controller 3320.

[0453] The controller 3320 may include a processor 3321. The processor 3321 controls the overall operation of the components of the computing device 3300. The processor 3321 may be implemented as at least one of various processing units such as a central processing unit (CPU), an application processor (AP), and a graphics processing unit (GPU). In some embodiments, the controller 3320 may be implemented as an integrated circuit or a system on a chip (SoC).

[0454] In some embodiments, as illustrated in FIG33, the controller 3320 may further include an interface 3334, a memory controller 3323, a display controller 3324, and a bus 3325. In some embodiments, at least some of the interface 3334, the memory controller 3323, the display controller 3324, and the bus 3325 may be provided external to the controller 3320. In some embodiments, the controller 3320 may further include an image signal processor.

[0455] Interface 3322 can transmit the image signal received from image sensor 3311 to memory controller 3323 or display controller 3324 via bus 3325.

[0456] Memory 3330 can store various data and commands. Memory controller 3323 can control the transfer of data or commands to memory 3330 and the transfer of data or commands from memory 3330.

[0457] The display controller 3324, under the control of the processor 3321, can transmit data to be displayed on the display 3340, and the display 3340 can display the data on the screen. In some embodiments, the display 3340 may further include a touch screen. The touch screen can transmit user input for controlling the operation of the computing device 3300 to the controller 3320. User input can be generated when a user touches the touch screen.

[0458] Bus 3325 provides communication functionality between components of controller 3320. Bus 3325 may include at least one type of bus, depending on the communication protocol between components.

[0459] Although embodiments of the present invention have been described in detail above, the scope of this disclosure is not limited thereto. Those skilled in the art to which this disclosure pertains will understand that this disclosure can be implemented in other specific forms without altering the technical concept or essential characteristics of the disclosure. Therefore, it should be understood that the embodiments described above are illustrative and not restrictive in all respects.

[0460] While this disclosure has been described in conjunction with embodiments now considered practical examples, it should be understood that the nature of the invention is not limited to the disclosed embodiments. Rather, it should be understood that various modifications and equivalent configurations may be made without departing from the spirit and scope of the appended claims.

[0461] 100, 600, 900, 1900, 2600, 2900, 3311: Image sensor 101,102,103,104,105,106,111,112,113,114,115,116,121,122,123,124,125,126,131,132,133,134,135,136,141,142,143,144,145,146,151,152,153,1 54, 155, 156, 161, 162, 163, 164, 165, 166, 171, 172, 173, 174, 175, 176, 201, 202, 203, 204, 205, 206, 401, 402, 403, 404, 501, 502, 503, 504, 701, 702, 703, 704: Time Period 110,610,910,1910,2610,2910,3320: Controller 120,2920: Timing generator 130: Column Driver 140, 640, 940, 1940, 2640, 2940: Pixel array 150, 650, 950, 1950, 2650, 2950: Readout circuits 151,651,951,1951,2651,2951: Selectors 153,153_1,153_2,653,653_1,653_2,953,953_1,953_2,1953,1953_1,1953_2,1953_3,1953_4,2653,2653_1,2653_2,2653_3,2953,2953_1,2953_2: Comparator 155,155_1,155_2,655,655_1,655_2,955,955_1,955_2,1955,1955_1,1955_2,1955_3,1955_4,2655,2655_1,2655_2,2655_3,2955,2955_1,2955_2: Counter 157,157_1,157_2,657,657_1,657_2,957,957_1,957_2,1957,1957_1,1957_2,1957_3,1957_4,2657,2657_1,2657_2,2657_3,2957,2957_1,2957_2: CDS circuit 160, 660, 960, 1960, 2660, 2960: Ramp signal generator 170: Data Buffer 180: Image Signal Processor 801, 803, 1403, 1701, 1703, 1801, 1803, 2201, 2203, 2301, 2303, 2401, 2403, 2501, 2503, 3101, 3103: Curve graph 1400, PX, PX1, PX2, PX3, PX4, PXa, PXb, PXc: pixels 1401: Subpixel Groups / Graphs 1401_1,1401_2,1402_1,1402_2,9401,9402: Subpixels 1402: Subpixel group 3300: Computing device 3310: Camera 3321: Processor 3322: Interface 3323: Memory controller 3324: Display Controller 3325: Busbar 3330: Memory 3340: Monitor CL, CL1, CL2: Row lines d221,d223,d231,d241,d243,d251,d253,d1411,d1412,d1421,d1422,d1711,d1712,d1721,d1722,d1811,d1812,d1821,d1822,d3111,d3113,d8011,d8031: SNR decreases DCG, DCG1, DCG2: Gain control signals DR1, DR3, DR801, DR803: Dynamic Range DX1, DX2, DX3, DX4: Driving transistors Exposure: period of exposure f1, f2: Quantity FD11, FD12, FD21, FD22, FD31, FD32, FD33, FD41, FD42, FD43: Floating diffusion FN11, FN12, FN21, FN22, FN31, FN32, FN41, FN42: Floating nodes IMS: Image Signal PC1, PC2, PC3, PC4: Pixel circuits PD11, PD12, PD13, PD14, PD21, PD22, PD23, PD24, PD31, PD32, PD33, PD34, PD41, PD42, PD43, PD44: Optoelectronic devices R_EN: Slope-enabled signal R1,R2,R3,R4,R5,R6,R11,R12,R13,R14,R15,R16,R21,R22,R23,R24,R25,R26,R31,R32,R33,R34,R3 5,R36,R41,R41',R42,R42',R43,R43',R44,R44',R45,R45',R46,R46',R51,R51',R52,R52',R53,R5 3',R54,R54',R55,R55',R56,R56',R61,R61',R62,R62',R63,R63',R64,R65,R65',R66,R66',R71,R71',R72,R72',R73,R74,R74',R75,R75',R76,R76',R102,R103,R104,R105,R105',R106,R106': Ramp signal RAMP, RAMP1, RAMP2, RAMP3, RAMP4: Reference signals Readout: Readout period Reset: Reset time period RG,RG1: Reset control signal RL: Column line RST_H:HCG reset signal RST_L:LCG reset signal RST_LOFIC: LOFIC reset signal RX1, RX2, RX3, RX4: Reset Transistor s1, s2, s3, s4: Slope SEL, SEL1, SELi, SELi+1, SELi+2: Selection signals SEL_M, SEL_M1, SEL_M2: DEMUX selection signals SIG_H: HCG signal SIG_L:LCG signal SIG_LOFIC: LOOFC signal SW1, SW2, SW31, SW32, SW41, SW42: Switching transistors SX1, SX2, SX3, SX4: Selectable transistors TG, TG11, TG12, TG13, TG14, TG31, TG32, TG33, TG34, TTi, TTi+1, TTi+2, TTi+3, TTi+4, TTi+5: Transfer signals TX11, TX12, TX13, TX14, TX21, TX22, TX23, TX24, TX31, TX32, TX33, TX34, TX41, TX42, TX43, TX44: Transfer transistors VDD: Power supply voltage VS, VS1, VS2: Pixel signals

Claims

1. An image sensor, comprising: A pixel includes a first floating diffuser and a second floating diffuser including a lateral overflow integral capacitor (LOFIC), generates a first pixel signal based on the charge amount of the first floating diffuser, and generates a second pixel signal based on the charge amount of the first floating diffuser and the charge amount of the second floating diffuser; a row line is connected to the pixel and transmits the first pixel signal or the second pixel signal; a ramp signal generator generates a first reference signal and a second reference signal; and a readout circuit is connected to the row line and generates an image signal based on a plurality of comparison results, the plurality of comparison results including a first comparison result obtained by comparing the first pixel signal with the first reference signal, a second comparison result obtained by comparing the second pixel signal with the first reference signal, and a third comparison result obtained by comparing the second pixel signal with the second reference signal.

2. The image sensor as claimed in claim 1, wherein: The first reference signal includes a plurality of ramp signals having a first slope, the second reference signal includes a plurality of ramp signals having a second slope different from the first slope, and the plurality of comparison results further include a fourth comparison result obtained by comparing the first pixel signal with the second reference signal.

3. The image sensor as claimed in claim 1, wherein: The pixel further includes a third floating diffusion, the second pixel signal is further generated based on the charge amount of the third floating diffusion, and the pixel further generates a third pixel signal based on the charge amount of the first floating diffusion and the charge amount of the third floating diffusion.

4. The image sensor as claimed in claim 3, wherein: The first reference signal includes a plurality of ramp signals having a first slope, the second reference signal includes a plurality of ramp signals having a second slope different from the first slope, and the plurality of comparison results further include a fourth comparison result obtained by comparing the third pixel signal with the second reference signal.

5. The image sensor as described in claim 4, further comprising: A first comparator receives the first pixel signal, the second pixel signal, and the first reference signal, and outputs the first comparison result and the second comparison result. And a second comparator, which receives the second pixel signal, the third pixel signal and the second reference signal and outputs the third comparison result and the fourth comparison result.

6. The image sensor as claimed in claim 3, wherein: The first reference signal includes a plurality of ramp signals having a first slope, the second reference signal includes a plurality of ramp signals having a second slope different from the first slope, and the plurality of comparison results further include a fourth comparison result obtained by comparing the first pixel signal with the second reference signal.

7. The image sensor as claimed in claim 6, wherein: The ramp signal generator further generates a third reference signal with a third slope, and the plurality of comparison results further include a fifth comparison result obtained by comparing the third pixel signal with the third reference signal.

8. The image sensor as claimed in claim 7, wherein: As the analog gain of the image sensor increases, the ramp signal generator maintains the third slope.

9. The image sensor as claimed in claim 7, wherein: The readout circuit includes: a first comparator that receives the first pixel signal, the second pixel signal, and the first reference signal, and outputs the second comparison result and the fourth comparison result; and a second comparator that receives the first pixel signal, the second pixel signal, and the second reference signal, and outputs the third comparison result and the fourth comparison result. And a third comparator, which receives the third pixel signal and the third reference signal and outputs the fifth comparison result.

10. The image sensor as claimed in claim 9, wherein: The ramp signal generator further generates a fourth reference signal having a fourth slope different from the third slope, and the plurality of comparison results further include a sixth comparison result obtained by comparing the third pixel signal with the fourth reference signal.

11. The image sensor as claimed in claim 10, wherein: As the analog gain of the image sensor increases, the ramp signal generator maintains the fourth slope.

12. The image sensor as claimed in claim 10, wherein: The readout circuit further includes: a fourth comparator, which receives the third pixel signal and the fourth reference signal and outputs the sixth comparison result.

13. The image sensor as claimed in claim 3, wherein: The pixel includes a first floating diffuser, a second floating diffuser, and a third floating diffuser as a first sub-pixel, and includes a fourth floating diffuser having the same capacitance as the first floating diffuser, a fifth floating diffuser having the same capacitance as the second floating diffuser, and a sixth floating diffuser having the same capacitance as the third floating diffuser as a second sub-pixel. A fourth pixel signal is generated based on the charge of the fourth floating diffuser, a fifth pixel signal is generated based on the charge of the fourth floating diffuser and the fifth floating diffuser, and a sixth pixel signal is generated based on the charge of the fourth floating diffuser, the fifth floating diffuser, and the sixth floating diffuser. The row lines include a first row line connected to the first sub-pixel and a second row line connected to the second sub-pixel. The readout circuit generates a first comparison result by comparing the average of the first pixel signal and the fourth pixel signal with the first reference signal when comparing the first pixel signal with the first reference signal; generates a second comparison result by comparing the average of the second pixel signal and the fifth pixel signal with the first reference signal when comparing the second pixel signal with the first reference signal; generates a third comparison result by comparing the average of the second pixel signal and the fifth pixel signal with the second reference signal when comparing the second pixel signal with the second reference signal; and generates a fourth comparison result by comparing the average of the third pixel signal and the sixth pixel signal with the second reference signal when comparing the second pixel signal with the second reference signal.

14. An image sensor, comprising: Optoelectronic devices; A transfer transistor is connected between the first node and the optoelectronic device; The first floating diffusion connects to the first node; A first switching transistor is connected between the first node and the second node; a second floating diffuser is connected to the second node; a second switching transistor is connected between a power supply voltage line and the second node; a driving transistor generates a pixel signal in response to the voltage of the first node and outputs the pixel signal to the row line; a readout circuit is connected to the row line and compares the pixel signal with a first reference signal that includes a ramp signal with a first slope among a plurality of reference signals, and compares the pixel signal with a second reference signal that includes a ramp signal with a second slope different from the first slope among the plurality of reference signals to generate an image signal; and a ramp signal generator generates the plurality of reference signals that include the plurality of ramp signals and transmits the plurality of reference signals to the readout circuit.

15. The image sensor as claimed in claim 14, wherein: The pixel signal includes a first pixel signal generated by the driving transistor when the first switching transistor is off, and a second pixel signal generated by the driving transistor when the first switching transistor is on and the second switching transistor is off.

16. The image sensor as claimed in claim 15, further comprising: A third switching transistor is connected between the first node and the third node; And a third floating diffusion, connected to the third node, wherein the pixel signal further includes a third pixel signal generated by the driving transistor when the first switching transistor and the third switching transistor are turned on.

17. The image sensor as claimed in claim 15, further comprising: The third floating diffusion is connected in series with the second switching transistor, wherein the pixel signal further includes a third pixel signal generated by the driving transistor when the first switching transistor and the second switching transistor are turned on.

18. The image sensor as claimed in claim 17, wherein: The readout circuit compares the first pixel signal and the third pixel signal with the first reference signal, and compares the second pixel signal and the third pixel signal with the second reference signal to generate the image signal.

19. The image sensor as claimed in claim 17, wherein: The plurality of reference signals further includes a third reference signal containing a ramp signal with a third slope, generated synchronously by the ramp signal generator and the third pixel signal, and the readout circuit compares the first pixel signal and the second pixel signal with the first reference signal, compares the first pixel signal and the second pixel signal with the second reference signal, and compares the third pixel signal with the third reference signal to generate the image signal.

20. The image sensor as claimed in claim 19, wherein: As the analog gain of the image sensor increases, the ramp signal generator maintains the slope of the ramp signal in the third reference signal.

21. The image sensor as claimed in claim 19, wherein: The plurality of reference signals further includes a fourth reference signal having a fourth slope, generated synchronously by the ramp signal generator and the third pixel signal, and the readout circuit further includes a fourth comparator for comparing the third pixel signal with the fourth reference signal.

22. The image sensor as claimed in claim 21, wherein: As the analog gain of the image sensor increases, the ramp signal generator maintains the slope of the ramp signal in the fourth reference signal.

23. A method performed by an image sensor, comprising: In a pixel comprising a first floating diffusion and a second floating diffusion, a first pixel signal is generated based on the charge amount of the first floating diffusion and a second pixel signal is generated based on the charge amount of the first floating diffusion and the charge amount of the second floating diffusion; a first reference signal comprising a ramp signal having a first slope and a second reference signal comprising a ramp signal having a second slope different from the first slope are generated; and an image signal is generated based on a plurality of comparison results, the plurality of comparison results including a first comparison result obtained by comparing the first pixel signal with the first reference signal, a second comparison result obtained by comparing the second pixel signal with the first reference signal, and a third comparison result obtained by comparing the second pixel signal with the second reference signal.

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