Methods for etching molybdenum

Abstract

A method of substrate processing includes: providing a substrate comprising an etch mask above a molybdenum layer in a recessed feature; exposing the substrate to a plasma-induced deposition gas forming an etch protection layer on a sidewall of the recessed feature; and exposing the substrate to a plasma-induced etching gas etching the molybdenum layer according to the etch mask, wherein the exposure steps are performed alternately multiple times.

Description

Molybdenum etching method [Cross Reference to Co-applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 287,371 (filed December 8, 2021), which is incorporated herein by reference. The present invention relates generally to a method for manufacturing a semiconductor device, and in a specific embodiment, to a method for dry etching molybdenum. Semiconductor integrated circuits (ICs) are networks of electronic components built by sequentially depositing and patterning numerous material layers to form a monolithic structure on a substrate. At each new technology node, component density approximately doubles to reduce the unit cost of ICs. Thanks to advancements in patterning, hundreds of transistors can be packaged within a 1μm area. 2 In the region of the signal and power supply, the metal lines are connected via a half-pitch of less than 15 nm. The resistance of such narrow lines depends primarily on conduction near the edges. The pads used as diffusion barriers and random electron scattering along the metal edges create a narrow width effect (NWE), where the resistance increases sharply as the width decreases. Therefore, for sub-5 nm nodes, molybdenum in silicon oxide is an interesting metal for wires at the highest density interconnect levels due to its low diffusivity (eliminating the need for diffusion barriers), low bulk mean free path (less edge scattering), high melting point, and low coefficient of thermal expansion. While molybdenum possesses promising properties, integrating it into high-volume IC manufacturing requires dry etching methods that allow for good control over the etching profile, etching rate, and etch selectivity for masking materials and underlying layers. Therefore, further innovation in dry etching processes for molybdenum is needed. A method of substrate processing includes: providing a substrate comprising an etch mask above a molybdenum layer in a recessed feature; exposing the substrate to a plasma-induced deposition gas forming an etch protection layer on a sidewall of the recessed feature; and exposing the substrate to a plasma-induced etching gas etching the molybdenum layer according to the etch mask, wherein the exposure steps are performed alternately multiple times. A method of substrate processing includes: providing a substrate comprising an etch mask over a molybdenum layer in a recessed feature; depositing an etch protection layer in the recessed feature, wherein the etch protection layer comprises an oxide layer; performing a through-etch step that etches through the etch protection layer to the bottom of the recessed feature; and exposing the substrate to a plasma-excited etching gas that etches the molybdenum layer in accordance with the etch mask. A method for processing a substrate includes: providing a substrate comprising an etch mask over a molybdenum layer in a recessed feature; depositing an etch protection layer on a sidewall of the etch mask, wherein the etch protection layer includes an oxide layer; and exposing the substrate to a plasma-excited etching gas, the plasma-excited etching gas etching the molybdenum layer according to the etch mask, wherein the deposition and exposure are alternated multiple times. [Simplified illustration] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein: Figure 1A illustrates a flowchart of a process for patterning molybdenum layers, based on a summary of several embodiments; Figures 1B-1D show cross-sectional views of the semiconductor devices at each intermediate step of the processing flow summarized in the flowchart shown in Figure 1A. Figures 2A and 2B illustrate cross-sectional views of a semiconductor device, showing undesirable etch characteristics and defects resulting from patterning a molybdenum layer using anisotropic dry etching with insufficient processing windows. Figure 3A illustrates a flowchart of a gas pulsed cyclic etching technique for patterning molybdenum metal layers, based on several embodiments. Figures 3B-3F illustrate various cross-sectional views of a semiconductor device that uses the gas pulsed cyclic etching technique summarized in the flowchart shown in Figure 3A to pattern a molybdenum layer at various intermediate stages. Figure 4 illustrates a flowchart of an ALD-based cyclic etching technique for patterned molybdenum metal layers, summarized according to several embodiments; and Figure 5 illustrates a flowchart of a single cycle of a cyclic etching technique according to several embodiments. This disclosure describes embodiments of a dry etching method for subtractive etching of metallic molybdenum. In this disclosure, metallic molybdenum refers to elemental molybdenum and its alloys, including molybdenum containing small amounts of impurities and dopants. In subtractive etching of metal, a patterned etch mask is formed over a metal layer, and the pattern is transferred to the metal layer by directly etching through recessed features of the metal to form a pattern of metal lines. Typically, a dry etching process, such as reactive ion etching (RIE), is used. Before forming the etch mask, a metal layer is uniformly formed on a flat surface of an interlayer dielectric (ILD) layer. After patterning the metal by subtractive etching, another ILD layer can be formed to fill the recessed features and cover the metal lines for insulation. Conventional copper interconnects use a more complex damascene process in which trenches for metal lines are etched into the ILD layer using a patterned etch mask and overfilled with metal. Overfill material, including all metal deposited on the dielectric surface between the trenches, is removed using, for example, chemical mechanical polishing (CMP) to form metal lines damascened in the ILD. As those skilled in the art know, depositing metal on a flat surface is simpler than filling 10 nm to 20 nm wide trenches with void-free metal. Furthermore, the CMP step is expensive, thus increasing manufacturing costs. If the etching process meets appropriate manufacturing criteria, subtractive etching is simpler and cheaper than damascene etching for patterning metals. For example, the etching process must meet specifications for etching rate, etching selectivity, sidewall profile, line edge roughness (LER), and defect density (e.g., bridging and line breakage defects), and have good control for robust manufacturing. This disclosure describes a dry etching process for patterning molybdenum-containing metal layers, which offers several advantages, such as suppressed lateral etching to reduce undercut, low LER, and more vertical edge profiles, as well as improved etching rate and etching selectivity. ILD layers are typically based on silicon oxide dielectrics. Copper is a contaminant that readily diffuses in silicon oxide, therefore a continuous diffusion barrier layer is required within the trench before filling it with copper. Typically, a sufficiently thick pad (e.g., 1.5 nm to 3 nm) is formed to ensure there are no holes or breaks at the edges and corners through which copper can leak into the ILD and reduce the time-dependent dielectric breakdown (TDDB) lifetime of the interconnect structure. Pads can increase the resistance of the metal line primarily through two methods. A low-resistivity core metal can be replaced by a pad material containing a higher-resistivity metal or insulator. Furthermore, the higher diffuse electron scattering rate at the interface between the core metal and the pad can further increase the line resistance. Diffusion scattering along the edges is more dominant in metals where the bulk mean free path (λ) of electrons is longer than the cross-sectional area of ​​the line. Geometric effects (reduced cross-sectional area) and scattering effects (higher scattering rate at the interface), as edge effects, lead to increased resistance as... W decreases the resistance of the metal wire and rises by more than 1 / W is faster. Here, W refers to the line width including the padding. For example, in inlay work, W will be the trench width. This means the effective resistivity ρ( W) With The decrease in W and the increase in W is an undesirable phenomenon referred to in this disclosure as the narrow width effect (NWE). Effective resistivity ρ( W) is for L / ( Wt) standardized line resistance, of which L is the length of the line. t is the thickness of the metal. Due to NWE, ρ increases ( Undesirable consequences of W) include a larger ohmic voltage drop (reduced circuit speed) and more Joule heating leading to accelerated electromigration (EM) at higher temperatures. Copper is required for diffusion barrier pads, exhibiting strong NWE. For example, when When W decreases to 10 nm, ρ( W) may be higher than its bulk resistivity (ρ) ο =16.8 Ω-nm) increases by an order of magnitude. The strong NWE of copper wires is a problem in scaling copper interconnects, which has spurred research into replacing copper with suitable metals (at least in the lower metal layers where the most densely packed metal wires are placed). As mentioned in the previous technical paragraph, molybdenum does not require a diffusion barrier layer due to its low diffusivity in silicon oxide. Furthermore, due to its short λ ​​= 11.2 nm, diffusion scattering along the edges of molybdenum wires is less significant than that along the edges of copper wires, where λ = 39.9 nm. When W decreases to approximately 10 times the padding thickness, the geometric effect (reduced cross-sectional area) becomes significant, and when When W decreases below λ, the scattering effect (the higher scattering rate at the interface) affects ρ ( W) has a significant impact. In fact, when comparing different metals, ρ ο ×λ is often used as an indicator of the magnitude of the scattering effect component in the NWE. For copper, ρ is used as a measure. ο ×λ is 670 Ω-nm 2 In contrast, despite having a higher ρ ο = 53.4 Ω-nm, ρ of molybdenum ο ×λ is 600 Ω- nm 2 Therefore, molybdenum's NWE is less severe compared to copper. This is due to other attractive properties, such as a reasonably low ρ. ο Low coefficient of thermal expansion (5×10) -6 With its high melting point (a good indicator of EM reliability), high temperature (per °C), and stable interface with silicon oxide, molybdenum is being considered as a replacement for copper. In IC design, replacing embedded copper with subtractive etch patterned unobstructed metal lines to achieve the tightest spacing wiring levels in IC design is one of the technological expansion goals of several architectural changes that may urgently require performance, power, area, and cost (PPAC). As mentioned above, molybdenum is expected to be used for this purpose. Integrating molybdenum interconnects into the IC manufacturing process requires the following steps: forming a metal layer containing molybdenum over a substrate, forming a patterned etch mask over the metal layer, and transferring the pattern to the metal layer by etching a pattern of recessed features extending through the metal layer. In this disclosure, we describe an embodiment of a method for etching a pattern of recessed features extending through the molybdenum layer and exposing a portion of a major surface of the underlying layer. This method employs a cyclic process to separate the vertically advancing etch front from the controlled sidewall profile to achieve improved process optimization. For example, each cycle of the cyclic process may include a first portion of the sidewall protected using a set of optimized process parameters and gases for depositing passivation solid byproducts, and a different set of optimized process parameters and gases for selectively removing the molybdenum to vertically extend the recessed features. The time separation of the deposition and etching steps in the cyclic etching process allows for improved optimization, providing a wider process window to achieve smooth vertical sidewalls with negligible undercut and foot defects during manufacturing. Figure 1A illustrates a flowchart summarizing a process flow 100 for patterning a molybdenum layer using subtractive etching. Process flow 100 may be part of the manufacturing process of a semiconductor device 110, in which a metal line layer including molybdenum has been integrated using embodiments described in this disclosure. The basic processing steps in process flow 100 are described with reference to the schematic cross-sectional views of the semiconductor device 110 depicted in Figures 1B-1D. As shown in step 102 of the flowchart in Figure 1A, process 100 includes providing a substrate having a molybdenum layer formed over an underlying layer and an etch mask patterned over the molybdenum layer. In step 104, a subtractive etching process is performed using the patterned etch mask to form a pattern of metal lines containing molybdenum. The subtractive etching process includes a cyclic etching process. Each cycle of the cyclic etching process includes depositing an etch guard layer and anisotropically etching molybdenum in recessed features in the molybdenum layer. After the metal lines are formed, any remaining portions of the etch mask can be removed, as shown in step 106. Figure 1B illustrates a cross-sectional view of the semiconductor device 110 after a molybdenum layer 116 is formed over an underlying layer 114 and an etch mask 122 is patterned over the molybdenum layer 116, as shown in step 104 of the flowchart in Figure 1A. The underlying layer 114 may include a dielectric layer, such as an ILD layer comprising low-k silicon oxide or an insulating etch-stop layer in the ILD layer. A suitable film growth technique, such as plasma-enhanced chemical vapor deposition (PECVD), can be used to form the molybdenum layer 116. Optionally, a thin adhesive layer (not shown) (e.g., TiN or TaN) may be deposited on the underlying layer 114 prior to the formation of the molybdenum layer 116. In addition to aiding adhesion, the adhesive layer can also help improve the morphology of the molybdenum layer 116 during film growth. Various other layers beneath the underlying layer 114 are collectively shown as a substrate layer 112. The etch mask 122 is the first pattern of the recessed features 124, each recessed feature 124 having vertical sidewalls and a bottom portion exposing one of the main surfaces of the molybdenum layer 116. In the exemplary embodiment of FIG. 1B, the etch mask 122 includes a patterned hard mask layer 118 and a patterned photoresist layer 120. The patterned hard mask layer 118 can be formed by depositing a hard mask material on the molybdenum layer 116 and then etching the hard mask material using the patterned photoresist layer 120 as an etch mask. The patterned photoresist layer 120 can be formed using a suitable lithography technique such as extreme ultraviolet (EUV) lithography. The minimum half-pitch (critical size) in the patterned photoresist layer can range from about 5 nm to about 15 nm. Examples of hard mask materials include silicon oxide, silicon nitride, titanium nitride, etc., or combinations of multiple layers. In several other embodiments, the patterned hard mask layer 118 may be omitted from the etch mask 122. In FIG1C, a subtractive etching process is performed by patterned etching mask 122 to anisotropically remove the molybdenum layer 116, thereby further extending the recessed features 124 in FIG1B to form a second pattern of the recessed features, wherein each recessed feature 126 has a vertical sidewall and a bottom portion exposing one of the main surfaces of the underlying layer 114. Depending on the selectivity of the etching chemistry, specific portions of the etching mask 122 are etched, as shown in FIG1C. As described above, the embodiments of the etching process described in this disclosure employ a cyclic process to achieve the vertical sidewalls schematically depicted in FIG1C. In each cycle of the cyclic etching process, the process switches between a sidewall passivation step and an etching step for vertical removal of the molybdenum. Several different embodiments of this method for etching molybdenum are described in further detail below. The metal thickness is between about 50 nm and about 200 nm, and the minimum half-pitch in the pattern is between about 5 nm and about 15 nm. The aspect ratio of the recessed features 126 is within a range in which good control of the sidewall profile must be provided to make the process manufacturable. As shown in Figure 1D, after the subtractive etching process is completed, any residual portions of the etch mask 122 can be removed. Typically, a capping layer 128, such as another ILD layer, is formed over the patterned molybdenum layer 116 to cover the metal lines and fill the spaces between them. Figures 2A and 2B show the undesirable etching characteristics and defects caused by insufficient processing window during the etching step described with reference to Figure 1C for etching the recessed features 126 in the molybdenum layer 116 by an anisotropic dry etching process (e.g., conventional RIE process). Typically, the substrate is exposed to plasma in a processing chamber where molybdenum is etched using halogen-based chemicals (e.g., chlorine or fluorine). Plasma-excited halogen radicals react with molybdenum to form volatile byproducts, which may be pumped out of the chamber. In conventional RIE processes, anisotropy is achieved by applying a bias signal (e.g., DC bias or radio frequency (RF) bias) to the substrate and by using a plasma-excited gas mixture containing elements such as carbon, hydrogen, and oxygen in addition to halogens to induce chemical reactions that form solid byproducts (e.g., oxides and polymers). These solid byproducts are selectively deposited on vertical surfaces to protect the sidewalls of the recessed features; this technique is known as sidewall passivation. A passivation layer is selectively formed on the sidewalls by sputtering away the solid byproducts from the bottom of the recessed features using plasma-excited and vertically guided high-energy ions (e.g., argon ions) directed by a bias signal. Furthermore, surface bombardment with ions increases the reaction rate at that location by disrupting the bonds between molybdenum atoms, thus promoting bonding with halogen radicals. Therefore, ion bombardment at the bottom surface increases the vertical etching rate, while sidewall passivation decreases the lateral etching rate. A delicate balance must be struck between passivation and removal rates to provide a sufficiently wide processing window for robust manufacturing. With aggressive scaling of the lateral dimensions, the top opening of the recessed feature 126 becomes smaller, and the aspect ratio of the recessed feature 126 becomes higher. Therefore, opening a sufficiently wide processing window using conventional RIE methods becomes increasingly difficult. Figure 2A illustrates an example of undercut or lateral etching formed in a molybdenum layer using a halogen-poor chemical. A halogen-poor chemical refers to a gas mixture in which the relative halogen content is increased, resulting in more removal and less passivation. As illustrated in Figure 2A, insufficient sidewall passivation leads to excessive lateral etching. The combination of lateral etching and narrow linewidth can even result in broken-line defects. Figure 2B illustrates a different embodiment where a tapered sidewall profile and bottom foot defects are formed when the etching chemical is adjusted to promote sidewall passivation by depositing a protective layer of solid byproducts on the sidewalls. In the example shown in Figure 2B, the foot defects are severe enough to cause bridging defects. It should also be noted that poor sidewall profile control increases surface roughness along the sidewalls. This exacerbates the LER of the metal lines in the etched pattern, exceeding the LER of the lines in the patterned etch mask 122 introduced by lithography. Since line resistance depends on line width ( The increased LER (resistivity W) will increase the variance and average value of the resistance of short metal wires, even for a fixed resistivity ρ. Therefore, NWE, i.e., ρ = ρ ( W), the effect of LER on line resistance is aggravated. Furthermore, the high-frequency components of LER (i.e., roughness over a wire length of approximately 1 nm or less) increase diffuse edge scattering by reflecting electrons at random angles, independent of the incident angle, which is the opposite of specular edge scattering, where the reflection angle equals the incident angle. Specular scattering preserves electron momentum in the current direction, while diffuse scattering randomizes momentum, increasing ρ( W), thereby increasing NWE unintentionally. The embodiments of the invention described below provide greater flexibility in adjusting sidewall passivation and material removal, thus improving sidewall profile and sidewall profile control. Referring to Figures 3A-3F, an embodiment of the process flow 100 is described using the gas pulse cyclic etching technique 300. Figure 3A illustrates a flowchart summarizing the gas pulse cyclic etching technique 300, and Figures 3B-3F illustrate various cross-sectional views of the semiconductor device 320 during the various intermediate stages of patterning a molybdenum layer using the gas pulse cyclic etching technique 300. As shown in step 302 of the flowchart illustrated in Figure 3A and the cross-sectional view of the semiconductor device 320 in Figure 3B, the gas pulsed cyclic etching technology 300 receives an incoming substrate, similar to the substrate described above with reference to Figure 1B. The substrate includes an underlying layer 324, and a molybdenum layer 326 formed above the underlying layer 324. A patterned etch mask 332 is formed over the molybdenum layer 326. The pattern includes recessed features 334, each having an exposed surface of the molybdenum layer 326 as its bottom. In one embodiment, the patterned etch mask 332 includes a patterned photoresist layer 330 and a hard mask layer 328, for example, a tetraethyl orthosilicate (TEOS) hard mask layer 328. The hard mask layer 328 has been patterned using the photoresist layer 330 as a mask layer. In several other embodiments, the patterned photoresist layer 330 may not be present on the incoming substrate, having been removed during the process of patterning the hard mask layer 328. In several embodiments, the gas pulse cycle etching technique 300 includes an initial etching step (step 304 in FIG. 3A) that anisotropically etches a portion of the molybdenum layer 326 to extend the recessed feature 334, thereby forming the extended recessed feature 336, as shown in the cross-sectional view of the semiconductor device 320 illustrated in FIG. 3C. After the initial etching step (step 304) completes the formation of the extended recessed feature 336, a gas pulse cycle in the gas pulse cycle etching technique 300 can be performed. As shown in the flowchart in Figure 3A, each gas pulse cycle 312 includes two parts: a first part is a deposition step (step 306 and Figure 3D), and a second part is an etching step (step 310 and Figure 3F). In some embodiments, the gas pulse cycle etching technique 300 may have an optional through-etching step (step 308 and Figure 3E) inserted between step 306 and etching step 310 to expose a molybdenum surface located vertically below the material deposited on the bottom of the extended recessed feature 336. During the deposition steps of the gas pulsed cyclic etching technique 300 (Figures 3A-306 and 3D), the substrate is exposed to a plasma-excited deposition gas. As shown in the cross-sectional view of the semiconductor device 320 in Figure 3D, exposure to the plasma-excited deposition gas causes an etch protection layer 340 to form along the sidewalls and bottom of the recessed feature 336. A set of plasma processing parameters and gases for the deposition step in step 306 of the gas pulsed cyclic etching technique 300 can be optimized to deposit passivation solid byproducts for sidewall protection. In several embodiments, the deposition gas includes fluorocarbons (C600C6). x F y ) or hydrofluorocarbons (C x H y F z ), wherein the ratio of carbon atoms to fluorine atoms is greater than 1 / 4 and less than or equal to 1. Non-limiting examples of fluorocarbons may include C 2F 4. C 2F 6. C 4F 8. and C 4F 6. Deposited gases. Non-limiting examples of hydrofluorocarbons may include CHF. 3. CH 2F 2. and CH The deposition gas at 3F. Additional gases that can be included in the deposition gas are H₂. 2. O 2. A diluting inert gas (e.g., argon, helium, or nitrogen). Plasma processing parameters include a chamber pressure of approximately 30 mTorr to approximately 300 mTorr, an RF source power of approximately 50 W to approximately 800 W at a frequency of approximately 25 MHz to approximately 60 MHz, and a pulsed RF bias power of approximately 0 W (without RF bias) to approximately 100 W at a frequency of approximately 0.1 kHz to approximately 100 kHz. The substrate temperature is controlled between approximately 0°C and approximately 60°C. In these embodiments, the formed etch protection layer 340 (shown in FIG. 3D) is an organic film containing C and H atoms, for example, made of CH4. Organic films are formed by the deposition of chemical substances generated by the dissociation of 3F plasma. In several other embodiments, the deposition gas includes a sulfur-containing gas, such as sulfur dioxide (SO₂). 2) Carbonyl sulfide (COS), etc. In many embodiments, the deposition gas contains SO₂. 2 or COS, meaning only containing SO 2 or COS or containing SO 2 or COS. Additional gases that can be included in the deposition gas are H₂. 2. O 2. A diluting inert gas (e.g., argon, helium, or nitrogen). Plasma processing parameters include a chamber pressure of approximately 30 mTorr to approximately 300 mTorr, an RF source power of approximately 50 W to approximately 800 W at a frequency of approximately 25 MHz to approximately 60 MHz, and a pulsed RF bias power of approximately 0 W (without RF bias) to approximately 100 W at a frequency of approximately 0.1 kHz to approximately 100 kHz. The substrate temperature is controlled between approximately 0°C and approximately 60°C. In this embodiment, the formed etch protection layer 340 (as shown in Figure 3D) may be a sulfide or a group with highly oxidized sulfur groups, such as sulfonic acid groups and sulfates, which is formed from SO 2 / O 2 or SO 2 / O 2. It is produced by the deposition of chemical substances generated by plasma dissociation. In many embodiments, the deposition thickness of the etched protective layer 340 can be between approximately the thickness of one material monolayer and approximately several monolayers. In other words, the thickness ranges from 0.3 nm to approximately 2 nm. During the etching steps (Figures 3A-310 and 3F), the substrate is exposed to a plasma-excited etching gas. Typically, halogen-poor chemicals (chlorine or fluorine-based chemicals) are used to selectively remove metallic molybdenum to vertically extend the recessed features. For example, recessed feature 336 is further extended to form recessed feature 342, as shown in Figure 3F. Non-limiting examples of fluorine-containing gases that can be used as etching gases include F... 2. CF 4. NF 3. and SF 6. Non-limiting examples of chlorine-containing gases that can be used as etching gases include Cl. 2. CCl 4. and BCl 3. In some embodiments, the gaseous mixture may further include oxygen. In some embodiments, the gaseous mixture may further include an inert gas, such as argon. Molybdenum is removed anisotropically, with removal preferentially occurring above the horizontal surface. Anisotropy is achieved by applying a vertical bias signal to the substrate and by depositing a passivation etch protective layer on the vertical sidewalls. As described above, the bias causes ions (e.g., argon ions) to be vertically accelerated and collide with molybdenum atoms. The collisions enhance the etching rate at the bottom surface of the recessed feature (e.g., recessed feature 342). The RF bias signal may be DC, RF, or a pulsed RF signal. In some embodiments, a pulsed RF bias power of about 300 W to about 1200 W at a frequency of about 0.1 kHz to about 100 kHz may be used. Other plasma processing parameters include a chamber pressure of about 5 mTorr to about 100 mTorr and an RF source power of about 100 W to about 800 W at a frequency of about 25 MHz to about 60 MHz. The substrate temperature is controlled between approximately 0°C and approximately 60°C. The initial etching step (step 304 and Figure 3C) can be performed using a process similar to the etching step (step 310) used during gas pulse cycle 312. The initial etching step is a non-deposition step, for example, using a carbon-free plasma to excite the etching gas, such as Cl... 2. As shown in the cross-sectional view in Figure 3D, the bottom of the extended recessed feature 336 is covered by deposited solid byproducts to form an etch protective layer 340. In an exemplary embodiment of the gas pulsed cycle etching technique 300 described with reference to Figures 3A-3F, an optional through-etching step (steps 308 and 3E) has been inserted into the deposition step in step 306 and the etching step in step 310 (see the flowchart in Figure 3A) to expose the molybdenum surface vertically below the recessed feature 336. In Figure 3E, an optional through-etching step (step 308) has been performed, and a portion of the surface of the molybdenum layer 326 is once again exposed to the environment. In this exemplary embodiment, the through-etching in step 308 is a sputtering etching process using, for example, high-energy argon ions. Typically, ions are accelerated by a vertical electric field in a plasma sheath, which can be enhanced by applying a bias signal, such as a pulsed RF bias signal. In several embodiments, a pulsed RF bias power of about 50 W to about 1200 W at a frequency of about 0.1 kHz to about 100 kHz can be applied to the substrate. While the exemplary embodiment uses an optional through-etching step (step 308) to remove a portion of the etch protection layer 340 formed above the horizontal surface at the bottom of the recessed feature 336, in several other embodiments, the plasma parameters of the etching step in step 310 of each gas pulse cycle 312 can be adjusted to penetrate the etch protection layer 340. For example, the oxygen content and RF bias power can be increased to help remove the etch protection layer 340 from the horizontal surface. Note that some organic polymers in the etch protection layer 340 can be oxidized by oxygen free radicals. Therefore, care must be taken to prevent oxygen from ashing the etch protection layer 340 from the surface portion along the sidewalls, resulting in a loss of control over the sidewall profile. Once the etch protection layer 340 covering the bottom of the recessed feature 336 has been removed, the etching step in step 310 can continue to extend the recessed feature 336 further downward to form the recessed feature 342 in FIG. 3F. In the description of the gas pulse cycle technique 300 above, the steps in each gas pulse cycle 312, namely the deposition step in step 306 and the etching step in step 310, are different in time. Temporarily separating these two steps not only provides the advantage of independently optimizing the processing parameters of the passivation and material removal portions, but also provides the advantage of having a new etch protection layer that passivates the newly formed sidewall portions of the etched molybdenum layer. In several embodiments, the number of gas pulse cycles 312 may be a fixed number predetermined in the processing formulation. In several other embodiments, the processing may be terminated by a processing controller upon receiving an endpoint signal indicating that the lower layer 324 has been exposed. In several embodiments, an over-etching step may be performed after the gas pulse cycle etching technique 300 has been performed. In another embodiment of the process flow 100, the deposition-etch cycle etching technique uses atomic layer deposition (ALD) to form an etch protection layer. The ALD-based cycle etching technique 400 is summarized in the flowchart shown in Figure 4. The ALD-based cycle etching technique 400 is similar to the gas pulse cycle etching technique 300, except for the method of forming the etch protection layer. Furthermore, the optional through-etch step is not optional in the ALD-based cycle etching technique 400. These variations are indicated in bold in the flowchart of Figure 4. An etch protection layer is formed using ALD technology in the deposition step (step 406) of each deposition-etch cycle 412 of the ALD-based cyclic etch technology 400. The etch protection layer is a thin oxide layer containing an oxide that exhibits high etch resistance to plasma containing halogen radicals (e.g., chlorine and fluorine radicals). In one example, the oxide layer comprises silicon oxide (SiO₂). 2). As those skilled in the art will know, in ALD technology, the deposition reaction proceeds as two self-limiting half-reactions. In one example, the substrate can be exposed to a silicon precursor (e.g., SiCl₂) with or without plasma excitation. 4 or SiF 4) It is then exposed to an oxidant (e.g., plasma-excited oxygen) to deposit a silicon oxide layer. The etched protective layer can be conformally formed over the entire exposed surface of the substrate, including the horizontal surface of the molybdenum layer. Therefore, the through-etch step (step 408) may not be an optional step. Other steps in the ALD-based cyclic etching technique 400 have been described above in the context of the gas pulse cyclic etching technique 300 with reference to Figures 3A-3F. Although the deposition and etching steps in the aforementioned cyclic etching techniques can be performed in a separate processing chamber, such a process is time-consuming and expensive. In the embodiments disclosed herein, the cyclic etching techniques, namely gas pulse cyclic etching technique 300 and ALD-based cyclic etching technique 400, can be performed in a single processing chamber in conjunction with appropriate chamber conditioning steps within the processing flow. Figure 5 illustrates a flowchart of a cycle 500 of a cyclic etching process, such as a gas pulse cycle 312 (of a gas pulse cyclic etching technique 300) and a deposition-etch cycle 412 (of an ALD-based cyclic etching technique 400). Each cycle 500 has a time-separated deposition step 502 and an etching step 508. To reduce variability in the process, deposition step 502 and etching step 508 include power stabilization and gas flow stabilization periods, as determined by the process controller. Several other actions can be taken to further reduce process-induced variability, as shown in the flowchart in Figure 5. A gas purge step 504 can be performed after each deposition step 502 to completely remove contaminants and gaseous reaction byproducts. Similarly, another gas purge step 510 can be performed after each etching step 508. In several embodiments, a chamber pre-coating step 506 can be performed before etching step 508 to ensure that the initial state of the processing chamber is the same each time etching step 508 is performed. The chamber pre-coating step deposits a coating on the walls of the processing chamber. The coating may comprise silicon, oxides (e.g., silicon oxide), or carbon deposited using plasma treatment. The chamber pre-coating step 506 is performed with a wafer covering a chuck (substrate holder) to avoid deposition on the chuck. For example, a blank wafer may be placed on the chuck prior to chamber pre-coating step 506. These additional precautions help meet the stringent process control specifications required for integrating metallic molybdenum into high-volume IC manufacturing. As described above, the embodiments using patterned molybdenum cyclic etching processes offer several advantages by separating the passivation portion from the material removal portion. These advantages include reduced undercut, low LER, vertical edge profile, and good control over etch rate and etch selectivity. However, it should be understood that the methods described in this disclosure allow for partial time overlap between deposition and etching. (In embodiments including the gas pulse cycle 312 of step 308, etch refers to the through-etch step in step 308.) This summary outlines exemplary embodiments of the invention. Other embodiments may also be understood from the entirety of this specification and the claims set forth herein. Example 1: A method for processing a substrate, comprising: providing a substrate including an etching mask above a molybdenum layer in a recessed feature; exposing the substrate to a plasma-induced deposition gas, the plasma-induced deposition gas forming an etching protective layer on a sidewall of the recessed feature; exposing the substrate to a plasma-induced etching gas, the plasma-induced etching gas etching the molybdenum layer according to the etching mask, wherein the exposure steps are performed alternately multiple times. Example 2, as in Example 1, wherein the plasma-induced deposition gas includes fluorocarbons (C). x F y ) or hydrofluorocarbons (C x H y F z ), in which the ratio of carbon to fluorine atoms is greater than 1 / 4 and less than or equal to 1. Example 3, as in Example 1 or 2, wherein the plasma-induced deposition gas includes a sulfur-containing gas. Example 4: The method as in Examples 1 to 3, wherein the sulfur-containing gas includes SO₂. 2 and COS gas. Example 5, as in Examples 1 to 4, wherein the plasma-excited etching gas includes a halogen-containing gas. Example 6, as in Examples 1 to 5, wherein the halogen-containing gas includes F 2. CF 4. NF 3. SF 6. Cl 2. CCl 4. or BCl 3. Gases. Example 7, as in Examples 1 to 6, wherein the plasma-induced etching gas further includes an oxygen-containing gas. Example 8, as in Examples 1 to 7, wherein the plasma-induced etching gas further includes argon. Example 9, the method of Examples 1 to 8, further includes: performing a through-etching step that etches through the etch protection layer at the bottom of the recessed feature. Example 10, the method of Examples 1 to 9, wherein exposing the substrate to the plasma-induced etching gas further includes applying a bias signal to the substrate. Example 11. A method of substrate processing, comprising: providing a substrate including an etch mask above a molybdenum layer in a recessed feature; depositing an etch protection layer in the recessed feature, wherein the etch protection layer includes an oxide layer; performing a through-etch step, the through-etch step etching through the etch protection layer to the bottom of the recessed feature; and exposing the substrate to a plasma-excited etching gas, the plasma-excited etching gas etching the molybdenum layer according to the etch mask. Example 12, the method of Example 11, wherein depositing the etch protective layer includes exposing the substrate to a silicon-containing precursor and an oxidant to form a silicon oxide layer. Example 13, the method of Example 11 or 12, wherein depositing the etch protective layer includes alternately exposing the substrate to a silicon-containing precursor and an oxidant to form a silicon oxide layer. Example 14, the method of Examples 11 to 13, wherein the plasma-excited etching gas includes a halogen-containing gas. Example 15, as in Examples 11 to 14, wherein the halogen-containing gas includes F 2. CF 4. NF 3. SF 6. Cl 2. CCl 4. or BCl 3. Gases. Example 16, the method of Examples 11 to 15, wherein the plasma-induced etching gas further includes an oxygen-containing gas. Example 17. A method of substrate processing, comprising: providing a substrate including an etch mask above a molybdenum layer in a recessed feature; depositing an etch protection layer on a sidewall of the etch mask, wherein the etch protection layer includes an oxide layer; and exposing the substrate to a plasma-excited etching gas that etches the molybdenum layer according to the etch mask, wherein the deposition and exposure are performed alternately multiple times. Example 18, the method of Example 17, wherein exposing the substrate to the plasma-induced etching gas further includes applying a bias signal to the substrate. Example 19, the method of Example 17 or 18, wherein depositing the etch protective layer includes exposing the substrate to a silicon-containing precursor and an oxidant to form a silicon oxide layer. Example 20, the method of Examples 17 to 19, wherein depositing the etch protective layer includes alternately exposing the substrate to a silicon-containing precursor and an oxidant to form a silicon oxide layer. Example 21, the method of Examples 17 to 20, wherein the plasma-excited etching gas includes a halogen-containing gas. Example 22, as in Examples 17 to 21, wherein the halogen-containing gas includes F 2. CF 4. NF 3. SF 6. Cl 2. CCl 4. or BCl 3. Gases. Example 23, the method of Examples 17 to 22, wherein the plasma-induced etching gas further includes an oxygen-containing gas. Example 24, the method of Examples 17 to 23, further includes: performing a through-etching step that etches through the etch protection layer at the bottom of the recessed feature. Example 25, the method of Examples 17 to 24, wherein both the deposition and the exposure are performed in a processing chamber, and wherein the method further includes performing a chamber pre-coating step after the deposition and before the exposure, the chamber pre-coating step depositing a coating on the walls of the processing chamber. Although the invention has been described with reference to illustrative embodiments, this section on embodiments is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art from this section on embodiments. Therefore, the appended claims are intended to cover any such modifications or embodiments. 100: Processing flow; 102-106: Steps; 110: Semiconductor device; 110 112: Substrate layer; 114: Underlying layer; 116: Molybdenum layer; 118: Patterned hard mask layer; 120: Patterned photoresist layer; 122: Etching mask; 124: Recessed feature; 126: Recessed feature; 128: Cover layer; 300: Gas pulsed cyclic etching technology; 302-312: Steps; 320: Semiconductor device; 322: Patterned etched mask; 324: Underlying layer; 326: Molybdenum layer; 328: Hard mask layer; 330: Patterned photoresist layer; 332: Patterned etched mask; 334: Recessed feature; 336: Extended recessed feature; 340: Etching protective layer; 342: Recessed feature; 400: ALD-based cyclic etching technology; 406-408: Steps; 412: Deposition-etching cycle; 500: Cycle; 502: Deposition step; 504: Gas cleaning step; 506: Pre-coating step; 508: Etching step; 510: Gas cleaning step. 320: Semiconductor device 322: Patterned Etching Mask 324: Underlying layer 326: Molybdenum layer 328: Hard mask layer 330: Patterned photoresist layer 332: Patterned Etching Mask 336: Extended concave feature 340: Etching protective layer

Claims

1. A method for processing a substrate, comprising: A substrate is provided, the substrate including an etching mask above a molybdenum layer in a recessed feature; the substrate is exposed to a plasma-induced deposition gas forming an etching protective layer on a sidewall of the recessed feature; and the substrate is exposed to a plasma-induced etching gas etching the molybdenum layer according to the etching mask, wherein the exposure steps are performed alternately multiple times by stopping exposure to the plasma-induced deposition gas and exposing to the plasma-induced etching gas, and stopping the plasma-induced etching gas and exposing to the plasma-induced deposition gas, thereby separating the exposure to the plasma-induced deposition gas and the exposure to the plasma-induced etching gas in time, wherein the plasma-induced deposition gas includes a fluorocarbon (CxFy) or a hydrofluorocarbon (CxHyFz), and wherein the plasma-induced etching gas includes a halogen-containing gas.

2. The method of claim 1, wherein the ratio of carbon to fluorine atoms is greater than 1 / 4 and less than or equal to 1.

3. The method of claim 1, wherein the plasma-induced deposition gas includes a sulfur-containing gas.

4. The method of claim 3, wherein the sulfur-containing gas includes SO2 or COS gas.

5. The method of claim 1, wherein both exposure to the plasma-induced deposition gas and exposure to the plasma-induced etching gas are performed in a processing chamber, and wherein the method further comprises: After exposure to the plasma-induced deposition gas and before exposure to the plasma-induced etching gas, a chamber pre-coating step is performed, which deposits a coating onto the wall of the processing chamber.

6. The method of claim 1, wherein the halogen-containing gas includes Cl2, CCl4, or BCl3 gas.

7. The method of claim 1, wherein the halogen-containing gas includes F2, CF4, NF3, and SF6.

8. The method of claim 1, wherein the plasma-induced etching gas further comprises an oxygen-containing gas.

9. The method of claim 1, wherein the plasma-induced etching gas further comprises argon.

10. A method for processing a substrate, comprising: A substrate is provided in a processing chamber, the substrate comprising an etch mask above a molybdenum layer in a recessed feature; an etch protection layer comprising an oxide layer is deposited in the recessed feature; after the deposition, a through-etch step is performed, the through-etch step etching through the etch protection layer at the bottom of the recessed feature; after the deposition, a coating is applied to the wall of the processing chamber; and after the coating, the substrate is exposed to a plasma-excited etching gas, the plasma-excited etching gas etching the molybdenum layer according to the etch mask.

11. The method of claim 10, wherein depositing the etch protective layer includes exposing the substrate to a silicon-containing precursor and an oxidant to form a silicon oxide layer.

12. The method of claim 10, wherein depositing the etch protective layer includes alternately exposing the substrate to a silicon-containing precursor and an oxidant to form a silicon oxide layer.

13. The method of claim 10, wherein the plasma-induced etching gas includes a halogen-containing gas.

14. The method of claim 13, wherein the halogen-containing gas includes F2, CF4, NF3, SF6, Cl2, CCl4, or BCl3 gas.

15. A method for processing a substrate, comprising: A substrate is provided, the substrate comprising an etch mask above a molybdenum layer in a recessed feature; A deposition gas and an etching gas are pulsed to perform a gas pulse cycle process, each cycle comprising: depositing an etch protection layer on a sidewall of the etch mask, wherein the etch protection layer comprises an oxide layer; exposing the substrate to a plasma-induced etching gas formed by the etching gas, the plasma-induced etching gas etching the molybdenum layer according to the etch mask, wherein the deposition and exposure are alternately performed during each cycle to temporally separate the exposure to the deposition gas and the exposure to the plasma-induced etching gas during the deposition, wherein both the deposition and the exposure are performed in a processing chamber; and performing a chamber pre-coating step after the deposition and before the exposure, the chamber pre-coating step depositing a coating on the wall of the processing chamber.

16. The method of claim 15, wherein exposing the substrate to the plasma-induced etching gas further comprises applying a bias signal to the substrate.

17. The method of claim 15, wherein depositing the etch protective layer includes exposing the substrate to a silicon-containing precursor and an oxidant to form a silicon oxide layer.

18. The method of claim 15, wherein depositing the etch protective layer includes alternately exposing the substrate to a silicon-containing precursor and an oxidant to form a silicon oxide layer.

19. The method of claim 15, wherein the plasma-induced etching gas includes a halogen-containing gas.

20. The method of claim 15 further includes: A penetration etching step is performed, which etches through the etch protection layer at the bottom of the recessed feature.

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