Passivation-enhanced image sensor and surface-passivation method

Abstract

An image sensor includes a semiconductor substrate and a multilayer film. The semiconductor substrate includes a photodiode and a back surface, the back surface having a recessed region surrounding the photodiode. The multilayer film is on and conforms to the recessed region and includes an N-layer group of adjacent high-k material layers. Each pair of adjacent high-k material layers in the N-layer group includes (i) an outer layer having an external fixed charge density, and (ii) an inner layer having an internal fixed charge density located between the outer layer and the recessed region. Each of the external fixed charge density and the internal fixed charge density is negative. The negativeness of the internal fixed charge density is greater than the negativeness of the external fixed charge density.

Description

[Technical Field]

[0001] This invention relates to an image sensor, and more particularly to a passivation-enhanced image sensor and a surface passivation method. [Previous Technology]

[0002] Camera modules in commercial products such as standalone digital cameras, mobile devices, automotive components, and medical devices include image sensors. One type of image sensor is a complementary metal-oxide-semiconductor (CMOS) image sensor, which includes a semiconductor substrate in which a pixel array is formed. Images generated by CMOS image sensors may include artifacts, some of which are caused by one or both of electrical crosstalk and optical crosstalk between adjacent pixels in the pixel array. Measures to reduce this crosstalk may introduce other image artifacts. [Summary of the Invention]

[0003] In some CMOS image sensors, each pixel formed in a semiconductor substrate is optically and electrically isolated from adjacent pixels by a deep trench isolation (DTI) structure formed in a trench surrounding the photodiode of the pixel and including multiple DTI trenches formed in one surface of the semiconductor substrate. The trench is created by etching a portion of the back surface of one of the semiconductor substrates, resulting in a recessed region defining the trench. This etching creates defects in the recessed region, which increases the dark current detected by pixels near the defects. For example, plasma etching causes defects by disrupting the semiconductor lattice, such that the recessed surface includes dangling bonds and / or charge trap sites. The increased dark current results in "white pixel" defects, where a pixel outputs a large signal regardless of the illumination above it. White pixel defects degrade image quality.

[0004] A high-k dielectric film on the recessed region and the back surface passivates these surfaces; this reduces white pixel defects. This embodiment includes a multilayer film, wherein the relative charge density of adjacent layers generates dipoles at the interface of adjacent layers. The electric dipole moment of each dipole points away from the recessed surface. That is, the negative end of each dipole is closer to the recessed region and therefore between the recessed region and the positive end of the dipole. The negative end of the dipole attracts holes in the semiconductor substrate to the recessed region. This diffusion of holes reduces the height of the potential barrier at the interface between the semiconductor substrate (recessed region) and the multilayer film. The reduced barrier height induces electrons to tunnel from the semiconductor substrate to the dielectric filling material on the recessed region, which increases the hole density in the induced hole accumulation region around the recessed region and thus enhances the passivation around the recessed region.

[0005] In a first aspect, an image sensor includes a semiconductor substrate and a multilayer film. The semiconductor substrate includes a photodiode and a back surface having a recessed region surrounding the photodiode. The multilayer film is on and conforms to the recessed region and includes an N-layer group of adjacent high-k material layers. Each pair of adjacent high-k material layers in the N-layer group includes (i) an outer layer having an external fixed charge density, and (ii) an inner layer located between the outer layer and the recessed region having an internal fixed charge density. Each of the external fixed charge density and the internal fixed charge density is negative. The degree of negativeness of the internal fixed charge density is greater than the degree of negativeness of the external fixed charge density.

[0006] In the second viewpoint, a surface passivation method includes depositing a multilayer film on a surface.

Implementation Method

[0015] The terms "an example" or "an embodiment" used in this specification mean that a particular feature, structure, or characteristic described in connection with that example is included in at least one example of the invention. Therefore, the appearance of the phrases "in an example" or "in an embodiment" throughout this specification does not necessarily refer to the same example. Furthermore, in one or more examples, a particular feature, structure, or characteristic may be combined in any suitable manner.

[0016] For ease of description, spatially relative terms such as “below,” “under,” “down,” “below,” “above,” “up,” etc., may be used herein to describe the relationship of one element or feature as shown in the accompanying drawings to another element(s) or feature(s). It should be understood that, in addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, then the element described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Thus, the terms “below” and “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein are interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0017] The term semiconductor substrate can refer to a substrate formed of one or more semiconductors, such as silicon, silicon-germanium, germanium, gallium arsenide, indium gallium arsenide, III-V compounds, and other semiconductor materials known to those skilled in the art. The term semiconductor substrate can also refer to a substrate formed of one or more semiconductors that has undergone prior process steps to form regions and / or junctions in the substrate. Semiconductor substrates can also include various features, such as doped and undoped semiconductors, silicon epitaxial layers, and other semiconductor structures formed on the substrate. It should be noted that, herein, element names and symbols are used interchangeably (e.g., Si and silicon); both have the same meaning.

[0018] FIG1 depicts a camera 195 for imaging a scene. The camera 195 includes an image sensor 100, which includes a semiconductor substrate 110. The constituent elements of the semiconductor substrate 110 may include at least one of silicon and germanium. The semiconductor substrate 110 includes a pixel array 112A. The image sensor 100 may be part of a wafer-level package or a wafer-on-a-chip package. The camera 195 is shown as an element of a handheld device; however, it should be understood that other devices such as security devices, automotive cameras, drone cameras, endoscopes, etc., may also utilize the camera 195 without departing from the scope of the invention.

[0019] Figure 2 is a schematic cross-sectional view of the semiconductor substrate 200, which may be a component of the image sensor 100. The cross-section shown in Figure 2 is parallel to the plane formed by the orthogonal axes A1 and A3, referred to below as the xz plane, and axes A1 and A3 are both orthogonal to axis A2.

[0020] In this document, the xy plane is formed by orthogonal axes A1 and A2, and a plane parallel to the xy plane is called a transverse plane. Unless otherwise stated, the height and depth of an object in this document refer to the extent of the object along axis A3. In this document, references to axes x, y, or z refer to axes A1, A2, and A3, respectively. Furthermore, in this document, the horizontal plane is parallel to the xy plane, the width refers to the extent of the object along the x or y axis, and the vertical direction is along the z axis.

[0021] The semiconductor substrate 210 includes a front surface 211, a rear surface 219 opposite to the front surface 211, and a photodiode region 212 between surfaces 211 and 219. The semiconductor substrate 210 has a thickness 216, which may be between 2 micrometers and 7 micrometers. The rear surface 219 has a recessed region 219R surrounding the photodiode 212 (1). In some embodiments, the semiconductor substrate 200 includes additional photodiodes 212, shown as photodiodes 212 (2) and 212 (3) in FIG. 2.

[0022] A recessed region 219R forms a trench 220 in the semiconductor substrate 210. The trench 220 has a width 221 in a plane, such as a horizontal plane, that includes at least a portion of the rear surface 219. The width 221 is in at least one of directions A1 and A2, and can be between 0.10 micrometers and 0.15 micrometers. The trench 220 has a depth 223 relative to a plane spanning the trench 220, and includes at least a portion of the rear surface 219. Depending on the thickness of the semiconductor substrate 210, the depth 223 can be between 1.5 micrometers and 3.0 micrometers.

[0023] Each photodiode region 212 has a width 213 and is at least partially located in one region of the semiconductor substrate 210. This region has a width 215. The width 213 is less than or equal to the width 215. The width 213 may be equal to the width 215 to (a) increase the volume of the photodiode 212 to maximize charge accumulation capacity, or (b) increase the width 221 for isolation.

[0024] FIG3 is a schematic cross-sectional view of a semiconductor substrate 300, which is an example of a semiconductor substrate 200. The cross-sectional view of FIG3 is in the horizontal cross-sectional plane 3-3' shown in FIG2. In some embodiments, the cross-sectional plane 3-3' is parallel to the rear surface 219.

[0025] The semiconductor substrate 300 has a rear surface 319 and includes an array of photodiodes 212, which includes photodiodes 212 (1-9). The rear surface 319 is one example of the rear surface 219 and includes a recessed region 319R, which is one example of the recessed region 219R. The recessed region 319R forms a grid trench to separate adjacent photodiodes 212. The recessed region 319R may include one of a plurality of recessed segments that together form a grid trench between each pair of adjacent photodiodes 212. The width of each recessed segment is a width 221. For example, FIG3 shows a recessed segment 318(1) between photodiodes 212(1) and 212(2) and a recessed segment 318(7) between photodiodes 212(1) and 212(7).

[0026] Figures 4 and 5 are schematic cross-sectional views of one of the passivation-enhanced image sensors 400 (hereinafter referred to as image sensors 400). The cross-sectional view of Figure 5 is in the cross-sectional plane 5-5' of Figure 4. In the following description, Figures 4 and 5 are preferably viewed together.

[0027] The image sensor 400 includes a semiconductor substrate 210 and a multilayer film 430. The multilayer film 430 is on and conforms to the recessed region 219R, and includes a plurality of high-k material layers 431. The high-k material layers 431 include layers 431 (1-3), and in some embodiments, include at least one additional layer 431, such as layer 431 (4) shown in FIG. 4. Each high-k material layer 431 may be formed of one of aluminum oxide, hafnium dioxide, zirconium dioxide, tantalum pentoxide, and gallium oxide.

[0028] The multilayer film 430 may extend from the recessed region 219R such that a portion of the multilayer film 430 is above a portion of the rear surface 219, in at least one of the following cases: (a) parallel to the front surface 211, (b) adjacent to the recessed region 219R, and (c) above the photodiode 212.

[0029] Adjacent material layers 431 can be classified as belonging to one of N layers of adjacent high-k material layers 431, where the number of layers N is a positive integer. In some embodiments, the number of layers N is the total number of layers of the multilayer film 430.

[0030] Each pair of adjacent high-κ material layers 431 in the same layer group of N layers includes (i) an outer layer and (ii) an inner layer, located between the outer layer and the recessed region 219R. Reiterating, the distance between the inner layer and the recessed region 219R is less than the distance between the outer layer and the recessed region 219R. The outer layer and the inner layer have an external fixed charge density and an internal fixed charge density, respectively. Each of the external fixed charge density and the internal fixed charge density is negative. The negativeness of the internal fixed charge density is greater than the negativeness of the external fixed charge density (>), which enhances passivation at the recessed region 219R by forming the aforementioned dipoles at one interface of adjacent layers 431. The corresponding charge densities of layers 431 (1-4) are represented as , , and , respectively, where each is negative.

[0031] In some embodiments, the internal fixed charge density exceeds the external fixed charge density by at least twice (≥ 2) to ensure sufficient passivation. To improve passivation, it can be at least 5.

[0032] The charge density difference between the inner and outer layers allows the formation of interface dipoles with a specific orientation, where the negative charge of the dipoles faces the substrate-trench interface and the positive charge faces the outer layer. This orientation reduces the barrier height between the semiconductor substrate 210 and the recessed region 219R, which (i) enables electron tunneling and (ii) creates a hole-rich region near the substrate-trench interface, thereby enhancing the passivation of defects and traps caused by plasma etching damage on the trench sidewall surface.

[0033] For example, Figure 4 illustrates a dipole 433(1) formed at the interface between layers 431(1) and 431(2), and a dipole 433(3) formed at the interface between layers 431(3) and 431(4). The dipoles 433(1) and 433(3) allow electrons generated by etching damage to move away from the photodiode 212 and toward the recessed region 219R. Without the dipoles, these electrons would instead move toward the photodiode 212 and generate a dark current, i.e., electrons generated in the absence of light.

[0034] In one embodiment, the multilayer film 430 includes only one layer group (e.g., N=1), and the high-κ material layer 431 includes three layers 431 (1-3). The three layers 431 (1-3) include two adjacent layer pairs, each layer pair including layer 431 (2). The first layer pair includes layer 431 (1) as an inner layer and layer 431 (2) as an outer layer, wherein the negativeness of charge density is greater than the negativeness of charge density: >. The second layer pair includes layer 431 (2) as an inner layer and layer 431 (3) as an outer layer, wherein the negativeness of charge density is greater than the negativeness of charge density: >. Therefore, the negativeness of charge density of layers 431 (1-3) increases as a function of the proximity of the layers to the recessed region 319R: >>. When layer 431 includes layer 431 (4), layer 431 includes a third layer pair. The third layer includes an inner layer 431(3) and an outer layer 431(4), wherein the negative value of the charge density is greater than the negative value of the charge density: >.

[0035] In some embodiments, the multilayer film 430 comprises at least two layers (e.g., N=2), and the total number of adjacent high-k material layers in each layer group is greater than or equal to 2. For example, the first layer group comprises layers 431(1,2), where > and the second layer group comprises layers 431(3,4), where >. In this embodiment, layers 431(2) and 431(3) are in different layer groups and therefore do not need to be suitable as a layer pair. Therefore, the negativeness of the charge density of layer 431(2) may, but is not necessary, be greater than the negativeness of the charge density of layer 431(3). For example, the charge densities may be equal, or the negativeness of the charge density of layer 431(2) may be less than the negativeness of the charge density: >.

[0036] Layers 431 (1-4) have corresponding thicknesses 432 (1-4). Each of the thicknesses 432 may exceed 3 nanometers to ensure sufficient fixed charge to form dipoles at the interfaces between adjacent layers 431 (e.g., between layers 431 (1) and 431 (2), between layers 431 (2) and 431 (3), and between layers 431 (3) and 431 (4)). In some embodiments, the total thickness of the multilayer film 430 is less than half the trench width 221 to ensure that the multilayer film 430 does not completely fill the trench 220, such that the trench 220 can accommodate at least one of an antireflective coating and a dielectric filler material (e.g., an oxide). For this purpose, each of the thicknesses 432 may be less than 30 nanometers. In some embodiments, the total thickness of the multilayer film 430 is equal to half the trench width 221, such that the multilayer film 430 fills the trench 220. For example, when the trench width 221 is 0.15 micrometers, the total thickness of the multilayer film 430 is 75 nanometers.

[0037] Each of the N-layer groups can be a single layer pair, such that each of the N-layer groups includes a single pair of adjacent high-κ material layers 431, wherein the inner and outer layers have corresponding first and second thicknesses. The first and second thicknesses can be equal. The first thickness can exceed the second thickness, which increases the strength of the dipoles 433 and ensures that their associated dipole moments point away from the recessed region 219R. The first thickness can exceed the second thickness by 1.5 to 2.0 times. Given an appropriate difference between the charge density of the inner layer and the charge density of the outer layer, this difference is sufficient to ensure a better dipole orientation without occupying excessive volume within the trench 420.

[0038] In one embodiment, the multilayer film 430 includes two layers: the first layer group includes only layers 431(1,2), where > and the second layer group includes only layers 431(3,4), where >. In this embodiment, thickness 432(1) exceeds thickness 432(2), and thickness 432(3) exceeds thickness 432(4).

[0039] In some embodiments, the multilayer film 430 includes layers 431(1-3) forming two layer groups. The first layer group includes only layers 431(1,2), where > and the second layer group includes only layers 431(2,3), where >. In such embodiments, thickness 432(1) exceeds thickness 432(2), thickness 432(2) exceeds thickness 432(3), and the multilayer film 430 may or may not include layer 431(4).

[0040] When the multilayer film 430 comprises two layers, the first total thickness of the “outer” layer group farther from the recessed region 219R may exceed the second total thickness of the “inner” layer group closest to the recessed region 219R. Because the outer layer group is farther from the recessed region 219R, it may be necessary to form a larger dipole moment in the outer layer group than in the inner layer group to achieve the same or equivalent passivation effect with the outer layer group. In some embodiments, the first layer group comprises layers 431(1,2) and the second layer group comprises layers 431(3,4), wherein the sum of thicknesses 432(3) and 432(4) exceeds the sum of thicknesses 432(1) and 432(2).

[0041] In some embodiments, and for the same passivation motivation, the ratio of thicknesses 432(3) to 432(4) exceeds the ratio of thicknesses 432(1) to 432(2). For example, the ratio may exceed the ratio by less than or equal to 2.

[0042] When the multilayer film 430 comprises two layers, the multilayer film 430 may include a third layer adjacent to the second layer, wherein the third layer has a third total thickness. Due to the passivation motivation described above, the third total thickness may exceed the second total thickness. For example, when the second layer comprises layers 431(3) and 431(4), the multilayer film 430 may include an additional layer on top of layer 431(4), wherein the third total thickness of the additional layer exceeds the sum of thicknesses 432(3) and 432(4). Figure 8 illustrates layers 831(5,6), which together are an example of such an additional layer.

[0043] In some embodiments, one of the N layers of the multilayer film 430 is a layer pair, wherein the inner layer of the layer pair is formed of alumina and the outer layer of the layer pair is formed of hafnium dioxide. The layer pair may be layers 431(1,2), wherein the inner layer and the outer layer are layers 431(1) and 432(2), respectively. Additionally or alternatively, the layer pair may be layers 431(3,4), wherein the inner layer and the outer layer are layers 431(3) and 432(4), respectively.

[0044] Each of the N layers in the multilayer film 430 may be a corresponding single pair of adjacent high-κ material layers, wherein N is at least 2, and the inner layer of the layer pair is formed of alumina, while the outer layer of the layer pair is formed of hafnium dioxide. For example, each of layers 431(1) and 432(3) may be formed of alumina, and each of layers 431(2) and 431(4) may be formed of hafnium dioxide.

[0045] In some embodiments, the N-layer group of the multilayer film 430 includes (i) a first layer pair, wherein the inner and outer layers are formed of a first material and a second material, respectively, and (ii) a second layer pair above the first layer pair, wherein the inner and outer layers are formed of a third material and a fourth material, respectively. At least one of the following conditions exists: (i) the third material is different from the first material, and (ii) the fourth material is different from the second material. The first layer pair may be layers 431(1,2), wherein the inner and outer layers are layers 431(1) and 432(2), respectively. The second layer pair may be layers 431(3,4), wherein the inner and outer layers are layers 431(3) and 432(4), respectively.

[0046] Figure 6 is a cross-sectional schematic diagram of an image sensor 600, which is an example of an image sensor 400, including at least one of a multilayer film 630, an anti-reflective coating 640, and a dielectric 650. The multilayer film 630 is an example of a multilayer film 430, wherein each layer of the multilayer film 630 is a continuous layer extending from the recessed region 219R to the rear surface 219 and covering the photosensitive area of ​​the photodiode 212.

[0047] The anti-reflective coating 640 is a continuous layer lining the recessed region 219R and the back surface 219, and covers the photosensitive area of ​​the photodiode 212 and increases the light transmitted to the photodiode 212. A dielectric 650 fills the trench 220 and electrically and optically isolates adjacent photodiodes 212. The dielectric 650 may include silicon oxide or a dielectric material with a refractive index lower than that of the semiconductor substrate 210 to induce total internal reflection. The anti-reflective coating 640 is attached to a multilayer film 630 on the recessed region 219R and the back surface of the semiconductor substrate 210. The dielectric 650 fills the trench 220 such that the multilayer film 630 is located between the dielectric 650 and the semiconductor substrate 210.

[0048] The multilayer film 630 and the anti-reflective coating 640 have corresponding thicknesses 632 and 642. The thickness 642 may exceed the thickness 632. In some embodiments, the thickness 642 is uniform; however, in other embodiments, the thickness 642 is non-uniform, such that the anti-reflective coating 640 has a vertical thickness 642V in direction A3 and a horizontal thickness 642H in at least one of directions A1 and A2 (adjacent to the recessed region 219R).

[0049] When the thickness 642 is non-uniform, the horizontal thickness 642H can be less than the vertical thickness 642V. The advantage of this thickness difference is that a desired transmittance coefficient is achieved for the thicker areas, while the thinner areas accommodate sufficient spacing to include the required number of layer groups and the number of layers in each layer group of the multilayer film 630. In such an embodiment, the thickness 632 can exceed the horizontal thickness 642H and be less than the vertical thickness 642V. Alternatively, the thickness 642 of a portion of the antireflective coating 640 on the rear surface 219 can exceed the thickness 632 of a portion of the multilayer film 630 on the rear surface 219, while the thickness 642 of the portion of the antireflective coating 640 adjacent to the recessed region 219R can be less than the thickness 632 of the portion of the multilayer film 630 adjacent to the recessed region 219R.

[0050] Figure 7 is a schematic cross-sectional view of a dark current suppression image sensor 700, which is an image sensor 400 with the addition of a metal grid 762, a color filter array 760A, and a microlens array 770A. The image sensor 700 includes at least one of an anti-reflective coating 640 and a dielectric 650.

[0051] A metal grid 752 is aligned with the recessed region 219R and the dielectric 650 (when present) to define a plurality of apertures, each aperture aligned with a corresponding photodiode 212. A color filter array 760A includes a plurality of color filters 760, each of which is aligned with a corresponding photodiode 212 and is located within a corresponding aperture of one of the metal grids 762. The metal grid 752 separates adjacent color filters 760. Each color filter 760 may be one of a red, blue, green, cyan, magenta, yellow, infrared, or panchromatic color filter. A microlens array 770A includes a plurality of microlenses 770, each of which is disposed on a corresponding color filter 760 for guiding incident light (e.g., light passing through an imaging lens) to the corresponding photodiode 212.

[0052] The image sensor 700 may include a buffer layer 750 located between the multilayer film 430 and a plane including one of two metal grids 762. The buffer layer 750 is also located between the color filter array 760A and the multilayer film 430, as with the metal grids 762. When the image sensor 700 includes both the anti-reflective coating 640 and the buffer layer 750, the buffer layer 750 is located between the anti-reflective coating 640 and the color filter array 760A. The buffer layer 750 may be formed of oxide and separates the metal grids 762 from the anti-reflective coating 640, and provides a flat surface for the fabrication processes (material deposition and etching) of the metal grids 762 and the color filter array 760A.

[0053] Figure 8 is a cross-sectional schematic diagram of a passivation-enhanced image sensor 800 (hereinafter referred to as image sensor 800). The image sensor 800 is an example of an image sensor 400 including a multilayer film 830. The multilayer film 830 is an example of a multilayer film 430 and includes layers 831 (1-6), each of which is an example of layer 431. Layers 831 (1-4) are examples of layers 431 (1-4), and their corresponding charge densities are represented as in the multilayer film 430. Layers 831 (5) and 831 (6) have corresponding charge densities, each of which is negative.

[0054] In some embodiments, at least one of the following conditions exists: (i) exceeding, and (ii) exceeding, which enhances the passivation at the recessed region 219R as described above. In some embodiments, >> and >>, such that the multilayer film 830 includes two groups of layers: a first group including layers 831 (1-3), and a second group including layers 831 (4-6). Each of the charge densities, can be equal to, and, respectively. In some embodiments, >, such that the degree of negativity of the charge density of layers 831 (1-6) increases as a function of the proximity of the layer to the recessed region 219R: >>>>>>.

[0055] At least one property of layer 831(4,5,6), such as material, thickness, and charge density, may be the same as that of the corresponding layer 831(1,2,3). That is, for at least one of =1, =2, and =3, at least one of the following properties of layers 831(1) and 831(2) may be the same: material, thickness, and charge density. In some embodiments, the total thickness of layers 831(4,5,6) exceeds the total thickness of layers 831(1,2,3).

[0056] Figure 9 is a flowchart illustrating one aspect of a surface passivation method 900. Method 900 includes step 910. Step 910 includes depositing a multilayer film on a surface, the multilayer film comprising N groups of adjacent high-k material layers. Each pair of adjacent high-k material layers in the same group of N layers includes (i) an outer layer having an external fixed charge density, and (ii) an inner layer located between the outer layer and a recessed region of the surface and having an internal fixed charge density. Each of the external fixed charge density and the internal fixed charge density is negative. The degree of negativity of the internal fixed charge density is greater than the degree of negativity of the external fixed charge density. In the example of step 910, the multilayer film 430 is deposited on the recessed region 219R. Step 910 may also include depositing the multilayer film 430 on a portion of a rear surface 219, the portion of which is at least one of the following: (a) parallel to the front surface 211, and (b) adjacent to the recessed region 219R.

[0057] Step 910 may be performed after forming a plurality of trenches for isolation in the semiconductor substrate. Step 910 may include step 912. Step 912 includes forming a first layer group of one of the N-layer groups by depositing a plurality of high-k material layers into the plurality of trenches and onto the subsequent surface of the semiconductor substrate. The deposition process may be atomic layer deposition (ALD).

[0058] In some embodiments, during the deposition of each high-κ material layer (e.g., deposition of each high-κ material layer 431(1-4)), hydrogen atoms are introduced or injected into the semiconductor substrate, which can stabilize dangling bonds at the silicon-oxide interface on the front side of the semiconductor substrate, reduce surface defects, and thereby further reduce dark current associated with surface defects.

[0059] In some embodiments of a stacked layer group having three layers, step 912 includes (i) depositing a first high-κ material layer on a surface, (ii) depositing a second high-κ material layer directly on the first high-κ material layer, and depositing a third high-κ material layer directly on the second high-κ material layer. The first high-κ material layer and the second high-κ material layer are the first pair of adjacent high-κ material layers in the first layer group. The second high-κ material layer and the third high-κ material layer are the second pair of adjacent high-κ material layers in the first layer group. In an example of step 912, high-κ material layer 431(1) is deposited on the recessed region 219R, high-κ material layer 431(2) is deposited directly on high-κ material layer 431(1), and high-κ material layer 431(3) is deposited directly on high-κ material layer 431(2). Layers 431(1,2,3) have corresponding charge densities < 0, < 0, and < 0. In this example, the negative value of charge density is greater than the negative value of charge density, and the negative value of charge density is greater than the negative value of charge density, therefore >>. Layer 431 (1-3) is therefore in the same layer group of multilayer film 430.

[0060] Step 910 may include steps 915 and 917. Step 915 includes forming a first layer group of N layers by (i) depositing a first high-κ material layer on the surface and (ii) depositing a second high-κ material layer directly on the first high-κ material layer. In the example of step 915, the high-κ material layer 431(1) is deposited on the recessed region 219R, and the high-κ material layer 431(2) is deposited directly on the high-κ material layer 431(1). Layers 431(1,2) have corresponding charge densities < 0 and < 0. In this example, the negative value of the charge density is greater than the negative value of the charge density: >, such that layers 431(1,2) are in the same layer group of the multilayer film 430.

[0061] Step 917 includes forming a second layer group of N layers by (i) depositing a third high-κ material layer on the second high-κ material layer and (ii) depositing a fourth high-κ material layer directly on the third high-κ material layer. In the example of step 917, high-κ material layer 431(3) is deposited on high-κ material layer 431(2), and high-κ material layer 431(4) is deposited directly on high-κ material layer 431(3). Layers 431(3,4) have corresponding charge densities < 0 and < 0. In this example, the negativeness of the charge density is greater than the negativeness of the charge density: >, such that layers 431(3,4) are in the same layer group of the multilayer film 430.

[0062] In some embodiments, after step 917, an anti-reflective coating material is deposited into the plurality of trenches and onto the rear surface of the semiconductor substrate to form an anti-reflective coating layer. For example, anti-reflective coating 640 is deposited on multilayer film 430, including portions of multilayer film 430 on surface 219 of semiconductor substrate 210 and on recessed region 219R. Subsequently, a dielectric filling material (e.g., an oxide-based material) is deposited and fills each of the plurality of trenches. For example, dielectric 650 is deposited on recessed region 219R and fills trench 220. In one embodiment, dielectric filling material is deposited into trench 220 and onto rear surface 219 of semiconductor substrate 210 to form buffer layer 750. In such embodiments, a chemical polishing process can be applied to planarize buffer layer 750 so that a metal grid 762, color filter array 760A, and microlens array 770A can subsequently be formed. Feature Combination

[0063] The features described above and the features claimed below can be combined in various ways without departing from the scope of the invention. The examples listed below illustrate some possible non-limiting combinations.

[0064] (A1) An image sensor includes a semiconductor substrate and a multilayer film. The semiconductor substrate includes a photodiode and a back surface having a recessed region surrounding the photodiode. The multilayer film is on and conforms to the recessed region and includes an N-layer group of adjacent high-k material layers. Each pair of adjacent high-k material layers in the N-layer group includes (i) an outer layer having an external fixed charge density, and (ii) an inner layer located between the outer layer and the recessed region having an internal fixed charge density. Each of the external fixed charge density and the internal fixed charge density is negative. The negativeness of the internal fixed charge density is greater than the negativeness of the external fixed charge density.

[0065] (A2) In the embodiment of the image sensor (A1), N equals 1, and the total number of adjacent high-κ material layers is greater than or equal to 3.

[0066] (A3) In the embodiment of the image sensor (A1), N equals 2, and the total number of adjacent high-κ material layers in each layer group is greater than or equal to 2.

[0067] (A4) In any embodiment of the image sensor (A1) to (A3), each of the N-layer groups is a layer pair, such that each of the N-layer groups includes a single pair of adjacent high-k material layers. The first thickness of the inner layer exceeds the second thickness of the outer layer.

[0068] (A5) In any of the embodiments of the image sensors (A1) to (A4), the thickness of each high-κ material layer is between 3 nanometers and 30 nanometers.

[0069] (A6) In any of the embodiments of the image sensor (A1) to (A5), each high-k material layer is formed of one of aluminum oxide, hafnium dioxide, zirconium dioxide, tantalum pentoxide and gallium oxide.

[0070] (A7) In any embodiment of the image sensor (A1) to (A6), the N-layer group includes (i) a first layer group having a first total thickness, and (ii) a second layer group adjacent to the first layer group having a second total thickness exceeding the first total thickness. The first layer group is located between the recessed region and the second layer group.

[0071] (A8) In an embodiment of the image sensor (A7), each of the first layer group and the second layer group is a layer pair, and has a corresponding first layer and a corresponding second layer thereon. The first layer group has a first ratio of the thickness of its first layer to the thickness of its second layer. The second layer group has a second ratio of the thickness of its first layer to the thickness of its second layer, the second ratio being greater than or equal to the first ratio.

[0072] (A9) In any embodiment of the image sensor (A7) and (A8), the second total thickness exceeds the first total thickness by less than or equal to twice.

[0073] (A10) In any of the image sensors (A7) to (A9), the N-layer group includes a third layer group adjacent to the second layer group, the third layer group having a third total thickness exceeding the second total thickness.

[0074] (A11) In any embodiment of the image sensor (A1) to (A10), one of the N layers is a layer pair, the inner layer of which is formed of aluminum oxide and the outer layer of which is formed of hafnium dioxide.

[0075] (A12) In any of the image sensors (A1) to (A11), each of the N-layer groups is a single pair of adjacent high-κ material layers, the inner layer of which is formed of alumina and the outer layer of which is formed of hafnium dioxide.

[0076] (A13) In any embodiment of the image sensor (A1) to (A12), the N-layer group includes: (a) a first layer pair, wherein the inner and outer layers are formed of a first material and a second material, respectively; and (b) a second layer pair on the first layer pair, wherein the inner and outer layers are formed of a third material and a fourth material, respectively. At least one of the following conditions exists: (i) the third material is different from the first material and (ii) the fourth material is different from the second material.

[0077] (A14) In any of the image sensors (A1) to (A13), the multilayer film includes a region above a trench on a region of a rear surface partially adjacent to the recessed region.

[0078] (A15) An embodiment of any one of the image sensors (A1) to (A14) further includes an anti-reflective coating on a multilayer film.

[0079] (A16) In the embodiment of the image sensor (A15), the total thickness of the anti-reflective coating exceeds the total thickness of the multilayer film.

[0080] (A17) An embodiment of any one of the image sensors (A1) to (A16) further includes, when the recessed region forms a trench around the photodiode, a dielectric material filling the trench such that the multilayer film is located between the dielectric material and the semiconductor substrate.

[0081] (A18) In any of the embodiments of the image sensor (A1) to (A17), the semiconductor substrate further includes a photodiode array comprising photodiodes. A recessed region forms a lattice trench to separate each of the photodiodes in the photodiode array. A multilayer film conformally liner is applied to at least a portion of the lattice trench.

[0082] (A19) In an embodiment of the image sensor (A18), the recessed region includes one of a plurality of recessed segments between each pair of adjacent photodiodes in the photodiode array, the plurality of recessed segments together forming a grid-like groove.

[0083] (A20) In an embodiment of the image sensor (A19), in a cross-sectional plane intersecting each photodiode of the photodiode array, the width of each of the plurality of recessed segments is between 0.10 micrometers and 0.15 micrometers.

[0084] (A21) In any embodiment of the image sensor (A1) to (A20), the thickness of the semiconductor substrate is between 2 micrometers and 7 micrometers. The depth of the recessed region is between 1.5 micrometers and 3 micrometers.

[0085] (B1) A surface passivation method comprising depositing any one of a multilayer film (A1) to (A20) on a surface.

[0086] (B2) In an embodiment of method (B1), depositing a multilayer film includes: (i) depositing a first high-κ material layer on a surface, (ii) depositing a second high-κ material layer directly on the first high-κ material layer, and (iii) depositing a third high-κ material layer directly on the second high-κ material layer to form a first layer group of N layer groups. The first high-κ material layer and the second high-κ material layer are a first pair of adjacent high-κ material layers in the first layer group. The second high-κ material layer and the third high-κ material layer are a second pair of adjacent high-κ material layers in the first layer group.

[0087] (B3) In an embodiment of method (B1), depositing a multilayer film includes: (a) forming a first layer group of N layers by (i) depositing a first high-κ material layer on a surface and (ii) depositing a second high-κ material layer directly on the first high-κ material layer; and (b) forming a second layer group of N layers by (i) depositing a third high-κ material layer on the second high-κ material layer and (ii) depositing a fourth high-κ material layer directly on the third high-κ material layer.

[0088] (B4) In an embodiment of any of methods (B1) to (B3), the surface is a substrate surface of a semiconductor substrate having a photodiode, and the substrate surface includes a recessed region that defines a trench around the photodiode in the semiconductor substrate. Such embodiments may further include depositing a multilayer film on the recessed region and on the substrate; and filling the trench with a dielectric material, the multilayer film being between the dielectric material and the recessed region.

[0089] (B5) An embodiment of method (B4) further includes depositing an anti-reflective layer on the multilayer film and on the substrate surface before filling the trench, wherein a first portion of the anti-reflective layer on the substrate surface has a first thickness exceeding a second portion of the anti-reflective layer on the recessed region.

[0090] The above description is a preferred embodiment of the present invention. Those skilled in the art should understand that it is used to illustrate the present invention and not to limit the scope of the patent rights claimed by the present invention. The scope of patent protection shall be determined by the appended claims and their equivalent fields. Any modifications or refinements made by those skilled in the art without departing from the spirit or scope of this patent are equivalent changes or designs made under the spirit disclosed in the present invention and should be included in the scope of the following claims. [Simplified Explanation of the Diagram]

[0007] [Figure 1] depicts a camera that images a scene; the camera includes an image sensor.

[0008] [Figure 2] is a cross-sectional schematic diagram of one of the semiconductor substrates in the embodiment.

[0009] [Figure 3] is a cross-sectional schematic diagram of a semiconductor substrate, which is an example of a semiconductor substrate of Figure 2.

[0010] [Figure 4] and [Figure 5] are schematic cross-sectional views of one of the passivation-enhanced image sensors in the embodiment, including the semiconductor substrate of Figure 2.

[0011] [Figure 6] is a cross-sectional schematic diagram of one of the image sensors, which is an example of one of the image sensors of Figures 4 and 5.

[0012] [Figure 7] is a cross-sectional schematic diagram of one of the image sensors of the embodiments of Figures 4 and 5, including a metal grid, a color filter array and a microlens array.

[0013] [Figure 8] is a cross-sectional schematic diagram of one of the passivation-enhanced image sensors including the semiconductor substrate of Figure 2 in an embodiment.

[0014] [Figure 9] is a flowchart of one of the surface passivation methods in the illustrated embodiment.

Claims

1. A passivation-enhanced image sensor, comprising: A semiconductor substrate includes a photodiode and a rear surface, the rear surface having a recessed region surrounding the photodiode; And a multilayer film, on and conformally to the recessed region, comprising an N-layer group of adjacent high-k material layers, wherein each pair of adjacent high-k material layers in the same N-layer group comprises (i) an outer layer having an external fixed charge density, and (ii) an inner layer located between the outer layer and the recessed region and having an internal fixed charge density, each of the external fixed charge density and the internal fixed charge density being negative, the negativeness of the internal fixed charge density being greater than the negativeness of the external fixed charge density; wherein the N-layer group comprises: a first layer group having a first total thickness and comprising a first inner layer and a first outer layer, the first inner layer and the first outer layer having a first fixed charge density -ρ1 and a second fixed charge density -ρ2, respectively; a second layer group adjacent to the first layer group, having a second total thickness exceeding the first total thickness, and comprising a second inner layer and a second outer layer, the second inner layer and the second outer layer having a third fixed charge density -ρ3 and a fourth fixed charge density -ρ4, respectively; The first layer group is located between the recessed region and the second layer group; and the second inner layer is located between the first outer layer and the second outer layer; wherein |ρ3|>|ρ2| and |ρ3|>|ρ4|.

2. The passivation-enhanced image sensor as claimed in claim 1, wherein the total number of adjacent high-κ material layers included in at least one of the first and second layer groups is greater than or equal to 3.

3. The passivation-enhanced image sensor as claimed in claim 1, wherein N equals 2, and the total number of adjacent high-κ material layers in each layer group is greater than or equal to 2.

4. The passivation-enhanced image sensor as claimed in claim 1, wherein each of the N-layer groups is a layer pair, such that each of the N-layer groups includes a single pair of adjacent high-k material layers, the inner layer having a first thickness exceeding a second thickness of one of the outer layers.

5. The passivation-enhanced image sensor as claimed in claim 1, wherein one of the high-κ material layers has a corresponding thickness between 3 nm and 30 nm.

6. The passivation-enhanced image sensor as claimed in claim 1, wherein each high-κ material layer is formed of one of aluminum oxide, hafnium dioxide, zirconium dioxide, tantalum pentoxide, and gallium oxide.

7. The passivation-enhanced image sensor as claimed in claim 1, wherein the first layer group is located between the recessed region and the second layer group.

8. The passivation-enhanced image sensor as claimed in claim 7, wherein each of the first layer group and the second layer group is a layer pair and has a corresponding first layer and a corresponding second layer thereon, the first layer group having a first ratio of the thickness of its first layer to the thickness of its second layer, and the second layer group having a second ratio of the thickness of its first layer to the thickness of its second layer, the second ratio being greater than or equal to the first ratio.

9. The passivation-enhanced image sensor as claimed in claim 7, wherein the second total thickness exceeds the first total thickness by less than or equal to twice.

10. The passivation-enhanced image sensor as claimed in claim 7, wherein the N-layer group includes a third layer group adjacent to the second layer group, the third layer group having a third total thickness exceeding the second total thickness.

11. The passivation-enhanced image sensor as claimed in claim 1, wherein one of the N-layer groups is a layer pair, the inner layer of which is formed of aluminum oxide and the outer layer of which is formed of hafnium dioxide.

12. The passivation-enhanced image sensor as claimed in claim 1, wherein each of the N-layer groups is a single pair of adjacent high-κ material layers, the inner layer of which is formed of alumina and the outer layer of which is formed of hafnium dioxide.

13. The passivation-enhanced image sensor as claimed in claim 1, wherein the N-layer group comprises: A first layer pair, wherein the inner layer and the outer layer are formed of a first material and a second material, respectively; And a second layer pair, on which the inner and outer layers are formed of a third material and a fourth material, respectively, wherein at least one of the following conditions exists: (i) the third material is different from the first material, and (ii) the fourth material is different from the second material.

14. The passivation-enhanced image sensor as claimed in claim 1, wherein the multilayer film includes a region above a trench on one of the rear surfaces, which is partially adjacent to the recessed region.

15. The passivation-enhanced image sensor as claimed in claim 1, further comprising an anti-reflective coating on the rear surface of the semiconductor substrate above the multilayer film and the photodiode.

16. The passivation-enhanced image sensor as claimed in claim 15, wherein the total thickness of one of the antireflective coatings on the rear surface exceeds the total thickness of one of the multilayer films.

17. The passivation-enhanced image sensor of claim 1, wherein the recessed region forms a trench surrounding the photodiode, and further includes a dielectric filling the trench such that the multilayer film is located between the dielectric and the semiconductor substrate.

18. The passivation-enhanced image sensor as claimed in claim 1, wherein: The semiconductor substrate further includes a photodiode array, the photodiode array including the photodiodes, the recessed region forming a grid trench to separate each of the photodiodes in the photodiode array; and the multilayer film conformally lining at least a portion of the grid trench.

19. The passivation-enhanced image sensor as claimed in claim 18, wherein the recessed region includes a corresponding one of a plurality of recessed segments between each pair of adjacent photodiodes in the photodiode array, the plurality of recessed segments collectively forming the lattice trench.

20. A surface passivation method comprising depositing a multilayer film on a surface, the multilayer film comprising N layers of adjacent high-k material layers, each pair of adjacent high-k material layers in the same layer group comprising (i) an outer layer having an external fixed charge density, and (ii) an inner layer located between the outer layer and a recessed region of the surface and having an internal fixed charge density, each of the external fixed charge density and the internal fixed charge density being negative, the negativeness of the internal fixed charge density being greater than the negativeness of the external fixed charge density; wherein the N layers comprise: a first layer group having a first total thickness and including a first inner layer and a first outer layer, the first inner layer and the first outer layer having a first fixed charge density -ρ1 and a second fixed charge density -ρ2, respectively; a second layer group adjacent to the first layer group, having a second total thickness exceeding the first total thickness, and including a second inner layer and a second outer layer, the second inner layer and the second outer layer having a third fixed charge density -ρ3 and a fourth fixed charge density -ρ4, respectively; The first layer group is located between the recessed region and the second layer group; and the second inner layer is located between the first outer layer and the second outer layer; wherein |ρ3|>|ρ2| and |ρ3|>|ρ4|.

21. The surface passivation method as described in claim 20, wherein depositing the multilayer film comprises: By (i) depositing a first high-κ material layer on the surface, (ii) depositing a second high-κ material layer directly on the first high-κ material layer, and (iii) depositing a third high-κ material layer directly on the second high-κ material layer, a first layer group of one of the N layer groups is formed, wherein the first high-κ material layer and the second high-κ material layer are a first pair of adjacent high-κ material layers of one of the first layer groups, and the second high-κ material layer and the third high-κ material layer are a second pair of adjacent high-κ material layers of one of the first layer groups.

22. The surface passivation method as described in claim 20, wherein depositing the multilayer film comprises: A first layer group, one of the N layer groups, is formed by (i) depositing a first high-κ material layer on the surface and (ii) depositing a second high-κ material layer directly on the first high-κ material layer; And by (i) depositing a third high-κ material layer on the second high-κ material layer and (ii) directly depositing a fourth high-κ material layer on the third high-κ material layer, a second layer group of one of the N layer groups is formed.

23. The surface passivation method of claim 20, wherein the surface is a substrate surface of a semiconductor substrate having a photodiode, the substrate surface including a recessed region defining a trench around the photodiode in the semiconductor substrate, the method further comprising: The multilayer film is deposited on the recessed region and on the substrate; The trench is filled with a dielectric material, and the multilayer film is located between the dielectric material and the recessed region.

24. The surface passivation method as described in claim 23, further comprising, before filling the trench: An antireflective layer is deposited on the multilayer film and on the substrate surface, wherein a first portion of the antireflective layer on the substrate surface has a first thickness exceeding a second portion of the antireflective layer on the recessed region.

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