Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for manufacturing semiconductor devices, which mainly involves first providing a wafer, then forming a dicing channel on the front side of the wafer, performing a plasma dicing process to cut the wafer along the dicing channel without completely separating the wafer, performing a layer pressing process to form an adhesive tape on the front side of the wafer, performing a grinding process on the back side of the wafer, and then performing an expansion process to divide the wafer into a plurality of wafers.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing semiconductor elements, and in particular to a method for cutting wafers using a plasma cutting process. Prior Art

[0002] With the advancement of science and technology, technologies such as augmented reality (AR) and virtual reality (VR) are gradually maturing. In the foreseeable future, AR and VR will be widely used in human life, for example in education, logistics, medical care, and the military. Currently, augmented reality and virtual reality are primarily implemented using head-mounted displays (HMDs). Existing HMDs typically connect display driver integrated circuits (DDICs), which include high-voltage, medium-voltage, and / or low-voltage components, to a display module via long wires or metal interconnects. This design often results in a large product, taking up space and making it difficult to wear. Therefore, improving existing manufacturing processes to provide a display suitable for AR or VR environments is a key issue. Summary of the Invention

[0003] An embodiment of the present invention discloses a method for manufacturing semiconductor devices, which mainly provides a wafer, then forms a cutting line on the front side of the wafer, performs a plasma cutting process to cut the wafer along the cutting line but does not completely separate the wafer, performs a layer pressing process to form a tape on the front side of the wafer, performs a grinding process on the back side of the wafer, and then performs an expansion process to divide the wafer into multiple chips.

[0004] Another embodiment of the present invention discloses a semiconductor element, which mainly includes a chip obtained after a cutting process, wherein the chip includes a first sidewall including an upper half and a lower half, the upper half includes a first contour, the lower half includes a second contour, and the first contour is different from the second contour. Simple diagram description

[0005] FIG1 to FIG5 are schematic diagrams of a method for manufacturing a micro display according to an embodiment of the present invention. FIG6 is a top view of the lower wafer after the bonding pad is fabricated according to an embodiment of the present invention. FIG7 is a cross-sectional view of the lower wafer after the bonding pad is fabricated according to an embodiment of the present invention. Figure 8 is a schematic diagram of the process flow and process location when the upper wafer is cut. Figure 9 is a cross-sectional view of the upper wafer when it is cut. FIG10 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. Implementation Method

[0006] Although specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the relevant art that this disclosure may also be used in a variety of other applications.

[0007] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0008] In general, terms can be understood at least in part based on usage in context. For example, as used herein, the term "one or more" (depending at least in part on context) can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a plural combination of features, structures, or characteristics. Similarly, terms such as "a," "an," or "the" can again be understood to express singular usage or to convey plural usage, depending at least in part on context. Furthermore, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can instead allow for the presence of additional factors that may not necessarily be explicitly described and that depend at least in part on context.

[0009] It should be readily understood that the meanings of “on,” “over,” and “above” in the disclosure of this case should be interpreted in the broadest manner, such that “on” not only means “directly” on something, but also includes being on something with intermediate features or layers therebetween, and that “on” or “above” not only means being on something or above something, but also includes being without intermediate features or layers (i.e., directly on something).

[0010] Furthermore, for ease of description, as shown in the drawings, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used to describe the relationship of one element or feature to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0011] As used herein, the term "substrate" refers to the material onto which layers of material are subsequently added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and others. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0012] As used herein, the term "layer" refers to a portion of a material comprising an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent less than that of the underlying or superstructure. In addition, a layer may be a region of a continuous structure, uniform or non-uniform, having a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer that may include one or more layers and / or may have one or more layers above and / or below it. A layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0013] Please refer to Figures 1 to 5, which are schematic diagrams of a method for fabricating a microdisplay according to an embodiment of the present invention. As shown in Figure 1, wafers 12 and 14 composed of semiconductor materials are first provided. Wafer 12 preferably has medium-voltage components, high-voltage components, and pixel circuits, while wafer 14 preferably has low-voltage components such as a low-voltage driver circuit and / or a graphics processing unit (GPU). More specifically, each wafer 12 and 14 includes a substrate 16 composed of a semiconductor material. Each substrate 16 can be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or even a substrate composed of a silicon-on-insulator (SOI). These material options are all within the scope of the present invention.

[0014] It should be noted that since the wafer 12 is preferably used to carry or connect some low-voltage components and display modules after the wafer 14 is cut in subsequent processes, a plurality of die areas 52 can be first defined on the wafer 12 to be subsequently bonded to other chips before being cut. The area or size of each die area 52 is preferably much larger than the chip to be subsequently bonded, and three regions are preferably defined on each die area 52, including a first region 18, a second region 20, and a third region 22. The first region 18 includes a bonding region for subsequent connection to an external circuit, the second region 20 includes a chip-to-wafer region for subsequent bonding after the wafer 14 is cut into a plurality of dies or chips, and the third region 22 is a micro-display region for connecting a micro-display module.

[0015] Furthermore, wafers 12 and 14 in this embodiment may each include, depending on the process or product, metal oxide semiconductor (MOS) transistors, oxide field effect semiconductor transistors (OSFETs), fin-shaped transistors (FinFETs), or other active and / or passive devices. For example, the fabrication of MOS transistors may include a gate structure disposed on a substrate 16, sidewalls (not shown) disposed on the sidewalls of the gate structure, source / drain regions disposed in the substrate on either side of the sidewalls, an interlayer dielectric layer or intermetallic dielectric layer 24 disposed on each MOS transistor, and metal interconnects 26 disposed within the interlayer dielectric layer or intermetallic dielectric layer 24 to connect the MOS transistors. In this embodiment, the devices on wafer 12 are preferably fabricated using a 65-80 nm technology node, while the devices on wafer 14 are preferably fabricated using a 28-40 nm technology node.

[0016] Furthermore, at this stage or before other cut chips are bonded to the wafer 12, the wafer 12 is preferably provided with a plurality of bonding pads 28, 30, 32 in each of the first region 18, the second region 20, and the third region 22 for electrically connecting to the aforementioned active or passive components. To achieve optimal connection with subsequent components, the bonding pads 28, 30, 32 in the first region 18, the second region 20, and the third region 22 on the wafer 12 may be made of the same or different materials as the objects to which the bonding pads 28, 30, 32 are subsequently connected. Furthermore, the bonding pads 28, 30, 32 between each of the first region 18, the second region 20, and the third region 22 may also be made of the same or different materials.

[0017] For example, in this embodiment, the bonding pads 28 in the first region 18 and the bonding pads 30 in the second region 20 may comprise the same or different materials. The bonding pads 28 in the first region 18 and the bonding pads 32 in the third region 22 may comprise the same or different materials. Furthermore, the bonding pads 30 in the second region 20 and the bonding pads 32 in the third region 22 may comprise the same or different materials. In this embodiment, the bonding pads 28 in the first region 18 are preferably made of a low-impedance material, such as, but not limited to, gold, because they will later be used for external circuit connections. The bonding pads 30 in the second region 20 are preferably made of copper. The bonding pads 32 in the third region 22 are used to connect to solder balls or bumps of the subsequent micro-display module and may therefore be made of copper or aluminum. It should be noted that, whereas the wafer 12 already has a plurality of bonding pads 28, 30, and 32 in each of the first region 18, the second region 20, and the third region 22 at this stage, the wafer 14 only has the aforementioned active components and metal interconnects 26 connecting the active components, but no bonding pads.

[0018] Furthermore, the bonding pads 28, 30, and 32 in each of the first region 18, the second region 20, and the third region 22 preferably have different line widths (pitch) or spacings. For example, in this embodiment, the line width or spacing between the bonding pads 28 in the first region 18 is preferably greater than the line width or spacing between the bonding pads 30 in the second region 20, and the line width or spacing between the bonding pads 32 in the third region 22. The line width or spacing between the bonding pads 30 in the second region 20 can be equal to or slightly smaller than the line width or spacing between the bonding pads 32 in the third region 22. In this embodiment, the line width or spacing between the bonding pads 28 in the first region 18 is preferably between 20 and 200 microns, the line width or spacing between the bonding pads 30 in the second region 20 is preferably between 1 and 20 microns, and the line width or spacing between the bonding pads 32 in the third region 22 is preferably between 2 and 20 microns.

[0019] It should also be noted that the aforementioned line width or spacing between the bonding pads 28, 30, 32 in each region preferably means that the line width or spacing between each bonding pad 28, 30, 32 in each region is smaller or larger than the line width or spacing between each bonding pad 28, 30, 32 in other regions. In other words, the line width or spacing between the bonding pads 28 in the first region 18 is larger than the line width or spacing between the bonding pads 30 in the second region 20 and the line width or spacing between the bonding pads 32 in the third region 22. This preferably means that the line width or spacing between each bonding pad 28 in the first region 18 is larger than the line width or spacing between each bonding pad 30 in the second region 20 and the line width or spacing between each bonding pad 32 in the third region 22.

[0020] Then, as shown in FIG. 2 , a thinning process is performed on the wafer 14 to remove a portion of the substrate 16 of the wafer 14 so that its total thickness is slightly reduced, and then a wafer dicing process is performed to separate the wafer 14 into a plurality of dies or chips 34 .

[0021] As shown in FIG3 , the previously diced wafer 34 is then flipped over and subjected to a bonding process to bond components such as low-voltage driver circuits and / or a graphics processor to the undiced wafer 12, which is provided with medium-voltage and high-voltage components. In this embodiment, the metal interconnects 26 on the wafer 34 are preferably bonded to the bonding pads 30 on the second region 20 of the wafer 12 using a hybrid bonding process. The metal interconnects 26 on the wafer 34 are preferably made of copper, and the bonding pads 30 on the second region 20 are also preferably made of copper. Therefore, the two are preferably bonded face-to-face using hybrid bonding.

[0022] As shown in FIG. 4 , a display module manufacturing process is then performed to form microdisplays 36 on the third region 22 of the wafer 12 and connect to the bonding pads 32 on the third region 22. In this embodiment, the microdisplays 36 may include display elements such as organic light emitting diode displays (OLED displays), mini organic light emitting diode displays (MLD displays), or micro LLD displays, depending on the manufacturing process or product requirements. Each microdisplay 36 may include red, green, and blue display pixels 38.

[0023] Next, as shown in FIG. 5 , wires 40 for connecting to external circuits are formed and connected to bonding pads 28 located on the first region 18 of the wafer 12. Then, based on process requirements, the wafer 12 is cut along the initially defined die regions 52 into dies or chips of desired sizes for subsequent packaging. In this embodiment, the wires 40 for connecting to external circuits are preferably made of copper, while the bonding pads 28 on the first region 18 are preferably made of a low-resistance material such as gold. This completes the fabrication of a microdisplay according to the present invention.

[0024] Please refer to Figures 6 and 7, which are respectively top views and cross-sectional views of the lower wafer after bonding pad fabrication in the aforementioned embodiment of the present invention. The right half of Figure 6 is a top view of the lower wafer as a whole, while the left half is a top view of a sub-bonding region within the right-half bonding region. As shown in Figure 6, the semiconductor device primarily comprises a circuit region 62 disposed on substrate 16 or wafer 12, a bonding region 64 surrounding circuit region 62, and a bonding pad region 66 surrounding bonding region 64. The right-half bonding pad region 66 is provided with a plurality of bonding pads 28. The bonding region 64 further comprises a plurality of sub-bonding regions 70. Each sub-bonding region 70, as shown in the left half, further comprises a bonding pad 72 and a bonding pad 74.

[0025] If compared with the previous process diagram, the pad area 66 is preferably the aforementioned first area 18 and the pad 28 is preferably the pad 28 of the first area 18, the bonding area 64 is the second area 20 or the third area 22 on the aforementioned die area 52, and the pads 72 and 74 can be the pad 30 on the second area 20 or the pad 32 on the third area 22.

[0026] From a detailed perspective, the plurality of sub-joint areas 70 are preferably evenly distributed on the joint area 64 and surround the circuit area 62. Each sub-joint area 70 appears roughly rectangular when viewed from above. Each sub-joint area 70 further includes a plurality of solder pads 72 and solder pads 74, and the solder pads 72 and solder pads 74 are arranged on different layers. The solder pads 72 and solder pads 74 preferably have different shapes when viewed from above. For example, the solder pads 72 may be square when viewed from above, while the solder pads 74 may be hexagonal when viewed from above.

[0027] In this embodiment, the distance a from the edge of bonding pad 72 to the edge of bonding pad 74 is preferably between 0 and 6 microns, or more preferably, approximately 0.3 microns. The distance b from the edge of secondary bonding region 70 to the edge of bonding pad 28 in bonding pad region 66 is preferably between 0 and 8 microns, or most preferably, 4 microns. The distance c from the edge of secondary bonding region 70 to the edge of circuit region 62 is preferably between 0 and 6 microns, or most preferably, 3 microns.

[0028] From the cross-sectional perspective of FIG. 7 , first, as previously described, active components such as MOS transistors are formed on the substrate 16 of the substrate or wafer 12 according to the process or product requirements, and then an interlayer dielectric layer or intermetallic dielectric layer 24 is formed on each metal oxide semiconductor transistor, and metal interconnects 26 are provided in the interlayer dielectric layer or intermetallic dielectric layer 24 to connect each metal oxide semiconductor transistor. In this embodiment, the circuit area 62 is provided with a plurality of dummy pads, such as the pad 100 and the metal wrap 106, the joint area 64 is provided with pads 72 and 74, and the pad area 66 is provided with a pad 28. Each pad 28, 72, 74 is preferably provided on the active component and connected to the metal interconnect 26. The upper intermetallic dielectric layer structure provided on the metal interconnect 26 and surrounding the pads 28, 72, 74, 100 may include a stop layer 76, an intermetallic dielectric layer 78, a stop layer 80, an intermetallic dielectric layer 82, a stop layer 84, an intermetallic dielectric layer 86, and a stop layer 88.

[0029] From a detailed perspective, metal interconnect 26 preferably extends from bonding region 64 to pad region 66, and metal interconnect 26 preferably simultaneously connects bonding pads 72 and 74 respectively located in bonding region 64, and bonding pad 28 located in pad region 66. Bond pad 72 in bonding region 64 includes a lower portion 92 connected to metal interconnect 26 and an upper portion 94 located on lower portion 92. Bond pad 74 includes a lower portion 96 connected to upper portion 94 of bond pad 72 and an upper portion 98 located on lower portion 96. Bond pad 28 located in pad region 66 also includes a lower portion 102 connected to metal interconnect 26 and an upper portion 104 located on lower portion 102.

[0030] Overall, the top surface of the lower half 92 of the bonding pad 72 in the bonding area 64 is preferably aligned with the top surface of the intermetal dielectric layer 78 and the top surface of the lower half 102 of the bonding pad 28 in the bonding pad area 66; the top surface of the upper half 94 of the bonding pad 72 in the bonding area 64 is preferably aligned with the top surface of the upper half 104 of the bonding pad 28 in the bonding pad area 66; the top surface of the lower half 96 of the bonding pad 74 in the bonding area 64 is preferably aligned with the top surface of the intermetal dielectric layer 82; and the top surface of the upper half 98 of the bonding pad 74 in the bonding area 64 is preferably aligned with the top surface of the bonding pad 100 in the circuit area 62. As shown in FIG6 , the distance a from the left sidewall of the lower half 92 of the bonding pad 72 in the bonding area 64 to the right sidewall of the lower half 96 of the upper bonding pad 74 is preferably between 0 and 6 microns, or more preferably, approximately 0.3 microns. The distance b from the approximate left sidewall of the upper half 94 of the bonding pad 72 in the bonding area 64 to the approximate right sidewall of the upper half 104 of the bonding pad 28 in the bonding pad area 66 is preferably between 0 and 8 microns, or optimally, 4 microns. The distance c from the right sidewall of the upper half 98 of the bonding pad 74 in the bonding area 64 to the left sidewall of the bonding pad 100 in the circuit area 62 is preferably between 0 and 6 microns, or optimally, 3 microns.

[0031] From a material perspective, each bonding pad 28, 72, 74, and 100 may further comprise a barrier layer and a metal layer. The barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer may be selected from the group consisting of, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), and cobalt tungsten phosphide (CoWP). In this embodiment, bonding pads 28 and 72, which directly contact and connect to metal interconnect 26, are preferably made of the same material, such as aluminum, while the upper layer including bonding pads 74 and 100 is preferably made of copper. However, this is not limiting. According to other embodiments of the present invention, bonding pad 28 may also be made of gold, as described in the aforementioned embodiment. In addition, the intermetal dielectric layers 78, 82, and 86 preferably include silicon oxide or ultra-low-k dielectric layers, and the stop layers 76, 80, 84, and 88 include nitrogen doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but are not limited thereto.

[0032] Please continue to refer to Figures 8 and 9, which are schematic diagrams of the process of dicing wafer 14 as described in Figures 1 and 2. Figure 8 illustrates the process flow and location of dicing wafer 14, while Figure 9 shows a cross-sectional view of wafer 14 during dicing and after separation. Generally speaking, the processes described in Figures 1 to 5 are preferably performed in a wafer fab or an outsourced semiconductor assembly and test (OSAT) facility. For example, processes such as forming active devices and bonding pads on wafer 12 are preferably performed in a wafer fab, while processes such as separating wafer 14 and bonding it to wafer 12 are preferably performed in an outsourced OSAT facility.

[0033] From a detailed perspective, as shown in the upper half of FIG. 8 , the present invention can perform a series of wafer fab processes 120 before the aforementioned process in FIG. 2 or after the completion of active or passive device fabrication on wafer 14. These processes include a photoresist process 122 in the wafer fab. For example, a patterned photoresist is first formed on wafer 14 to define the scribe lines required for the dicing process. A plasma dicing process 124 is then performed using the patterned photoresist as a mask to form trenches 130 within wafer 14, serving as scribe lines 128, through a multi-pass etching process. A photoresist stripping process 126 is then performed to remove the patterned photoresist. It should be noted that while the plasma dicing process 124 removes multiple dielectric layers or protective layers on wafer 14 to form trenches, it only removes a portion of wafer 14 or substrate 16 during the dicing process to form trenches 130 for scribe lines 128, without completely separating wafer 14.

[0034] As shown in the upper half of FIG. 9 , the depth T1 of the trenches 130 formed in the wafer 14 at this stage is preferably between 25 and 200 microns, while the thickness T2 of the entire wafer 14 is preferably approximately 700 to 800 microns, or more preferably 750 microns. In other words, the depth of the trenches 130 formed in the wafer 14 during this stage, which serve as the scribe lines 128, is preferably approximately 5 to 30% of the original thickness of the wafer 14. It should also be noted that because the present invention uses plasma dicing or etching to remove a portion of the substrate 16 of the wafer 14 to form the trenches 130, the left and right sidewalls of the trenches 130 preferably form a scalloped profile during the dicing process, while the bottom of the trenches 130 remains flat.

[0035] As shown in the lower half of FIG. 8 , the subsequent outsourced packaging and testing foundry process 140 includes a laminating process 142 performed within the cooperating outsourced packaging and testing foundry to form a tape and adhere it to the front surface of the wafer 14 to prevent contamination of the surface of the wafer 14 during subsequent grinding. A grinding process 144 is performed on the back side of the wafer 14 to remove a portion of the wafer 14. An expanding process 146 is then performed using an instrument such as a wafer expander to separate the wafer 14 into a plurality of dies or chips 34.

[0036] As shown in the upper half of FIG. 9 , the polishing process 144 performed at this stage preferably removes most of the substrate 16 starting from the back side of the wafer 14, leaving a thickness T3 from the back side of the wafer 14 to the front trench 130 that is less than one-tenth the thickness of the original wafer 14. In this embodiment, the thickness T3 from the trench 130 to the remaining back surface of the wafer 14 is preferably approximately 5-10 microns.

[0037] As shown in the lower half of FIG. 9 , because the thickness of the trenches 130 to the back surface of the wafer 14 is only approximately one percent, or even less than one percent, of the overall thickness of the original wafer 14, the wafer 14 can be easily and completely separated along the trenches 130 defined in the dicing streets 128 during the expansion process 146 to form multiple dies or chips 34. As shown in the lower half of FIG. 9 , each separated die or chip 34 preferably includes a left sidewall 148 and a right sidewall 150. The left sidewall 148 is preferably a flat surface, while the right sidewall 150 further includes an upper portion 152 and a lower portion 154. In detail, the profile of the upper portion 152 is preferably different from that of the lower portion 154. For example, the profile of the upper portion 152 includes a scalloped surface or a wavy surface composed of multiple continuous curved surfaces, while the profile of the lower portion 154 includes a flat surface. In addition, the thickness of the upper half 152 is preferably approximately the depth T1 of the aforementioned trench 130, and the thickness of the lower half 154 is approximately the aforementioned thickness T3. Moreover, the thickness of the lower half 154 is preferably less than half of the thickness of the upper half 152, for example, less than 50%, 40%, 30%, 20%, 10%, 5% or less of the thickness of the upper half 152, all of which are within the scope of the present invention.

[0038] Please continue to refer to FIG. 10, which is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 9, compared to FIG. 9, where the die 34 may be located near the entire edge of the wafer 14, the left side wall 148 and right side wall 150 of the cut die 34 may have different profiles. In this embodiment, if the die 34 is originally located in a relatively central area of ​​the wafer 14, the left side wall 148 and right side wall 150 of the cut die 34 may preferably have the same profile. More specifically, the separated die or die 34 includes a left side wall 148 and a right side wall 150, wherein the left side wall 148 and the right side wall 150 each include an upper portion 152 and a lower portion 154, respectively. The profile of the upper portion 152 is different from that of the lower portion 154. For example, the profile of the upper portion 152 includes a scalloped surface or a wavy surface composed of multiple continuous curved surfaces, while the profile of the lower portion 154 includes a flat surface.

[0039] In summary, the present invention primarily performs a plasma dicing process within the wafer fab before sending the wafer to an outsourced packaging and testing foundry for grinding and complete separation into multiple chips. This process primarily utilizes multiple dry etching processes to remove portions of the wafer along defined scribe lines to form trenches without completely separating the wafer. The partially-cut wafer is then sent to the outsourced packaging and testing foundry for lamination, grinding, and expansion processes. The expansion process completely separates the partially-cut wafer into multiple dies or chips. As described in the previous embodiment, at least one sidewall of the wafer formed by the plasma dicing process preferably comprises two different profiles. For example, the profile of the upper portion 152 of the wafer sidewall may comprise a scalloped surface or a wavy surface composed of multiple continuous curved surfaces, while the profile of the lower portion 154 comprises a flat surface. According to a preferred embodiment of the present invention, compared to conventional laser-cutting methods, the plasma cutting process used in the present invention preferably does not cause damage to the edge of the wafer, the blank area left by the cutting path is also smaller, and more wafers can be obtained per wafer while keeping the wafer size unchanged. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0040] 12: Wafer 14: Wafer 16: Base 18: First Area 20: Second Area 22: The third area 24: Intermetallic dielectric layer 26: Metal interconnects 28: Solder pad 30: Solder pad 32: Solder pad 34: Chip 36: Microdisplay 38: Display pixels 40: Wire 52: Grain area 62: Circuit Area 64: Junction area 66: Solder pad area 70: Secondary junction area 72: Solder pad 74: Solder pad 76: Stop layer 78: Intermetallic dielectric layer 80: Stop layer 82: Intermetallic dielectric layer 84: Stop layer 86: Intermetallic dielectric layer 88: Stop layer 92: Lower half 94: Upper half 96: Lower half 98: Upper half 100: Solder pad 102: Lower half 104: Upper half 106:Metal winding 108:Metal interconnect 120: Fab Process 122: Photoresist process 124: Plasma cutting process 126: Photoresist stripping process 128: Cutting Road 130: Ditch 140: Outsourced packaging and testing foundry process 142:Lamination process 144: Grinding process 146:Expanding Process 148: Left wall 150: right wall 152: Upper half 154: Lower half

Claims

1. A method for manufacturing a semiconductor device, characterized in that it comprises: providing a wafer; forming a dicing channel on the front side of the wafer; performing a plasma dicing process to dicing the wafer along the dicing channel and creating a trench but not completely separating the wafer; and performing a polishing process on the back side of the wafer, wherein the polishing process reduces the thickness of the wafer but does not touch a bottom surface of the trench; and performing an expansion process to completely separate the wafer along the bottom surface of the trench into a plurality of wafers.

2. The method as described in claim 1 further comprises: performing a layer pressing process to form an adhesive tape on the front side of the wafer; and performing the polishing process.

3. The method as described in claim 2 further includes performing the lamination process at an outsourced semiconductor assembly and test (OSAT) facility.

4. The method as described in claim 1 further includes performing the grinding process in an outsourced packaging and testing facility.

5. The method as described in claim 1 further includes performing the plasma dicing process in a wafer fab.

6. A semiconductor device, characterized in that it comprises: a wafer obtained after a dicing process, the wafer comprising: a first sidewall comprising an upper half and a lower half, wherein the upper half comprises a first contour, the lower half comprises a second contour and the first contour is different from the second contour, wherein a ratio of a thickness of the lower half to a thickness of the upper half is within 5%, and the thickness of the lower half is between 5 and 10 micrometers.

7. The semiconductor element as described in claim 6, wherein the first profile includes a scalloped surface.

8. The semiconductor element as described in claim 7, wherein the second profile includes a flat surface.

9. The semiconductor element as described in claim 6, wherein the wafer includes a second sidewall comprising an upper half and a lower half, wherein the upper half includes a third profile and the lower half includes a fourth profile and the third profile is different from the fourth profile.

10. The semiconductor element as described in claim 9, wherein the third profile includes a scalloped surface.

11. The semiconductor element as described in claim 10, wherein the fourth profile includes a flat surface.

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