Method of manufacturing semiconductor devices

Abstract

In a method of manufacturing a semiconductor device, alignment bonds are formed through a portion of a substrate comprising a first surface and a second surface opposite to each other, said portion being adjacent to the second surface of the substrate. A transistor comprising a gate structure and a source / drain layer is formed on the second surface of the substrate. A portion of the substrate adjacent to the first surface of the substrate is removed to expose the alignment bonds. A contact plug is formed through the portion of the substrate adjacent to the first surface of the substrate to be electrically connected to the source / drain layer. A power rail is formed on the first surface of the substrate to be electrically connected to the contact plug.

Description

Semiconductor device Exemplary embodiments relate to a semiconductor device. More specifically, the exemplary embodiments relate to a semiconductor device having contact plugs. [Cross-reference to related applications] This application claims the priority of Korean Patent Application No. 10-2022-0133858, filed on October 18, 2022, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. In a logic device, contact plugs and via structures may be formed such that a gate structure and a source / drain layer can be connected to an upper wiring for applying an electrical signal thereto. However, the total resistance of the gate structure, the source / drain layer, the contact plug structure, and the via structure increases due to the contact resistance between the gate structure and the contact plug structure or between the source / drain layer and the contact plug structure. In addition, the gate structure and the contact plug structure may be electrically short-circuited, or the contact plug structure and the via structure may be electrically short-circuited. Exemplary embodiments provide a semiconductor device having enhanced characteristics. According to an exemplary embodiment, a method of manufacturing a semiconductor device is provided. In the method, an alignment key may be formed through a portion of a substrate including a first surface and a second surface opposite to each other, and the portion may be adjacent to the second surface of the substrate. A transistor including a gate structure and a source / drain layer may be formed on the second surface of the substrate. A portion of the substrate adjacent to the first surface of the substrate may be removed to expose the alignment key. A contact plug may be formed through the portion of the substrate adjacent to the first surface of the substrate to be electrically connected to the source / drain layer. A power rail may be formed on the first surface of the substrate to be electrically connected to the contact plug. According to an exemplary embodiment, a method of manufacturing a semiconductor device is provided. In the method, a portion of a substrate may be removed in a wafer region and a scribe lane region to respectively form a first trench and a second trench, and the portion may be adjacent to a second surface of the substrate. The substrate may include a first surface and a second surface opposite to each other. An isolation pattern and an alignment key may be respectively formed in the first trench and the second trench. A dummy gate structure may be formed on the second surface of the substrate. A source / drain layer may be formed on a portion of the substrate adjacent to the dummy gate structure. The dummy gate structure may be replaced with a gate structure. A portion of the substrate adjacent to a first surface of the substrate may be removed to expose the alignment key. A contact plug may be formed through the portion of the substrate adjacent to the first surface of the substrate to electrically connect to the source / drain layer. A power rail may be formed on the first surface of the substrate to electrically connect to the contact plug. According to an exemplary embodiment, a method of manufacturing a semiconductor device is provided. In the method, a portion of a substrate may be removed in a scribe lane region to form a first trench, and the portion may be adjacent to a second surface of the substrate. The substrate may include a first surface and a second surface opposite to each other, a wafer region, and a scribe lane region. A sacrificial layer and a semiconductor layer may be alternately and repeatedly stacked on the second surface of the substrate having the first trench thereon. An insulating layer may be formed on the uppermost semiconductor layer in the semiconductor layer on the first trench to form an alignment key. A portion of the semiconductor layer, the sacrificial layer, and the substrate adjacent to a second surface of the substrate may be partially removed in the wafer region to respectively form a semiconductor line, a sacrificial line, and a second trench, and the second trench may define an active pattern. An isolation pattern may be formed in the second trench. A dummy gate structure may be formed on the semiconductor line, the sacrificial line, the active pattern, and the isolation pattern. A source / drain layer may be formed on a portion of the active pattern adjacent to the dummy gate structure. The dummy gate structure may be replaced with a gate structure. A portion of the substrate adjacent to a first surface of the substrate may be removed to expose the alignment key. A contact plug may be formed through the portion of the substrate adjacent to the first surface of the substrate to electrically connect to the source / drain layer. A power rail may be formed on the first surface of the substrate to electrically connect to the contact plug. In a method of manufacturing a semiconductor device according to an exemplary embodiment, the alignment key may be used to position and align structures on a first surface of a substrate and may be exposed by removing a portion of the substrate adjacent to a second surface of the substrate. Accordingly, the alignment key may also be used to position and align structures on the second surface of the substrate. Accordingly, even if the power rail is formed on the second surface of the substrate rather than on the first surface of the substrate, the first structure located at a portion of the substrate adjacent to the first surface of the substrate and receiving power from the power rail can be aligned with the second structure located at a portion of the substrate adjacent to the second surface of the substrate and electrically connecting the first structure to the power rail. The semiconductor device according to an exemplary embodiment and a method of manufacturing the semiconductor device will be described more fully hereinafter with reference to the accompanying drawings. Hereinafter, in the specification (and not necessarily in the claims), two directions (substantially parallel to the upper surface of the substrate) intersecting each other in the horizontal direction may be referred to as a first direction D1 and a second direction D2, respectively, and a vertical direction substantially perpendicular to the upper surface of the substrate may be referred to as a third direction D3. In an exemplary embodiment, the first direction D1 and the second direction D2 may be substantially perpendicular to each other. In the specification, up and down, above and below, upper surface and lower surface, and upper portion and lower portion are relative concepts to describe opposite sides in the vertical direction, and each term may have an opposite meaning depending on the specific portion to be described in the specification. FIGS. 1 to 26 are plan views and cross-sectional views showing a method of manufacturing a semiconductor device according to an exemplary embodiment. Specifically, FIGS. 1, 4, 7, 11, 14, 18, 20, and 23 are plan views, and FIGS. 2, 3, 5, 6, 8 to 10, 12, 13, 15 to 17, 19, 21, 22, and 24 to 26 are cross-sectional views. FIGS. 2, 5, 15, and 24 are cross-sectional views taken along line A-A' of the corresponding plan views, FIGS. 3, 6, 8, 10, 12, 13, 16, 19, 21, and 25 are cross-sectional views taken along line B-B' of the corresponding plan views, and FIGS. 9, 17, 22, and 26 are cross-sectional views taken along line C-C' of the corresponding plan views. Referring to FIGS. 1 to 3, an upper portion of the substrate 100 including a first region I and a second region II can be removed to form a first trench and a second trench in the first region I and the second region II of the substrate 100, respectively. The substrate 100 may include a semiconductor material (e.g., silicon, germanium, silicon-germanium, etc.) or a III-V semiconductor compound (e.g., GaP, GaAs, GaSb, etc.). In some embodiments, the substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In an exemplary embodiment, the first region I of the substrate 100 may be a chip region, and the second region II of the substrate 100 may be a scribe lane region. In an exemplary embodiment, the second region II of the substrate 100 may surround the first region I of the substrate 100, and FIGS. 1 and 3 show a part of the second region II of the substrate 100. The substrate 100 may have a first surface 101 and a second surface 103 that face each other in a third direction D3, and FIGS. 2 and 3 show that the first surface 101 and the second surface 103 of the substrate 100 are the lower surface and the upper surface of the substrate 100, respectively. Accordingly, each of the first trench 102 and the second trench 104 may be formed by removing a portion of the substrate 100 adjacent to the second surface 103 of the substrate 100. A first insulating layer may be formed on the second surface 103 of the substrate 100 to fill the first trench 102 and the second trench 104, and the first insulating layer may be planarized until the second surface 103 of the substrate 100 is exposed. Accordingly, a first active pattern 105 may be defined by the first trench 102 on the first region I of the substrate 100, and a first alignment key 115 or a first capping key 115 may be defined in the second trench 104 on the second region II of the substrate 100. The first alignment key 115 or the first capping key 115 may be used to achieve precise alignment between layers stacked on the substrate 100 and to form features and devices in and on the substrate 100. The first active pattern 105 may protrude upward from the substrate 100 and may thus also be referred to as an active fin. In an exemplary embodiment, the first active pattern 105 may extend in a first direction D1 on the first region I of the substrate 100, and a plurality of first active patterns 105 may be spaced apart from each other in a second direction D2. FIG. 1 shows that the first alignment key 115 has a rectangular shape in a plan view. However, aspects of the inventive concept may not be limited thereto. Accordingly, the first alignment key 115 may have a shape such as circular, elliptical, rectangular, etc. in a plan view. In an exemplary embodiment, a plurality of first alignment keys 115 may be spaced apart from each other in the first direction D1 and / or in the second direction D2 on the second region II of the substrate 100, and FIG. 1 shows that two first alignment keys 115 are spaced apart from each other in the second direction D2 on the second region II of the substrate 100. The first insulating layer may include an oxide (e.g., silicon oxide), and the first alignment key 115 may also include an oxide (e.g., silicon oxide). Remove a portion of the first insulating layer at an upper portion of the first trench 102 to form a first isolation pattern 110 at a lower portion of the first trench 102. Accordingly, the first active pattern 105 defined by the first trench 102 may include a first lower active pattern 105a whose sidewalls are covered by the first isolation pattern 110 and a first upper active pattern 105b whose sidewalls are not covered by the first isolation pattern 110. Alternatively, the first alignment key 115 and the first isolation pattern 110 may be formed by depositing an insulating layer and removing an inter-insulating layer portion, respectively. For example, a second trench 104 may be formed on a second region II of the substrate 100, the first alignment key 115 may be formed to fill the second trench 104, the first trench 102 may be formed on a first region I of the substrate 100 to define the first active pattern 105, and the first isolation pattern 110 may be formed at a lower portion of the first trench 102. In this case, the first alignment key 115 may be used to position and align the first trench 102 and may include an insulating material different from the insulating material of the first isolation pattern 110. For example, the first isolation pattern 110 may include an oxide (e.g., silicon oxide), and the first alignment key may include an insulating nitride (e.g., silicon nitride). Alternatively, the first alignment key 115 may have a multilayer structure formed of a first layer including an oxide and a second layer including an insulating nitride. Referring to FIGS. 4 to 6, a first dummy gate structure 150 may be formed on a first region I of the substrate 100 having the first active pattern 105 and the first isolation pattern 110 thereon, and the first alignment key 115 may be used to position and align the first dummy gate structure 150. The first dummy gate structure 150 may include a first dummy gate insulating pattern 120, a first dummy gate electrode 130, and a first dummy gate capping 140 stacked in sequence. The first dummy gate insulating pattern 120 may include an oxide (e.g., silicon oxide), the first dummy gate electrode 130 may include, for example, polysilicon, and the first dummy gate capping 140 may include an insulating nitride (e.g., silicon nitride). In an exemplary embodiment, the first dummy gate structure 150 may extend in a second direction D2 on a first region I of the substrate 100, and a plurality of first dummy gate structures 150 may be spaced apart from each other in a first direction D1. Referring to FIGS. 8 to 10, a first gate spacer 160 may be formed on each of opposite sidewalls of the first dummy gate structure 150 in the first direction D1, and a fin spacer 170 may be formed on each of opposite sidewalls of the first active pattern 105 in the second direction D2. The first gate spacer 160 and the fin spacer 170 can be formed in the following manner: A first spacer layer is formed on the first active pattern 105, the first isolation pattern 110, the first alignment key 115, and the first dummy gate structure 150, and the first spacer layer is etched anisotropically. The first gate spacer 160 can include an insulating nitride (such as silicon nitride, silicon oxynitride, silicon carbon oxynitride, etc.). The upper portion of the first active pattern 105 can be etched using the first dummy gate structure 150 and the first gate spacer 160 as an etch mask to form the first recess 180. FIG. 8 shows the formation of the first recess 180 by partially removing the first upper active pattern 105b. However, aspects of the inventive concept are not limited thereto. In some embodiments, the first recess 180 can be formed by partially removing both the first lower active pattern 105a and the first upper active pattern 105b. In an exemplary embodiment, the anisotropic etching process of the first spacer layer and the etching process for forming the first recess 180 can be performed in-situ. The upper surface of the first active pattern 105 exposed by the first recess 180 can be used as a seed to perform a selective epitaxial growth (SEG) process to form the first source / drain layer 190 on the first active pattern 105. A silicon source gas (such as dichlorosilane (SiH 2 Cl 2 ), a germanium source gas (such as germane (GeH 4 ), and a p-type impurity source gas (such as diborane (B 2 H 6 )) can be used to perform the SEG process, so that a p-type impurity-doped single crystal silicon-germanium layer can be formed as the first source / drain layer 190. As an alternative, a silicon source gas (such as disilane (Si 2 H 6 ), SiH 3 CH 3 gas, etc.) and an n-type impurity source gas (such as PH 3 ), POCl 3, P 2 O 5 etc.) to perform the SEG process, so that a single-crystalline silicon layer doped with n-type impurities or a single-crystalline silicon carbide layer doped with n-type impurities can be formed as the first source / drain layer 190. The first source / drain layer 190 can fill the first recess 180 and can further grow to contact the lower sidewalls of the first gate spacer 160. The first source / drain layer 190 can grow in the horizontal direction and in the vertical direction to have a cross-section with a pentagonal shape taken along the second direction D2. If the distance between adjacent first active patterns 105 in the second direction D2 in the first active pattern 105 is small, the first source / drain layers 190 in the first source / drain layer 190 grown from the upper surfaces of the adjacent first active patterns 105 in the first active pattern 105 can merge with each other. A first insulating interlayer 200 can be formed on the substrate 100 having the first dummy gate structure 150, the first gate spacer 160, the fin spacer 170, the first source / drain layer 190, the first isolation pattern 110, and the first alignment key 115 thereon to have an upper surface higher than the upper surfaces of the first dummy gate structure 150 and the first gate spacer 160. Referring to FIG. 10, a planarization process can be performed until the upper surface of the first dummy gate electrode 130 included in the first dummy gate structure 150 is exposed, the upper portion of the first insulating interlayer 200 and the first dummy gate capping 140 included in the first dummy gate structure 150 are removed, and the upper portion of the first gate spacer 160 can also be removed. The first dummy gate electrode 130 and the first dummy gate insulating pattern 120 can be removed to form a first opening 210 exposing the upper surfaces of the first active pattern 105 and the first isolation pattern 110. In an exemplary embodiment, the first dummy gate electrode 130 and the first dummy gate insulating pattern 120 can be removed by sequentially performing a dry etching process and a wet etching process. For example, hydrofluoric acid (HF) can be used as the etching solution to perform the wet etching process. Referring to FIGS. 11 and 12, a first gate insulating layer and a first conductive layer can be sequentially stacked on the bottom and sidewalls of the first opening 210 and the upper surface of the first insulating interlayer 200, a second conductive layer can be formed on the first conductive layer to fill the remaining portion of the first opening 210, and the second conductive layer, the first conductive layer, and the first gate insulating layer can be planarized until the upper surface of the first insulating interlayer 200 is exposed. Therefore, a first gate structure 255 including a first gate insulating pattern 225, a first conductive pattern 235, and a second conductive pattern 245 stacked in sequence can be formed in the first opening 210, and the first conductive pattern 235 and the second conductive pattern 245 can form a first gate electrode. In an exemplary embodiment, each of the first conductive pattern 235 and the second conductive pattern 245 may include a metal (e.g., tungsten, aluminum, copper, titanium, etc.), a metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.), or a metal alloy. Referring to FIG. 13, an upper portion of the first gate structure 255 can be removed to form a second recess, and a first capping pattern 260 can be formed in the second recess. The first capping pattern 260 may include an insulating nitride, such as silicon nitride, silicon oxynitride, carbon oxynitride, etc. Referring to FIGS. 14 to 17, a second interlayer dielectric 270 can be formed on the first interlayer dielectric 200, the first capping pattern 260, and the first gate spacer 160, and the second interlayer dielectric 270 can be partially etched to form a second opening exposing the upper surface of the first source / drain layer 190. The second opening can partially extend through an upper portion of the first source / drain layer 190. The second interlayer dielectric 270 may include an oxide, such as silicon oxide. A first ohmic contact pattern 280 can be formed on the upper surface of the first source / drain layer 190 exposed by the second opening. Specifically, a first metal layer can be formed on the upper surface of the first source / drain layer 190 exposed by the second opening, the sidewalls of the second opening, and the upper surface of the second interlayer dielectric 270, and a heat treatment process can be performed on the first metal layer such that the metal contained in the first metal layer and the silicon contained in the first source / drain layer 190 can react with each other to form a first ohmic contact pattern 280 on the upper surface of the first source / drain layer 190. The unreacted portion of the first metal layer that has not reacted with the first source / drain layer 190 can be removed. The first ohmic contact pattern 280 may include a metal silicide, such as cobalt silicide, nickel silicide, titanium silicide, etc. A first contact plug layer can be formed on the first ohmic contact pattern 280 and the second interlayer dielectric 270 to fill the second opening, and the first contact plug layer can be planarized until the upper surface of the second interlayer dielectric 270 is exposed, thereby forming a first contact plug 290 in the second opening. In an exemplary embodiment, the first contact plug 290 may have a width that gradually decreases from its top to its bottom in the third direction D3. The first contact plug 290 may include, for example, a metal, a metal nitride, etc. An upper via and upper wiring may be further formed on the first contact plug 290 and the first gate electrode included in the first gate structure 255. Referring to FIGS. 18 and 19, the substrate 100 may be flipped so that the first surface 101 and the second surface 103 of the substrate 100 may face upward and downward, respectively, and the upper and lower portions of the structure located on the substrate 100 may hereinafter be referred to as the lower and upper portions of the structure, respectively. The upper portion of the substrate 100, i.e., the portion of the substrate 100 adjacent to the second surface 103, may be removed to expose the first alignment key 115. In an exemplary embodiment, the upper portion of the substrate 100 may be removed by, for example, a grinding process and / or a chemical mechanical polishing (CMP) process. After removing the upper portion of the substrate 100, the upper surface of the substrate 100 may be referred to as the third surface 107. Referring to FIGS. 20 to 22, a third opening may be formed through the first active pattern 105 of the substrate 100 to expose the upper surface of the first source / drain layer 190, and the third opening may partially extend through the upper portion of the first source / drain 190. In an exemplary embodiment, when forming the third opening, the first alignment key 115 located on the second region II of the substrate 100 may be used to position and align the third opening. A second ohmic contact pattern 300 may be formed on the upper surface of the first source / drain layer 190 exposed by the third opening. Specifically, a second metal layer may be formed on the upper surface of the first source / drain layer 190 exposed by the third opening, the sidewalls of the third opening, and the upper surface of the substrate 100, i.e., the third surface, and a heat treatment process may be performed on the second metal layer so that the metal contained in the second metal layer and the silicon contained in the first source / drain layer 190 may react with each other to form the second ohmic contact pattern 300 on the upper surface of the first source / drain layer 190. The unreacted portion of the second metal layer that has not reacted with the first source / drain layer 190 may be removed. The second ohmic contact pattern 300 may include a metal silicide, such as cobalt silicide, nickel silicide, titanium silicide, etc. A second contact plug layer may be formed on the second ohmic contact pattern 300 and the substrate 100 to fill the third opening, and the second contact plug layer may be planarized until the upper surface of the substrate 100, i.e., the third surface, is exposed to form a second contact plug 310 in the third opening. In an exemplary embodiment, the second contact plug 310 may have a width that gradually decreases from its top to its bottom in a third direction D3. The second contact plug 310 may comprise, for example, a metal, a metal nitride, or the like. In some embodiments, a second insulating layer may be further formed on the sidewalls of the third opening, and thus the sidewalls of the second contact plug 310 may be electrically insulated from the substrate 100 by the second insulating layer. Referring to FIGS. 23 to 26, a third inter-insulating layer 320 may be formed on the third surface 107 of the substrate 100, the first alignment key 115, and the second contact plug 310, and a first through hole 330 may be formed through the third inter-insulating layer 320 to contact the upper surface of the second contact plug 310. A fourth inter-insulating layer 340 may be formed on the third inter-insulating layer 320 and the first through hole 330, and a first wiring 350 may be formed through the fourth inter-insulating layer 340 to contact the upper surface of the first through hole 330. In an exemplary embodiment, the first wiring 350 may be used as a power rail for providing power. In an exemplary embodiment, the first wiring 350 may extend in a first direction D1. Alternatively, the first wiring 350 may extend in a second direction D2. FIGS. 23 to 25 show the first wiring 350 overlapping the first gate structure 255 in a third direction D3. However, aspects of the inventive concept are not limited thereto. For example, the second contact plug 310 may extend in a second direction D2 to a length greater than the length of the first gate structure 255, and each of the first through hole 330 and the first wiring 350 may not overlap the first gate structure 255 in a third direction D3. The first through hole 330 and the first wiring 350 may comprise, for example, a metal, a metal nitride, or the like. The second region II of the substrate 100 may be removed by, for example, a sawing process, and the first alignment key 115 may also be removed. By the above process, a semiconductor device may be manufactured. The semiconductor device may include a fin field-effect transistor (finFET), and the finFET may have a first gate structure 255 and a first source / drain layer 190. The first gate structure 255 is located on the first active pattern 105, and the first source / drain layer 190 is located at a portion of the first active pattern 105 adjacent to the first gate structure 255. As described above, the first alignment key 115 can be formed adjacent to the second surface 103 of the substrate 100 and can be used to position and align a structure (e.g., the first dummy gate structure 150) located on the second surface 103 of the substrate 100, and can be exposed by removing a portion of the substrate 100 adjacent to the first surface 101 of the substrate 100. Therefore, the first alignment key 115 can also be used to position and align a structure (e.g., the third opening for forming the second contact plug 310) located on the third surface 107 of the substrate 100. Accordingly, even if the first wiring 350 is formed on the third surface 107 of the substrate 100 rather than on the second surface 103 of the substrate 100, a structure (e.g., the second contact plug 310) for electrically connecting a structure (e.g., the first source / drain layer 190) adjacent to the second surface 103 of the substrate 100 to the first wiring 350 can also be aligned with the first source / drain layer 190 in the third direction D3. FIGS. 27 to 49 are plan views and cross-sectional views showing a semiconductor device according to an exemplary embodiment. Specifically, FIGS. 27, 30, 33, 37, 40, 44, and 46 are plan views, and FIGS. 28, 29, 31, 32, 34 to 36, 38, 39, 41 to 43, 45, and 47 to 49 are cross-sectional views. FIGS. 28, 31, 41, and 47 are cross-sectional views taken along line E-E' of the corresponding plan views, FIGS. 29, 32, 34, 36, 38, 39, 42, 45, and 48 are cross-sectional views taken along line F-F' of the corresponding plan views, and FIGS. 35, 43, and 49 are cross-sectional views taken along line G-G' of the corresponding plan views. This method may include a process substantially the same as or similar to the process shown in FIGS. 1 to 26, and thus its repeated description will be omitted here. That is, the semiconductor device may be a multi-bridge channel field effect transistor (MBCFET) including semiconductor patterns 424 spaced apart from each other in a third direction D3, which may serve as channels, respectively. Other components except for the semiconductor patterns 424 may respectively have structures and functions substantially the same as or similar to those of the corresponding components of the finFET shown in FIGS. 1 to 26, and may be respectively formed by processes substantially the same as or similar to those of the corresponding components. Therefore, repeated explanations are omitted herein. When referring to orientation, layout, position, shape, size, composition, quantity, or other metrics, terms such as "same", "equal", "flat", or "coplanar" used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, composition, quantity, or other metrics, but are intended to encompass almost the same orientation, layout, position, shape, size, composition, quantity, or other metrics within an acceptable range of variations that may occur, for example, due to the manufacturing process. Unless the context or other statements indicate otherwise, the term "substantially" is used herein to emphasize this meaning. For example, the terms described as "substantially the same", "substantially equal", or "substantially flat" may be exactly the same, exactly equal, or exactly flat, or may be the same, equal, or flat within an acceptable variation that may occur, for example, due to the manufacturing process. Referring to FIGS. 27 to 29, a sacrificial layer and a semiconductor layer may be alternately and repeatedly stacked on a substrate 400, and the upper portions of the semiconductor layer, the sacrificial layer, and the substrate 400 may be etched to form a third trench 402 and a fourth trench 404 in a first region I and a second region II of the substrate 400, respectively. The substrate 400 may include a first surface 401 and a second surface 403 opposite to each other in a third direction D3, and FIG. 29 shows that the first surface 401 and the second surface 403 of the substrate 400 face downward and upward, respectively. Therefore, the third trench 402 and the fourth trench 404 may be formed by removing portions of the substrate 400 adjacent to the second surface 403 of the substrate 400. In an exemplary embodiment, the third trench 402 may extend in a first direction D1 in the first region I of the substrate 400, and a plurality of third trenches 402 may be spaced apart from each other in a second direction D2. Accordingly, a plurality of second active patterns 405 may be defined on the first region I of the substrate 400. Each of the plurality of second active patterns 405 may extend in a first direction D1, be spaced apart from each other in a second direction D2, and a fin structure including sacrificial lines 412 and semiconductor lines 422 that are alternately and repeatedly stacked in a third direction D3 may be formed on each of the second active patterns 405. In an exemplary embodiment, the plurality of fin structures may be spaced apart from each other in the second direction D2 on the first region I of the substrate 400. FIG. 28 and FIG. 29 illustrate three sacrificial lines 412 and three semiconductor lines 422 formed at three levels, respectively. However, aspects of the inventive concept may not be limited thereto. The semiconductor lines 422 may include, for example, silicon, and the sacrificial lines 412 may include a material having an etching selectivity relative to the substrate 400 and the semiconductor lines 422 (e.g., silicon-germanium). FIG. 27 shows that the fourth trench 404 has a rectangular shape in a plan view. However, aspects of the inventive concept may not be limited thereto. Accordingly, the fourth trench 404 may have various shapes such as circular, elliptical, polygonal, etc. In some embodiments, a plurality of fourth trenches 404 may be formed on the second region II of the substrate 400. A third insulating layer may be formed to fill the third trench 402 and the fourth trench 404. The third insulating layer may include an oxide (e.g., silicon oxide). In an exemplary embodiment, the upper surface of the third insulating layer may be lower than the upper surface of the second active pattern 405 on the first region I of the substrate 400 and may be lower than the second surface 403 of the second region II of the substrate 400. However, aspects of the inventive concept may not be limited thereto. For example, the upper surface of the third insulating layer may be substantially coplanar with the upper surface of the second active pattern 405 and the second surface 403 of the substrate 400. When forming the third insulating layer, a second isolation pattern 430 may be formed in the third trench 402 on the first region I of the substrate 400, and a second alignment key 415 may be formed in the fourth trench 404 on the second region II of the substrate 400. As another alternative, the second alignment key 415 and the second isolation pattern 430 may be formed independently by depositing different insulating layers. For example, the fourth trench 404 may be formed on the second region II of the substrate 400, the second alignment key 415 may be formed in the fourth trench 404, the third trench 402 may be formed on the first region I of the substrate 400 to define the second active pattern 405, and the second isolation pattern 430 may be formed in the third trench 402. In such a case, the second alignment key 415 can be used to position and align the third trench 402. In some embodiments, the second alignment key 415 and the second isolation pattern 430 may comprise different materials. For example, the second isolation pattern 430 may comprise an oxide (e.g., silicon oxide), and the second alignment key 415 may comprise an insulating nitride (e.g., silicon nitride). Alternatively, the second alignment key 415 may have a multilayer structure formed by a third layer comprising an oxide and a fourth layer comprising an insulating nitride. Referring to FIGS. 30 to 32, a second dummy gate structure 470 can be formed on a first region I of the substrate 400 to partially cover the fin structure and the second isolation pattern 430, and the second alignment key 415 located on a second region II of the substrate 400 can be used to position and align the second dummy gate structure 470. The second dummy gate structure 470 may include a second dummy gate insulating pattern 440, a second dummy gate electrode 450, and a second dummy gate capping 460 that are sequentially stacked in a third direction D3 on a portion of the second active pattern 405 and the second isolation pattern 430 adjacent to the second active pattern 405. In an exemplary embodiment, the second dummy gate structure 470 can extend on the fin structure and the second isolation pattern 430 in a second direction D2, and can cover the upper surface and the opposite sidewalls in the second direction D2 of the fin structure. In an exemplary embodiment, a plurality of second dummy gate structures 470 can be spaced apart from each other in a first direction D1 on a first region I of the substrate 400. The second dummy gate insulating pattern 440 may comprise an oxide (e.g., silicon oxide), the second dummy gate electrode 450 may comprise polysilicon, and the second dummy gate capping 460 may comprise an insulating nitride (e.g., silicon nitride). Referring to FIGS. 33 to 35, a second gate spacer 480 can be formed on the sidewalls of the second dummy gate structure 470. Specifically, a second spacer can be formed on the substrate 400 having a fin structure, a second isolation pattern 430, a second dummy gate structure 470, and a second alignment key 415 thereon, and anisotropic etching can be performed to form the second gate spacer 480 covering each of the opposite sidewalls in the first direction D1 of the second dummy gate structure 470. The second dummy gate structure 470 and the second gate spacer 480 can be used as an etching mask to etch an upper portion of the fin structure and the second active pattern 405 located on a first region I of the substrate 400 to form a fourth opening 490. Accordingly, the sacrificial line 412 and the semiconductor line 422 located under the second dummy gate structure 470 and the second gate spacer 480 can be respectively transformed into a sacrificial pattern 414 and a semiconductor pattern 424, and the fin structure extending in the first direction D1 can be divided into a plurality of parts spaced apart from each other in the first direction D1. Hereinafter, the second dummy gate structure 470, the second gate spacers 480 on each of the opposite sidewalls of the second dummy gate structure 470, and the fin structure may be referred to as a stacked structure. In an exemplary embodiment, the stacked structure may extend in the second direction D2, and a plurality of stacked structures may be spaced apart from each other in the first direction D1. In some embodiments, a portion of each of the sacrificial patterns 414 adjacent to the fourth opening 490 may be removed to form a gap, and an internal spacer (not shown) may be formed in the gap. The upper surface of the second active pattern 405 and the sidewalls of the semiconductor pattern 424 and the sacrificial pattern 414 exposed by the fourth opening 490 may be used as seeds to perform a selective epitaxial growth (SEG) process to form a second source / drain layer 510 on the inner wall of the fourth opening 490. In an exemplary embodiment, a single crystal silicon-germanium layer doped with a p-type impurity may be formed as the second source / drain layer 510. Alternatively, a single crystal silicon layer doped with an n-type impurity or a single crystal silicon carbide layer doped with an n-type impurity may be formed as the second source / drain layer 510. A fifth insulating interlayer 530 may be formed on the substrate 400 to cover the stacked structure, the second source / drain layer 510, and the first alignment key 415. Referring to FIG. 36, a process substantially the same as or similar to the process shown in FIG. 10 may be performed. Accordingly, a planarization process may be performed until the upper surface of the second dummy gate electrode 450 included in the stacked structure is exposed, so that the upper portion of the fifth insulating interlayer 530 and the second dummy gate capping 460 included in the second dummy gate structure 470 can be removed. The second dummy gate electrode 450, the second dummy gate insulating pattern 440, and the sacrificial pattern 414 may be removed by, for example, a wet etching process and / or a dry etching process to form a fifth opening 540 exposing the inner sidewall of the second gate spacer 480 and the upper surface of the uppermost semiconductor pattern in the semiconductor pattern 424, and a sixth opening 550 exposing the sidewall of the second source / drain layer 510, the surface of the semiconductor pattern 424, and the upper surface of the second active pattern 405. Referring to FIGS. 37 and 38, a process substantially the same as or similar to the processes shown in FIGS. 11 and 12 may be performed. Therefore, a second gate insulating layer and a third conductive layer can be sequentially stacked on the upper surface of the second active pattern 405, the upper surface of the second isolation pattern 430, the sidewalls of the second source / drain layer 510, the surface of the semiconductor pattern 424, the inner sidewalls of the second gate spacer 480 exposed by the fifth opening 540 and the sixth opening 550, and the upper surface of the second active pattern 405. A fourth conductive layer can be formed on the third conductive layer to fill the fifth opening 540 and the sixth opening 550, and the fourth conductive layer, the third conductive layer, and the second gate insulating layer can be planarized until the upper surface of the fifth insulating interlayer 530 is exposed. Therefore, a second gate structure 595 including a second gate insulating pattern 565, a third conductive pattern 575, and a fourth conductive pattern 585 stacked in sequence can be formed in the fifth opening 540 and the sixth opening 550, and the third conductive pattern 575 and the fourth conductive pattern 585 can form a second gate electrode. Referring to FIG. 39, an upper portion of the second gate structure 595 can be removed to form a third recess, and a second capping pattern 600 can be formed in the third recess. The second capping pattern 600 can include an insulating nitride, such as silicon nitride, silicon oxynitride, silicon carbon oxynitride, etc. Referring to FIGS. 40 to 43, a process substantially the same as or similar to the process shown in FIGS. 14 to 17 can be implemented. Therefore, a sixth insulating interlayer 610 can be formed on the fifth insulating interlayer 530, the second capping pattern 600, and the second gate spacer 480, and a seventh opening can be formed through the fifth insulating interlayer 530 and the sixth insulating interlayer 610 to expose the upper surface of the second source / drain layer 510. The seventh opening can also extend through an upper portion of the second source / drain layer 510. The sixth insulating interlayer 610 can include an oxide, such as silicon oxide. A third ohmic contact pattern 620 can be formed on the upper surface of the second source / drain layer 510 exposed by the seventh opening, and the third ohmic contact pattern 620 can include a metal silicide, such as cobalt silicide, nickel silicide, titanium silicide, etc. A third contact plug 630 can be formed in the seventh opening. In an exemplary embodiment, the third contact plug 630 can have a width that gradually decreases in a third direction D3 from its top to its bottom. The third contact plug 630 can include a metal, a metal nitride, etc. An upper via and upper wiring can be formed to electrically connect to the third contact plug 630 and the second gate electrode of the second gate structure 595. Referring to FIGS. 44 and 45, the substrate 400 can be flipped so that the first surface 401 and the second surface 403 can face upward and downward respectively, and thus the upper and lower portions of the structures located on the substrate 400 can be referred to as the lower portion and the upper portion respectively. The upper portion of the substrate 400, i.e., the portion of the substrate 400 adjacent to the second surface 403, can be removed to expose the second alignment key 415. Hereinafter, after removing the upper portion of the substrate 400, the upper surface of the substrate 400 can be referred to as the third surface 407 of the substrate 400. Referring to FIGS. 46 to 49, a process substantially the same as or similar to the process shown in FIGS. 20 to 26 can be implemented. Specifically, an eighth opening can be formed through the substrate 400 and the second active pattern 405 to expose the upper surface of the second source / drain layer 510, and the eighth opening can also extend through the upper portion of the second source / drain layer 510. In an exemplary embodiment, when forming the eighth opening, the second alignment key 415 located on the second region II of the substrate 400 can be used to position and align the eighth opening. A fourth ohmic contact pattern 650 can be formed on the upper surface of the second source / drain layer 510 exposed by the eighth opening, and a fourth contact plug 660 can be formed in the eighth opening. In an exemplary embodiment, the fourth contact plug 660 can have a width that gradually decreases in the third direction D3 from its top to its bottom. However, in some embodiments, a fourth insulating layer can be further formed on the sidewall of the eighth opening, and thus the fourth contact plug 660 can be electrically insulated from the substrate 400 by the fourth insulating layer. A seventh insulating interlayer 670 can be formed on the third surface 407 of the substrate 400, the second alignment key 415, and the fourth contact plug 660, and a second through hole 680 can be formed through the seventh insulating interlayer 670 to contact the upper surface of the fourth contact plug 660. An eighth insulating interlayer 690 can be formed on the seventh insulating interlayer 670 and the second through hole 80, and a second wiring 700 can be formed through the eighth insulating interlayer 690 to contact the upper surface of the second through hole 680. In an exemplary embodiment, the second wiring 700 can be used as a power rail. In an exemplary embodiment, the second wiring 700 can extend in the first direction D1. Alternatively, the second wiring 700 can extend in the second direction D2. FIG. 48 shows that the second wiring 700 overlaps with the second gate structure 595 in the third direction D3. However, aspects of the inventive concept are not limited thereto. For example, the fourth contact plug 660 may extend in the second direction D2 to a length greater than the length of the second gate structure 595, and each of the second vias 680 and the second wiring 700 may not overlap with the second gate structure 595 in the third direction D3. The second region II of the substrate 400 may be removed by, for example, a sawing process, and the second alignment key 415 may also be removed. Through the above process, a semiconductor device can be manufactured. As described above, the second alignment key 415 may be formed adjacent to the second surface 403 of the substrate 400 and may be used to position and align a structure (such as the second dummy gate structure 470) located on the second surface 403 of the substrate 400, and may be exposed by removing a portion of the substrate 400 adjacent to the first surface 401 of the substrate 400. Therefore, the second alignment key 415 may also be used to position and align a structure (such as the eighth opening for forming the fourth contact plug 660) located on the third surface 407 of the substrate 400. Therefore, even if the second wiring 700 is formed on the third surface 407 of the substrate 400 instead of the first surface 403 of the substrate 400, the structure (such as the fourth contact plug 660) for electrically connecting a structure (such as the second source / drain layer 510) adjacent to the second surface 403 of the substrate 400 to the second wiring 700 may also be aligned with the second source / drain layer 510 in the third direction D3. FIGS. 50 to 55 are a plan view and cross-sectional views showing a method of manufacturing a semiconductor device according to an exemplary embodiment. Specifically, FIG. 51 is a plan view, FIG. 52 is a cross-sectional view taken along line E-E' of the corresponding plan view, and FIGS. 50 and 53 to 55 are cross-sectional views taken along line F-F' of the corresponding plan view. This method may include processes substantially the same as or similar to the processes shown in FIGS. 27 to 49, and thus repeated explanations thereof will be omitted here. Referring to FIG. 50, a fourth trench 404 may be formed in the second region II of the substrate 400 including the first region I and the second region II, and a sacrificial layer 410 and a semiconductor layer 420 may be alternately and repeatedly stacked on the substrate 400 having the fourth trench thereon. A fifth insulating layer may be formed on the uppermost semiconductor layer in the semiconductor layer 420, and an upper portion of the fifth insulating film may be planarized until the upper surface of the uppermost semiconductor layer in the semiconductor layer 420 is exposed to form a third key pattern 417 on a portion of the uppermost semiconductor layer in the fourth trench 404. In the following text, the portions of the sacrificial layer 410 and the semiconductor layer 420 in the fourth trench 404 and the region of the second region II of the substrate 400 adjacent to the fourth trench 404 may be respectively referred to as the first key pattern 411 and the second key pattern 421, and the first key pattern 411 and the second key pattern 421 may jointly form a key pattern structure 500. Additionally, the key pattern structure 500 and the third key pattern 417 may jointly form a third alignment key 419. Referring to FIGS. 51 to 53, the semiconductor layer 420, the sacrificial layer 410, and the upper portion of the substrate 400 on the first region I of the substrate 400 may be partially removed to form a third trench 402 on the first region I of the substrate 400, and a second isolation pattern 430 may be formed in the third trench 402. Therefore, each second active pattern 405 that can extend in the first direction D1 may be spaced apart from each other in the second direction D2 on the first region I of the substrate 400, and a fin structure may be formed on each of the second active patterns 405, and the fin structure includes sacrificial lines 412 and semiconductor lines 422 that are alternately and repeatedly stacked in the third direction D3. A process substantially the same as or similar to the process shown in FIGS. 30 to 43 may be implemented. Referring to FIG. 54, a process substantially the same as or similar to the process shown in FIGS. 44 and 45 may be implemented. The upper portion of the substrate 400, that is, the portion of the substrate 400 adjacent to the second surface 403 of the substrate 400, may be removed to expose the third alignment key 419. In an exemplary embodiment, when the portion of the substrate 400 adjacent to its second surface 403 is removed, the upper portions of the key pattern structure 500 and the third key pattern 417 included in the third alignment key 419 may also be removed. Therefore, the portion of the key pattern structure 500 located on the upper surface of the third key pattern 417 may be removed, and the first key pattern 411 and the second key pattern 421 included in the key pattern structure 500 may be alternately and repeatedly stacked in the horizontal direction on the sidewalls of the third key pattern 417. Referring to FIG. 55, in another exemplary embodiment, when the portion of the substrate 400 adjacent to its second surface 403 is removed, the upper surface of the key pattern structure 500 included in the third alignment key 419 may be exposed, and the upper portions of the key pattern structure 500 and the third key pattern 417 may not be removed. A process substantially the same as or similar to the process shown in FIGS. 46 to 49 may be implemented to complete the fabrication of the semiconductor device. The semiconductor device can be used in various types of memory devices and / or systems including power rails. For example, the semiconductor device can be applied to logic devices such as a central processing unit (CPU), an application processor (AP), etc. As another option, the semiconductor device can be applied to volatile memory devices such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, etc., or can be applied to non-volatile memory devices such as a flash memory device, a phase change random access memory (PRAM) device, a magnetic random access memory (MRAM) device, a resistance random access memory (RRAM) device, etc. The foregoing is an illustration of exemplary embodiments and should not be construed as a limitation thereof. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the aspects of the inventive concept as defined in the claims. In the claims, the means-plus-function clause is intended to cover the structures described herein as performing the recited function, and covers not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is an illustration of various exemplary embodiments and should not be construed as being limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments as well as other exemplary embodiments are also intended to be included within the scope of the appended claims. 100, 400: Substrate 101, 401: First surface 102: First trench 103, 403: Second surface 104: Second trench 105: First active pattern 105a: First lower active pattern 105b: First upper active pattern 107, 407: Third surface 110: First isolation pattern 115: First alignment key / first capping key 120: First dummy gate insulating pattern 130: First dummy gate electrode 140: First dummy gate capping 150: First dummy gate structure 160: First gate spacer 170: Fin spacer 180: First recess 190: First source / drain layer 200: First inter-insulating layer 210: First opening 225: First gate insulating pattern 235: First conductive pattern 245: Second conductive pattern 255: First gate structure 260: First capping pattern 270: Second inter-insulating layer 280: First ohmic contact pattern 290: First contact plug 300: Second ohmic contact pattern 310: Second contact plug 320: Third inter-insulating layer 330: First via 340: Fourth inter-insulating layer 350: First wiring 402: Third trench 404: Fourth trench 405: Second active pattern 410: Sacrificial layer 411: First key pattern 412: Sacrificial line 414: Sacrificial pattern 415: Second alignment key 417: Third key pattern 419: Third alignment key 420: Semiconductor layer 421: Second key pattern 422: Semiconductor line 424: Semiconductor pattern 430: Second isolation pattern 440: Second dummy gate insulating pattern 450: Second dummy gate electrode 460: Second dummy gate capping 470: Second dummy gate structure 480: Second gate spacer 490: Third opening 500: Key pattern structure 510: Second source / drain layer 530: Fifth inter-insulating layer 540: Fifth opening 550: Sixth opening 565: Second gate insulating pattern 575: Third conductive pattern 585: Fourth conductive pattern 595: Second gate structure 600: Second capping pattern 610: Sixth inter-insulating layer 620: Third ohmic contact pattern 630: Third contact plug 650: Fourth ohmic contact pattern 660: Fourth contact plug 670: Seventh inter-insulating layer 680: Second via 690: Eighth inter-insulating layer 700: Second wiring A-A', B-B', C-C', E-E', F-F', G-G': Lines D1: First direction D2: Second direction D3: Third direction I: First region II: Second region FIGS. 1 to 26 are plan views and cross-sectional views showing a method of manufacturing a semiconductor device according to an exemplary embodiment. FIGS. 27 to 49 are plan views and cross-sectional views showing a semiconductor device according to an exemplary embodiment. FIGS. 50 to 55 are plan views and cross-sectional views showing a method of manufacturing a semiconductor device according to an exemplary embodiment. 100: Substrate 103: Second surface 105: First active pattern 105a: First lower active pattern 105b: First upper active pattern 107: Third surface 115: First alignment key / first capping key 160: First gate spacer 190: First source / drain layer 200: First inter-insulating layer 225: First gate insulating pattern 235: First conductive pattern 245: Second conductive pattern 255: First gate structure 260: First capping pattern 270: Second inter-insulating layer 280: First ohmic contact pattern 290: First contact plug B-B': Line D1: First direction D2: Second direction D3: Third direction I: First region II: Second region

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A portion extending through the substrate forms an alignment bond, the substrate comprising a first surface and a second surface opposite to each other, the portion being adjacent to the second surface; A transistor is formed on the second surface of the substrate, the transistor including a gate structure and a source / drain layer; Remove a portion of the substrate adjacent to the first surface of the substrate to expose the alignment key; A contact plug is formed through a portion of the substrate adjacent to the first surface of the substrate, and the contact plug is electrically connected to the source / drain layer; A power rail is formed on the first surface of the substrate, the power rail being electrically connected to the contact plug.

2. The method as described in claim 1, wherein forming the alignment key comprises: Remove a portion of the substrate adjacent to the second surface of the substrate to form a first trench; And an insulating layer is formed in the first trench.

3. The method of claim 2, wherein the substrate includes a wafer region and a scribe line region, and the first trench is formed in the scribe line region of the substrate, and wherein the method further includes: In the wafer region, a portion of the substrate adjacent to the second surface of the substrate is removed to form a second trench; And to form an isolation pattern in the second ditch.

4. The method of claim 3, wherein the second trench defines an active pattern in the wafer region of the substrate, and wherein the isolation pattern is formed in a lower portion of the second trench and covers the lower sidewall of the active pattern.

5. The method as described in claim 1, wherein forming the alignment key comprises: A sacrificial layer and a semiconductor layer are alternately and repeatedly stacked on the second surface of the substrate, the sacrificial layer comprising silicon-germanium and the semiconductor layer comprising silicon; Partially remove the sacrificial layer, the semiconductor layer, and portions of the substrate adjacent to the second surface of the substrate; and form an insulating layer in the first trench.

6. The method of claim 5, wherein the substrate includes a wafer region and a scribe line region, the first trench is formed in the scribe line region of the substrate, and wherein the method further comprises: In the wafer region, a portion of the sacrificial layer, the semiconductor layer, and the portion of the substrate adjacent to the second surface of the substrate is partially removed to form a second trench; And to form an isolation pattern in the second ditch.

7. The method as described in claim 1, wherein forming the alignment key comprises: Remove a portion of the substrate adjacent to the second surface of the substrate to form a first trench; A sacrificial layer and a semiconductor layer are alternately and repeatedly stacked on the second surface having the first trench on the substrate; and an insulating layer is formed on the uppermost portion of the semiconductor layer in the first trench.

8. The method of claim 7, wherein the substrate includes a wafer region and a scribe line region, the first trench is formed in the scribe line region of the substrate, and wherein the method further comprises: In the wafer region, a portion of the sacrificial layer, the semiconductor layer, and the portion of the substrate adjacent to the second surface of the substrate is partially removed to form a second trench; And to form an isolation pattern in the second ditch.

9. A method for manufacturing a semiconductor device, the method comprising: A portion of the substrate is removed from the wafer region and the scribe line region to form a first trench and a second trench, respectively. The substrate includes a first surface and a second surface opposite to each other, and the portion is adjacent to the second surface of the substrate. Isolation patterns and alignment keys are formed in the first trench and the second trench, respectively. A dummy gate structure is formed on the second surface of the substrate. A source / drain layer is formed on the portion of the substrate adjacent to the dummy gate structure. The dummy gate structure is replaced with a gate structure; Remove a portion of the substrate adjacent to the first surface of the substrate to expose the alignment key; A contact plug is formed through a portion of the substrate adjacent to the first surface of the substrate, and the contact plug is electrically connected to the source / drain layer; A power rail is formed on the first surface of the substrate, the power rail being electrically connected to the contact plug.

10. A method of manufacturing a semiconductor device, the method comprising: A portion of the substrate is removed from the scribe line region to form a first trench. The substrate includes a first surface and a second surface opposite to each other, a wafer region, and the scribe line region, and the portion is adjacent to the second surface of the substrate. A sacrificial layer and a semiconductor layer are alternately and repeatedly stacked on the second surface of the substrate having the first trench. An insulating layer is formed on the uppermost semiconductor layer of the semiconductor layers in the first trench to form alignment bonds. In the wafer region, a portion of the semiconductor layer, the sacrificial layer, and a portion of the substrate adjacent to the second surface of the substrate is partially removed to form a semiconductor line, a sacrificial line, and a second trench, respectively, the second trench defining an active pattern; an isolation pattern is formed in the second trench; A dummy gate structure is formed on the semiconductor line, the sacrificial line, the active pattern, and the isolation pattern; a source / drain layer is formed on the portion of the active pattern adjacent to the dummy gate structure; and the dummy gate structure is replaced with a gate structure. Remove a portion of the substrate adjacent to the first surface of the substrate to expose the alignment key; A contact plug is formed through a portion of the substrate adjacent to the first surface of the substrate, and the contact plug is electrically connected to the source / drain layer; A power rail is formed on the first surface of the substrate, the power rail being electrically connected to the contact plug.

Images