Semiconductor device and method of manufacturing the same

Abstract

A method for forming a semiconductor structure includes depositing a dummy material stack over a fin, patterning the top of the dummy material stack in a first etching process, patterning the middle of the dummy material stack in a second etching process, patterning the bottom of the dummy material stack in a third etching process to form a dummy gate stack, and replacing the dummy gate stack with a metal gate stack, wherein the second etching process is weaker than the first etching process and the third etching process is weaker than the second etching process.

Description

Semiconductor Device and Method of Forming the Same Embodiments of the present invention relate to semiconductor technology, and more particularly, to a semiconductor device and a method of forming the same. The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits, each with smaller and more complex circuits than the previous generation. During the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per unit wafer area) generally increases while the geometric size (i.e., the smallest component (or line) that can be produced using the process) decreases. This process of miniaturization generally provides benefits by increasing production efficiency and reducing related costs. This miniaturization also increases the complexity of manufacturing integrated circuits. Recently, multi-gate semiconductor devices have been introduced to attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). One such multi-gate semiconductor device that has been introduced is the gate-all-around (GAA) transistor. The name GAA device comes from the gate structure, which extends around the channel region, providing access to the channel region from four sides, thereby allowing the channel region to be more fully depleted and resulting in a smaller short-channel effect due to a steeper sub-threshold current swing (SS) and a smaller drain induced barrier lowering (DIBL). The GAA device provides a channel region in the form of a stacked channel layer. However, as transistor sizes continue to shrink to below the 3-nanometer process generation (technology nodes), maintaining gate control and mitigating SCE and DIBL can be challenging. Although current methods have been satisfactory in many respects, further improvements to multi-gate semiconductor devices are still needed as transistor sizes are rapidly miniaturized. In one illustrative aspect, the present disclosure relates to a method of forming a semiconductor structure, the method including providing a structure including a substrate and fins protruding from the substrate, depositing a dummy material stack over the fins, patterning a top of the dummy material stack in a first etching process having a first etching strength, patterning a middle of the dummy material stack in a second etching process having a second etching strength weaker than the first etching strength, patterning a bottom of the dummy material stack in a third etching process having a third etching strength weaker than the second etching strength to form a dummy gate stack, and replacing the dummy gate stack with a metal gate stack. In another illustrative aspect, the present disclosure relates to a method of forming a semiconductor device, the method comprising forming fins protruding from a substrate, depositing a dummy electrode layer over the fins, etching a top portion of the dummy electrode layer in a first etching process to form a first sidewall above a top surface of the fins, etching a bottom portion of the dummy electrode layer in a second etching process to form a second sidewall below the top surface of the fins, wherein the first etching process and the second etching process use different etching recipes, and the second sidewall tapers from the first sidewall, depositing a gate spacer layer on the first sidewall and the second sidewall of the dummy electrode layer, removing the dummy electrode layer to form a gate trench, and depositing a metal gate stack in the gate trench. In yet another illustrative aspect, the present disclosure relates to a semiconductor device, the device comprising a substrate, a plurality of channel layers vertically stacked and suspended over the substrate, and a gate structure surrounding each of the channel layers, wherein the gate structure has a first gate critical dimension measured at a top surface of the topmost channel layer of the channel layers, a second gate critical dimension measured at an edge of the topmost channel layer of the channel layers, and a third gate critical dimension measured at an edge of the bottommost channel layer of the channel layers, wherein the second gate critical dimension is greater than the first gate critical dimension, and the third gate critical dimension is greater than the second gate critical dimension. The following disclosure provides many examples or exemplifications for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, when it is described that a first element is formed over a second element, it may include an embodiment where the first and second elements are in direct contact, or it may include an embodiment where additional elements are formed between the first and second elements so that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations being discussed. Furthermore, spatially relative terms may be used, such as "under", "below", "lower", "above", "higher", etc., for ease of describing the relationship between one or more components or components in a drawing. Spatially relative terms are intended to include different orientations of the device in use or operation, as well as the orientations described in the drawing. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the orientation after turning. In addition, when using terms such as "about", "approximate", etc. to describe a number or a range of numbers, such terms are intended to cover numbers within + / - 10% of the stated number. For example, the term "about 5 nm" covers dimensions in the range of 4.5 nm to 5.5 nm. This disclosure generally relates to semiconductor devices and methods of formation, and more particularly to forming multi-gate devices having gate structures with a coverage profile that provides tapered (increasing) gate critical dimensions (CDs). These multi-gate devices can include p-type metal oxide semiconductor devices or n-type metal oxide semiconductor devices. Specific embodiments of one type of multi-gate transistor, referred to as a gate-all-around (GAA) device, are provided herein. A GAA device includes any device in which its gate structure or a portion thereof is formed on four sides of a channel region (e.g., surrounding a portion of the channel region). The channel region includes a stack of channel layers (or referred to as channel members) in the form of nanosheets, nanowires, rods, and / or other suitable channel configurations associated with a single, continuous gate structure. However, one of ordinary skill in the art will understand that this teaching can be applied to a single channel layer (e.g., a single nanowire / nanosheet) or any number of channel layers. Other examples of semiconductor devices (such as fin field-effect transistor (FinFET) transistors) that can benefit from aspects of this disclosure will be understood by one of ordinary skill in the art. In some IC designs, such as multi-gate device designs, one advancement enabled by scaling down the process generation is replacing dummy gates (e.g., polysilicon gates) with metal gates (e.g., high-k gates) to improve device performance as component sizes are reduced. A process for forming a metal gate is referred to as a replacement gate or “gate-last” process, where the metal gate is fabricated “last” to replace an earlier-formed dummy gate, which allows for a reduction in the number of subsequent processes. Generally, the goal of the patterning process for forming a dummy gate is to provide vertical gate sidewall profiles, particularly the vertical corner profiles in the intersecting junctions where the dummy gate structure, fin epitaxial stack, intersects the top surface of the substrate (the top of the substrate may include isolation regions, as will be further explained in detail below). The vertical corner profiles improve gate critical dimension (CD) uniformity. In contrast, embodiments of the present disclosure intentionally introduce gate CD non-uniformity and introduce a “corner” (or “footing”) into the gate sidewall profile. In some embodiments, multiple etch steps with different etch intensities are applied during the gate patterning process to form a gate structure with tapered gate sidewalls. The coverage of the tapered gate sidewalls forms a “corner”. The gate CD at the corner is greater than the gate CD above the fin top surface. The larger the gate CD, the stronger the gate drive capability, thereby alleviating the short-channel effect (SCE) and drain induced barrier lowering (DIBL). FIG. 1 is a flowchart illustrating a method 10 for forming a semiconductor device 100 (or device 100) according to an embodiment of the present disclosure. Method 10 is merely illustrative and is not intended to limit the present disclosure beyond what is expressly recited in the claims. Additional operations may be provided before, during, and after method 10, and some of the described operations may be replaced, deleted, or moved for additional embodiments of the method. Method 10 will be described below in conjunction with FIGS. 2 through 24. FIGS. 2 through 24 illustrate various perspective views and cross-sectional views of device 100 during intermediate manufacturing steps according to method 10 of FIG. 1. Device 100 is provided for illustrative purposes and is not intended to limit embodiments of the present disclosure to any number of devices, any number of regions, or any configuration of structures or regions. For example, device 100 illustrated in the following embodiments may be applied to, but is not limited to, GAA FETs, FinFETs, or other transistors including multi-gate structures. Referring to FIGS. 1 and 2, at operation 12, method 10 provides or is equipped with a device 100 having a substrate 102. In some embodiments, substrate 102 includes a crystalline silicon substrate (e.g., a wafer). According to design requirements, substrate 102 may include various doped regions (e.g., p-type wells and / or n-type wells). In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants such as boron or boron difluoride (BF 2 ), n-type dopants such as phosphorus or arsenic, and / or combinations thereof. The doped regions may be configured for n-type transistors, or alternatively, for p-type transistors. In some embodiments, an anti-punch-through (APT) implant is performed on top of substrate 102 to form an APT region. The dopant of the implanted APT region has the same conductivity type as the doped region (or well). The APT region may extend below the subsequently formed source / drain (S / D) regions and is used to reduce leakage from the S / D regions to substrate 102. For clarity, the doped regions and the APT regions are not shown in FIG. 1 and subsequent figures. In some alternative embodiments, substrate 102 includes an elemental semiconductor such as silicon or germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, an alloy semiconductor such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP), or combinations thereof. As shown in FIG. 2, a semiconductor stack 104 is formed on substrate 102. Semiconductor stack 104 may include a plurality of first layers 106 and a plurality of second layers 108 stacked alternately along the Z direction. Although only three first layers 106 and three second layers 108 are shown in FIG. 2, the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of first layers 106 and second layers 108 may be adjusted as needed, such as one layer, two layers, four layers, or more first layers 106 and second layers 108. In some embodiments, the first layer 106 and the second layer 108 comprise different materials. For example, the second layer 108 is a silicon germanium (SiGe) layer having a germanium atom percentage in the range of about 15% to 40%, and the first layer 106 is a germanium-free silicon (Si) layer. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the first layer 106 and the second layer 108 may have materials with different etching selectivities. In some embodiments, the first layer 106 and the second layer 108 are formed by an epitaxial growth process, such as a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, etc. Therefore, the semiconductor stack 104 may also be referred to as an epitaxial semiconductor stack 104. In this case, the first layer 106 is an epitaxial silicon (Si) layer, and the second layer 108 is an epitaxial silicon germanium (SiGe) layer. In some alternative embodiments, the first layer 106 and the second layer 108 are formed by suitable depositions, such as chemical vapor deposition (CVD), atomic layer deposition process (ALD), etc. The first layer 106 and the second layer 108 may have the same or different thicknesses. In some embodiments, the first layer 106 has the same thickness T1 and the second layer 108 has the same thickness T2. In some embodiments, the thickness T1 ranges from about 5 nanometers to about 20 nanometers, and the second thickness T2 ranges from about 5 nanometers to about 20 nanometers. Alternatively, the first layer 106 from top to bottom may have different thicknesses, and the second layer 108 from top to bottom may have different thicknesses. As shown in FIG. 2, a mask layer 110 is formed on the semiconductor stack 104. The mask layer 110 may include a single-layer structure, a two-layer structure, or a multi-layer structure. For example, the mask layer 110 includes a silicon oxide layer and a silicon nitride layer on the silicon oxide layer. In some embodiments, the mask layer 110 is formed by CVD, ALD, etc. Referring to FIGS. 1 and 3, in operation 14, method 10 patterns mask layer 110 to form a plurality of mask bars 110S. Then, by using mask bars 110S as a mask, semiconductor stack 104 and substrate 102 are patterned to form a plurality of trenches 114. In this case, a plurality of fin bases 116 and a plurality of semiconductor strip stacks 120 on fin bases 116 are formed between trenches 114. Trenches 114 extend into substrate 102 and have a longitudinal direction parallel to each other. Herein, semiconductor strip stack 120 is referred to as nanosheet stack 120, and the combination of fin base 116 and nanosheet stack 120 thereon is referred to as fin 122 due to its fin shape. As shown in FIG. 3, nanosheet stack 120 includes a plurality of first nanosheets 126 (by patterning first layer 106) and a plurality of second nanosheets 128 (by patterning second layer 108) stacked alternately in the Z direction and extending in the Y direction. As will be further explained in detail below, nanosheet 126 or a portion thereof may form a channel layer of a multi-gate device, and nanosheet 128 may ultimately be removed and used to define the vertical distance between channel layers. Nanosheet 126 may also be referred to as channel layer (or channel member) 126, and nanosheet 128 may also be referred to as sacrificial layer 128. In some embodiments, fins 122 may be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multi-patterning processes) may be used to pattern the structure. Generally, double patterning or multi-patterning processes combine lithography processes with self-alignment processes to create patterns with, for example, a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as a mask to pattern fins 122. Although only two fins 122 are shown in FIG. 3, the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of fins 122 can be adjusted as needed, such as 1 fin, 3 fins, 4 fins, or more fins. Additionally, mask bar 110S shown in FIG. 3 has a flat top surface. However, the embodiments of the present disclosure are not limited thereto, and in other embodiments, due to deep aspect ratio etching, mask bar 110S may have a dome top surface. Referring to FIGS. 1 and 4, in operation 16, method 10 forms an insulating layer 130 in trench 114. In some embodiments, an insulating material is formed on substrate 102 to cover fin 122 and fill trench 114. In addition to fin 122, the insulating material also covers mask bar 110S. The insulating material may include silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric material, or a low dielectric constant dielectric material. In the present disclosure, a low dielectric constant dielectric material is generally a dielectric material having a dielectric constant lower than 3.9. The insulating material may be formed by flowable chemical vapor deposition (FCVD), high density plasma chemical vapor deposition (HDP-CVD), sub-atmospheric chemical vapor deposition (SACVD), or spin-on coating. A planarization process may be performed to remove a portion of the insulating material and mask bar 110S until fin 122 is exposed. In this case, as shown in FIG. 4, the top surface 122t (also referred to as the fin top surface or fin top) of fin 122 is substantially coplanar with the top surface 130t of the planarized insulating layer 130. In some embodiments, the planarization process includes chemical mechanical polish (CMP), etch-back process, combinations thereof, and the like. Referring to FIGS. 1 and 5, in operation 18, method 10 recesses the insulating layer 130 to form a plurality of isolation regions 132. After recessing the insulating layer 130, the fins 122 protrude from the top surface 132t of the isolation regions 132, that is, the top surface 132t of the isolation regions 132 can be lower than the top surface 122t of the fins 122. In some embodiments, the nanosheet stack 120 is exposed by the isolation regions 132, that is, the top surface 132t of the isolation regions 132 can be substantially coplanar with or lower than the bottom surface 120bt of the nanosheet stack 120. In addition, the top surface 132t of the isolation regions 132 can have a flat surface, a convex surface, a concave surface (such as a recess), or a combination of the foregoing as shown in the figure. In some embodiments, the insulating layer 130 is recessed by using an appropriate etching process (such as a wet etching process using hydrofluoric acid (HF), a dry etching process, or a combination of the foregoing). In some embodiments, the height difference between the top surface 122t of the fins 122 and the top surface 132t of the isolation regions 132 ranges from about 30 nm to about 100 nm. In some embodiments, the isolation regions 132 can be shallow trench isolation (STI) regions, deep trench isolation (DTI) regions, etc. Referring to FIGS. 1 and 6, in operation 20, method 10 forms a dummy dielectric layer 142 on the substrate 102. In some embodiments, the dummy dielectric layer 142 conformally covers the exposed surfaces of the fins 122 (nanosheet stack 120) and the top surface 132t of the isolation regions 132. The dummy dielectric layer 142 can be formed by thermal oxidation, CVD, sputtering, or any other method known in the art and used for forming a dummy dielectric layer. In some embodiments, the dummy dielectric layer 142 can be formed of the same material as the isolation regions 132. In other embodiments, the dummy dielectric layer 142 can be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant dielectric such as carbon-doped oxide, an extremely low dielectric constant dielectric such as porous carbon-doped silica, a polymer such as polyimide, etc., or a combination of the foregoing. In other embodiments, the dummy dielectric layer 142 includes a dielectric material having a high dielectric constant (k value), for example, greater than 3.9. These materials can include silicon nitride, nitrogen oxides, metal oxides (such as hafnium oxide (HfO 2 ), hafnium zirconium oxide (HfZrO x ), hafnium silicon oxide (HfSiO), hafnium titanium oxide (HfTiO x ), hafnium aluminum oxide (Hf AlO x), etc.) or combinations and multiple layers of the foregoing. Referring to FIGS. 1 and 7, in operation 22, method 10 forms a dummy electrode layer 144 covering the dummy dielectric layer 142 and a hard mask layer 146 covering the dummy electrode layer 144. The dummy dielectric layer 142, the dummy electrode layer 144, and the hard mask layer 146 are collectively referred to as the dummy gate material stack 140. Subsequently, the dummy gate material stack 140 is patterned to form a dummy gate stack, which will be used to define and form the source / drain regions. Then the dummy gate stack is removed to allow processing of the fins in the channel region, and a metal gate stack is formed over the channel region. The dummy electrode layer 144 is formed over the dummy dielectric layer 142. In some embodiments, the dummy electrode layer 144 is a conductive material and can be selected from combinations including polysilicon (poly-Si), polysilicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. In one embodiment, the dummy electrode layer 144 can be deposited by a physical vapor deposition process (PVD), CVD, sputter deposition, or other techniques known in the art and used for depositing conductive materials. Other materials, conductive and non-conductive, can be used. The top surface of the dummy electrode layer 144 generally has a non-flat top surface and can be planarized after deposition. Also shown in FIG. 7 is the hard mask layer 146 formed over the dummy electrode layer 144. The hard mask layer 146 includes one or more mask layers and will be used to pattern the dummy electrode layer 144 to form the dummy gate electrode. In some embodiments, the hard mask layer 146 includes a first hard mask layer 146a and a second hard mask layer 146b. The first hard mask layer 146a can be an oxide layer (e.g., silicon oxide), and the second hard mask layer 146b can be a nitride layer (e.g., silicon nitride). The first hard mask layer 146a and the second hard mask layer 146b can be deposited by a process such as CVD or spin-on glass (SOG) process, but any acceptable process can be utilized. In some embodiments, the first hard mask layer 146a can have a thickness of about 10 angstroms (Å) to about 50 angstroms, and the second hard mask layer 146b can have a thickness of about 150 angstroms to about 850 angstroms. Referring to FIGS. 1 and 8, in operation 24, method 10 patterns the hard mask layer 146 to form a plurality of hard mask bars 146S. Although a single hard mask bar 146S is illustrated in FIG. 8, the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of hard mask bars 146S can be adjusted as needed, such as two bars, three bars, or more bars. The hard mask bars 146S extend along the X direction perpendicular to the longitudinal direction of the fins 122. As discussed in further detail below, the pattern defined in the hard mask bars 146S will be transferred to the underlying dummy electrode layer 144 and the dummy dielectric layer 142 to form a dummy gate stack spanning the fins 122. In some embodiments, method 10 uses a lithography process in operation 24, which includes forming a photoresist layer (not shown) (e.g., by spin coating) over the hard mask layer 146, performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the photoresist layer is exposed to radiation energy (e.g., ultraviolet (UV) light, deep ultraviolet (DUV) light, or extreme ultraviolet (EUV) light), where the mask blocks, transmits, and / or reflects the radiation to the photoresist layer according to the mask pattern and / or mask type of the mask (e.g., binary mask, phase-shift mask, or EUV mask), such that an image is projected onto the photoresist layer corresponding to the mask pattern. Since the photoresist layer is sensitive to radiation energy, the exposed portion of the photoresist layer undergoes a chemical change, and depending on the characteristics of the photoresist layer and the developer solution used in the development process, the exposed (or unexposed) portion of the photoresist layer is dissolved in the development process. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the mask. Alternatively, the exposure process can be implemented or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, or a combination of the foregoing. Method 10 then etches the second hard mask layer 146b and the first hard mask layer 146a through the openings defined in the patterned photoresist layer in operation 24. The etching process can include wet etching, dry etching, RIE, ashing, and / or other suitable techniques. After forming the hard mask bars 146S, the patterned photoresist layer can be stripped from the device 100. In addition, the hard mask bars 146S illustrated in FIG. 8 have a flat top surface. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, due to the high aspect ratio etching, the hard mask bars 146S can have a dome-shaped top surface. Referring to FIGS. 1 and 9, at operation 26, method 10 etches the top of dummy electrode layer 144 through an opening defined in hard mask strip 146S. In this way, hard mask strip 146S serves as an etch mask. Generally, dummy electrode layer 144 is patterned in an anisotropic etch step to expose fin 122 thereunder, such as in a plasma etch process with high power and high bias to ensure strong etch directionality. The patterned dummy electrode layer 144 of the resulting structure generally has substantially vertical sidewalls, that is to say, the gate CD can remain substantially the same from the top of the gate to the bottom of the gate (i.e., at the top surface 132t of isolation region 132). However, as transistor sizes continue to shrink to process generations below 3 nanometers, maintaining gate control can be challenging. In some IC applications, it is necessary to increase the gate CD, especially the gate CD at the bottom of the channel region, to mitigate SCE and DIBL. To intentionally introduce a tapered gate CD profile to achieve a larger gate CD and stronger gate control near the bottom of the nanosheet stack 120, as explained in more detail below, method 10 includes multiple etch steps to pattern dummy electrode layer 144 instead of a single etch step. The multiple etch steps employ a stronger etch step followed by one or more weaker etch steps to reduce the etch intensity as the etch approaches the bottom of the gate, thereby intentionally introducing a tapered gate sidewall and thus a tapered gate CD profile at the intersection of the gate stack and the underlying protruding fin (FIG. 14). In some embodiments, the multiple etch steps are in-situ. In some embodiments, operation 26 includes a plasma etch process. In a further embodiment, operation 26 includes a first RIE step 150a. In the sequence of multiple etch steps for patterning dummy electrode layer 144, the first RIE step 150a is the strongest step in terms of etch rate and etch directionality. Various etch parameters can be adjusted to enhance the first RIE step 150a, such as etchant composition, etch temperature, etch solution concentration, etch time, etch pressure, source radio frequency (RF) power, bias RF voltage, etchant flow rate, other suitable etch parameters, or combinations of the foregoing. In some embodiments, the etchant can be a plasma containing a sulfur-containing compound, such as sulfur dioxide (SO 2 ) mixed with an inert gas selected from helium (He), argon (Ar), xenon (Xe), krypton (Kr), neon (Ne), and combinations of the foregoing. In a specific illustration, the first RIE step 150a has SO 2Applied at a He flow rate, a gas pressure between 0 and about 60 millitorr (mTorr), a source RF power between about 200 and about 600 Watts, a bias RF voltage between about 300 Volts (V) and about 800 V, a frequency between about 12 megahertz (MHz) and about 14 MHz, and a temperature between about 50 °C and about 60 °C. As the strongest step in a sequence of multiple etching steps, the first RIE step 150a creates substantially vertical sidewalls at the top of the patterned dummy electrode layer 144, denoted as the top sidewalls 144T. The first RIE step 150a also recesses the top surface of the dummy electrode layer 144 at a rapid rate, thereby reducing manufacturing time and increasing product throughput. The first RIE step 150a can be a timed etch that is designed to stop at a distance (denoted as ΔH) from the fin top surface of the fin 122. The distance ΔH allows the etching process to transition to the process window of a subsequent weaker etching step. The distance ΔH also protects the fin top from being damaged during the strong plasma etch. In some embodiments, the distance ΔH ranges from about 10 nanometers to about 20 nanometers. This range is not arbitrary. If the distance ΔH is less than 10 nanometers, the process window for the etching intensity transition may be too small and may damage the fin top. If the distance ΔH is greater than 20 nanometers, the sidewalls of the patterned dummy electrode layer 144 may start to taper prematurely and result in the gate bottom protruding into an adjacent dummy gate stack (i.e., device-level metal short). Referring to FIGS. 1 and 10, at operation 28, method 10 etches the middle portion of the dummy electrode layer 144 using an etching step that is weaker than the previous etching step applied at operation 26. Under the weaker etching step, the sidewalls of the patterned dummy electrode layer 144 start to taper. In some embodiments, operation 28 includes a plasma etching process. In a further embodiment, operation 28 includes a second RIE step 150b. In terms of etching rate and etching directionality, the second RIE step 150b is weaker than the first RIE step 150a. In some embodiments, the second RIE step 150b has the same etchant, flow rate, gas pressure, and temperature as the first RIE step 150a, but has a lower source RF power and a lower bias RF voltage. In a further embodiment, during the transition from the first RIE step 150a to the second RIE step 150b, the source RF power and the bias RF voltage can be reduced by approximately half. In a specific illustration, the second RIE step 150b has a SO between 0 and about 500 sccm 2Applied at a He flow rate, a gas pressure between 0 and about 60 millitorr (mTorr), a source RF power between about 100 and about 300 watts, a bias RF voltage between about 150 volts (V) and about 400 V, a frequency between about 12 megahertz (MHz) and about 14 MHz, and a temperature between about 50 °C and about 60 °C. The second RIE step 150b can be a timed etch that is designed to stop when the fin top is exposed or about to be exposed (i.e., ΔH≈0). The weaker second RIE step 150b creates a midsection (designated 144M) of the sidewall of the patterned dummy electrode layer 144 that begins to taper away from the top 144T. Referring to FIGS. 1 and 11, in operation 30, method 10 etches the bottom of the dummy electrode layer 144 below the fin top using an etch step that is weaker than the previous etch step applied in operation 28. Even with the weaker etch step, the sidewalls of the patterned dummy electrode layer 144 continue to taper. In some embodiments, operation 30 includes a plasma etching process. In a further embodiment, operation 30 includes a third RIE step 150c. The third RIE step 150c is weaker than the first RIE step 150a and the second RIE step 150b in terms of etch rate and etch directionality. The even weaker third RIE step 150c creates a bottom (designated 144B) of the sidewall of the patterned dummy electrode layer 144 that tapers further away from the midsection 144M. In some embodiments, the third RIE step 150c has the same etchant, flow rate, gas pressure, and temperature as the second RIE step 150b, but with a further reduced source RF power and bias RF voltage. In a further embodiment, the source RF power and bias RF voltage are reduced by approximately half in the transition from the second RIE step 150b to the third RIE step 150c. In a specific illustration, the third RIE step 150c is applied at a SO 2 Applied at a He flow rate, a gas pressure between 0 and about 60 millitorr (mTorr), a source RF power between about 50 and about 150 watts, a bias RF voltage between about 75 volts (V) and about 200 V, a frequency between about 12 megahertz (MHz) and about 14 MHz, and a temperature between about 50 °C and about 60 °C. In some embodiments, the third RIE step 150c uses an etchant different from the first RIE step and the second RIE step, such as a plasma that includes a mixture of carbon tetrafluoride (CF 4 ), in addition to a sulfur-containing compound, and chlorine (Cl 2 ), (i.e., CF 4 / Cl 2 Plasma). In addition, the third RIE step 150c can intentionally introduce an etchant that can produce a polymer as a by-product, such as a fluorine-containing etchant mixed with a nitrogen-containing carrier gas. Among other locations, the by-product polymer can form on the bottom 144B of the sidewall. The polymer can slow down the etching of the recessed dummy electrode layer 144. In comparison, the first RIE step 150a and the second RIE step 150b can be free of by-product polymers. In this way, the third RIE step 150c has the weakest etching intensity among a series of multiple etching steps. The third RIE step 150c exposes the top surface of the dummy dielectric layer 142. The uncovered portion of the dummy dielectric layer 142 can be further removed in a separate selective etching process. In some embodiments, the third RIE step 150c also removes the uncovered portion of the dummy dielectric layer 142 and exposes the top surface of the isolation region 132. A cleaning process can be applied to remove the by-product polymer (if any) from the device 100. The resulting structure is as shown in FIG. 12, and the patterned dummy dielectric layer 142, the patterned dummy electrode layer 144, and the hard mask strip 146S are collectively referred to as the dummy gate stack 160. The patterned dummy dielectric layer 142 is also referred to as the dummy gate dielectric layer 142. The patterned dummy electrode layer 144 is also referred to as the dummy gate electrode 144. Still referring to FIG. 12, the multiple RIE steps 150a-c produce a protruding corner at the intersection of the dummy gate stack 160 and the underlying protruding fin 122. The protruding corner starts from the middle 144M of the sidewall of the dummy gate stack 160, continues to the bottom 144B, and stops at the top surface of the isolation region 132. At the protruding corner, the gate CD (denoted as CD1) is greater than the gate CD (denoted as CD0) away from the protruding corner. Since the protruding corner starts above the fin top, the channel region (starting from the topmost channel layer 126 and going down) benefits from a relatively large gate CD. However, in some alternative embodiments, depending on the specific etching parameters of the above-mentioned anisotropic etching process (for example, the second RIE step 150b can be optionally skipped), the protruding corner can start below the fin top (i.e., there is no 144M above the fin top). In this way, the topmost channel layer 126 can still be joined by the gate CD (i.e., CD0), while the middle channel layer 126 and the bottommost channel layer 126 are joined by gate CDs (i.e., all greater than CD0). FIG. 13 shows a cross-sectional view of the structure shown in FIG. 12. The cross-sectional view is obtained from a horizontal plane including line I-I in FIG. 12. The horizontal plane passes through one of the channel layers 126 (e.g., the topmost channel layer 126, one of the intermediate channel layers 126, or the bottommost channel layer 126). As shown in FIG. 13, one of the dummy gate stacks 160 is illustrated. The gate length (measured in a direction perpendicular to the longitudinal direction of the gate stack; i.e., measured along the Y direction in FIG. 13) is represented as the gate critical dimension (CD). Due to the gate patterning process discussed above, the portion of the dummy gate stack 160 that intersects the fin 122 may be wider than other portions away from the fin 122. The widening in the portion of the dummy gate stack 160 that intersects the fin 122 is also referred to as the "footing effect", and the widened portion is referred to as the footing region (or protruding corner), as marked by portion 162. Thus, the gate CD measured at different portions of the dummy gate stack 160 may have different values. FIG. 13 illustrates the gate CD measured at two different regions of the dummy gate stack 160, denoted as CD0 and CD1. CD0 is measured in a region away from the fin, which is referred to as the "outer fin" region. CD1 is measured near the edge (sidewall) of the protruding fin 122 (or channel layer 126), which is referred to as the "on-fin" region. The term "near" refers to a distance less than about 1 nm or exactly on the edge of the protruding fin. In some embodiments, CD0 ranges from about 10 nm to about 12 nm, the width of the protruding corner 162 measured along the Y direction ((CD1 - CD0) / 2) ranges from about 0.8 nm to about 2.8 nm, and the width of the channel layer 126 measured along the X direction (denoted as Wc) ranges from about 20 nm to about 25 nm. Along the Z direction, by measuring the gate CD at different heights of the dummy gate stack 160, the gate CD profile of the dummy gate stack 160 can be obtained. In various embodiments, the gate CD can be measured by prior art metrology, such as scanning electron microscopy (SEM), transmission electron microscopy (TEM), critical dimension scanning electron microscopy (CD-SEM). Others such as optical critical dimension (OCD), atomic force microscope (AFM), and critical dimension-atomic force microscope (CD-AFM) can also be used to measure the gate CD. FIG. 14 shows a graph of an exemplary gate CD profile measured in different regions of the dummy gate stack 160. The graph in FIG. 14 is common to both the dummy gate stack and the replacement gate stack (e.g., a metal gate stack) because the replacement gate stack can inherit the shape of the dummy gate stack. The horizontal axis in the graph represents the gate CD value, and the vertical axis in the graph represents the height of the gate stack relative to the top surface 132t of the isolation region 132. The total height (H1) of the gate stack and the total height (H2) of the protruding portion of the fin 122 are also marked on the vertical axis for reference. In particular, in the graph, the line "CD0" represents the gate CD measured in the "outer fin" region of the gate stack, and the line "CD1" represents the gate CD measured in the "on fin" region of the gate stack. Still referring to FIG. 14, when above the height ΔH above the fin top of the protruding fin, the gate CD measured in the "outer fin" region and the "on-fin" region has substantially the same value (i.e., CD0 = CD1), which corresponds to the vertical top 144T of the sidewall of the gate stack. As described above, in some embodiments, ΔH can range from about 10 nm to about 20 nm. Along the line "CD0", the gate CD remains substantially the same due to the vertical sidewall of the gate stack in the "outer fin" region. The line "CD0" can taper slightly when near the top surface 132t of the isolation region 132, which is mainly due to the etching residues retained in the corner region of the gate stack. Along the line "CD1", the gate CD begins to taper below the height ΔH above the fin top of the protruding fin, which corresponds to the tapered middle 144M of the sidewall of the gate stack, and further tapers below the fin top (H2) of the protruding fin 122, which corresponds to the tapered bottom 144B of the sidewall of the gate stack. The larger gate CD in the "on-fin" region can provide stronger gate control ability. In addition, the closer to the bottom of the channel region, the larger the gate CD in the "on-fin" region becomes, which effectively counteracts SCE and DIBL. In some embodiments, DIBL can be suppressed by about 10%. Referring to FIGS. 1 and 15, in operation 32, method 10 conformally forms a gate spacer 164 on the sidewall of the dummy gate stack 160. FIG. 15 is a cross-sectional view obtained from a horizontal plane including line I-I in FIG. 12. The gate spacer 164 can follow the contour of the sidewall of the dummy gate stack 160 and thus cover the protruding corners of the dummy gate stack 160. In some embodiments, the gate spacer 164 is formed of a dielectric material, such as silicon oxide, silicon nitride, silicon carbonitride (SiCN), silicon oxynitride (SiCON), or a combination of the foregoing. In some embodiments, the thickness of the gate spacer 164 ranges from about 1 nm to about 5 nm. Although the gate spacer 164 shown in FIG. 15 is a single-layer structure, the embodiments of the present disclosure are not limited thereto. In other embodiments, the gate spacer 164 can be a multi-layer structure. For example, the gate spacer 164 can include a silicon oxide layer and a silicon nitride layer disposed on the silicon oxide layer. Referring to FIGS. 1 and 16, at operation 34, method 10 removes the ends of the nanosheet stack 120 to form a recess 170. FIG. 16 is a cross-sectional view obtained from a horizontal plane including line II-II in FIG. 12. Here, the recess 170 can be referred to as a source / drain (S / D) recess 170. In some embodiments, the ends of the nanosheet stack 120 can be removed by an anisotropic etching process, an isotropic etching process, or a combination of the foregoing. In some embodiments, the S / D recess 170 also extends into the fin base 116 and is lower than the top surface 132t of the isolation region 132. In other words, the ends of the nanosheet stack 120 are completely removed, and the top of the fin base 116 is further removed. Referring to FIGS. 1 and 17, at operation 36, method 10 forms inner spacers 172 at opposite ends of the sacrificial layer 128. In some embodiments, the opposite ends of the sacrificial layer 128 exposed in the source / drain trench 170 are selectively and partially recessed to form inner spacer recesses (not shown), while the channel layer 126 is substantially not etched. In embodiments where the channel layer 126 is mainly composed of silicon (Si) and the sacrificial layer 128 is mainly composed of silicon germanium (SiGe), the selective and partial recess of the sacrificial layer 128 can include a silicon germanium oxidation process, followed by removal of the silicon germanium oxide. The silicon germanium oxidation process can include using ozone (O 3 ). In some other embodiments, the selective recess can be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recess of the sacrificial layer 128 is controlled by the duration of the etching process. The selective dry etching process can include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process can include hydrofluoric acid (HF) or ammonia water (NH 4 OH) etchant. After forming the inner spacer recesses, an inner spacer material layer is deposited over the device 100, including in the inner spacer recesses. The inner spacer material layer can include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, metal nitride, or a suitable dielectric material. Then, the deposited inner spacer material layer is etched back to remove the excess inner spacer material layer above the gate spacer 164 and the sidewalls of the channel layer 126, thereby forming the inner spacers 172. In some embodiments, the etch-back process can be a dry etching process, which includes using an oxygen-containing gas, hydrogen, nitrogen, a fluorine-containing gas (e.g., carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), difluoromethane (CH 2 F 2 ), chloroform (CHF 3 ), and / or hexafluoroethane (C 2 F 6 ), chlorine-containing gases (such as chlorine (Cl 2 ), chloroform (CHCl 3 ), carbon tetrachloride (CCl 4 ), and / or boron trichloride (BCl 3 ), bromine-containing gases (such as hydrogen bromide (HBr) and / or hydrogen bromide (CHBR 3 ), iodine-containing gases (such as trifluoroiodomethane (CF 3 I)), other suitable gases and / or plasmas, and / or combinations thereof. Referring to FIG. 1 and FIG. 18, at operation 38, method 10 epitaxially grows source / drain (S / D) component 174 from S / D recess 170. In this case, S / D component 174 includes a source disposed on one side of dummy gate stack 160 and a drain disposed on the other side of dummy gate stack 160. The source covers one end of fin base 116, while the drain covers the other end of fin base 116. S / D component 174 is adjacent to and electrically connected to channel layer 126, while S / D component 174 is electrically isolated from sacrificial layer 128 by inner spacer 172. In some embodiments, S / D component 174 extends beyond the top surface of nanosheet stack 120. However, embodiments of the present disclosure are not limited thereto, and in other embodiments, the top surface of S / D component 174 is substantially aligned with the top surface of nanosheet stack 120. The S / D component 174 includes any acceptable material, such as materials suitable for p-type transistors or n-type transistors. For example, the S / D component 174 may include silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium (Ge), germanium tin (GeSn), etc., which are suitable for p-type transistors. In some alternative embodiments, the S / D component 174 may include silicon, silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon phosphide (SiP), etc., which are applicable to n-type transistors. In some embodiments, the S / D component 174 is formed by MOCVD, MBE, ALD, etc. The S / D component 174 may include one or more semiconductor material layers. For example, the S / D component 174 may include a bottom semiconductor material layer, an intermediate semiconductor material layer, and a covering semiconductor material layer. Any number of semiconductor material layers can be used for the S / D component 174. Each semiconductor material layer may be formed of a different semiconductor material and may be doped to different dopant concentrations. In an embodiment where the S / D component 174 includes three semiconductor material layers, the bottom semiconductor material layer may be deposited, the intermediate semiconductor material layer may be deposited above the bottom semiconductor material layer, and the covering semiconductor material layer may be deposited above the intermediate semiconductor material layer. In some embodiments, the S / D component 174 is doped with a conductive dopant. For example, the S / D component 174 such as SiGe can be epitaxially grown with a p-type dopant for applying strain in p-type transistors. That is, the S / D component 174 is doped with a p-type dopant to become the source and drain of a p-type transistor. The p-type dopant includes boron or boron difluoride (BF 2 ), and the S / D component 174 can be epitaxially grown by a low-pressure chemical vapor deposition (LPCVD) process with in-situ doping. As described above, the S / D component 174 can be epitaxially grown with multi-film layers having different dopant concentrations, such as a SiGe:B bottom layer with a Ge atomic percentage of about 45% to 55% and a boron concentration of about 1x10 21 / cm³ to about 2x10 21 / cm³, a SiGe:B intermediate layer with a Ge atomic percentage of about 45% to 60% and a boron concentration of about 8x10 20 / cm³ to about 3x10 21 / cm³, and a SiGe:B covering layer with a Ge atomic percentage of about 25% to 45% and a boron concentration of about 1x10 20 / cm³ to about 8x10 20 / cm³. In some alternative embodiments, the S / D component 174 (such as silicon carbide (SiC), silicon phosphide (SiP), a combination of SiC / SiP, or silicon carbide phosphide (SiCP)) utilizes n-type dopant epitaxial growth for applying strain in the n-type transistor, that is, the S / D component 174 is doped with an n-type dopant to become the source and drain of the n-type transistor. The n-type dopant includes arsenic and / or phosphorus, and the S / D component 174 can be epitaxially grown by an LPCVD process with in-situ doping. In some embodiments, the S / D component 174 is epitaxially grown with multiple film layers having different dopant concentrations, such as an Si:P bottom layer with a phosphorus concentration of about 1x10 21 / cm³ to about 2x10 21 / cm³, an Si:P intermediate layer with a phosphorus concentration of about 1x10 21 / cm³ to about 4x10 21 / cm³, and an Si:As capping layer with an arsenic concentration of about 1×10 20 / cm³ to about 1×10 21 / cm³. As a result of the epitaxial growth process for forming the S / D component 174, the cross-section of the S / D component 174 can have a rhombic or pentagonal shape. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the cross-section of the S / D component 174 also has a hexagonal shape, a cylindrical shape, or a strip shape. FIG. 19 depicts a perspective view of an exemplary resulting structure after the epitaxial growth process is completed. As shown in FIG. 19, after the epitaxial growth process is completed, adjacent S / D components 174 are separated from each other. Alternatively, adjacent S / D components 174 can be combined. Referring to FIGS. 1 and 20, in operation 40, the method 10 forms an interlayer dielectric (ILD) layer 178 above the device 100. FIG. 20 is a cross-sectional view obtained from a vertical plane including line II-II in FIG. 19. A contact etch stop layer (CESL) 176 can also be formed between the S / D component 174 and the ILD layer 178. In some embodiments, the CESL 176 conformally covers the sidewalls of the outer sidewalls of the S / D component 174 and the gate spacer 164. The CESL 176 can include silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, and / or other materials; and can be formed by CVD, PVD, ALD, or other suitable methods. The ILD layer 178 includes silicon oxide, silicon nitride, silicon oxynitride, phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silicate glass (FSG), carbon-doped silicon oxide (e.g., silicon carbon oxide (SiCOH)), polyimide, and / or a combination of the foregoing. In some other embodiments, the ILD layer 178 includes a low dielectric constant dielectric material. Exemplary low dielectric constant dielectric materials include Black Diamond® (Applied Materials, Santa Clara, Calif.), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK® (Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF) and / or a combination of the foregoing. In alternative embodiments, the ILD layer 178 includes one or more dielectric materials and / or one or more dielectric layers. In some embodiments, the ILD layer 178 is formed to a suitable thickness by FCVD, CVD, HDPCVD, SACVD, spin coating, sputtering, or other suitable methods. For example, an interlayer dielectric material layer is first formed to cover the isolation region 132, the dummy gate stack 160, and the gate spacer 164. Subsequently, the thickness of the interlayer dielectric material layer is reduced until the dummy gate electrode 144 is exposed, thereby forming the ILD layer 178. The process of reducing the thickness of the interlayer dielectric material layer can be achieved by a CMP process, an etching process, or other suitable processes. In this case, the top surface of the ILD layer 178 can be coplanar with the top surface of the dummy gate electrode 144. Referring to FIGS. 1 and 21, at operation 42, method 10 removes the dummy gate stack 160 to form the gate trench 180. The CESL 176 and the ILD layer 178 can protect the S / D components 174 during the removal of the dummy gate stack 160. Plasma dry etching and / or wet etching can be used to remove the dummy gate stack 160. When the dummy gate electrode 144 is polysilicon and the ILD layer 178 is silicon oxide, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode 144. Thereafter, the dummy gate dielectric layer 142 is removed by using another plasma dry etching and / or wet etching. Also as shown in FIG. 21, an etching process is performed to remove the sacrificial layer 128. In this case, the sacrificial layer 128 can be completely removed to form multiple gaps between the channel layers 126. Thus, the channel layers 126 are separated from each other by the gaps. Additionally, the bottommost channel layer 126 can also be separated from the fin base 116 by the gaps, such that the channel layers 126 are suspended. In this embodiment, the channel layers 126 include silicon and the sacrificial layer 128 includes silicon germanium. The sacrificial layer 128 can be selectively removed by oxidizing the sacrificial layer 128 using a suitable oxidant such as ozone. Thereafter, the oxidized sacrificial layer 128 can be selectively removed from the gate trench 180. In some embodiments, the etching process includes a dry etching process to selectively remove the sacrificial layer 128, for example, by applying hydrogen chloride (HCl) gas at a temperature of about 20°C to about 300°C, or by applying a gas mixture of 4 carbon tetrafluoride (CF 6 ), sulfur hexafluoride (SF 3 )), and chloroform (CHF Referring to FIGS. 1 and 22 to 23, in operation 44, method 10 forms a metal gate stack 190, such as a high-k metal gate stack, in gate trench 180. FIG. 22 is a cross-sectional view obtained from a vertical plane including line II-II in FIG. 19. FIG. 23 is a horizontal cross-sectional view obtained from a horizontal plane including line I-I in FIG. 19. The horizontal plane passes through one of the channel layers 126 (e.g., the topmost channel layer 126, one of the intermediate channel layers 126, or the bottommost channel layer 126). Metal gate stack 190 includes a gate dielectric layer 192 and a gate electrode 194. Gate dielectric layer 192 surrounds channel layer 126. In some embodiments, gate dielectric layer 192 includes one or more dielectric materials, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Exemplary high-k dielectric materials include hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), aluminum oxide (Al 2 O 3 ), hafnium oxide-aluminum oxide alloy (HfO 2 -Al 2 O 3 alloy), other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, gate dielectric layer 192 includes an interfacial layer (not shown) formed between channel layer 126 and the high-k dielectric material. Gate dielectric layer 192 can be formed by CVD, ALD, or any suitable method. In one embodiment, gate dielectric layer 192 is formed by using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer with a uniform thickness is formed around each channel layer 126. In some embodiments, the thickness of gate dielectric layer 192 ranges from about 0.5 nanometers to about 3 nanometers. The gate electrode 194 is formed on the gate dielectric layer 192 and then planarized by using, for example, a CMP process until the top surface of the ILD layer 178 is exposed. The gate electrode 194 may include various conductive materials such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials, and / or combinations of the foregoing. The gate electrode 194 may include one or more conductive materials such as a work function metal (WFM) layer and a metal fill layer (not shown) and / or other suitable film layers. As shown in FIG. 23, the gate dielectric layer 192 and / or the gate electrode 194 may completely fill the space in the protruding corner 162. In an alternative embodiment as shown in FIG. 24, since it is difficult to fill the corner region in the high aspect ratio gate trench, the void 196 may be sealed by the gate dielectric layer 192 in the protruding corner 162. The void 196 may trap air or other ambient gases applied during the manufacturing process. In addition, since it is more difficult to fill the corner region closer to the bottom of the high aspect ratio gate trench, the size of the void 196 in the cross-sectional view becomes larger when the cross-sectional view cuts through the bottom channel layer of the channel layer 126. In one embodiment, the cross-sectional view cutting through the topmost channel layer 126 has no void 196 as shown in FIG. 23, while the cross-sectional view cutting through the underlying intermediate channel layer 126 (specifically, the bottommost channel layer 126) may have a void 196. Although the size of the void 196 may increase when approaching the bottom of the gate, as shown in FIG. 14, due to the tapered gate sidewalls, the "on-fin" gate CD (CD1 in FIG. 14) still increases when approaching the bottom of the gate. In some embodiments, instead of the void 196, residues of the dummy gate dielectric layer 142 and / or the dummy gate electrode 144 are retained in the corner region of the protruding corner 162 due to the difficulty in removing residues from the high aspect ratio gate trench during the removal process. Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits for semiconductor devices and methods of forming the same. For example, embodiments of the present disclosure provide a simple and cost-effective system and method for forming a gate without significantly reducing production capacity. In the present disclosure, the gate critical dimension measured near or on the edge of the fin where the gate stack is joined is magnified to provide better gate control. In addition, the workflow for gate formation can be easily incorporated into existing semiconductor manufacturing processes. In an exemplary aspect, the present disclosure relates to a method of forming a semiconductor structure, the method comprising providing a structure including a substrate and fins protruding from the substrate, depositing a dummy material stack over the fins, patterning a top portion of the dummy material stack in a first etching process having a first etching strength, patterning a middle portion of the dummy material stack in a second etching process having a second etching strength weaker than the first etching strength, patterning a bottom portion of the dummy material stack in a third etching process to form a dummy gate stack, the third etching process having a third etching strength weaker than the second etching strength, and replacing the dummy gate stack with a metal gate stack. In some embodiments, the first etching process produces substantially vertical sidewalls of the top portion of the dummy material stack. In some embodiments, the second etching process produces tapering sidewalls of the middle portion of the dummy material stack. In some embodiments, the third etching process produces tapering sidewalls of the bottom portion of the dummy material stack. In some embodiments, the third etching process produces polymer by-products deposited on the tapering sidewalls of the bottom portion of the dummy material stack. In some embodiments, the first etching process and the second etching process do not produce polymer by-products. In some embodiments, the first etching process stops at a height above the top surface of the fin. In some embodiments, the height above the top surface of the fin ranges from about 10 nanometers to about 20 nanometers. In some embodiments, the second etching process stops at the top surface of the fin. In some embodiments, the metal gate stack has a first gate critical dimension (CD) measured at the edge of the fin and a second gate critical dimension measured at a location away from the fin, and the first gate critical dimension is greater than the second gate critical dimension. In another illustrative aspect, the present disclosure relates to a method of forming a semiconductor device, the method comprising forming fins protruding from a substrate, depositing a dummy electrode layer over the fins, etching a top portion of the dummy electrode layer in a first etching process to form a first sidewall above a top surface of the fins, etching a bottom portion of the dummy electrode layer in a second etching process to form a second sidewall below the top surface of the fins, wherein the first etching process and the second etching process use different etching recipes, and the second sidewall tapers from the first sidewall, depositing a gate spacer layer on the first sidewall and the second sidewall of the dummy electrode layer, removing the dummy electrode layer to form a gate trench, and depositing a metal gate stack in the gate trench. In some embodiments, the method further comprises etching a middle portion of the dummy electrode layer in a third etching process after the first etching process and before the second etching process, wherein the first etching process, the second etching process, and the third etching process use different etching recipes. In some embodiments, the third etching process of the middle portion of the dummy electrode layer forms a third sidewall between the first sidewall and the second sidewall, and the third sidewall tapers from the first sidewall. In some embodiments, the second sidewall further tapers from the third sidewall. In some embodiments, the first sidewall is substantially vertical. In some embodiments, the second etching process has an etching strength that is less than the etching strength of the first etching process. In yet another illustrative aspect, the present disclosure relates to a semiconductor device, the device comprising a substrate, a plurality of channel layers vertically stacked and suspended over the substrate, and a gate structure surrounding each of the channel layers, wherein the gate structure has a first gate critical dimension measured at a height above a top surface of a topmost channel layer of the channel layers, a second gate critical dimension measured at an edge of the topmost channel layer of the channel layers, and a third gate critical dimension measured at an edge of a bottommost channel layer of the channel layers, wherein the second gate critical dimension is greater than the first gate critical dimension, and the third gate critical dimension is greater than the second gate critical dimension. In some embodiments, the gate structure includes a protruding corner at an intersecting region of the gate structure and the channel layers, and wherein a tip of the protruding corner is above the top surface of the topmost channel layer of the channel layers. In some embodiments, the gate structure includes a void trapped in the protruding corner. In some embodiments, the gate structure includes a vertical sidewall terminating above the top surface of the topmost channel layer of the channel layers, and a tapered sidewall starting above the top surface of the topmost channel layer of the channel layers. The components of several embodiments are outlined above so that those of ordinary skill in the art to which the present invention pertains can more easily understand the viewpoints of the embodiments of the present invention. Those of ordinary skill in the art to which the present invention pertains should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those of ordinary skill in the art to which the present invention pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention. 10: Method 12 / 14 / 16 / 18 / 20 / 22 / 24 / 26 / 28 / 30 / 32 / 34 / 36 / 38 / 40 / 42 / 44: Operation 100: (Semiconductor) Device 102: Substrate 104: (Epitaxial) Semiconductor Stack 106: First Film Layer 108: Second Film Layer 110: Mask Layer 110S: Mask Strip 114: Trench 116: Fin Base 120: Semiconductor Strip Stack / Nanosheet Stack 120bt: Bottom Surface 122: Fin 122t: Top Surface / Fin Top Surface / Fin Top 126: First Nanosheet / Channel Layer / Channel Member 128: Second Nanosheet / Sacrificial Layer 130: Insulating Layer 130t / 132t: Top Surface 132: Isolation Region 140:Dummy Gate Material Stack 142: (Patterned) Dummy (Gate) Dielectric Layer 144: (Patterned) Dummy (Gate) Electrode Layer 144B: Bottom Sidewall / Bottom 144M: Middle Sidewall / Middle 144T: Top Sidewall / Top 146: Hard Mask Layer 146a: First Hard Mask Layer 146b: Second Hard Mask Layer 146S: Hard Mask Strip 150a: First Reactive Ion Etching Step 150b: Second Reactive Ion Etching Step 150c: Third Reactive Ion Etching Step 160: Dummy Gate Stack 162: Protruding Corner 164: Gate Spacer 170: (Source / Drain) Depression 172: Inner Spacer 174: Source / Drain Component 176: Contact Etch Stop Layer 178: Interlayer Dielectric Layer 180: Gate Trench 190: Metal Gate Stack 192: Gate Dielectric Layer 194: Gate Electrode Layer 196: Void ΔH: Distance CD0 / CD1: Critical Dimension H: Height T1 / T2: Thickness W1: Width The various aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the elements can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention. FIG. 1 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure. FIGS. 2 to 12 and FIG. 19 are perspective views of a semiconductor structure during a manufacturing process according to the method of FIG. 1 according to an embodiment of the present disclosure. FIG. 14 is a graph showing the relationship between the gate critical dimension profile and the gate height according to an embodiment of the present disclosure. FIGS. 13, 15, 23, and 24 are cross-sectional views of a horizontal plane cut through the semiconductor structure during a manufacturing process according to the method of FIG. 1 according to an embodiment of the present disclosure. FIGS. 16, 17, 18, 20, 21, and 22 are cross-sectional views of a vertical plane cut through the semiconductor structure during a manufacturing process according to the method of FIG. 1 according to an embodiment of the present disclosure. 100: (Semiconductor) device 116: Fin base 126: First nanosheet / channel layer / channel member 164: Gate spacer 172: Inner spacer 174: Source / drain component 176: Contact etch stop layer 178: Interlayer dielectric layer 190: Metal gate stack 192: Gate dielectric layer 194: Gate electrode layer

Claims

1. A method for forming a semiconductor structure, comprising: A structure is provided, the structure including a base and a fin projecting from the base; A dummy material stack is deposited above the fin; In a first etching process, a top of the dummy material stack is patterned, the first etching process having a first etching intensity; In a second etching process, a middle portion of the dummy material stack is patterned, the second etching process having a second etching intensity weaker than the first etching intensity; in a third etching process, a bottom portion of the dummy material stack is patterned to form a dummy gate stack, the third etching process having a third etching intensity weaker than the second etching intensity, wherein the third etching process creates a tapered sidewall of the bottom portion of the dummy material stack below a top surface of the fin; and the dummy gate stack is replaced with a metal gate stack. The metal gate stacked on the top surface of the topmost channel layer of the plurality of channel layers has a first gate critical dimension measured at a height, a second gate critical dimension measured at an edge of the topmost channel layer of the channel layers, and a third gate critical dimension measured at an edge of the bottommost channel layer of the channel layers, wherein the second gate critical dimension is greater than the first gate critical dimension, and the third gate critical dimension is greater than the second gate critical dimension, wherein the first gate critical dimension, the second gate critical dimension, and the third gate critical dimension are measured along a longitudinal direction of the channel layers.

2. A method for forming a semiconductor structure as claimed in claim 1, wherein the first etching process produces a substantially vertical sidewall on the top of the dummy material stack.

3. A method for forming a semiconductor structure as claimed in claim 1 or 2, wherein the second etching process produces a tapered sidewall in the middle of the dummy material stack.

4. The method of forming a semiconductor structure as claimed in claim 1, wherein the third etching process produces a polymer byproduct deposited on the tapered sidewall of the bottom of the dummy material stack.

5. The method of forming a semiconductor structure as claimed in claim 1, wherein the first etching process stops at a height above a top surface of the fin, the height being in the range of about 10 nanometers to about 20 nanometers, and wherein the second etching process stops at the top surface of the fin.

6. A method for forming a semiconductor device, comprising: A fin protrudes from a base; A dummy electrode layer is deposited above the fin; In a first etching process, the top of the dummy electrode layer is etched to form a first sidewall on a top surface of the fin; In a second etching process, a bottom of the dummy electrode layer is etched to form a second sidewall below the top surface of the fin, wherein the first etching process and the second etching process use different etching recipes, and the second sidewall gradually tapers from the first sidewall; a gate spacer layer is deposited on the first sidewall and the second sidewall of the dummy electrode layer; the dummy electrode layer is removed to form a gate trench; And a metal gate stack is deposited in the gate trench, wherein a height measurement of the metal gate stack above a top surface of a top channel layer of a plurality of channel layers has a first gate critical dimension, a second gate critical dimension is measured at an edge of the top channel layer of the channel layers, and a third gate critical dimension is measured at an edge of a bottom channel layer of the channel layers, wherein the second gate critical dimension is greater than the first gate critical dimension, and the third gate critical dimension is greater than the second gate critical dimension, wherein the first gate critical dimension, the second gate critical dimension, and the third gate critical dimension are measured along a longitudinal direction of the channel layers.

7. The method of forming a semiconductor device as described in claim 6 further includes: After the first etching process and before the second etching process, a middle portion of the dummy electrode layer is etched in a third etching process, wherein the first etching process, the second etching process, and the third etching process use different etching formulations.

8. A semiconductor device, comprising: One base; Multiple channel layers are vertically stacked and suspended on the substrate; And a gate structure surrounding each of the channel layers, wherein the gate structure has a first critical dimension (CD) measured at a height above a top surface of a top surface of a top channel layer of the channel layers, a second critical dimension measured at an edge of the top channel layer of the channel layers, and a third critical dimension measured at an edge of a bottom channel layer of the channel layers, wherein the second critical dimension is greater than the first critical dimension, and the third critical dimension is greater than the second critical dimension, wherein the first critical dimension, the second critical dimension, and the third critical dimension are measured along a longitudinal direction of the channel layers.

9. The semiconductor device of claim 8, wherein the gate structure includes a protruding corner located in an intersecting region between the gate structure and the channel layers, and wherein a tip of the protruding corner is on the top surface of the topmost channel layer of the channel layers.

10. The semiconductor device of claim 9, wherein the gate structure includes a void trapped in the protruding corner.

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