Electronic device

Abstract

An electronic device includes a substrate and electronic components. The electronic components are disposed on the substrate and include a first gate, a semiconductor pattern, a source, a drain, and a second gate. The semiconductor pattern includes an overlap region, a first side region, and a second side region. The portion where the semiconductor pattern and the first gate overlap is defined as the overlap region. In a first direction, the first side region and the second side region are respectively connected to two opposite sides of the overlap region and each includes two opposite first edges of the semiconductor pattern. The source and drain are electrically connected to the first side region and the second side region, respectively. At least a portion of the second gate overlaps with the second side region of the semiconductor pattern.

Description

Technical Field

[0001] The invention relates to an electronic device, and in particular to an electronic device with two gates of different sizes. Prior Art

[0002] Currently, thin film transistors are used in more and more high voltage operating products (such as electrophoretic displays, antenna devices, etc.). However, with the increase of operating voltage, thin film transistors face problems such as increased leakage current and increased size. Summary of the invention

[0003] The present invention provides an electronic device, which helps to improve the problem of leakage current or size increase.

[0004] In one embodiment of the present invention, an electronic device includes a substrate and an electronic component. The electronic component is disposed on the substrate and includes a first gate, a semiconductor pattern, a source, a drain, and a second gate. The semiconductor pattern includes an overlap region, a first side region, and a second side region. The overlapped portion of the semiconductor pattern and the first gate is defined as an overlap region. In a first direction, the first side region and the second side region are respectively connected to two opposite sides of the overlap region. The first side region and the second side region respectively include two opposite first edges of the semiconductor pattern. The source and the drain are respectively electrically connected to the first side region and the second side region. At least a portion of the second gate overlaps the second side region of the semiconductor pattern.

[0005] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. Simple diagram description

[0006] FIG. 1 is a schematic top view of an electronic device according to an embodiment of the present disclosure. FIG. 2 is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. FIG. 3 is a partial top view schematically showing the embodiment of FIG. 2 . FIG. 4 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. FIG. 5 and FIG. 6 are two partial top views corresponding to the embodiment of FIG. 4 . FIG. 7 is a partial cross-sectional schematic diagram of an electronic device according to yet another embodiment of the present disclosure. FIG. 8 is a partial top view schematically showing the embodiment of FIG. 7 . FIG. 9 is a partial cross-sectional schematic diagram of an electronic device according to yet another embodiment of the present disclosure. FIG. 10 is a partial top view schematically showing the embodiment of FIG. 9 . 11 to 16 are partial cross-sectional schematic diagrams of electronic devices according to other embodiments of the present disclosure. Implementation

[0007] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

[0008] Certain words are used throughout this disclosure and in the attached claims to refer to specific components. A person of ordinary skill in the art will understand that electronic device manufacturers may refer to the same component by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and claims, the words "including" and "comprising" are open-ended words and should therefore be interpreted as "including but not limited to..."

[0009] The directional terms mentioned herein, such as "upper", "lower", "front", "back", "left", "right", etc., are only references to the directions of the drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In the drawings, each diagram depicts the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these diagrams should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0010] In the present disclosure, a structure (or layer, element, substrate) described is located on / above another structure (or layer, element, substrate), which may mean that the two structures are adjacent and directly connected, or that the two structures are adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate interval) between the two structures, and the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is set "on" another structure, it may mean that the certain structure is "directly" on the other structure, or that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0011] The terms "approximately", "equal to", "equal to" or "same", "substantially" or "approximately" are generally interpreted as within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range. In addition, the phrases "a range from a first value to a second value" and "a range between a first value and a second value" mean that the range includes the first value, the second value and other values ​​therebetween.

[0012] The ordinal numbers used in the specification and the patent application, such as "first", "second", etc., are used to modify the elements. They do not imply or represent any previous ordinal numbers of the (or those) elements, nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the element with a certain name clearly distinguishable from another element with the same name. The patent application and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the patent application.

[0013] The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there is a switch, a diode, a capacitor, an inductor, a resistor, other suitable components, or a combination of the above components between the endpoints of the components on the two circuits, but it is not limited thereto.

[0014] In the present disclosure, the thickness, length and width can be measured by an optical microscope (OM), and the thickness or width can be measured by a cross-sectional image in an electron microscope, but it is not limited thereto. In addition, any two values ​​or directions used for comparison may have a certain error. In addition, the terms "equal", "equal", "same", "substantially" or "substantially" mentioned in the present disclosure generally represent a range of 10% within a given value or range. In addition, the term "a given range is a first value to a second value", "a given range falls within the range of a first value to a second value" or "a given range is between a first value and a second value" means that the given range includes the first value, the second value and other values ​​therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0015] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0016] In the present disclosure, the electronic device may include a display device, a backlight device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The display device may, for example, include liquid crystal, light-emitting diode, fluorescence, phosphor, quantum dot (QD), other suitable display media or a combination thereof. The antenna device may, for example, include a frequency selective surface (FSS), a radio frequency filter (RF-Filter), a polarizer, a resonator or an antenna, etc. The antenna may be a liquid crystal antenna or a non-liquid crystal antenna. The sensing device may be a sensing device for sensing capacitance, light, heat or ultrasound, but is not limited thereto. In the present disclosure, the electronic device may include electronic components, and the electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light emitting diode or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot light emitting diode (quantum dot LED), but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto. In addition, the appearance of the electronic device may be a rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, and a light source system to support a display device, an antenna device, a wearable device (for example, including augmented reality or virtual reality), a vehicle-mounted device (for example, including a car windshield), or a splicing device.

[0017] It should be noted that the following embodiments can replace, reorganize, or mix features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features between embodiments can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0018] FIG. 1 is a schematic top view of an electronic device according to an embodiment of the present disclosure. Referring to FIG. 1 , the electronic device may include an active region RA and a peripheral region RB. The peripheral region RB may be located on at least one side of the active region RA. In some embodiments, as shown in FIG. 1 , the peripheral region RB may surround the active region RA, but is not limited thereto. In FIG. 1 , a boundary IF between the active region RA and the peripheral region RB is indicated by a thick solid line to facilitate the distinction between the active region RA and the peripheral region RB. According to some embodiments, the substrate 10 may include an active region RA and a peripheral region RB.

[0019] A plurality of units U (one is schematically shown in FIG. 1 ) may be disposed in the active area RA. The plurality of units U may be arranged in an array in the first direction D1 and the second direction D2. The types of components in the unit U may vary according to the application of the electronic device. For example, if the electronic device is used as a display device, the unit U may include a display component and a switch component, but is not limited thereto. On the other hand, if the electronic device is used as an antenna device, the unit U may include an antenna structure and a switch component, but is not limited thereto.

[0020] A plurality of driving circuits C may be disposed in the peripheral region RB. The plurality of driving circuits C are electrically connected to the plurality of units U in the active region RA. For example, the plurality of driving circuits C may be electrically connected to the plurality of units U in the active region RA via a plurality of wires (not shown). The driving circuit C may include active components, passive components, or a combination thereof, but is not limited thereto. The plurality of wires may include wires extending along a first direction D1 (e.g., scan lines) and wires extending along a second direction D2 (e.g., data lines). The electronic components including the semiconductor pattern, the first gate, and the second gate described below may be implemented as switch components in the unit U or active components in the driving circuit C, and will not be repeated below.

[0021] FIG2 is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure. FIG3 is a partial top view schematic diagram corresponding to the embodiment of FIG2 , wherein the cross-sectional view along the section line 2 - 2 ′ in FIG3 can refer to FIG2 , and FIG3 only schematically illustrates the semiconductor pattern, the first gate, the second gate, the source, and the drain in FIG2 .

[0022] Referring to FIG. 2 and FIG. 3 , the electronic device 1 may include a substrate 10 and an electronic component 12. The electronic component 12 is disposed on the substrate 10. The electronic component 12 may be, for example, a switch component in the aforementioned unit U or an active component in the aforementioned driving circuit C, and is not limited here. According to some embodiments, the electronic component 12 may be disposed in the peripheral region RB. According to some embodiments, the electronic component 12 may be disposed in the active region RA. The electronic component 12 includes a first gate GE1, a semiconductor pattern CH, a source SE, a drain DE, and a second gate GE2. The semiconductor pattern CH includes an overlap region R1, a first side region R2, and a second side region R2′. The overlapped portion of the semiconductor pattern CH and the first gate GE1 is defined as the overlap region R1. In the first direction D1, the first side region R2 and the second side region R2′ are respectively connected to two opposite sides of the overlap region R1. The first side region R2 and the second side region R2′ respectively include two opposite first edges (such as the first edge EC1 and the first edge EC2) of the semiconductor pattern CH. The source electrode SE and the drain electrode DE are electrically connected to the first side region R2 and the second side region R2', respectively. At least a portion of the second gate electrode GE2 overlaps the second side region R2' of the semiconductor pattern CH. FIG. 3 is a top view, which can show the plane formed by the first direction D1 and the second direction D2. FIG. 2 is a cross-sectional view, in which the thickness of each layer is the thickness along the third direction D3. The first direction D1, the second direction D2, and the third direction D3 are different directions. For example, the first direction D1, the second direction D2, and the third direction D3 can be perpendicular to each other.

[0023] Specifically, the substrate 10 may be a hard substrate or a flexible substrate. The material of the substrate 10 may include, for example, glass, quartz, ceramic, sapphire or plastic, but is not limited thereto. The plastic may include polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), other suitable flexible materials or a combination of the aforementioned materials, but is not limited thereto. In addition, the light transmittance of the substrate 10 is not limited, that is, the substrate 10 may be a light-transmitting substrate, a semi-transmitting substrate or an opaque substrate.

[0024] The electronic element 12 is, for example, an active element, such as a low-temperature polycrystalline silicon (LTPS) N-metal-oxide-semiconductor (NMOS) thin film transistor (TFT), but is not limited thereto.

[0025] The semiconductor pattern CH is disposed on the substrate 10 and is, for example, located between the first gate GE1 and the substrate 10. The material of the semiconductor pattern CH includes, for example, amorphous silicon, polysilicon, or metal oxide, but is not limited thereto. The metal oxide may be, for example, indium gallium zinc oxide (IGZO). For example, the overlapping region R1 of the semiconductor pattern CH may be a channel region (i.e., the region where the semiconductor pattern CH overlaps with the first gate GE1 in the third direction D3), the first side region R2 and the second side region R2' of the semiconductor pattern CH may each include an N-type high-doping region (such as an N-type high-doping region R21 and an N-type high-doping region R21') and an N-type low-doping region (such as an N-type low-doping region R22 and an N-type low-doping region R22') located between the overlapping region R1 and the N-type high-doping region, and the second gate GE2 at least overlaps with the N-type low-doping region of the second side region R2' (for example, at least overlaps with the N-type low-doping region R22'). Taking Figures 2 and 3 as examples, the second gate GE2 can extend from above the overlapping region R1 toward above the N-type highly doped region (including the N-type highly doped region R21 and the N-type highly doped region R21'), so that in the length direction of the semiconductor pattern CH (such as the first direction D1), the edge of the second gate GE2 is closer to the edge of the semiconductor pattern CH than the edge of the first gate GE1.

[0026] The first gate GE1 and the second gate GE2 may have different sizes. Specifically, according to some embodiments, as shown in FIG. 3 , in the first direction D1, the first gate GE1 has two opposite second edges (such as the second edge E21 and the second edge E22), and the second gate GE2 has two opposite third edges (such as the third edge E31 and the third edge E32). On a single side of the semiconductor pattern, with the semiconductor edge of the semiconductor pattern on that side as a reference, the distance between the second gate and the semiconductor edge is smaller than the distance between the first gate and the same semiconductor edge. In detail, on a single side of the semiconductor pattern (for example, the left side in FIG. 3 ), with the semiconductor edge of the semiconductor pattern on that side (such as the first edge EC1) as a reference, the distance DT13 between the third edge E31 of the second gate GE2 and the first edge EC1 corresponding to the semiconductor pattern CH is smaller than the distance DT12 between the second edge E21 of the first gate GE1 and the first edge EC1 corresponding to the semiconductor pattern CH. On the other side of the semiconductor pattern (for example, the right side in FIG. 3 ), with the semiconductor edge of the semiconductor pattern on the other side (such as the first edge EC2) as a reference, the distance DT13′ between the third edge E32 of the second gate GE2 and the first edge EC2 corresponding to the semiconductor pattern CH is smaller than the distance DT12′ between the second edge E22 of the first gate GE1 and the first edge EC2 corresponding to the semiconductor pattern CH.

[0027] In FIG. 3 , the third edge E31 of the second gate GE2 exceeds the boundary IF21 between the N-type high-doped region R21 and the N-type low-doped region R22, and the third edge E31 is located between the boundary IF21 and the first edge EC1 of the semiconductor pattern CH. In addition, the third edge E32 of the second gate GE2 exceeds the boundary IF22 between the N-type high-doped region R21′ and the N-type low-doped region R22′, and the third edge E32 is located between the boundary IF22 and the first edge EC2 of the semiconductor pattern CH. However, the positions of the third edge E31 and the third edge E32 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E31 may not exceed the boundary IF21, for example, the third edge E31 may be located between the boundary IF11 between the overlapping region R1 and the N-type low-doped region R22 and the boundary IF21, or the third edge E31 may be aligned with the boundary IF21. In addition, the third edge E32 may not exceed the interface IF22. For example, the third edge E32 may be located between the interface IF12 between the overlapping region R1 and the N-type low-doped region R22' and the interface IF22, or the third edge E32 may be aligned with the interface IF22.

[0028] In some embodiments, as shown in FIG. 2 , the electronic device 1 may further include a first dielectric layer 14. The first dielectric layer 14 is disposed between the semiconductor pattern CH and the first gate GE1. The material of the first dielectric layer 14 includes, for example, an organic insulating material, an inorganic insulating material, or a combination thereof. The organic insulating material includes, for example, polymethyl methacrylate (PMMA), epoxy, acrylic-based resin, silicone, polyimide polymer, or a combination thereof, but is not limited thereto. The inorganic insulating material includes, for example, silicon oxide or silicon nitride, but is not limited thereto.

[0029] The first gate GE1 is, for example, disposed on the first dielectric layer 14 and located above the overlapping region R1. In some embodiments, the second edge E21 and the second edge E22 of the first gate GE1 may be respectively aligned with the intersection IF11 and the intersection IF12, but not limited thereto. The material of the first gate GE1 includes, for example, metal or metal stacks, such as aluminum, molybdenum, or titanium / aluminum / titanium, but not limited thereto.

[0030] In some embodiments, as shown in FIG. 2 , the electronic device 1 may further include a second dielectric layer 16. The second dielectric layer 16 is disposed on the first dielectric layer 14 and the first gate GE1 and, for example, is located between the first gate GE1 and the second gate GE2. The material of the second dielectric layer 16 includes, for example, an organic insulating material, an inorganic insulating material, or a combination thereof.

[0031] The second gate GE2 is, for example, disposed on the second dielectric layer 16 and in a top view, at least a portion of the second gate GE2 is located between the first gate GE1 and the drain DE. Taking FIG. 3 as an example, the second gate GE2 may, for example, cover the overlapping region R1, the N-type low-doping region R22, the N-type low-doping region R22', the local N-type high-doping region R21, and the local N-type high-doping region R21', but is not limited thereto. The material of the second gate GE2 includes, for example, metal or metal stacks, such as aluminum, molybdenum, or titanium / aluminum / titanium, but is not limited thereto.

[0032] The source electrode SE and the drain electrode DE are, for example, disposed on the second dielectric layer 16, and the second gate electrode GE2, the source electrode SE, and the drain electrode DE, for example, belong to the same conductive layer. Specifically, the electronic element 12 may include a conductive layer, and the conductive layer includes the second gate electrode GE2, the source electrode SE, and the drain electrode DE. As shown in FIG. 2 , the source electrode SE may penetrate the first dielectric layer 14 and the second dielectric layer 16 and be electrically connected to the N-type highly doped region R21. In addition, the drain electrode DE may penetrate the first dielectric layer 14 and the second dielectric layer 16 and be electrically connected to the N-type highly doped region R21′.

[0033] By setting the second gate GE2, the leakage current can be reduced without significantly reducing the on-current (Ion) of the electronic component 12. Specifically, taking the LTPS NMOS TFT as an example, when the electronic component 12 is in the off state (for example, when the voltage of the first gate GE1 is less than zero), the voltage of the second gate GE2 can be made less than zero to reduce the electrons accumulated on the upper surface (the surface facing the first gate GE1) of the N-type low-doping region (including the N-type low-doping region R22 and the N-type low-doping region R22'), so that the resistance of the N-type low-doping region is increased, which helps to reduce the leakage current of the electronic component 12. On the other hand, when the electronic component 12 is in the on state (for example, when the voltage of the first gate GE1 is greater than zero), the voltage of the second gate GE2 can be made greater than zero to induce electrons to accumulate on the upper surface of the N-type low-doping region, so that the resistance of the N-type low-doping region is reduced, which helps to increase the on-current of the electronic component 12.

[0034] In the structure of FIG. 2 , the first gate electrode GE1 is separated from the semiconductor pattern CH by the first dielectric layer 14, and the second gate electrode GE2 is separated from the semiconductor pattern CH by the first dielectric layer 14 and the second dielectric layer 16. That is, the influence of the first gate electrode GE1 on the carriers in the semiconductor pattern CH is related to the thickness and dielectric constant of the first dielectric layer 14, and the influence of the second gate electrode GE2 on the carriers in the semiconductor pattern CH is not only related to the thickness and dielectric constant of the first dielectric layer 14, but also to the thickness and dielectric constant of the second dielectric layer 16. In some embodiments, the absolute value of the voltage applied to the second gate electrode GE2 is, for example, greater than or equal to the absolute value of the voltage applied to the first gate electrode GE1.

[0035] The electronic device may be a high voltage product. According to some embodiments, the voltage between the source and the drain in the electronic device may be between 8 volts and 70 volts, such as between 10 volts and 60 volts, such as between 15 volts and 50 volts, such as between 20 volts and 50 volts, and may be greater than 10 volts. When the electronic component 12 is applied to a product with high voltage operation (e.g., the voltage between the source SE and the drain DE is greater than 10 volts), such as an electrophoretic display or an antenna device, the second gate GE2 is provided to help miniaturize the electronic component 12. In detail, taking the LTPS NMOS TFT as an example, when the electronic component 12 is in the off state (for example, when the voltage of the first gate electrode GE1 is less than zero) or in the on state (for example, when the voltage of the first gate electrode GE1 is greater than zero), the resistance of the N-type low-doping region (including the N-type low-doping region R22 and the N-type low-doping region R22') can be increased by making the voltage of the second gate electrode GE2 less than zero, thereby reducing the effectiveness of the electric field in the channel region and improving the withstand voltage of the electronic component 12. In this way, the withstand voltage of the electronic component 12 can be increased without increasing the length of the N-type low-doping region in the first direction D1, which helps to miniaturize the electronic component 12.

[0036] FIG4 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. FIG5 and FIG6 are two partial top-view schematic diagrams corresponding to the embodiment of FIG4 , wherein the cross-sectional diagrams along the section line 4-4' in FIG5 and FIG6 can refer to FIG4 , and FIG5 and FIG6 only schematically illustrate the semiconductor pattern, the first gate, the second gate, the source and the drain in FIG4 .

[0037] In some embodiments, as shown in the electronic device 1A of FIG. 4 and FIG. 5 , the second gate GE2 may include a first branch portion GE21 and a second branch portion GE22, wherein in the top view, as shown in FIG. 5 , a portion of the first branch portion GE21 may be disposed between the first gate GE1 and the drain DE, and a portion of the second branch portion GE22 may be disposed between the first gate GE1 and the source SE. The first branch portion GE21 and the second branch portion GE22 may be electrically independent or electrically connected. In some embodiments, as shown in FIG. 6 , the second gate GE2 may further include a connecting portion GE23, wherein the first branch portion GE21 and the second branch portion GE22 of the second gate GE2 are connected via the connecting portion GE23, and in the top view, the first branch portion GE21, the second branch portion GE22 and the connecting portion GE23 form a concave portion (such as a U-shaped second gate GE2). The extending direction of the concave portion is, for example, parallel to the second direction D2.

[0038] In the electronic device 1A, by reducing the overlapping area between the first gate GE1 and the second gate GE2, the stray capacitance between the first gate GE1 and the second gate GE2 can be reduced, which helps to reduce the signal interference between the first gate GE1 and the second gate GE2.

[0039] In FIG. 5 and FIG. 6 , the third edge E31 of the second gate GE2 is located between the junction IF21 and the first edge EC1 of the semiconductor pattern CH, the third edge E32 of the second gate GE2 is located between the junction IF22 and the first edge EC2 of the semiconductor pattern CH, the third edge E33 of the second gate GE2 is located between the junction IF11 and the third edge E34 of the second gate GE2, and the third edge E34 of the second gate GE2 is located between the junction IF12 and the third edge E33 of the second gate GE2. However, the positions of the third edge E31, the third edge E32, the third edge E33 and the third edge E34 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E31 may be located between the junction IF11 and the junction IF21 or may be aligned with the junction IF21. The third edge E32 may be located between the junction IF12 and the junction IF22 or may be aligned with the junction IF22. The third edge E33 may be located between the interface IF11 and the interface IF21 or may be aligned with the interface IF11. The third edge E34 may be located between the interface IF12 and the interface IF22 or may be aligned with the interface IF12.

[0040] Fig. 7 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. Fig. 8 is a partial top view schematic diagram corresponding to the embodiment of Fig. 7, wherein the cross-sectional view along the section line 7-7' in Fig. 8 can refer to Fig. 7, and Fig. 8 only schematically illustrates the semiconductor pattern, the first gate, the second gate, the source and the drain in Fig. 7.

[0041] In some embodiments, as shown in the electronic device 1B of FIG. 7 and FIG. 8 , the second gate GE2 may be located at a side of the first gate GE1 close to the drain DE.

[0042] In FIG8 , the third edge E32 of the second gate GE2 is located between the junction IF22 and the first edge EC2 of the semiconductor pattern CH, and the third edge E34 of the second gate GE2 is located between the junction IF12 and the junction IF11. However, the positions of the third edge E32 and the third edge E34 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E32 may be located between the junction IF12 and the junction IF22 or may be aligned with the junction IF22. The third edge E34 may be located between the junction IF12 and the junction IF22 or may be aligned with the junction IF12.

[0043] Fig. 9 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. Fig. 10 is a partial top view schematic diagram corresponding to the embodiment of Fig. 9, wherein the cross-sectional view along the section line 9-9' in Fig. 10 can refer to Fig. 9, and Fig. 10 only schematically illustrates the semiconductor pattern, the first gate, the second gate, the source and the drain in Fig. 9.

[0044] In some embodiments, as shown in the electronic device 1C of FIG. 9 and FIG. 10 , the second gate GE2 may be physically connected to the drain DE. For example, the second gate GE2 is in direct contact with the drain DE, and the second gate GE2 and the drain DE may be formed by the same patterning process, so that there is no obvious boundary between the second gate GE2 and the drain DE. Under this architecture, in the top view, the boundary IF22 may be used as the boundary between the second gate GE2 and the drain DE.

[0045] In FIG10 , the third edge E34 of the second gate GE2 is located between the junction IF12 and the junction IF11. However, the position of the third edge E34 of the second gate GE2 is not limited thereto. In other embodiments, although not shown, the third edge E34 may be located between the junction IF12 and the junction IF22 or may be aligned with the junction IF12.

[0046] FIG. 11 to FIG. 16 are partial cross-sectional schematic diagrams of electronic devices according to other embodiments of the present disclosure. Please refer to FIG. 11 first, and the main differences between the electronic device 1D and the electronic device 1 of FIG. 2 are described as follows. In the electronic device 1D, in the cross-sectional view, the second gate GE2 and the first gate GE1 are respectively located on opposite sides of the semiconductor pattern CH. For example, the second gate GE2 and the first gate GE1 are respectively located on opposite sides of the semiconductor pattern CH in the third direction D3. In detail, the second gate GE2 is, for example, disposed on the substrate 10. The electronic device 1D further includes a third dielectric layer 18, wherein the third dielectric layer 18 is disposed on the substrate 10 and the second gate GE2 and is, for example, located between the second gate GE2 and the semiconductor pattern CH. The material of the third dielectric layer 18 includes, for example, an organic insulating material, an inorganic insulating material, or a combination thereof.

[0047] By arranging the second gate GE2 and the first gate GE1 on opposite sides of the semiconductor pattern CH, the distance between the second gate GE2 and the semiconductor pattern CH can be shortened, which helps to reduce the absolute value of the voltage applied to the second gate GE2. In the structure of FIG. 11, the influence of the second gate GE2 on the carriers in the semiconductor pattern Ch is related to the thickness and dielectric constant of the third dielectric layer 18, and the absolute value of the voltage applied to the second gate GE2 can be greater than, less than or equal to the absolute value of the voltage applied to the first gate GE1.

[0048] The top view of the second gate GE2 in FIG. 11 can refer to FIG. 3 , which will not be repeated here. In addition, in FIG. 11 , the third edge E31 of the second gate GE2 is located between the junction IF21 and the junction IF11, and the third edge E32 of the second gate GE2 is located between the junction IF12 and the junction IF22. However, the positions of the third edge E31 and the third edge E32 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E31 may be located between the first edge EC1 of the semiconductor pattern CH and the junction IF21 or aligned with the junction IF21. The third edge E32 may be located between the first edge EC2 of the semiconductor pattern CH and the junction IF22 or aligned with the junction IF22.

[0049] Referring to FIG. 12 , the main differences between the electronic device 1E and the electronic device 1D of FIG. 11 are described as follows. In the electronic device 1E, the second gate GE2 includes a first branch portion GE21 and a second branch portion GE22. In some embodiments, although not shown in FIG. 12 , the second gate GE2 may further include a connecting portion GE23 (see FIG. 6 ).

[0050] The top view of the second gate GE2 in FIG. 12 can refer to FIG. 5 , which will not be repeated here. In addition, in FIG. 12 , the third edge E31 of the second gate GE2 is located between the junction IF21 and the first edge EC1 of the semiconductor pattern CH, the third edge E32 of the second gate GE2 is located between the junction IF22 and the first edge EC2 of the semiconductor pattern CH, the third edge E33 of the second gate GE2 is located between the junction IF11 and the third edge E34 of the second gate GE2, and the third edge E34 of the second gate GE2 is located between the junction IF12 and the third edge E33 of the second gate GE2. However, the positions of the third edge E31, the third edge E32, the third edge E33 and the third edge E34 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E31 may be located between the junction IF21 and the junction IF11 or may be aligned with the junction IF21. The third edge E32 may be located between the interface IF12 and the interface IF22 or aligned with the interface IF22. The third edge E33 may be located between the interface IF21 and the interface IF11 or aligned with the interface IF11. The third edge E34 may be located between the interface IF12 and the interface IF22 or aligned with the interface IF12.

[0051] 13, the main differences between the electronic device 1F and the electronic device 1E of FIG12 are described as follows. In the electronic device 1F, the second gate GE2 is located on a side of the first gate GE1 close to the drain DE.

[0052] The top view of the second gate GE2 in FIG. 13 can refer to FIG. 8 , which will not be repeated here. In addition, in FIG. 13 , the third edge E32 of the second gate GE2 is located between the junction IF22 and the first edge EC2 of the semiconductor pattern CH, and the third edge E34 of the second gate GE2 is located between the junction IF12 and the junction IF11. However, the positions of the third edge E32 and the third edge E34 of the second gate GE2 are not limited thereto. In other embodiments, although not shown, the third edge E32 may be located between the junction IF12 and the junction IF22 or aligned with the junction IF22. The third edge E34 may be located between the junction IF12 and the junction IF22 or aligned with the junction IF12.

[0053] Referring to FIG. 14 , the main differences between the electronic device 1G and the electronic device 1F of FIG. 13 are described as follows. In the electronic device 1G, the second gate GE2 is electrically connected to the drain DE through the N-type high-doped region R21′. Taking FIG. 14 as an example, the electronic device 1G may further include a via CV, wherein the via CV electrically connects the second gate GE2 to the N-type high-doped region R21′, so that the second gate GE2 can be electrically connected to the drain DE through the via CV and the N-type high-doped region R21′.

[0054] In FIG. 14 , the third edge E34 of the second gate GE2 is located between the junction IF12 and the junction IF11. However, the position of the third edge E34 of the second gate GE2 is not limited thereto. In other embodiments, although not shown, the third edge E34 may be located between the junction IF12 and the junction IF22 or may be aligned with the junction IF12.

[0055] Referring to FIG. 15 , the main differences between the electronic device 1H and the electronic device 1 of FIG. 2 are described as follows. In the electronic device 1H, the first dielectric layer 14 includes a first portion P1 and a second portion P2 connected to the first portion P1 in a first direction D1, wherein the first portion P1 is located between the overlap region R1 of the semiconductor pattern CH and the first gate GE1, and the thickness TH1 of the first portion P1 is less than the thickness TH2 of the second portion P2. By increasing the thickness of the first dielectric layer 14 at the edge corresponding to the overlap region R1, the N-type high-doped region R21, the N-type high-doped region R21′, the N-type low-doped region R22, and the N-type low-doped region R22′, the electric field between the first gate GE1 and the drain DE can be reduced, which helps to reduce the leakage current.

[0056] Although FIG. 15 shows the thickness design of the first dielectric layer 14 under the framework of FIG. 2 , it should be understood that this thickness design is applicable to any embodiment of the present disclosure and will not be repeated here.

[0057] Referring to FIG. 16 , the main differences between the electronic device 1I and the electronic device 1E of FIG. 12 are described as follows. In the electronic device 1I, the electronic element 12 includes, for example, a low-temperature polycrystalline silicon P-type metal oxide semiconductor (P-Metal-Oxide-Semiconductor, PMOS) thin film transistor. In the semiconductor pattern CH, the overlapping region R1 is, for example, a channel region, and the first side region R2 and the second side region R2′ each include, for example, a P-type highly doped region, for example, the first side region R2 includes a P-type highly doped region R23, and the second side region R2′ includes a P-type highly doped region R23′).

[0058] Although FIG. 16 changes the type of semiconductor pattern under the structure of FIG. 12 , it should be understood that the type of semiconductor pattern in any embodiment of the present disclosure can be changed in the same manner. Alternatively, the design of the second gate GE2 and / or the first dielectric layer 14 can be changed according to the above-mentioned embodiment under the structure of FIG. 16 . For example, the configuration of the second gate GE2 in FIG. 16 can be changed with reference to FIGS. 2 to 14 , and / or the thickness design of the first dielectric layer 14 in FIG. 15 can be adopted.

[0059] In summary, in the embodiments disclosed herein, the second gate is provided to reduce leakage current without significantly reducing the on-current of the electronic component. When the electronic component is applied to a product operating at high voltage, the second gate is provided to help miniaturize the electronic component.

[0060] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, a person with ordinary knowledge in the relevant technical field should understand that the technical solutions recorded in the above embodiments can still be modified, or some or all of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0061] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure, and the features between the embodiments can be arbitrarily mixed and replaced to form other new embodiments. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand from the disclosure content of the present disclosure that the processes, machines, manufacturing, material compositions, devices, methods and steps currently or in the future developed can be used according to the present disclosure as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each claim and embodiment. The protection scope of the present disclosure shall be determined by the scope of the attached patent application.

[0062] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I: Electronic devices 10:Substrate 12: Electronic components 14: First dielectric layer 16: Second dielectric layer 18: The third dielectric layer C: Driving circuit CH: Semiconductor pattern CV: Via hole D1: First direction D2: Second direction D3: Third direction DE: drain DT12, DT12', DT13, DT13': distance EC1, EC2: First Edge E21, E22: Second edge E31, E32, E33, E34: The third edge GE1: First Gate GE2: Second Gate GE21: First Branch GE22: Second branch GE23: Connection IF, IF11, IF12, IF21, IF22: Junction P1: Part 1 P2: Part 2 R1: Overlapping area R2: First side area R2': Second side region R21, R21': N-type high-doping area R22, R22': N-type low-doping region R23, R23': P-type high-doping area RA: Active Area RB: Peripheral area SE: Source TH1, TH2: thickness U: Unit 2-2', 4-4', 7-7', 9-9': section line

Claims

1. An electronic device comprising: substrate; The system also includes an electronic component disposed on the substrate and comprising: a first gate; a semiconductor pattern including an overlap region, a first side region, and a second side region, wherein the portion of the semiconductor pattern and the first gate overlapping is defined as the overlap region, wherein in a first direction, the first side region and the second side region are respectively connected to two opposite sides of the overlap region, and the first side region and the second side region respectively include two opposite first edges of the semiconductor pattern; a source and a drain, respectively electrically connected to the first side region and the second side region; and a second gate, at least a portion of the second gate overlapping the second side region of the semiconductor pattern, wherein, in a top view, at least a portion of the second gate is located between the first gate and the drain.

2. The electronic device as claimed in claim 1, wherein, In the first direction, the first gate has two opposing second edges, the second gate has two opposing third edges, and the distance between one of the third edges of the second gate and one of the first edges corresponding to the semiconductor pattern is less than the distance between one of the second edges of the first gate and one of the first edges corresponding to the semiconductor pattern.

3. The electronic device of claim 1, wherein the first side region and the second side region each comprise a P-type highly doped region.

4. The electronic device of claim 1, wherein the first side region and the second side region each include an N-type heavily doped region and an N-type lightly doped region located between the overlapping region and the N-type heavily doped region, and the second gate at least overlaps the N-type lightly doped region of the second side region.

5. The electronic device as claimed in claim 1, further comprising: A first dielectric layer is disposed between the semiconductor pattern and the first gate, wherein the first dielectric layer includes a first portion and a second portion connected to the first portion in the first direction, the first portion being located between the overlapping region of the semiconductor pattern and the first gate, wherein the thickness of the first portion is less than the thickness of the second portion.

6. The electronic device of claim 1, wherein the second gate includes a first branch and a second branch, wherein, in a top view, a portion of the first branch is disposed between the first gate and the drain, and a portion of the second branch is disposed between the first gate and the source.

7. The electronic device as claimed in claim 6, wherein the second gate further comprises: The first branch and the second branch of the second gate are connected via the connecting portion, and in the top view, the first branch, the second branch and the connecting portion form a recess.

8. The electronic device of claim 1, wherein the electronic element includes a conductive layer, the conductive layer including the second gate, the source, and the drain.

9. The electronic device as claimed in claim 8, wherein the second gate is connected to the drain entity.

10. The electronic device as claimed in claim 1, wherein, In the cross-sectional view, the second gate and the first gate are located on opposite sides of the semiconductor pattern.

11. The electronic device of claim 1, wherein the transvoltage between the source and the drain is between 8 volts and 70 volts.

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