Method of forming patterns of semiconductor device

Abstract

A method for forming a pattern of a semiconductor element, the method comprising: forming an insulating film on a substrate having a first region and a second region; sequentially forming a lower mask layer and an upper mask layer on the insulating film; forming a linear hard mask pattern on the upper mask layer, the linear hard mask pattern having a plurality of narrow openings having the same width in the first region and the second region respectively; forming linear spacers on the sidewalls of the openings of the linear hard mask pattern; and forming a composite mask pattern composed of the linear spacers and a pattern having a first width in the linear hard mask pattern by removing a pattern having a second width in the linear hard mask pattern, the second width being smaller than the first width.

Description

Technical Field

[0001] [Cross - Reference to Related Applications]

[0002] Korean Patent Application No. 10 - 2022 - 0173059, filed with the Korean Intellectual Property Office on December 12, 2022, is incorporated herein by reference in its entirety.

[0003] Discloses a method of forming a pattern of a semiconductor device. Prior Art

[0004] When manufacturing highly scaled and highly integrated semiconductor devices, it is necessary to implement fine patterns with fine widths and pitches that exceed the resolution limit of the lithography process. Summary of the Invention

[0005] An embodiment relates to a method of forming a pattern of a semiconductor device, the method including: forming an insulating film on a substrate having a first region and a second region; sequentially forming a lower mask layer and an upper mask layer on the insulating film; forming a linear hard mask pattern on the upper mask layer, the linear hard mask pattern having a plurality of narrow openings with the same width in the first region and the second region respectively; forming linear spacers on sidewalls of the openings of the linear hard mask pattern; forming a composite mask pattern composed of the linear spacers and the pattern of the linear hard mask pattern having a first width by removing the pattern of the linear hard mask pattern having a second width, the second width being smaller than the first width; sequentially etching the upper mask layer and the lower mask layer by using the composite mask pattern as an etching mask to form a lower mask pattern; using the lower mask pattern as an etching mask to etch the insulating film into a linear insulating pattern having the same plurality of narrow openings in each of the first region and the second region; forming a wide opening by removing the pattern of the linear insulating pattern having a third width in the first region, and retaining the plurality of narrow openings of the linear insulating pattern in the second region; forming a conductive material layer filling the wide opening and the plurality of narrow openings of the linear insulating pattern; and polishing the conductive material layer into a wide conductive line in the first region and narrow conductive lines in the second region.

[0006] An embodiment relates to a method of forming a pattern of a semiconductor device, the method comprising: forming an insulating film on a substrate; forming a lower mask layer on the insulating film; forming a linear hard mask pattern having an opening on the lower mask layer; forming a linear spacer on sidewalls of the opening of the linear hard mask pattern; forming a composite mask pattern composed of the linear spacer and a pattern of the linear hard mask pattern having a first width by removing a pattern having a second width among the linear hard mask patterns, the second width being smaller than the first width; forming a lower mask pattern by etching the lower mask layer using the composite mask pattern as an etching mask; forming a linear insulating pattern having a plurality of narrow openings by etching the insulating film using the lower mask pattern as an etching mask, each of the plurality of narrow openings having the same fourth width; forming a wide opening by removing a pattern having a third width among the linear insulating patterns; forming a conductive material layer filling the wide opening of the linear insulating pattern; and polishing the conductive material layer into a wide conductive line.

[0007] An embodiment relates to a method of forming a pattern of a semiconductor device, the method comprising: forming an insulating film on a substrate; forming a lower mask layer on the insulating film; forming a linear hard mask pattern having an opening on the lower mask layer; forming a linear spacer on sidewalls of the opening of the linear hard mask pattern; forming a composite mask pattern composed of the linear spacer and a pattern of the linear hard mask pattern having a first width by removing a pattern having a second width among the linear hard mask patterns, the second width being smaller than the first width; forming a lower mask pattern by etching the lower mask layer using the composite mask pattern as an etching mask; forming a linear insulating pattern having a plurality of narrow openings by etching the insulating film using the lower mask pattern as an etching mask; forming a wide opening between the plurality of narrow openings by removing a pattern having a third width among the linear insulating patterns; forming a conductive material layer filling the plurality of narrow openings and the wide opening of the linear insulating pattern; and polishing the conductive material layer into a conductive line having a bent portion at a position of the wide opening. Brief Description of the Drawings

[0008] By describing exemplary embodiments in detail with reference to the accompanying drawings, various features will be apparent to those skilled in the art, in which: FIGS. 1A and 1B are conceptual diagrams showing exemplary embodiments of a semiconductor device. FIGS. 2A to 11B are diagrams of respective stages of a method of forming a pattern of a semiconductor device according to an exemplary embodiment. FIG. 12 is a perspective view showing an exemplary embodiment of a multilayer conductive line. FIG. 13 is a cross-sectional view showing a comparative example of a conductive line. FIG. 14 to FIG. 16 are plan views showing exemplary embodiments of conductive lines of a semiconductor device. FIG. 17 is a configuration diagram showing an exemplary embodiment of a communication system including a semiconductor device. Embodiment

[0009] FIGS. 1A and 1B are conceptual diagrams showing exemplary embodiments of a semiconductor device. Referring to FIG. 1A, a semiconductor device 1000 according to an embodiment may include a memory cell array region 1010 and a peripheral region 1020 surrounding the memory cell array region 1010.

[0010] Memory elements may be located in the memory cell array region 1010. The memory elements may be, for example, static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), or flash memory. As used herein, the term "or" is not an exclusive term, for example, "A or B" will include A, B, or both A and B.

[0011] Circuit components required to drive the memory components in the memory cell array region 1010 may be located in the peripheral region 1020. The circuit components may be, for example, a read circuit or a write circuit.

[0012] Referring to FIG. 1B, a semiconductor device 1100 according to another embodiment may include a logic region 1110 and an SRAM region 1120. In some embodiments, conductive lines manufactured by a method of forming a pattern of a semiconductor device to be described below may be in the logic region 1110. The logic region 1110 and the SRAM region 1120 are shown as examples here. A region in which memory components other than the logic region 1110 are formed (for example, a region in which DRAM, MRAM, PRAM, RRAM, or flash memory is formed) may be applied.

[0013] FIGS. 2A to 11B are diagrams of stages of a method of forming a pattern of a semiconductor device according to an exemplary embodiment. Specifically, FIGS. 2A to 11B are plan views of stages of a method of forming a pattern of a semiconductor device. FIGS. 2A, 3A, and 11A are cross-sectional views taken along the position corresponding to line B-B' of FIGS. 2A to 11B.

[0014] In the drawings, two directions that are parallel to the upper surface of the substrate 100 and cross each other are respectively defined as a first horizontal direction (X direction) and a second horizontal direction (Y direction). In an embodiment, the first horizontal direction (X direction) and the second horizontal direction (Y direction) may cross each other substantially at a right angle. Additionally, a direction perpendicular to the upper surface of the substrate 100 is defined as a vertical direction (Z direction). In the drawings, the directions indicated by the arrows and their opposite directions are described as the same direction. This definition of direction also applies to all the drawings.

[0015] Referring together to FIGS. 2A and 2B, an insulating film 101 and a plurality of mask layers 110 and 120 may be sequentially formed on the substrate 100. The substrate 100 may include a semiconductor material, such as a Group IV semiconductor, a III-V compound semiconductor, or a II-VI oxide semiconductor. In an embodiment, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 100 may include a bulk wafer or an epitaxial layer. As an alternative, the substrate 100 may be a semiconductor substrate, such as a silicon on insulator (SOI) substrate or a gallium arsenide substrate. Unit components (such as various types of active components or passive components) necessary for forming semiconductor components may be located on the substrate 100. Additionally, a plurality of through holes V1 and V2 (see FIG. 11B) may be located in the substrate 100.

[0016] The substrate 100 may include a first region R1 and a second region R2 adjacent to each other. The first region R1 and the second region R2 may be arbitrarily divided regions only for convenience of explanation, and the first region and the second region R2 may not be directly projected onto semiconductor elements. As described below, a wide conductive line 150M1 (see FIG. 11B) may be located in the first region R1, while a narrow conductive line 150M2 (see FIG. 11B) may be located in the second region R2.

[0017] The insulating film 101 may be, for example, a silicon-based material (such as silicon oxide, silicon nitride, or silicon oxynitride). In some embodiments, the insulating film 101 may be a silicon oxide-based material. In other embodiments, the insulating film 101 may be a low dielectric layer having a dielectric constant of about 2.2 to about 3.0. As described below, the insulating film 101 may be used as an interlayer insulating film surrounding a plurality of conductive lines 150M1 and 150M2 (see FIG. 11B). For this reason, the insulating film 101 may be referred to as a film to be etched into a final target pattern.

[0018] The plurality of mask layers 110 and 120 may be material layers for forming a final target pattern on the insulating film 101. The plurality of mask layers 110 and 120 may be made of the same material or different materials. When the plurality of mask layers 110 and 120 are made of different materials, the plurality of mask layers 110 and 120 may have the same or similar etching rates or different etching rates.

[0019] The plurality of mask layers 110 and 120 may include a lower mask layer 110 and an upper mask layer 120. The lower mask layer 110 may first be formed on the substrate 100 and then the upper mask layer 120 may be formed on the lower mask layer 110.

[0020] The lower mask layer 110 may include, for example, a carbon-based material. More specifically, the lower mask layer 110 may be an amorphous carbon layer (ACL) or a spin-on hard mask (SOH), which is a film made of a hydrocarbon or its derivative having a relatively high carbon content of about 85 wt% to about 99 wt% by total weight.

[0021] The upper mask layer 120 may include, for example, a plasma enhanced oxide (PEOX), tetraethyl orthosilicate (TEOS), tetraethyl borosilicate (BTEOS), tetraethyl phosphosilicate (PTEOS), tetraethyl borophosphosilicate (BPTEOS), boro silicate glass (BSG), phospho silicate glass (PSG), or boro phospho silicate glass (BPSG).

[0022] The hard mask pattern 130M may be located on the upper mask layer 120. The hard mask pattern 130M may be a material having an etching selectivity with respect to the plurality of hard mask layers 110 and 120 and the preliminary spacer layer 140 (see FIG. 3A) to be formed subsequently. The hard mask pattern 130M may be, for example, amorphous silicon. To form the hard mask pattern 130M, a photoresist film may be formed, and a photolithography process and an etching process may be performed.

[0023] The hard mask pattern 130M may include a plurality of openings 130H. The plurality of openings 130H may extend parallel to each other in a second horizontal direction (Y direction) and be spaced apart from each other, wherein the openings 130H may each have the same first width 130W in a first horizontal direction (X direction). For ease of illustration, only two of the plurality of openings 130H are shown in each of the first region R1 and the second region R2. However, there may be three or more openings 130H here.

[0024] The first width 130W of the plurality of openings 130H may be greater than the line and space width 1F (see FIG. 11A). In an embodiment, the number and the first width 130W of the openings 130H may be modified based on the size and arrangement of the conductive lines to be ultimately formed.

[0025] Referring together to FIGS. 3A and 3B, a preliminary spacer layer 140 may be conformally formed on the exposed surface of the upper mask layer 120 and the entire surface of the hard mask pattern 130M.

[0026] The preliminary spacer layer 140 may be formed by, for example, a chemical vapor deposition process or an atomic layer deposition process. The preliminary spacer layer 140 may be any material that has an etching selectivity with respect to the upper mask layer 120 and the hard mask pattern 130M. In an embodiment, the preliminary spacer layer 140 may be made of silicon oxide.

[0027] The thickness of the preliminary spacer layer 140 may be about 1 / 3 to about 1 / 5 of the first width 130W of the plurality of openings 130H. In an embodiment, the thickness of the preliminary spacer layer 140 may be an appropriate thickness according to the width of the spacer 140S (see FIG. 4A) formed in a subsequent process.

[0028] Referring together to FIGS. 4A and 4B, the spacer 140S may be formed by anisotropically etching the preliminary spacer layer 140 (see FIG. 3A). To form the spacer 140S, for example, CF gas or CHF gas may be used as the main etching gas. As an alternative, at least one gas (such as oxygen or argon) may be mixed with the main etching gas.

[0029] In some embodiments, in the process of etching the preliminary spacer layer 140 (see FIG. 3A), etching can be performed in a plasma atmosphere by generating a plasma of an etching gas selected from exemplary etching gases in an etching chamber. In other embodiments, by not generating a plasma in the etching chamber, etching can be performed in an atmosphere of a selected etching gas without ion energy.

[0030] The width of the spacer 140S can be the same as the thickness of the preliminary spacer layer 140 (see FIG. 3A). In an embodiment, the width of the spacer 140S can be about 1 / 3 to about 1 / 5 of the first width 130W of the plurality of openings 130H. In an embodiment, the width of the spacer 140S can have a thickness formed based on the width of the conductive line. Referring together to FIGS. 5A and 5B, after the spacer 140S is formed, a part of the hard mask pattern 130M can be removed.

[0031] After the spacer 140S is formed, an appropriate etching process can be used to remove the said part of the hard mask pattern 130M according to the constituent material of the hard mask pattern 130M. The removal of the said part of the hard mask pattern 130M can be performed under conditions where the etching of the spacer 140S and the upper mask layer 120 can be suppressed. As an alternative, after a mask pattern is formed on the hard mask pattern 130M, a desired part can be etched.

[0032] A relatively narrow pattern can be removed from the hard mask pattern 130M to form an opening 130A, and the upper surface of the upper mask layer 120 can be exposed through the opening 130A. Thus, a composite mask pattern CM including a relatively wide pattern in the spacer 140S and the hard mask pattern 130M can be formed. For example, as shown in FIG. 5B, the distance (e.g., the second width) of the opening 130A in the X direction can be smaller than the distance (e.g., the first width) of the composite mask pattern CM in the X direction.

[0033] In some embodiments, in each of the first region R1 and the second region R2, the relatively narrow pattern among the hard mask patterns 130M can be the pattern between the spacers 140S. Therefore, the spacers 140S can be located on the sidewalls of the relatively wide patterns among the hard mask patterns 130M, and the spacers 140S can be separate.

[0034] Referring to FIGS. 6A and 6B together, the upper mask pattern 120M can be formed by anisotropically etching the upper mask layer 120 using the composite mask pattern CM (see FIG. 5A) as an etching mask. A reactive ion etching (RIE) process or an inductively coupled plasma (ICP) etching process can be used as the anisotropic etching process for forming the upper mask pattern 120M. In this case, the residue of the composite mask pattern CM (shown in FIG. 5A) can remain on the upper mask pattern 120M. For subsequent processes, the residue of the composite mask pattern (CM, see FIG. 5A) can be removed.

[0035] Referring to FIGS. 7A and 7B together, the lower mask pattern 110M can be formed by anisotropically etching the lower mask layer 110 using the upper mask pattern 120M (see FIG. 6A) as an etching mask. A reactive ion etching process or an inductively coupled plasma etching process can be used as the anisotropic etching process for forming the lower mask pattern 110M.

[0036] In this case, the residue of the upper mask pattern 120M (see FIG. 6A) can remain on the lower mask pattern 110M. For subsequent processes, the residue of the upper mask pattern 120M (see FIG. 6A) can be removed. Here, although the processes for forming the lower mask pattern 110M and the upper mask pattern 120M (see FIG. 6A) have been described separately, in other embodiments, the processes for forming the lower mask pattern 110M and the upper mask pattern 120M (see FIG. 6A) can be implemented in one process.

[0037] Referring to FIGS. 8A and 8B together, the insulating pattern 101M can be formed by anisotropically etching the insulating film 101, which can be a film to be etched, using the lower mask pattern 110M (see FIG. 7A) as an etching mask.

[0038] An RIE process or an ICP etching process can be used as the anisotropic etching process for forming the insulating pattern 101M. In this case, the residue of the lower mask pattern 110M (see FIG. 7A) can remain on the insulating pattern 101M. For subsequent processes, the residue of the lower mask pattern 110M (see FIG. 7A) can be removed. The insulating pattern 101M can include the same narrow openings 101N in the first region R1 and the second region R2, respectively. A linear insulating spacer pattern 101S extending in the second horizontal direction (Y direction) can be located between adjacent narrow openings 101N.

[0039] The narrow opening 101N may have a tapered shape in which the width of the narrow opening 101N narrows toward the substrate 100, and conversely, the insulating spacer pattern 101S may have a tapered shape that widens away from the substrate 100. Such a tapered shape may be characteristic of an anisotropic etching process. In an embodiment, ideally, the sidewalls of the narrow opening 101N and the sidewalls of the insulating spacer pattern 101S should be perpendicular to the upper surface of the substrate 100, but due to the nature of the anisotropic etching process and the ultra-fine process, such a perpendicular structure may not be implementable. Therefore, the narrow opening 101N may be as perpendicular as possible.

[0040] Referring together to FIGS. 9A and 9B, after forming the insulating pattern 101M (see FIG. 8A), the insulating spacer pattern 101S may be completely removed from the first region R1 to form the final insulating pattern 101D.

[0041] After forming the insulating pattern 101M (see FIG. 8A), a portion of the insulating spacer pattern 101S may be removed using an appropriate etching process depending on the constituent material of the insulating pattern 101M (see FIG. 8A). A portion of the insulating spacer pattern 101S may be removed under conditions where etching of the substrate 100 is suppressed. As an alternative, the insulating spacer pattern 101S may be removed from the first region R1 after forming a mask pattern on the insulating pattern 101M (see FIG. 8A).

[0042] In the first region R1, all of the insulating spacer pattern 101S may be removed to form a wide opening 101W in the first region R1. In contrast, the insulating spacer pattern 101S may be left in the second region R2 such that the narrow opening 101N may exist in the second region R2. The wide opening 101W may have a width (e.g., a third width) that depends on the number of the removed spacer patterns 101S.

[0043] In an embodiment, in order to form the final target pattern differently for each region, the remaining number of the insulating spacer patterns 101S in the first region R1 and the second region R2 may be adjusted. Therefore, the final insulating pattern 101D having the wide opening 101W and the narrow opening 101N may be formed on the substrate 100, and the wide opening 101W and the narrow opening 101N have different widths in the first horizontal direction (X direction). Each of the narrow openings 101N may have the same width (e.g., a fourth width).

[0044] Here, one sidewall (the left sidewall in the figure) of the wide opening 101W in the first region R1 corresponds to one sidewall (the leftmost sidewall in the figure) of the conventional narrow opening (narrow opening 101N) in the first region R1 that is located at the outermost part (see FIG. 8A). In addition, the other sidewall (the right sidewall in the figure) of the wide opening 101W in the first region R1 corresponds to the other sidewall (the rightmost sidewall in the figure) of the conventional narrow opening (narrow opening 101N) in the first region R1 that is located at the outermost part (see FIG. 8A). In other words, the first sidewall can be located at the first outermost part of the plurality of narrow openings, and the second sidewall can be located at the second outermost part of the plurality of narrow openings.

[0045] Referring together to FIGS. 10A and 10B, the conductive material layer 150 can fill the exposed surface of the substrate 100 and the entire surface of the final insulating pattern 101D. The conductive material layer 150 can be formed to a thickness sufficient to fill the wide opening 101W (see FIG. 9A) and the narrow opening 101N (see FIG. 8A) included in the final insulating pattern 101D and completely cover the final insulating pattern 101D.

[0046] The conductive material layer 150 can be copper (Cu) or a copper alloy. After forming a copper seed layer on the exposed surface of the substrate 100 and the final insulating pattern 101D, the conductive material layer 150 can be formed on the copper seed layer by performing electroplating. As an alternative, the conductive material layer 150 can include aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), palladium (Pd), platinum (Pt), molybdenum (Mo), or metal silicide.

[0047] Referring together to FIGS. 11A and 11B, a polishing process can be performed on the upper surface of the conductive material layer 150 (see FIG. 10A) on the final insulating pattern 101D to form a plurality of conductive lines 150M1 and 150M2. The polishing process can be performed using the final insulating pattern 101D as an etch stop layer. Therefore, the conductive material layer 150 (see FIG. 10A) can be planarized by the polishing process to expose the upper surface of the final insulating pattern 101D. In an embodiment, the upper surfaces of the plurality of conductive lines 150M1 and 150M2 can be planarized with the upper surface of the final insulating pattern 101D. The plurality of conductive lines 150M1 and 150M2 can be electrically insulated from each other by the final insulating pattern 101D. In an embodiment, the process of forming the plurality of conductive lines 150M1 and 150M2 can be performed as an inlay process.

[0048] The polishing process can be implemented by a chemical mechanical polishing (CMP) process or an etch-back process. The polishing of the conductive material layer 150 (see FIG. 10A) can be implemented under conditions where the etching of the final insulating pattern 101D can be suppressed. In an embodiment, when the removal process is implemented as a CMP process, the etching of the final insulating pattern 101D can be suppressed by adjusting the slurry, polishing pad, or polishing conditions.

[0049] By implementing the polishing process, a plurality of conductive lines 150M1 and 150M2 having different widths in the first horizontal direction (X direction) can be formed on the substrate 100. Specifically, the plurality of conductive lines 150M1 and 150M2 can include wide conductive lines 150M1 in the first region R1 and narrow conductive lines 150M2 in the second region R2.

[0050] Here, each of the wide conductive line 150M1 and the narrow conductive line 150M2 can have a tapered shape that can become narrower toward the substrate 100, and a first angle D1 between the outer wall of the wide conductive line 150M1 and the upper surface of the substrate 100 can be substantially equal to a second angle D2 between the outer wall of the narrow conductive line 150M2 and the upper surface of the substrate 100. Since the two side walls of the wide opening 101W (see FIG. 9A) of the first region R1 can correspond to the two side walls of the narrow opening 101N (see FIG. 8A) of the first region R1, each of the wide conductive line 150M1 and the narrow conductive line 150M2 having a tapered shape can be formed. In this way, the semiconductor component pattern 10 can be implemented using the pattern formation method described with reference to FIGS. 2A to 11B.

[0051] As described below, as the width of the wide conductive line 150M1 increases, a halo problem may occur in which the difference between the width of the uppermost surface and the width of the lowermost surface of the wide conductive line 150M1 increases. However, as described above, when using the pattern formation method of the semiconductor element, the following effects can be obtained: forming a high-density pattern using a pattern having a size that can be achieved within the resolution limit of the lithography process, in which the halo problem can be solved and at the same time having an ultra-fine width and pitch. In an embodiment, the contact area between the plurality of vertical vias V1 and V2 formed on the substrate 100 and the plurality of conductive lines 150M1 and 150M2 can be maximized, and the contact resistance can be significantly reduced.

[0052] FIG. 12 is a perspective view showing an exemplary embodiment of a multilayer conductive line. Referring to FIG. 12, a plurality of vertical vias V1 and V2 that electrically connect the metal wiring line ML to the plurality of conductive lines 150M1 and 150M2 are shown.

[0053] In an embodiment, the plurality of conductive lines 150M1 and 150M2 and the plurality of vertical vias V1 and V2 should be formed as shown in the figure. Due to various design variables and process variables in the actual semiconductor device manufacturing process, it may not be easy to form such a structure.

[0054] In the process of forming the plurality of conductive lines 150M1 and 150M2 having different widths, due to the reduction of design rules, the areas of the plurality of vertical vias V1 and V2 can be reduced, and quite a number of process technologies can be used to increase the contact area between the plurality of conductive lines 150M1 and 150M2 and the plurality of vertical vias V1 and V2.

[0055] Using the method of forming a pattern of a semiconductor device, each of the wide conductive line 150M1 and the narrow conductive line 150M2 can be formed into a tapered shape with a substantially same narrowing ratio, and the contact areas of the plurality of vertical vias V1 and V2 can be relatively increased.

[0056] FIG. 13 is a cross-sectional view showing a comparative example of a conductive line. Referring to FIG. 13, in the method of forming a pattern of a semiconductor device according to the comparative example, a lower mask pattern 110ME having a wide opening and a narrow opening can be formed.

[0057] Next, the insulating film 101 can be anisotropically etched using the lower mask pattern 110ME as an etching mask to form a final insulating pattern 101DE. In this case, in the wide opening of the final insulating pattern 101DE formed in the first region R1, the difference between the width of the uppermost surface and the width of the lowermost surface can be large.

[0058] Next, a wide conductive line 150ME1 can be formed in the first region R1, and a narrow conductive line 150ME2 can be formed in the second region R2. Here, the wide conductive line 150ME1 can be formed according to the shape of the wide opening, and the narrow conductive line 150ME2 can be formed according to the shape of the narrow opening.

[0059] A third angle D3 between the outer wall of the wide conductive line 150ME1 and the upper surface of the substrate 100 can be smaller than a second angle D2 between the outer wall of the narrow conductive line 150ME2 and the upper surface of the substrate 100.

[0060] In an embodiment, as the width of the wide conductive line 150ME1 increases, a halo problem may occur in which the difference between the width of the uppermost surface and the width of the lowermost surface of the wide conductive line 150ME1 increases. Therefore, the contact area between the vertical through-hole V1 located on the substrate 100 and the wide conductive line 150ME1 may decrease, which may cause the problem that the contact resistance becomes very large.

[0061] To effectively solve the problems that may occur in the method of forming a pattern of a semiconductor element according to the comparative example, a method of forming a pattern of a semiconductor element according to an embodiment may be implemented.

[0062] FIGS. 14 to 16 are plan views showing exemplary embodiments of conductive lines of a semiconductor element. Most of the manufacturing processes and components constituting the method of forming a pattern of a semiconductor element described below may be substantially the same as or similar to those described previously with reference to FIGS. 2A to 11B. Therefore, for ease of explanation, the differences from the above method of forming a pattern of a semiconductor element will be emphasized.

[0063] Referring to FIGS. 14 and 15 together, based on the design rules of the finally formed conductive line, the widths of the wide conductive lines 250M1 and 350M1 in the first region R1 may be smaller or larger.

[0064] The third width W3 of the wide conductive line 250M1 having a relatively small width in the semiconductor component pattern 20 (see FIG. 14) may be smaller than the first width W1 of the wide conductive line 150M1 (see FIG. 11A) described above by a line and space width 1F.

[0065] In contrast, the fourth width W4 of the wide conductive line 350M1 having a relatively large width in the semiconductor component pattern 30 (see FIG. 15) may be larger than the first width W1 of the wide conductive line 150M1 (see FIG. 11A) described above by a line and space width 1F. In an embodiment, based on the line and space width 1F of the narrow conductive line 150M2, the widths of the wide conductive lines 250M1 and 350M1 may be increased or decreased by multiples of the line and space width 1F.

[0066] Referring to FIG. 16, by using a method of forming a pattern of a semiconductor device, a conductive line 450M1 having a bent portion can be formed in the first region R1. The conductive line 450M1 having a bent portion in the first region R1 may include a pair of line patterns 450MA and 450MC and a bridge pattern 450MB. The bridge pattern 450MB may extend in a first horizontal direction (X direction) perpendicular to the extending direction of the pair of line patterns 450MA and 450MC, and may electrically connect the pair of line patterns 450MA and 450MC to each other.

[0067] Each of the pair of line patterns 450MA and 450MC may have the same width as the second width W2 of the narrow conductive line 150M2 located in the second region R2, and the bridge pattern 450MB may have the same width as the first width W1 of the wide conductive line 150M1 (see FIG. 11A) described previously.

[0068] The bridge pattern 450MB may contact one end of one of the pair of line patterns 450MA and 450MC and contact the other end of the other of the pair of line patterns 450MA and 450MC. In an embodiment, the bridge pattern 450MB may correspond to a part of the wide conductive line 150M1 (see FIG. 11A). By applying the pattern formation method as described above, a conductive line 450M1 having a bent portion can be formed in the first region R1 of the semiconductor device pattern 40.

[0069] FIG. 17 is a configuration diagram showing an exemplary embodiment of a communication system 2000 including a semiconductor device. Referring to FIG. 17, the communication system 2000 may include a controller 2010, an input / output element 2020, a storage element 2030, an interface 2040, and a bus 2050.

[0070] The communication system 2000 may be a mobile system or a system for transmitting or receiving information. In some embodiments, the mobile system may be a portable computer, a tablet computer, a mobile phone, a digital music player, or a memory card.

[0071] The controller 2010 may control the execution of programs of the communication system 2000 and may include a microprocessor, a digital signal processor, or a microcontroller. The input / output element 2020 may be used to input or output data from the communication system 2000. The communication system 2000 may be connected to external elements, such as a personal computer or a network, and may exchange data with the external elements using the input / output element 2020. The input / output element 2020 may be, for example, a touchpad, a keyboard, or a display.

[0072] The memory element 2030 can store data for the operation of the controller 2010 or data processed by the controller 2010. The memory element 2030 can include semiconductor elements manufactured by a method of forming a pattern of semiconductor elements according to the above embodiments.

[0073] The interface 2040 can be a data transmission path between the communication system 2000 and external components. The controller 2010, the input / output element 2020, the storage element 2030, and the interface 2040 can communicate with each other via the bus 2050.

[0074] In summary, a method of forming a pattern of semiconductor elements is disclosed, which includes a high-density pattern having ultra-fine widths and spacings in a high-density region of the semiconductor elements. A technique capable of forming a fine pattern within the resolution limit of an existing lithography process can be utilized, and semiconductor elements having a new fine pattern to which such a technique can be applied can be utilized.

[0075] A method of forming a pattern of semiconductor elements is disclosed, the method including a high-density pattern having ultra-fine widths and spacings and using a pattern having dimensions achievable within the resolution limit of a lithography process to solve the halo problem.

[0076] Exemplary embodiments are disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, for those of ordinary skill in the art at the time of filing this application, it will be apparent that features, characteristics, or components described in connection with a particular embodiment can be used alone or in combination with features, characteristics, or components described in connection with other embodiments, unless otherwise specifically stated. Accordingly, those skilled in the art will understand that various changes can be made in form and detail.

[0077] 1F: Line and space width 10, 20, 30, 40: Semiconductor component patterns 100: Substrate 101: Insulating film 101D, 101DE: Final insulating pattern 101M: Insulating pattern 101N: Narrow opening 101W: Wide opening 101S: Spacer pattern / Insulating spacer pattern / Linear insulating spacer pattern 110: Mask layer / Lower mask layer 110M, 110ME: Lower mask pattern 120: Mask layer / Upper mask layer 120M: Upper mask pattern 130A, 130H: Opening 130M: Hard mask pattern 130W, W1: First width 140: Preliminary spacer layer 140S: Spacer 150: Conductive material layer 150M1: Conductive line / Wide conductive line 150M2: Conductive line / Narrow conductive line 150ME1, 250M1, 350M1: Wide conductive line 150ME2: Narrow conductive line 450M1: Conductive line 450MA, 450MC: Line pattern 450MB: Bridge pattern 1000, 1100: Semiconductor element 1010: Memory cell array region 1020: Peripheral region 1110: Logic region 1120: SRAM region 2000: Communication system 2010: Controller 2020: Input / Output element 2030: Memory element 2040: Interface 2050: Bus B - B': Line CM: Composite mask pattern D1: First angle D2: Second angle D3: Third angle ML: Metal wiring line R1: First region R2: Second region V1, V2: Through - hole / Vertical through - hole W2: Second width W3: Third width W4: Fourth width X, Y, Z: Direction

Claims

1. A method for forming a pattern of a semiconductor element, the method comprising: Forming a high-density pattern within the resolution limits of existing lithography processes includes: forming an insulating film on a substrate having a first region and a second region; sequentially forming a lower mask layer and an upper mask layer on the insulating film; forming a linear hard mask pattern on the upper mask layer, the linear hard mask pattern having a plurality of narrow openings of the same width in the first region and the second region respectively; forming linear spacers on the sidewalls of the plurality of narrow openings of the linear hard mask pattern; forming a composite mask pattern composed of the linear spacers and a pattern of a first width in the linear hard mask pattern by removing a pattern of a second width from the linear hard mask pattern, the second width being smaller than the first width; forming a lower mask pattern by sequentially etching the upper mask layer and the lower mask layer using the composite mask pattern as an etching mask; and etching the insulating film using the lower mask pattern as an etching mask to form a linear insulating pattern having the same plurality of narrow openings in each of the first region and the second region. A wide opening is formed by removing a pattern with a third width from the linear insulating pattern in the first region, while retaining the plurality of narrow openings of the linear insulating pattern in the second region; a conductive material layer is formed to fill the wide opening and the plurality of narrow openings of the linear insulating pattern; and the conductive material layer is polished into a wide conductive line in the first region and a narrow conductive line in the second region.

2. The method of claim 1, wherein the wide conductive line and the narrow conductive line each have a tapered shape in which the width narrows toward the substrate, and a first angle between the outer wall of the wide conductive line and the upper surface of the substrate is substantially equal to a second angle between the outer wall of the narrow conductive line and the upper surface of the substrate.

3. The method of claim 1, wherein in the first region, the wide opening is formed by removing a linear insulating spacer pattern between the plurality of narrow openings.

4. The method as described in request item 3, wherein: The first sidewall of the wide opening is located at the first outermost portion of the plurality of narrow openings, and the second sidewall of the wide opening is located at the second outermost portion of the plurality of narrow openings.

5. The method of claim 3, wherein the third width of the wide opening is determined by the number of linear insulating spacer patterns removed between the plurality of narrow openings.

6. The method as described in claim 5, wherein the third width of the wide opening is increased or decreased as a multiple of the line and space width of the plurality of narrow openings.

7. The method as claimed in claim 1, wherein forming the linear spacer comprises: A preliminary spacer layer is formed, which conformally covers the upper masking layer and the linear hard masking pattern; Furthermore, the entire surface of the initial spacer layer is etched.

8. The method of claim 7, wherein the material constituting the composite mask pattern is a different material with an etching selectivity different from that of the linear hard mask pattern having the second width.

9. The method of claim 1, wherein the formation of the conductive material layer is performed by an inlay process.

10. The method of claim 1, wherein a conductive vertical through-hole is provided below the wide conductive line.

Images