Semiconductor device structure and forming method thereof

Abstract

Various embodiments disclosed herein provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a dielectric wall disposed above a substrate, a first metal gate structure portion and a second metal gate structure portion disposed on opposite sides of the dielectric wall. Each of the first and second metal gate structure portions includes a plurality of semiconductor layers stacked perpendicularly to each other and spaced apart, a high-k (HK) dielectric layer disposed around at least three surfaces of each of the semiconductor layers, and a gate electrode layer disposed between two adjacent semiconductor layers. The semiconductor device structure also includes metal layers disposed on two opposing sidewalls of the dielectric wall.

Description

Semiconductor Device Structure and Method of Forming the Same The present disclosure relates to a semiconductor device structure, particularly a semiconductor device structure having a fork-shaped dielectric wall structure and an embedded cut metal gate (CMG) isolation structure. As the semiconductor industry introduces new generations of integrated circuits (ICs) with higher performance and more functions, the density of components forming the ICs increases, while the dimensions, sizes, and pitches between components or elements decrease. The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, the integration process also makes it more difficult to adjust the component characteristics between different devices. For example, it is difficult to compromise the parasitic capacitances of different devices between devices having different metal sizes. Therefore, there is a need in the art to provide improved devices that can solve the above problems. The present disclosure provides a semiconductor device structure. The semiconductor device structure includes a dielectric wall, a first metal gate structure portion and a second metal gate structure portion, and a gate electrode layer. The dielectric wall is disposed above a substrate. The first metal gate structure portion and the second metal gate structure portion are individually disposed on two sides of the dielectric wall. Each of the first metal gate structure portion and the second metal gate structure portion includes a plurality of semiconductor layers vertically stacked and separated from each other, a high-k dielectric layer disposed around at least three surfaces of each of the semiconductor layers, and a gate electrode layer disposed between two adjacent ones of the semiconductor layers. A metal layer is disposed on two opposite sidewalls of the dielectric wall. The present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first dielectric wall, a first transistor, a first gate electrode layer, and a second dielectric wall. The first dielectric wall is disposed above a substrate. The first transistor includes a plurality of first semiconductor layers vertically stacked above the substrate and disposed on a first side of the first dielectric wall. A first side of each of the first semiconductor layers is connected to the first dielectric wall. The first gate electrode layer is disposed between two adjacent ones of the first semiconductor layers. The second dielectric wall is disposed adjacent to a second side of each of the first semiconductor layers and separated from the second side of each of the first semiconductor layers. The present disclosure provides a method for forming a semiconductor device structure. The method for forming a semiconductor device structure includes forming a first fin structure, a second fin structure, and a third fin structure from a substrate, wherein the second fin structure is disposed between the first fin structure and the third fin structure, and each of the first fin structure, the second fin structure, and the third fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; forming a first dielectric wall between the second fin structure and the third fin structure; removing the second semiconductor layers from the first fin structure, the second fin structure, and the third fin structure such that the first semiconductor layers of at least one of the first fin structure and the second fin structure extend epitaxially from a first side and a second side of the first dielectric wall; filling a space between two adjacent first semiconductor layers of the first fin structure, the second fin structure, and the third fin structure with a gate electrode layer; forming a second dielectric wall between the first fin structure and the second fin structure; recessing the second dielectric wall such that a top surface of the second dielectric wall is at a height below a top surface of the first dielectric wall; and forming a metal layer to cover the first dielectric wall, the second dielectric wall, and the first semiconductor layers of the first fin structure, the second fin structure, and the third fin structure. The present disclosure provides many different embodiments or examples for implementing different features of the present case. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to limit. For example, if the present disclosure describes a first feature component formed on or above a second feature component, it means that it may include an embodiment in which the first feature component and the second feature component are in direct contact, and may also include an embodiment in which an additional feature component is formed between the first feature component and the second feature component, so that the first feature component and the second feature component may not be in direct contact. Additionally, the following disclosure may reuse the same reference symbols and / or markings in different examples. These repetitions are for the purpose of simplification and clarity, and are not intended to limit a specific relationship between the different embodiments and / or structures discussed. In addition, there are terms related to space. For example, "below", "beneath", "lower", "above", "higher", and similar terms are used to facilitate the description of the relationship between one element or feature component and another (some) element or feature component in the drawings. Except for the orientation shown in the drawings, these space-related terms are intended to include different orientations of the device in use or operation. In addition, the device may be turned to different orientations (rotated 90 degrees or other orientations), and the space-related terms used herein may be interpreted in the same way accordingly. Embodiments of the present disclosure provide a semiconductor device structure having a fork-shaped dielectric wall structure and an embedded cut metal gate (CMG) isolation structure to minimize gate-to-source / drain parasitic capacitance. The fork-shaped dielectric wall structure and the dielectric wall structure can be formed as part of a metal gate isolation process. The various embodiments described herein can be used in the design and / or fabrication of any type of integrated circuit or portion thereof, which can include any one of a plurality of various devices and / or components, such as static random access memory (SRAM) and / or other logic circuits, passive components (such as resistors, capacitors, and inductors), and active components, such as P-channel field-effect transistors (PFETs), N-channel FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, Omega gate (Ω gate) devices or Pi gate (Π gate) devices, and strained semiconductor devices, silicon-on-insulator (SOI) devices, partially-depleted SOI (PD-SOI) devices, fully-depleted SOI (FD-SOI) devices, other memory cells, or other devices known in the art. One of ordinary skill in the art can recognize other embodiments of semiconductor devices and / or circuits, including their design and fabrication, which can benefit from aspects of the present disclosure. Although the embodiments of the present disclosure are discussed in terms of nanostructured channel FETs, implementations of some aspects of the present disclosure can be used in other processes and / or other devices, such as planar FETs, Fin-FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. Those of ordinary skill in the art will readily understand that other modifications that can be made are contemplated within the scope of the present disclosure. In the case of using a gate all around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multiple patterning processes) can be used to pattern the structure. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the generation of patterns with pitches smaller than those obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure. FIGS. 1 to 38 are cross-sectional views and / or perspective views of a semiconductor device structure 100 at various process stations constructed in accordance with aspects of one or more embodiments of the present disclosure. It should be understood that additional operations can be provided before, during, and after the processes shown in FIGS. 1 to 38, and for additional embodiments of the method, some of the operations described below can be replaced or eliminated. The order of the operations / processes is not limited and can be interchanged. FIG. 1 is a perspective view of a semiconductor device structure 100 to be processed in accordance with some embodiments of the present disclosure. The semiconductor device structure 100 includes a semiconductor layer stack 104 formed over a front surface of a substrate 101. The substrate 101 can be a semiconductor substrate. The substrate 101 can include crystalline semiconductor material, such as (but not limited to) silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), indium phosphide (InP), or a combination thereof. In one embodiment, the substrate 101 is made of silicon. The substrate 101 can be doped or undoped. The substrate 101 can be a bulk semiconductor substrate, such as a bulk silicon substrate as a wafer, a silicon-on-insulator (SOI) substrate, a multi-layer or gradient substrate, etc. The substrate 101 may include various regions that have been doped with impurities (e.g., a doping mist having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for n-type field effect transistors (NFETs) and boron for p-type field effect transistors (PFETs). The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanosheet channels in a multi-gate device, such as a nanosheet channel FET. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108 vertically stacked above the substrate 101. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof. The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, epitaxial growth of the layers of the semiconductor layer stack 104 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. The first semiconductor layer 106 or a portion thereof may form a nanosheet channel of the semiconductor device structure 100 at a subsequent process site. The term "nanosheet" is used herein to refer to any material portion having nanoscale, even micron-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, this term refers to elongated material portions with circular and generally circular cross-sections, as well as beam-shaped or bar-shaped material portions including, for example, cylindrical or generally rectangular cross-sections. The nanosheet channel of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanosheet transistors. Nanosheet transistors may be referred to as nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below. Each first semiconductor layer 106 may have a thickness in the range of about 5 nm and about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in the range of about 2 nm and about 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately as shown in FIG. 1, which is for illustrative purposes and is not intended to limit beyond what is specifically recited in the claims. It can be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100. A capping structure 110 is formed over the semiconductor layer stack 104. The capping structure 110 may include an oxygen-containing layer 110a and a nitrogen-containing layer 110b. The oxygen-containing layer 110a may be a pad oxide layer, such as a SiO 2 layer. The nitrogen-containing layer 110b may be a pad nitride layer, such as Si 3 N 4 . The capping structure 110 may be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process. FIG. 2 to FIG. 5 show cross-sectional views of various sites of the semiconductor device structure 100 taken along the cross-section A-A of FIG. 1 according to some embodiments. As shown in FIG. 2, the fin structure 112 is formed by the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed by the substrate 101. The fin structure 112 can be patterned by using multiple patterning operations including lithography and etching processes to pattern a hard mask layer (not shown) formed on the semiconductor layer stack 104. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer into a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element can be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 that pass through the mask structure 110, the semiconductor layer stack 104, and into the substrate 101 in unprotected areas, leaving a plurality of extended fin structures 112. 114 extends along the X direction. Dry etching (e.g., RIE), wet etching, and / or a combination thereof can be used to etch the trenches 114. The trenches 114 can be formed to have different widths. For example, the trench between the first set of two directly adjacent fin structures 112 can have a first width, and the trench between the second set of two directly adjacent fin structures 112 can have a second width. The first width can be equal to, less than, or greater than the second width, depending on the channel width of the devices required in the semiconductor device structure 100. In FIG. 3, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization process (such as a chemical mechanical polishing (CMP) method and / or an etch-back method) is performed so that the top of the capping structure 110 is exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD). In FIG. 4, the insulating material 118 is recessed to form isolation regions 120 between the fin structures 112. The recessing of the insulating material 118 exposes plural portions of the fin structures 112, such as the semiconductor layer stack 104. The recessing of the insulating material 118 reveals the trenches 114 between adjacent fin structures 112. The isolation regions 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be substantially flush with or below the surface of the second semiconductor layer 108 that contacts the well portion 116 formed by the substrate 101. One or more etching processes can be used to remove the capping structure 110. In FIG. 5, a cover layer 132 is formed on the exposed surfaces of the fin structures 112 and the isolation regions 120. The cover layer 132 can include one or more layers of dielectric materials, such as SiN, SiON, silicon carbonitride (SiCN), silicon oxynitride (SiOCN), or other suitable oxide materials. The cover layer 132 can be a conformal layer and can be formed by a conformal process, such as an atomic layer deposition (ALD) process. The term "conformal" can be used herein to facilitate the description of a layer having substantially the same thickness over various regions. FIG. 6 shows a perspective view of a semiconductor device structure 100 on which one or more sacrificial gate structures 130 are formed. In FIG. 6, after forming the capping layer 132, one or more sacrificial gate structures 130 are deposited over the semiconductor layer stack 104 and the substrate 101. Each sacrificial gate structure 130 is formed over a portion of the fin structure 112 and may include a sacrificial gate electrode layer 134 and a capping layer 136. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The capping layer 136 may include an oxide layer 136a and a nitride layer 136b. The sacrificial gate electrode layer 134 and the capping layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate electrode layer 134 and the capping layer 136 over the capping layer 132 and the isolation region 120. The capping layer 136 is patterned and used to pattern the sacrificial gate electrode layer 134, resulting in the sacrificial gate structures 130 extending in a direction perpendicular to the fin structure 112 (i.e., the Y direction). Although four sacrificial gate structures 130 are shown, more or fewer sacrificial gate structures 130 may be arranged in the X direction in some embodiments. In some embodiments, a plurality of portions of the capping layer 132 exposed through the sacrificial gate structures 130 may be removed, thereby exposing the topmost layer of the semiconductor layer stack 104, such as the first semiconductor layer 106 as shown in FIG. 6. FIGS. 7 to 10 are cross-sectional views of one of the intermediate semiconductor device structures 100 taken along section line B-B of FIG. 6. In FIG. 7, gate spacers 138 are formed over the sidewalls of the sacrificial gate structures 130. The gate spacers 138 may be formed by first depositing a conformal layer and subsequently etching back the conformal layer to form the gate spacers 138. For example, a spacer material layer may be conformally disposed on the exposed surfaces of the semiconductor device structure 100. The conformal spacer material layer may be formed by an ALD process. Subsequently, anisotropic etching is performed on the spacer material layer using, for example, RIE. During the anisotropic etching process, most of the spacer material layer is removed from the horizontal surfaces (such as the top of the fin structure 112), leaving the gate spacers 138 on the vertical surfaces (such as the sidewalls of the sacrificial gate structures 130). The gate spacers 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. Next, by using one or more suitable etch-to-win (e.g., dry etching, wet etching, or a combination thereof), the exposed portions of the fin structure 112 that are not covered by the sacrificial gate structure 130 and the gate spacers 138 are recessed downward below the top surface of the isolation region 120 (Figure 6). In some embodiments, the exposed portions of the semiconductor layer stack 104 of the fin structure 112 are removed, thereby exposing a plurality of portions of the well portion 116 of the substrate 101. In one embodiment, the exposed portions of the fin structure 112 are recessed to a level below the bottommost layer (e.g., the second semiconductor layer 108) of the semiconductor layer stack 104. At this site, the ends of the semiconductor layer stack 104 below the sacrificial gate structure 130 and the gate spacers 138 have a generally flat surface that can be flush with the corresponding gate spacers 138, as shown in Figure 7. In some embodiments, the ends of the semiconductor layer stack 104 below the sacrificial gate structure 130 and the gate spacers 138 are etched slightly horizontally. The plurality of portions of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serve as the channel regions of the semiconductor device structure 100. The fin structure 112 partially exposed on opposite sides of the sacrificial gate structure 130 defines the source / drain (S / D) regions of the semiconductor device structure 100. In some cases, some of the S / D regions can be shared among various transistors. In Figure 8, the edge portions of each of the second semiconductor layers 108 of the semiconductor layer stack 104 are removed horizontally along the X direction. The removal of the edge portions of the second semiconductor layers 108 forms cavities between the first semiconductor layers 106. Next, an insulating layer is filled into the cavities to form dielectric spacers 144. The insulating layer can include a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. In some embodiments, a conformal dielectric layer can be formed by using a conformal deposition process (e.g., ALD), followed by anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacers 144 to form the dielectric spacers 144. In FIG. 9, the epitaxial source / drain (S / D) features 146 are formed on opposite sides of the sacrificial gate structure 130. The epitaxial S / D features 146 may include one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. The epitaxial S / D features 146 can grow vertically and horizontally to form facets that can correspond to the crystal planes of the material applied to the substrate 101. The epitaxial S / D features 146 are formed by an epitaxial growth method using CVD, ALD, or MBE. The epitaxial S / D features 146 are in contact with the first semiconductor layer 106 and the dielectric spacer 144. The epitaxial S / D features 146 can be the S / D regions. For example, one of a pair of epitaxial S / D features 146 located on one side of the semiconductor layer stack 104 can be the source region, and the other of a pair of epitaxial S / D elements 146 located on the other side of the semiconductor layer stack 104 can be the drain region. A pair of epitaxial S / D features 146 includes a source epitaxial feature 146 and a drain epitaxial feature 146 connected by a channel (i.e., the first semiconductor layer 106). In this disclosure, the source and the drain can be used interchangeably, and their structures are generally the same. After forming the epitaxial S / D features 146, a contact etch stop layer (CESL) 162 is formed on the epitaxial S / D features 146 and the sacrificial gate structure 130. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc. or a combination thereof. The CESL 162 can be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL 162 is a conformal layer formed by an ALD process. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162. The material of the ILD layer 164 may include tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 164 can be deposited by a PECVD process or other suitable deposition techniques. In FIG. 10, a planarization process is performed on the semiconductor device structure 100 to remove a plurality of portions of the ILD layer 164 and the CESL 162 disposed on the sacrificial gate structure 130. The planarization process can be any suitable process, such as a CMP process. The planarization process can be performed until the sacrificial gate electrode layer 134 is exposed. After the planarization process, the top surfaces of the CESL 162, the ILD layer 164, the gate spacer 138, and the sacrificial gate electrode layer 134 are substantially coplanar. FIG. 11 shows a perspective view of the intermediate semiconductor device structure 100 after the planarization process. In FIG. 12, one or more isolation trenches 151 (only one is shown) are formed in the semiconductor device structure 100. The one or more isolation trenches 151 can be formed by providing a patterned mask structure (not shown) above the substrate 101. One or more lithography processes can be performed to form openings in the CESL 162, the ILD layer 164, the gate spacer 138, and the sacrificial gate electrode layer 134 of the semiconductor device structure 100. This opening defines the isolation trench 151 to be formed in the semiconductor device structure 100 and can be disposed between adjacent active regions 153. The term "active region" in the present disclosure refers to the region where the transistor is located. Therefore, the sacrificial gate structure 130 in the active region 153 is protected by the patterned mask structure. The isolation trench 151 can extend laterally in a direction parallel to the longitudinal direction of the fin structure 112. In some embodiments, the capping layer 132 is exposed through the bottom and the lower portion of the sidewall of the isolation trench 151. In some embodiments, a portion of the sacrificial gate electrode layer 134 is exposed through the upper portion of the sidewall of the isolation trench 151. In some embodiments, the isolation trench 151 can extend all the way to expose the top surface of the isolation region 120. In some embodiments, the isolation trench 151 is formed to at least expose the sidewall of the capping layer 132 formed above the fin structure 112. FIG. 13 shows a cross-sectional view of the semiconductor device structure 100 taken along section line C-C of FIG. 12. FIGS. 14 to 15 and FIGS. 17 to 27 are cross-sectional views of various stations for manufacturing the semiconductor device structure 100 taken along section line D-D of FIG. 12. In FIG. 14, a first dielectric wall 124 is formed to fill the isolation trench 151. In some embodiments, the first dielectric wall 124 can be a single-layer structure. In some embodiments, the first dielectric wall 124 can be a multi-layer structure. In one embodiment shown in FIG. 14, the first dielectric wall 124 is a double-layer structure, which includes a liner 126 and a dielectric layer 128 formed on the liner 126. The upper portion of the liner 126 can be disposed between the dielectric layer 128 and the sacrificial gate electrode layer 134, and the lower portion of the liner 126 can be disposed between the dielectric layer 128 and the capping layer 132. The thickness of the liner 126 is less than the thickness of the dielectric layer 128. The liner 126 and the dielectric layer 128 include different dielectric materials. The liner 126 and the dielectric layer 128 can be oxides, nitrides, or any suitable low-k or high-k dielectric material, or any combination thereof. The liner 126 and the dielectric layer 128 can include materials with different chemical properties from each other. Suitable low-k dielectric materials can include (but are not limited to) SiO 2 , SiN, SiCN, SiOC, SiOCN, etc. Suitable high-k dielectric materials can include (but are not limited to) HfO 2 , ZrO 2 , HfAlO x , HfSiO x , Al 2 O 3 etc. The liner 126 can be conformally formed before forming the dielectric layer 128. The dielectric material of the dielectric layer 128 can overfill the isolation trench 151 and reach a height above the top surface of the sacrificial gate electrode layer 134. Thereafter, a planarization process (such as a CMP process) can be performed on the semiconductor device structure 100 until the ILD layer 164 is exposed. After the planarization process, the top surfaces of the dielectric layer 128, the liner 126, the sacrificial gate electrode layer 134, the gate spacer 138, the ILD layer 164, and the CESL 162 are generally coplanar, as shown in FIG. 14. In FIG. 15, the remaining portion of the sacrificial gate electrode layer 134 is removed to form a plurality of trenches 155. The removal of the sacrificial gate electrode layer 134 can be achieved by any suitable removal process, such as dry etching, wet etching, or a combination thereof. The removal process can be a selective etching process that removes the sacrificial gate electrode layer 134 but does not remove the dielectric layer 128, the liner 126, the capping layer 132, the gate spacer 138, the ILD layer 164, and the CESL 162. As a result of the removal process, the capping layer 132 and the first dielectric wall 124 covering the semiconductor layer stack 104 are exposed through the sidewalls of each trench 155. FIG. 16 shows a perspective view of the semiconductor device structure 100 after the trenches 155 are formed. In FIG. 17, the dielectric layer 128 is trimmed and the exposed portions of the capping layer 132 and the liner 126 are removed. The trimmed dielectric layer 128 is shown as a dashed line. The dielectric layer 128 can be trimmed by first removing a portion of the liner 126 exposed through the trench 155 to expose the dielectric layer 128 through the sidewalls of the trench 155. In this case, the remaining portion of the liner 126 sandwiched between the dielectric layer 128 and the capping layer 132 can be non-permeable and thus remains. Thereafter, a portion of the exposed capping layer 132 is removed such that the semiconductor layer stack 104 is exposed through the trench 155. Removal of the capping layer 132, the dielectric layer 128, and the liner 126 can be achieved by any suitable removal process, such as dry etching, wet etching, or a combination thereof. The removal process is a selective etching process that removes dielectric material but not semiconductor material (e.g., the first semiconductor layer 106 and the second semiconductor layer 108). In some embodiments, the etching time of the removal process can be controlled to adjust the amount of trimming of the dielectric layer 128. In some embodiments, after the removal process, a portion of the liner 126 at the corners of the capping layer 132 and the dielectric layer 128 can be retained. Trimming of the dielectric layer 128 allows an increase in the surface area of the channel region (e.g., the first semiconductor layer 106) to the subsequent gate electrode layer. As a result, the overall performance of the semiconductor device structure 100 is improved. In FIG. 18, a plurality of portions of the semiconductor layer stack 104 are removed. In some embodiments, the second semiconductor layer 108 is removed such that the first semiconductor layer 106 remains and is separated from each other in the trench 155. In some embodiments, the first semiconductor layer 106 is coupled to the first dielectric wall 124 through the capping layer 132 and the liner 126 to form a fin-like isolation structure. In some embodiments, the first semiconductor layer 106 remaining in the trench 155 is further trimmed. In this case, each first semiconductor layer 106 is trimmed to have a predetermined shape and size (i.e., thickness and width). By adjusting the width and thickness of the first semiconductor layer 106, the threshold voltage (Vt) of the formed FRT device can be adjusted to meet the requirements. Additionally, in such embodiments, the capping layer 132 and the liner 126 may be consumed. Thus, the thicknesses of the capping layer 132 and the liner 126 are reduced. In some alternative embodiments, the capping layer 132 and the liner 126 exposed through the trench 155 can be completely consumed such that the first semiconductor layer 106 is suspended in the trench 155 and physically separated from the dielectric layer 128. Next, an interfacial layer (IL) 178 is formed to surround at least three surfaces of the first semiconductor layer 106 (except for the surface in contact with the capping layer 132). The IL 178 can be formed on the first semiconductor layer 106, but not on the capping layer 132 or the liner 126. In some embodiments, the IL 178 can also be formed on the exposed surface of the well portion 116 of the substrate 101. The IL 178 can include or be made of an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, nitrogen oxide, hafnium silicate, etc. The IL 178 can be formed by CVD, ALD, or any suitable conformal deposition technique. Next, a high-K (HK) dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100. In some embodiments, the HK dielectric layer 180 is formed on the IL 178, the isolation region 120, the capping layer 132, the liner 126, and the dielectric layer 128. The HK dielectric layer 180 can include or be made of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), strontium titanate (SrTiO 3 ), hafnium oxynitride (HfO x Ny), other suitable high-k materials, other suitable metal oxides, or combinations thereof. The HK dielectric layer 180 can be a conformal layer formed by a conformal process (such as an ALD process or a CVD process). The HK dielectric layer 180 can have a thickness of about 0.1 nm to about 3 nm, which can vary depending on the application. After forming the IL and HK dielectric layers 180, a gate electrode layer 182 is formed over the substrate 101 to cover the HK dielectric layer 180. The gate electrode layer 182 fills the trench 155 (FIG. 18) and surrounds a portion of each first semiconductor layer 106. Thus, the gate electrode layer 182 reaches the region between two adjacent first semiconductor layers 106 of each fin structure 112. The gate electrode layer 182 includes one or more layers of conductive materials such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 182 can be formed by PVD, CVD, ALD, electroplating, or other suitable methods. Although not shown, one or more optional conformal layers can be conformally (and sequentially, if more than one layer) deposited between the HK dielectric layer 180 and the gate electrode layer 182. The one or more optional conformal layers can include one or more barrier layers and / or capping layers and one or more work function adjustment layers. The one or more barrier layers and / or capping layers can include or be nitrides of tantalum and / or titanium, silicon nitride, carbon nitride, and / or aluminum nitride; nitrides, carbon nitrides, and / or carbides of tungsten; etc.; or combinations thereof. The one or more work function adjustment layers can include or be nitrides of titanium and / or tantalum, silicon nitride, carbon nitride, aluminum nitride, aluminum oxide, and / or aluminum carbide; nitrides, carbon nitrides, and / or carbides of tungsten; cobalt; platinum; etc.; or combinations thereof. In FIG. 20, a metal gate etch back (MGEB) process is performed on the gate electrode layer 182. Accordingly, plural portions of the gate electrode layer 182 are removed. In some embodiments, the etch back process is performed such that the gate electrode layer 182 remains between the first semiconductor layers 106. The removal of the plural portions of the gate electrode layer 182 exposes plural portions of the trench 155. In FIG. 21, a hard mask layer 147 is conformally formed over the HK dielectric layer 180 and the gate electrode layer 182. The hard mask layer 147 protects the HK dielectric layer 180, the gate electrode layer 182, and the first semiconductor layer 106 from being damaged during subsequent processes. The hard mask layer 147 can be formed of a dielectric material such as SiN, SiCN, SiOC, SiOCN, Al 2 O 3 etc., and can be deposited by any suitable deposition process (such as PVD, CVD, ALD, etc.). In FIG. 22, a protection structure 149 is formed in the trench 155. The protection structure 149 can be deposited to at least cover the first dielectric wall 124 and the first semiconductor layers 106 on opposite sides of the first dielectric wall 124. In some embodiments, the protection structure 149 can at least include a photoresist layer 150 and a bottom anti-reflective coating (BARC) layer 152 disposed between the photoresist layer 150 and the hard mask layer 147. The photoresist layer 150 is patterned to form a trench 157. The patterned photoresist layer 150 serves as a mask during subsequent processes (such as one or more lithography and etching processes) to transfer the pattern (i.e., the trench 157) in the photoresist layer 150 into the BARC layer 152. The trench 157 can extend through the entire thickness of the protection structure 149. In some embodiments, the trench 157 can extend into the hard mask layer 147 to expose a portion of the HK dielectric layer 180 above the isolation region 120. The trench 157 defines an isolation region where a second dielectric wall 161 (FIG. 24) will be formed. The isolation region can be disposed between adjacent fin structures 112 where the first dielectric wall 124 is absent. In some embodiments, the bottom of the trench 157 can laterally extend into the region between the BARC layer 152 and the HK dielectric layer 180. The lateral etching of the bottom of the protection structure 149 ensures that the hard mask layer 147 at the bottom is completely removed. The removal of the hard mask layer 147 at the bottom of the protection structure 149 forms a gap 159 between the BARC layer 152 and the HK dielectric layer 180. In some embodiments, the gap 159 has a height H1 that is approximately the same as the thickness of the hard mask layer 147 in contact with the HK dielectric layer 180. In some embodiments, the height H1 of the gap 159 is greater than the thickness of the hard mask layer 147 in contact with the HK dielectric layer 180. In some embodiments, the trench 157 extends through the HK dielectric layer 180 to expose the isolation region 120. In some embodiments, the gap 159 can have a depth D0 measured from the end of the exposed hard mask layer 147 to a line extending along the sidewall of the bottom BARC layer 152. The depth D0 can be in the range of about 0.1 nm to about 2.5 nm. In FIG. 23, a dielectric structure 161' is formed to fill the trench 157. The dielectric structure 161' can include a first dielectric layer 161a and a second dielectric layer 161b subsequently formed on the first dielectric layer 161a. The second dielectric layer 161b can have at least three surfaces in contact with the first dielectric layer 161a. The first dielectric layer 161a and the second dielectric layer 161b can include materials with chemically different properties. Exemplary materials for the first dielectric layer 161a can include (but are not limited to) oxides, SiO 2 、SiN、SiON、AlO x , AlSiO x , AlSiO x N y or other suitable dielectric materials. Exemplary materials for the second dielectric layer 161b may include (but are not limited to) oxides, SiO 2 , SiN, SiON, AlO x , AlSiO x , AlSiO x N y or other suitable dielectric materials. For example, the first dielectric layer 161a may include silicon oxide, and the second dielectric layer 161b may include silicon nitride. In some embodiments, the first dielectric layer 161a and the second dielectric layer 161b include the same material. In some embodiments, the materials of the first dielectric layer 161a and the second dielectric layer 161b may be the same as or different from the materials of the liner 126 and the dielectric layer 128. For example, the liner 126 and the first dielectric layer 161a may include the same or different materials from each other, and the dielectric layer 128 and the second dielectric layer 161b may include the same or different materials from each other. In some embodiments, the first dielectric layer 161a is conformally formed to cover the exposed surfaces of the photoresist layer 150, the BARC layer 152, and the HK dielectric layer 180 exposed through the trench 157. In the case where the hard mask layer 147 at the bottom of the trench 157 is removed, the first dielectric layer 161a is deposited on the isolation region 120. The first dielectric layer 161a is also deposited to fill the gap 159. After forming the first dielectric layer 161a, the second dielectric layer 161b is deposited on the first dielectric layer 161a. The second dielectric layer 161b fills the trench 157 and is deposited until the trench 157 is overfilled. The dielectric structure 161' can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD). The first dielectric layer 161a and the second dielectric layer 161b can be deposited in a low temperature range (e.g., about 200 to about 400 degrees Celsius) to avoid damaging the source / drain features or other transistor devices. FIG. 23-1 and FIG. 23-2 show enlarged views of a portion of the semiconductor device structure 100 in accordance with some embodiments of the present disclosure. In the embodiment shown in FIG. 23-1, the dielectric structure 161' includes a first portion 161a-1 and a second portion 161a-2 connected to the first portion 161a-1. The first portion 161a-1 has a first thickness T1, and the second portion 161a-2 has a second thickness T2 greater than the first thickness T1. The difference between the first thickness T1 and the second thickness T2 is partly attributable to the removal of the hard mask layer 147 at the bottom of the trench 157, and the second thickness T2 may vary depending on the height H1 of the gap 159, as discussed above with respect to FIG. 22. In some embodiments, the hard mask layer 147 has a third thickness T3 that is less than the second thickness T2 of the second portion 161a-2 of the dielectric structure 161'. In the embodiment shown in FIG. 23-2, the dielectric structure 161' includes a first portion 161a-3 and a second portion 161a-4 connected to the first portion 161a-3. The first portion 161a-3 has a first thickness T4, and the second portion 161a-4 has a second thickness T5 that is substantially the same as the first thickness T4. In some embodiments, the hard mask layer 147 has a third thickness T6 that is substantially the same as the second thickness T5 of the second portion 161a-4 of the dielectric structure 161'. In FIG. 24, an etch-back process is performed to remove a plurality of portions of the dielectric structure 161' to form a second dielectric wall 161. The second dielectric wall 161 can be used as a cut metal gate (CMG) isolation structure. Specifically, the second dielectric wall 161 is embedded in a gate electrode layer (e.g., metal layer 169) that will be formed in the trench 157, and thus reduces the amount of the gate electrode layer between adjacent transistors (which would cause a large gate-to-S / D parasitic capacitance). As a result, the gate-to-S / D parasitic capacitance of the semiconductor device structure 100 is reduced. The etch-back process can be a selective etching process that removes the first dielectric layer 161a and the second dielectric layer 161b but does not remove the photoresist layer 150 and the BARC layer 152. The etch-back process can be performed on the dielectric structure 161' such that the top surfaces of the first dielectric layer 161a and the second dielectric layer 161b are substantially coplanar. In some embodiments, the etch-back process is performed such that the top surface of the first dielectric layer 161a is slightly lower than the top surface of the second dielectric layer 161b. In some embodiments, the etch-back process is performed such that the top surface of the first dielectric layer 161a is slightly higher than the top surface of the second dielectric layer 161b. In some embodiments, the etch-back process is performed such that the top surface of the first dielectric layer 161a or the second dielectric layer 161b is at a height lower than or substantially flush with the top surface of the topmost first semiconductor layer 106. In some embodiments, the etch-back process is performed such that the top surface of the first dielectric layer 161a or the second dielectric layer 161b is at a height higher than the top surface of the topmost first semiconductor layer 106. The height of the second dielectric wall 161 controls the amount of the gate electrode layer formed thereon, and thus can effectively affect the gate-to-source / drain parasitic capacitance. Setting the top surface of the second dielectric layer 161b at a height higher than the top surface of the topmost first semiconductor layer 106 reduces the capacitance value. As a result, a better effective capacitance (Ceff) gain is obtained. In some embodiments, the etch-back process can be performed such that one or more second dielectric walls 161 in the first device region have a first height, and one or more second dielectric walls 161 in the second device region have a second height different from (e.g., greater than or less than) the first height. In FIG. 25, the protection structure 149 and the hard mask layer 147 are removed. One or more etching processes can be used to remove the protection structure 149 and the hard mask layer 147. The one or more etching processes can be selective strike / or time-controlled etching processes that remove the protection structure 149 and the hard mask layer 147 while substantially not affecting the HK dielectric layer 180, the second dielectric wall 161, and the gate electrode layer 182. The removal of the protection structure 149 and the hard mask layer 147 exposes the trench 157. In FIG. 26, a metal layer 169 is formed to fill the trench 157. The metal layer 169 serves as a gap-fill layer and becomes part of the gate electrode layer of the semiconductor device structure 100. A plurality of portions of the metal layer 169 are recessed, and the recessed metal layer 169 is combined with the gate electrode layer 182 to form a metal gate structure 173. Each channel layer (i.e., the first semiconductor layer 106) is surrounded by the metal gate structure 173. The metal layer 169 may use a material selected from the materials used for the gate electrode layer 182. In some embodiments, the metal layer 169 and the gate electrode layer 182 may include the same material. In some embodiments, the metal layer 169 and the gate electrode layer 182 may include different materials from each other. The metal layer 169 covers the exposed surfaces of the first dielectric wall 124 and the second dielectric wall 161 and contacts the gate electrode layer 182 exposed through the trench 157. The metal layer 169 may be formed in the same manner as the gate electrode layer 182 and may be deposited to a height above the top surface of the first dielectric wall 124. In FIG. 27, a planarization process (e.g., CMP) is performed on the semiconductor device structure 100. The planarization process may be performed until the dielectric layer 128 of the first dielectric wall 124 is exposed. In some embodiments, the planarization process is performed to remove a plurality of portions of the metal layer 169, the HK dielectric layer 180, and the dielectric layer 128 of the first dielectric wall 124. When the planarization process is completed, the top surfaces of the metal layer 169, the HK dielectric layer 180, and the dielectric layer 128 of the first dielectric wall 124 are substantially coplanar. In some embodiments, the metal gate structure 173 may include a first metal gate structure portion 173a, a second metal gate structure portion 173b, and a third metal gate structure portion 173c. The first metal gate structure portion 173a and the second metal gate structure portion 173b are separated from each other by the first dielectric wall 124. The second metal gate structure portion 173b and the third metal gate structure portion 173c are separated from each other by the second dielectric wall 161. Each metal gate structure portion 173a, 173b, 173c includes a plurality of first semiconductor layers 106 vertically stacked and separated from each other above the substrate 101, an HK dielectric layer 180 covering each first semiconductor layer 106, and an IL 178 disposed between the HK dielectric layer 180 and the first semiconductor layer 106. The first dielectric wall 124 is disposed above the substrate 101 and is physically connected (through the pad 126 and the cover layer 132) to the first semiconductor layers 106 disposed on opposite sides of the first dielectric wall 124. The second dielectric wall 161 is disposed above the substrate 101 and physically separates the second metal gate structure portion 173b and the third metal gate structure portion 173c from each other. The metal gate structure 173 disposed above the second dielectric wall 161 is electrically connected to the second metal gate structure portion 173b and the third metal gate structure portion 173c. If the second dielectric wall 161 completely separates the second metal gate structure portion 173b and the third metal gate structure portion 173c, subsequent via contacts for the metal gate structure may land on the second dielectric wall 161 and cause an electrical connection failure between the second metal gate structure portion 173b and the third metal gate structure portion 173c. Since the second dielectric wall 161 occupies a plurality of portions of the metal gate structure 173, the effective capacitance Ceff of the metal gate structure 173 is reduced. As a result, the gate-to-S / D (represented by the dashed line 175) parasitic capacitance (Cgd) is reduced. In some embodiments, a planarization process may be performed such that the top surface of the metal layer 169 is at a higher height than the top surface of the topmost first semiconductor layer 106. For example, a planarization process may be performed such that the distance H2 between the top surface of the metal layer 169 and the top surface of the topmost first semiconductor layer 106 is in the range of about 3 nm to about 30 nm. In some embodiments, a planarization process may be performed such that the distance H3 between the top surface of the metal layer 169 and the top surface of the second dielectric layer 161b of the second dielectric wall 161 is in the range of about 1 nm to about 50 nm. The distance H3 may be the same as or different from the distance H2. In some embodiments, the planarization process is performed until the top surface of the first dielectric layer 161a or the second dielectric layer 161b is exposed. In other words, the distance H3 is 0 nm. In this case, the transistor devices on one side of the second dielectric wall 161 are separated or isolated from the transistor devices on the opposite side of the second dielectric wall 161. In some embodiments, the second dielectric wall 161 in the first device region may have a first height, and the second dielectric wall 161 in the second device region may have a second height different from the first height, and this difference between the first height and the second height may cause the metal layer 169 to leave a different height H6 (the distance between the top surface of the metal layer 169 and the top surface of the HK dielectric layer 180 above the topmost first semiconductor layer 106) between the first device region and the second device domain. In some embodiments, the metal gate end cap space on the left side of the second dielectric wall 161 may have a distance D1, and the metal gate end cap space on the right side of the second dielectric wall 161 may have a distance D2 that is the same as or different from the distance D1. The term "metal gate end cap space" herein refers to the distance measured from the end of the first semiconductor layer 106 to the first dielectric layer 161a of the second dielectric wall 161. In various embodiments, the distances D1 and D2 may vary in the range of about 3 nm to about 30 nm. In some embodiments, the metal gate end cap space (e.g., distance D1) of the topmost first semiconductor layer 106 on the left side of the second dielectric wall 161 and the metal gate end cap space (e.g., distance D3) of the bottommost first semiconductor layer 106 are different from each other. The difference between the distances D1 and D3 may be in the range of 0 nm (meaning the second dielectric wall 161 has vertical sidewalls) to about 5 nm. In some embodiments, the metal gate end cap space (e.g., distance D2) of the topmost first semiconductor layer 106 on the right side of the second dielectric wall 161 and the metal gate end cap space (e.g., distance D4) of the bottommost first semiconductor layer 106 are different from each other. The difference between the distances D2 and D4 may be in the range of 0 nm (meaning the second dielectric wall 161 has vertical sidewalls) to about 5 nm. In some embodiments, the metal gate end cap space (e.g., distance D3) of the bottommost first semiconductor layer 106 on the left side of the second dielectric wall 161 and the metal gate end cap space (e.g., distance D4) of the bottommost first semiconductor layer 106 on the right side of the second dielectric wall 161 may be the same as or different from each other. In various embodiments, the distances D3 and D4 may vary in the range of about 3 nm to about 30 nm. In some embodiments, the second dielectric wall 161 may have a width W1a in the range of about 0.5 nm to about 48 nm. The width W1a is measured by combining the thicknesses of the first dielectric layer 161a and the second dielectric layer 161b, and may be measured at the height between the first and second topmost first semiconductor layers 106. In some embodiments where the second dielectric wall 161 has angled sidewalls (i.e., not vertical straight lines), the second dielectric wall 161 may have a width W1b in the range of about 5 nm to about 50 nm, and may be measured at the height between the second and third topmost first semiconductor layers 106. In some embodiments, the second dielectric layer 161b may have a width W2 in the range of about 2 nm to about 4.5 nm. In some embodiments, the second dielectric layer 161b of the second dielectric wall 161 may have a height H4 in the range of about 0.5 nm to about 60 nm. The second dielectric wall 161 may have a height H5 in the range of about 5 nm to about 60 nm. The height H5 is measured from the bottom of the first dielectric layer 161a to the top of the first dielectric layer 161a or the second dielectric layer 161b. The heights H4 and H5 may be different from each other. In some embodiments, the first dielectric layer 161a of the second dielectric wall 161 has a footing 171 that extends laterally from the bottom of the second dielectric wall 161. The footing 171 may have a depth D5 (FIG. 22) equal to the depth D0. The depth D5 may be in the range of about 0.1 nm to about 2.5 nm. In some embodiments, the distance D6 between the corresponding first semiconductor layers 106 on two opposite sides of the first dielectric wall 124 is equal to or greater than the width of the first dielectric wall 124. The distance D6 here refers to the distance between two adjacent active regions, that is, the distance from oxide diffusion to oxide diffusion. FIGS. 28 to 35 are cross-sectional side views of various sites for manufacturing the semiconductor device structure 200 according to some alternative embodiments. This alternative embodiment is similar to the embodiment shown in FIGS. 1 to 27, except that after forming the HK dielectric layer 180 (FIG. 18), a gate electrode layer 282 is conformally formed on the HK dielectric layer 180. The gate electrode layer 282 may include the same material as the gate electrode layer 182. The gate electrode layer 282 may be a conformal layer deposited by any suitable conformal deposition process. The gate electrode layer 282 may have a thickness in the range of about 0.5 nm to about 15 nm. Then, a capping layer 247 is formed in the trench 155 (FIG. 18). The capping layer 247 is deposited on the gate electrode layer 282 to protect the first dielectric wall 124 and the first semiconductor layers 106 on two opposite sides of the first dielectric wall 124. Then, a patterned photoresist layer (not shown) is formed on the capping layer 247. One or more etching processes are performed using the patterned photoresist layer as a mask to remove a plurality of portions of the capping layer 247 and form trenches 255. Each trench 255 is disposed between adjacent active regions and extends in a direction parallel to the longitudinal direction of the fin structure 112. Each trench 255 extends through the capping layer 247 to expose the gate electrode layer 282 above the isolation region 120. In FIG. 29, the gate electrode layer 282 exposed through the trench 255 is removed, exposing a portion of the HK dielectric layer 180 above the isolation region 120. Thereafter, the capping layer 247 is removed. The removal of the capping layer 247 exposes the trench 255. One or more etching processes may be used to remove the gate electrode layer 282 and the mask layer 247. In FIG. 30, a protection structure 249 is formed in the trench 255. Similar to the above-described protection structure 149, the protection structure 249 may include a photoresist layer 250 and a BARC layer 252. The photoresist layer 250 is patterned and used as a mask to form a trench 257 extending through the BARC layer 252. The trench 257 exposes a portion of the HK dielectric layer 180 above the isolation region 120. Similarly, the trench 257 defines the isolation region where the second dielectric wall 161 (FIG. 35) is to be formed. The isolation region may be provided between adjacent fin structures 112 where the first dielectric wall 124 does not exist. The bottom of the trench 257 may extend laterally to form a gap 259. In some embodiments, the height of the gap 259 is greater than the thickness of the gate electrode layer 282 in contact with the HK dielectric layer 180. In some embodiments, the trench 257 extends through the HK dielectric layer 180 to expose the isolation region 120. In FIG. 31, a dielectric structure 261' is formed to fill the trench 257. The dielectric structure 261' may include a first dielectric layer 261a and a second dielectric layer 261b subsequently formed on the first dielectric layer 261a. The first dielectric layer 261a and the second dielectric layer 261b may include the same materials as the first dielectric layer 161a and the second dielectric layer 161b, and may be deposited in a similar manner as discussed above with reference to FIG. 23. In FIG. 32, an etch-back process, such as the etch-back process discussed above with reference to FIG. 24, is performed to remove plural portions of the dielectric structure 261' to form the second dielectric wall 261. Similarly, an etch-back process may be performed on the dielectric structure 261' such that the top surfaces of the first dielectric layer 261a and the second dielectric layer 261b are generally coplanar or at different heights. In some embodiments, the etch-back process is performed such that the top surface of the first dielectric layer 261a or the second dielectric layer 261b is at a height lower than the top surface of the topmost first semiconductor layer 106 or generally flush with the top surface of the topmost first semiconductor layer 106. In some embodiments, the etch-back process is performed such that the top surface of the first dielectric layer 261a or the second dielectric layer 261b is at a height higher than the top surface of the topmost first semiconductor layer 106. In some alternative embodiments, an etch-back process may be performed such that one or more second dielectric walls 261 in the first device region have a first height and one or more second dielectric walls 261 in the second device region have a second height different from the first height. In FIG. 33, the protection structure 249 is removed. One or more etching processes are used to remove the protection structure 249. The one or more etching processes may be a selective etch / or time-controlled etch process that removes the protection structure 249 while generally not affecting the HK dielectric layer 180, the second dielectric wall 261, and the gate electrode layer 282. The removal of the protection structure 249 exposes the trench 257. In FIG. 34, a metal layer 269 (e.g., metal layer 169) is formed to fill the trench 257. The metal layer 269 serves as a gap-fill layer and becomes part of the gate electrode layer of the semiconductor device structure 200. A plurality of portions of the metal layer 269 are recessed, and the recessed metal layer 269 is combined with the gate electrode layer 282 to form a metal gate structure 273. The metal layer 269 and the gate electrode layer 282 may include the same or different materials and may be deposited in a manner similar to that of the gate electrode layer 282. In some embodiments, the metal layer 269 and the gate electrode layer 282 include the same material. In some embodiments, the metal layer 269 and the gate electrode layer 282 include materials with different chemical properties from each other. In FIG. 35, a planarization process is performed on the semiconductor device structure 200. The planarization process may be performed until the dielectric layer 128 of the first dielectric wall 124 is exposed. In some embodiments, the planarization process is performed to remove a plurality of portions of the metal layer 269, the HK dielectric layer 280, and the dielectric layer 128 of the first dielectric wall 124. When the planarization process is completed, the top surfaces of the metal layer 269, the HK dielectric layer 180, and the dielectric layer 128 of the first dielectric wall 124 are substantially coplanar. In some embodiments, the metal gate structure 273 may include a first metal gate structure portion 273a, a second metal gate structure portion 273b, and a third metal gate structure portion 273c. The first metal gate structure portion 273a and the second metal gate structure portion 273b are separated from each other by the first dielectric wall 124. The second metal gate structure portion 273b and the third metal gate structure portion 273c are separated from each other by the second dielectric wall 261. Each of the metal gate structure portions 273a, 273b, 273c includes a plurality of first semiconductor layers 106 vertically stacked and separated from each other above the substrate 101, an HK dielectric layer 180 covering each of the first semiconductor layers 106, and an IL 178 disposed between the HK dielectric layer 180 and the first semiconductor layer 106. Although not shown, it is expected that the various structural limitations / dimensions discussed above with respect to FIG. 27 apply to the embodiment shown in FIG. 35. Similarly, a first dielectric wall 124 is disposed above the substrate 101 and is physically connected (through a spacer 126 and a capping layer 132) to first semiconductor layers 106 disposed on opposite sides of the first dielectric wall 124. A second dielectric wall 261 is disposed above the substrate 101 and physically separates a second metal gate structure portion 273b and a third metal gate structure portion 273c from each other. A metal gate structure 273 disposed above the second dielectric wall 161 electrically connects the second metal gate structure portion 273b and the third metal gate structure portion 273c. Since the second dielectric wall 261 occupies plural portions of the metal gate structure 273, an effective capacitance Ceff of the metal gate structure 273 is reduced. As a result, a gate-to-S / D (represented by a dashed line 175) parasitic capacitance (Cgd) is reduced. FIGS. 36 to 38 show cross-sectional views of a portion of the semiconductor device structures 100 / 200 according to some embodiments. The semiconductor device structure 100 / 200 in FIG. 36 is substantially the same as the embodiments shown in FIGS. 27 and 35, except that the second dielectric wall 361 (e.g., the second dielectric walls 161, 261) is formed of a single material. That is, the first dielectric layer 161a / 261a and the second dielectric layer 161b / 261b are formed of the same material. The semiconductor device structure 100 / 200 in FIG. 37 is substantially the same as the embodiments shown in FIGS. 27 and 35, except that the second dielectric wall 461 (e.g., the second dielectric walls 161, 261) has a first dielectric layer 461a and a second dielectric layer 461b formed on the first dielectric layer 461a, and the first dielectric layer 461a does not laterally extend into the region between the gate electrode layer 169 / 269 and the HK dielectric layer 180. The semiconductor device structure 100 / 200 in FIG. 38 is substantially the same as the embodiments shown in FIGS. 27 and 35, except that the second dielectric wall 561 (e.g., the second dielectric walls 161, 261) has a first dielectric layer 561a and a second dielectric layer 561b formed on the first dielectric layer 561a, and the first dielectric layer 561a is in direct contact with the top surface of the isolation region 120. It should be understood that the semiconductor device structures 100 / 200 may undergo further complementary metal oxide semiconductor (CMOS) and / or back-end-of-line (BEOL) processes to form various features, such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc. The semiconductor device structures 100 / 200 may also include backside contacts (not shown) on the back surface of the substrate 101 such that the source or drain of the epitaxial S / D features are connected to a backside power rail (e.g., a positive voltage VDD or a negative voltage VSS) through the backside contacts. Various embodiments of the present disclosure provide semiconductor device structures having a fork-shaped dielectric wall structure and an embedded cut metal gate (CMG) isolation structure to minimize the gate-to-source / drain parasitic capacitance. The fork-shaped dielectric wall structure and the dielectric wall structure can be formed as part of a metal gate isolation process. In the fork-shaped dielectric wall structure, the metal gate structure is separated before the metal gate structure is formed. The CMG isolation structure is embedded in the gate electrode layer and thus reduces the amount of the gate electrode layer between adjacent transistors (which causes a large gate-to-S / D parasitic capacitance). As a result, the gate-to-S / D parasitic capacitance of the semiconductor device structure is reduced. One embodiment is a semiconductor device structure. The semiconductor device structure includes a dielectric wall disposed above a substrate, a first metal gate structure portion and a second metal gate structure portion individually disposed on two sides of the dielectric wall. Each of the first metal gate structure portion and the second metal gate structure portion includes a plurality of semiconductor layers vertically stacked and separated from each other, a high-k (HK) dielectric layer disposed around at least three surfaces of each of the semiconductor layers, and a gate electrode layer disposed between two adjacent ones of the semiconductor layers. The semiconductor device structure further includes a metal layer disposed above the top surface and two opposite sidewalls of the dielectric wall. In some embodiments, the top surface of the dielectric wall and the top surface of the topmost semiconductor layer of at least one of the first metal gate structure portion or the second metal gate structure portion are at substantially the same height. In some embodiments, the top surface of the dielectric wall is at a higher height than the top surface of the topmost semiconductor layer of at least one of the first metal gate structure portion or the second metal gate structure portion. In some embodiments, a first distance between an end of the topmost semiconductor layer of the first metal gate structure portion and a first side of the dielectric wall is different from a second distance between an end of the topmost semiconductor layer of the second metal gate structure portion and a second side of the dielectric wall. In some embodiments, the first distance is different from a third distance between an end of the bottommost semiconductor layer of the first metal gate structure portion and the first side of the dielectric wall. In some embodiments, the dielectric wall includes a first dielectric layer and a second dielectric layer, and the second dielectric layer has a sidewall in contact with the first dielectric layer. In some embodiments, a portion of the first dielectric layer extends laterally into the metal layer. In some embodiments, the metal layer is disposed between the gate electrode layer and the first dielectric layer and is in contact with the gate electrode layer and the first dielectric layer. In some embodiments, the metal layer and the gate electrode layer are formed of the same material. In some embodiments, the metal layer and the gate electrode layer include materials having different chemical properties from each other. Another embodiment is a semiconductor device structure. The semiconductor device structure includes a first dielectric wall disposed above a substrate, a first transistor including a plurality of first semiconductor layers vertically stacked above the substrate and disposed on a first side of the first dielectric wall, wherein a first side of each of the first semiconductor layers is connected to the first dielectric wall. The semiconductor device structure further includes a first gate electrode layer disposed between two adjacent semiconductor layers of the first semiconductor layers, and a second dielectric wall disposed adjacent to a second side of each of the first semiconductor layers and separated from the second side of each of the first semiconductor layers by the first gate electrode layer. In some embodiments, the semiconductor device structure further includes a liner, a capping layer, and a high-k dielectric. The capping layer surrounds the semiconductor layers and contacts the liner. Each of the first semiconductor layers is connected to the first dielectric wall through the capping layer and the liner. The high-k dielectric contacts the first dielectric wall, the liner, and the capping layer. In some embodiments, a top surface of the first dielectric wall and a top surface of the second dielectric wall are substantially coplanar. In some embodiments, the top surface of the second dielectric wall is at a higher height than a top surface of the topmost semiconductor layer of the first semiconductor layers. In some embodiments, the top surface of the first dielectric wall is at a higher height than the top surface of the second dielectric wall. In some embodiments, the first gate electrode layer contacts the top surface of the second dielectric wall. In some embodiments, the top surface of the second dielectric wall is at a height substantially flush with the top surface of the topmost semiconductor layer of the first semiconductor layers. Another embodiment is a method of forming a semiconductor device structure. The method of forming the semiconductor device structure includes forming a first fin structure, a second fin structure, and a third fin structure from a substrate, wherein the second fin structure is disposed between the first fin structure and the third fin structure, and each of the first fin structure, the second fin structure, and the third fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately. The method of forming the semiconductor device structure includes forming a first dielectric wall between the second fin structure and the third fin structure, and removing the second semiconductor layers from the first fin structure, the second fin structure, and the third fin structure such that the first semiconductor layers of at least one of the first fin structure and the second fin structure extend outwardly from the first side and the second side of the first dielectric wall. The method of forming the semiconductor device structure includes filling a space between two adjacent first semiconductor layers of the first fin structure, the second fin structure, and the third fin structure with a gate electrode layer, forming a second dielectric wall between the first fin structure and the second fin structure, and recessing the second dielectric wall such that a top surface of the second dielectric wall is at a height below a top surface of the first dielectric wall. The method of forming the semiconductor device structure includes forming a metal layer to cover the first dielectric wall, the second dielectric wall, and the first semiconductor layers of the first fin structure, the second fin structure, and the third fin structure. In some embodiments, the method of forming the semiconductor device structure further includes performing a planarization process such that a top surface of the first dielectric wall and a top surface of the metal layer are substantially coplanar. In some embodiments, the method of forming the semiconductor device structure further includes performing a planarization process such that a top surface of the first dielectric wall, a top surface of the second dielectric wall, and top surfaces of a plurality of topmost first semiconductor layers of the first fin structure, the second fin structure, and the third fin structure are substantially coplanar. The foregoing text outlines the features of many embodiments, enabling those of ordinary skill in the art to better understand the present disclosure from various aspects. Those of ordinary skill in the art should understand that and can easily design or modify other processes and structures based on the present disclosure and achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure. Various changes, substitutions, or modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure. 100: Semiconductor device structure 101: Substrate 104: Semiconductor layer stack 106: First semiconductor layer, semiconductor layer 108: Second semiconductor layer, semiconductor layer 110: Mask structure 110a: Oxygen-containing layer 110b: Nitrogen-containing layer A-A: Cross-section 112: Fin structure 114: Trench 116: Well portion 118: Insulating material 120: Isolation region 132: Capping layer 130: Sacrificial gate structure 134: Sacrificial gate electrode layer 136: Mask layer 136a: Oxide layer 136b: Nitride layer B-B: Cross-section 138: Gate spacer 144: Dielectric spacer 146: Epitaxial source / drain feature, source epitaxial feature, drain epitaxial feature 162: Contact etch stop layer 164: Interlayer dielectric layer 151: Isolation trench 153: Active region C-C: Cross-section D-D: Cross-section 124: First dielectric wall 126: Pad 128: Dielectric layer 155: Trench 178: Interface layer 180: High-K dielectric layer 182: Gate electrode layer 147: Hard mask layer 149: Protection structure 150: Photoresist layer 152: Bottom anti-reflective coating 157: Trench 159: Gap H1: Height D0: Depth 161’: Dielectric structure 161a: First dielectric layer 161b: Second dielectric layer 161a-1, 161a-3: First part 161a-2, 161a-4: Second part T1, T4: First thickness T2, T5: Second thickness T3, T6: Third thickness 161: Second dielectric wall 169: Metal layer 171: Footing 173: Metal gate structure 173a: First metal gate structure part 173b: Second metal gate structure part 173c: Third metal gate structure part 175: Dotted line H2, H3, H4, H5, H6: Height D1, D2, D3, D4, D6: Distance D5: Depth W1a, W1b, W2: Width 200: Semiconductor device structure 282: Gate electrode layer 247: Mask layer 255: Trench 249: Protection structure 250: Photoresist layer 252: Bottom anti-reflective coating 257: Trench 259: Gap 261’: Dielectric structure 261a: First dielectric layer 261b: Second dielectric layer 261: Second dielectric wall 269: Metal layer 273: Metal gate structure 273a: First metal gate structure part 273b: Second metal gate structure part 273c: Third metal gate structure part 361: Second dielectric wall 461: Second dielectric wall 461a: First dielectric layer 461b: Second dielectric layer 561: Second dielectric wall 561a: First dielectric layer 561b: Second dielectric layer Embodiments of the present disclosure can be understood in more detail by reading the following detailed description and examples and in conjunction with the corresponding drawings. It should be noted that, in accordance with industry standard practices, various feature components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of various feature components can be increased or decreased arbitrarily. FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23-1, 23-2, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, and 38 are perspective views of semiconductor device structures at various process stations constructed in accordance with aspects of one or more embodiments of the present disclosure. 100: Semiconductor device structure 106: First semiconductor layer, semiconductor layer 116: Well portion 120: Isolation region 132: Cover layer 124: First dielectric wall 126: Pad 128: Dielectric layer 178: Interface layer 180: High-k dielectric layer 182: Gate electrode layer 161a: First dielectric layer 161b: Second dielectric layer 161: Second dielectric wall 169: Metal layer 171: Foot 173: Metal gate structure 173a: First metal gate structure portion 173b: Second metal gate structure portion 173c: Third metal gate structure portion 175: Dotted line H2, H3, H4, H5, H6: Height D1, D2, D3, D4, D6: Distance D5: Depth W1a, W1b, W2: Width

Claims

1. A semiconductor device structure, comprising: A dielectric wall is disposed above a substrate; A first metal gate structure portion and a second metal gate structure portion are respectively disposed on both sides of the dielectric wall, wherein each of the first metal gate structure portion and the second metal gate structure portion includes: a plurality of semiconductor layers, which are stacked perpendicularly to each other and separated; a high-k dielectric layer, which is disposed around at least three surfaces of each of the semiconductor layers; a gate electrode layer, which is disposed between two adjacent semiconductor layers; and a metal layer, which is disposed on two opposite sidewalls of the dielectric wall.

2. The semiconductor device structure as claimed in claim 1, wherein a top surface of the dielectric wall and a top surface of a top semiconductor layer of at least one of the first metal gate structure portion or the second metal gate structure portion are at approximately the same height.

3. The semiconductor device structure as claimed in claim 1, wherein a top surface of the dielectric wall is at a height higher than a top surface of a top semiconductor layer of at least one of the first metal gate structure portion or the second metal gate structure portion.

4. The semiconductor device structure as claimed in claim 1, wherein a first distance between an end of a topmost semiconductor layer of the first metal gate structure portion and a first side of the dielectric wall is different from a second distance between an end of a topmost semiconductor layer of the second metal gate structure portion and a second side of the dielectric wall.

5. The semiconductor device structure as claimed in claim 4, wherein the first distance is different from a third distance between an end of a bottom semiconductor layer of the first metal gate structure portion and the first side of the dielectric wall.

6. The semiconductor device structure as claimed in claim 1, wherein the dielectric wall comprises a first dielectric layer and a second dielectric layer, and the second dielectric layer has a sidewall in contact with the first dielectric layer.

7. A semiconductor device structure, comprising: A first dielectric wall is disposed above a substrate; A first transistor includes a plurality of first semiconductor layers vertically stacked above the substrate and disposed on a first side of the first dielectric wall, wherein a first side of each of the first semiconductor layers is connected to the first dielectric wall; a first gate electrode layer disposed between two adjacent semiconductor layers of the first semiconductor layer; and a second dielectric wall disposed adjacent to a second side of each of the first semiconductor layers and separated from the second side of each of the first semiconductor layers, wherein a top surface of the first dielectric wall is higher than a top surface of the second dielectric wall.

8. The semiconductor device structure as described in claim 7, further comprising: A padding; A capping layer surrounds the semiconductor layers and contacts the pad, wherein each of the first semiconductor layers is connected to the first dielectric wall through the capping layer and the pad; and a high-k dielectric material contacts the first dielectric wall, the pad, and the capping layer.

9. The semiconductor device structure as claimed in claim 7, wherein the first gate electrode layer is in contact with a top surface of the second dielectric wall.

10. A method for forming a semiconductor device structure, comprising: A first fin structure, a second fin structure, and a third fin structure are formed from a substrate, wherein the second fin structure is disposed between the first fin structure and the third fin structure, and each of the first fin structure, the second fin structure, and the third fin structure includes alternately stacked plurality of first semiconductor layers and plurality of second semiconductor layers; a first dielectric wall is formed between the second fin structure and the third fin structure; a second semiconductor layer is removed from the first fin structure, the second fin structure, and the third fin structure, such that the first semiconductor layer of at least one of the first fin structure and the second fin structure extends epitaxially from a first side and a second side of the first dielectric wall; a gate electrode layer is filled in a space between two adjacent first semiconductor layers of the first fin structure, the second fin structure, and the third fin structure; a second dielectric wall is formed between the first fin structure and the second fin structure. The second dielectric wall is recessed such that a top surface of the second dielectric wall is at a height below a top surface of the first dielectric wall; and a metal layer is formed to cover the first semiconductor layer of the first dielectric wall, the second dielectric wall, the first fin structure, the second fin structure, and the third fin structure.

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