Semiconductor structure and methods of making same

Abstract

A method of manufacturing a semiconductor structure includes providing a workpiece. The workpiece includes a substrate, fins projecting from the substrate, and a dummy gate structure above the fins. The method further includes performing an oxidation process on exposed surfaces of the fins and the dummy gate structure to form an oxide layer above the exposed surfaces of the fins and the dummy gate structure; removing the oxide layer to expose an unoxidized top surface of the fins and a plurality of unoxidized sidewalls, and a plurality of unoxidized sidewalls of the dummy gate; epitaxially growing a capping layer on the unoxidized top surface of the fins and the unoxidized sidewalls of the fins and the unoxidized sidewalls of the dummy gate; forming source / drain features on the fins; and replacing the dummy gate structure with a metal gate structure.

Description

Fin step structure and manufacturing method thereof none The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have led to numerous generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC development, functional density (the number of interconnected devices per chip area) has generally increased, while geometry size (the smallest component (or circuit) that can be created using a manufacturing process) has decreased. This reduction in size has also increased the complexity of IC processing and manufacturing. As IC device geometries decrease, in some IC designs, such as field-effect transistor (FET) designs, the gate formation process with decreasing gate critical dimensions (CDs) and gate pitch may introduce footing profiles, voids in the polysilicon gate, and excessive fin top loss. These can cause defects in the IC device and potentially affect the overall performance of the IC device. While existing IC design and manufacturing methods are generally adequate for their intended purposes, they are not always satisfactory. none It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, dictate the relationship between the various embodiments and / or configurations discussed. In addition, the various features may be arbitrarily drawn at different scales for simplicity and clarity. In addition, for ease of description, the present disclosure may use spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., to describe the relationship of an element or feature to one or more other elements or features, as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the accompanying drawings. For example, if the device in the figure is turned over, elements described as being "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Furthermore, when terms such as "approximately" or "about" are used to describe a number or range of numbers, such terms are intended to encompass the inherent variations that occur during the manufacturing process within a reasonable range as understood by those of ordinary skill in the art. A number or range of numbers encompasses a reasonable range encompassing the described number, for example, based on known manufacturing tolerances associated with manufacturing features having the properties associated with the number, such as within + / –10% of the described number. For example, a material layer having a thickness of "approximately 5 nanometers (nm)" may encompass a range of dimensions between 4.25 nm and 5.75 nm, where manufacturing tolerances associated with depositing material layers are known to those of ordinary skill in the art to be + / –15%. Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations discussed. As integrated circuit (IC) technology progresses to smaller technology nodes, multi-gate devices are being introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short channel effects (SCE). A multi-gate device generally refers to a device with a metal gate structure, or portion thereof, disposed on more than one side of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. FinFETs feature an elevated channel surrounded by gates on multiple sides (e.g., the gates surround the top and sidewalls of a "fin" of semiconductor material extending from the substrate). MBC transistors feature a metal gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of an MBC transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region has also given MBC transistors alternative names, such as nanosheet transistors or nanowire transistors. Variants of MBC transistors have been proposed to reduce cell size, such as fishbone or fork-sheet structures. In a fork-sheet structure, adjacent stacks of channel elements can be separated by dielectric walls (also called dielectric fins). The height of the dielectric walls is typically substantially equal to or greater than the height of the topmost channel element or source / drain features. Complementary metal-oxide-semiconductor field-effect transistors (CMOS FETs) dominate the semiconductor industry due to their high noise immunity and low static power consumption. CMOS FETs consist of an n-type field-effect transistor (NFET) and a p-type field-effect transistor (PFET) arranged side by side on the same substrate, and the NFET and PFET share the same structure. In some embodiments, both the NFET and the PFET are planar devices, both are FinFETs, or both are MBC transistors. A semiconductor structure may have a dummy gate formed above a fin structure. The dummy gate may be a polysilicon gate structure that will be replaced by a gate stack (e.g., a high-k metal gate stack) during a gate-last process. The dummy gate may be formed through various process steps, such as layer deposition, patterning, etching, and other suitable process steps. During the formation of the dummy gate, the top portion of the fin structure not covered by the dummy gate may be etched, resulting in loss of the top portion of the fin, which can affect the overall performance of the semiconductor device and reduce device yield. Furthermore, the dummy gate at the bottom where it intersects the fin structure may have a footing portion, also known as corner residue. Corner residue refers to residue (or byproduct) left at the corner where the dummy gate structure, the fin structure, and the top surface of the substrate (which may include isolation features, as explained in further detail below) intersect. Residue accumulation in the corner results in uneven gate length along the height of the dummy gate structure. When a metal gate replaces the dummy gate during the gate-last process, the metal gate inherits this gate length nonuniformity and exhibits protruding profiles (i.e., greater gate length) at the corners, known as "protruding corners." This nonuniformity can affect many device operating parameters, such as speed performance and power consumption. There are also concerns that the increased protrusions could lead to electrical shorts between the gate stack formed after the dummy gate and the source / drain features. This could also cause device shorts due to metal material leakage from the protruding corners during the gate-last process, also known as "metal gate protrusion." Furthermore, layer deposition may form voids in the dummy gate. When gate spacers are formed on the sidewalls of the dummy gate, the gate spacers may form within the voids. Subsequently, when the dummy gate is replaced by the gate stack, the gate spacers within the voids are retained, leading to defects in the gate stack. The present disclosure generally relates to semiconductor structures and methods of manufacturing. More specifically, the present disclosure relates to a semiconductor structure including a fin, a gate structure on the fin, and a gate spacer on a sidewall of the gate structure. The height and width of a portion of the fin directly below the gate spacer are greater than the height and width of the fin directly below the gate structure. The method of manufacturing the semiconductor structure includes oxidizing a surface of a dummy gate structure and an exposed surface of the fin to form an oxide layer, removing the oxide layer and epitaxially growing a cap layer. The base portion of the dummy gate structure can be oxidized to form a portion of the oxide layer and then removed. The cap layer can enlarge the fin not covered by the dummy gate structure and reduce the size of any gaps in the dummy gate structure. Various aspects of the present disclosure will now be described in greater detail with reference to the accompanying drawings. In this regard, FIG. 1 illustrates a flow chart of a method 10 for forming a semiconductor structure according to an embodiment of the present disclosure. Method 10 is described below in conjunction with FIG. 2-10F, which illustrate partial perspective, top, and cross-sectional views of a workpiece 100 at various stages of fabrication according to an embodiment of method 10. Method 10 is merely an example and is not intended to limit the present disclosure to the content explicitly described therein. Additional steps may be provided before, during, and after method 10, and additional embodiments of the method may replace, eliminate, or move some of the steps described. For simplicity, not all steps are described in detail herein. Because workpiece 100 will be a semiconductor structure at the end of the fabrication process, workpiece 100 may be referred to as semiconductor structure 100, as the context dictates. For the avoidance of doubt, the X, Y, and Z directions in FIG. 2-10F are perpendicular to one another and are used consistently throughout this disclosure. Unless otherwise noted, similar reference numerals denote similar features throughout this disclosure. Referring to Figures 1, 2, and 3A-3B, method 10 includes step 12 of providing a workpiece 100. Figures 2 and 3A illustrate partial perspective and partial top views, respectively, of workpiece 100 undergoing various stages of operation in method 10 of Figure 1, according to various aspects of the present disclosure. Figures 3B-3E illustrate partial cross-sectional views of workpiece 100 taken along lines BB, CC, DD, and EE, respectively, as shown in Figure 3A. The workpiece 100 may be an intermediate device in the process of manufacturing an integrated circuit (IC), and may include static random access memory (SRAM) and / or logic circuits, passive components such as resistors, capacitors, and inductors, active components such as p-type field effect transistors (pFETs), n-type FETs, finFETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductors (CMOS), transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof. Furthermore, for simplicity and ease of understanding, various features including transistors, gate stacks, active regions, isolation structures, and other features are provided in various embodiments of the present disclosure, and the embodiments are not necessarily limited to any type of device, any number of devices, any number of regions, or any configuration of structures or regions. As shown in Figures 2-3E, workpiece 100 includes substrate 102. In the illustrated embodiment, substrate 102 is a silicon substrate. Alternatively, substrate 102 may include another elementary semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor, including silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, or a combination thereof. In another embodiment, substrate 102 includes indium tin oxide (ITO) glass. In various embodiments, substrate 102 is a wafer, such as a silicon wafer, and may include one or more epitaxially grown semiconductor layers thereon. In some embodiments, the workpiece 100 includes multiple active regions 104 (e.g., fin-shaped active regions, also referred to as fins 104). Fins 104a and 104b shown in Figures 2 and 3A may be individually or collectively referred to as fins 104. As shown in Figure 2, each fin 104 extends longitudinally along the X-direction. Fins 104 and fins 104b have widths Wa and Wb, respectively, along the Y-direction. The number of fins 104 and the number of dummy gate structures 130 shown in Figures 2 and 3A are for illustrative purposes only and should not be construed as limiting the scope of the present disclosure. In the depicted embodiment, the fins 104 are disposed above the substrate 102. In embodiments where the workpiece 100 includes a FinFET, the fins 104 may be formed from a single semiconductor element (e.g., Si). In embodiments where the workpiece 100 includes an MBC transistor, the fins 104 may include one or more nanostructures (e.g., multiple channel layers). Each nanostructure may be formed from silicon (Si). In this embodiment, the workpiece 100 further includes an isolation feature 106 formed around each fin 104 to isolate two adjacent fins 104. The isolation feature 106 may also be referred to as a shallow trench isolation (STI) feature and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In some embodiments, as shown in FIG. 2 , the workpiece 100 further includes a fin oxide layer 108 on the surface of the fin 104. In the illustrated embodiment, the fin oxide layer 108 is formed as a blanket layer over the top and sidewall surfaces of the fin 104, but not over the top surface of the isolation structure 106. In alternative embodiments, the fin oxide layer 108 is formed over the top and sidewall surfaces of the fin 104 and the top surface of the isolation structure 106. The fin oxide layer 108 can be formed before forming the dummy gate structure 130 and provides protection for the fin 104. The fin oxide layer 108 can be formed by various methods, such as chemical oxidation of silicon, thermal oxidation of silicon, ozone oxidation of silicon, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods. The fin oxide layer 108 may include silicon oxide or a high-k oxide (having a dielectric constant greater than that of silicon oxide), such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, or a combination thereof. The fin oxide layer 108 may be formed to have a thickness ranging from a few angstroms to tens of angstroms. For simplicity, the fin oxide layer 108 is not explicitly shown in FIG. 3A ; however, its thickness along the Y direction is reflected in the portion of the fin 104 that does not overlap the gate hard mask layer 132 (i.e., is not directly below the gate hard mask layer 132 (described below)). In other words, the portion of the fin 104 that does not overlap the gate hard mask layer 132 reflects a width along the Y direction, which includes the width of the fin 104 (e.g., Wa, Wb) and twice the thickness of the fin oxide layer 108; the portion of the fin 104 that overlaps the gate hard mask layer 132 (i.e., directly below the gate hard mask layer 132) reflects the width of the fin 104 along the Y direction (e.g., Wa, Wb). In some embodiments, the workpiece 100 further includes a dielectric fin 105 (also referred to as a dummy gate 105 ) above the isolation structure 106 . The dielectric fin 105 may be part of a hybrid fin. Forming the dielectric fin 105 may include depositing a dielectric layer above the isolation structure 106 , patterning the dielectric layer, and planarizing the top surface of the dielectric layer. The dielectric fin 105 may include any suitable dielectric material and may define a space for forming source / drain epitaxial features to prevent undesirable merging of adjacent source / drain epitaxial features. In some embodiments, the workpiece 100 further includes a dummy gate structure 130 located above the fin 104 and the fin oxide layer 108. The dummy gate structure 130 may be located on the top surface and sidewalls of the fin oxide layer 108. The dummy gate structure 130 may span one or more fins 104, isolation structures 106, and / or dielectric fins 105. The length of the dummy gate structure 130 is perpendicular to the length of the fin 104. In some examples, forming the dummy gate structure 130 includes depositing a dummy gate layer comprising polysilicon or other suitable material, and patterning the dummy gate layer through a photolithography process and etching. A gate hard mask layer 132 may be formed on the dummy gate material layer and serve as an etch mask during the formation of the dummy gate structure 130. The gate hard mask layer 132 may include any suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, other suitable materials, and / or combinations thereof. In one embodiment, the gate hard mask layer 132 comprises a multilayer film, such as silicon oxide and silicon nitride. In some embodiments, the patterning process for forming the dummy gate structure 130 includes forming a patterned photoresist layer via a photolithography process; etching the hard mask layer using the patterned photoresist layer as an etch mask; and etching the dummy gate layer using the patterned hard mask layer (i.e., the gate hard mask layer 132) as an etch mask to form the dummy gate structure 130. Due to process reasons such as etching effects during the formation of the dummy gate structure 130, the bottom portion of the dummy gate structure 130 where it intersects the fin 104 may be wider than other portions away from the fin. The widening of the bottom portion of the dummy gate structure 130 where it intersects the fin 104 is called the "footing effect," and the widened portion is called the footing region (or portion) 120. In the Z direction, the dummy gate structure 130 may include an upper portion having straight and vertical sidewalls, and a lower portion having inclined sidewalls. The inclined sidewalls may also be straight, or may be substantially straight but with a slight curvature. The dummy gate structure 130 includes exposed sidewalls S1. Due to process factors, such as etching effects during the formation of the dummy gate structure 130, the tops of some areas of the fin 104 and the fin oxide layer 108 above the fin may be removed. The area of ​​the fin 104 with this fin top loss is also referred to as the fin top loss region (FTL region), and the area of ​​the fin 104 without fin top loss is referred to as the non-FTL region. This fin top loss reduces the effective channel area and reduces the current flowing therein. In the embodiment shown in Figures 3B and 3E, the FTL region includes the portion of the fin 104a between two adjacent dummy gate structures 130, and the non-FTL region includes the fin 104b and the rest of the fin 104a. The top portion of the FTL region and the fin oxide layer 108 above it are removed (e.g., during the formation of the dummy gate structure 130), thereby forming an opening 112 (also referred to as a recess 112). The top portion of the non-FTL region is still protected by the fin oxide layer 108 and / or the dummy gate structure 130 thereon, and the top surface of the non-FTL region has a similar height. Therefore, the top surface S2 of the fin 104 a (e.g., the FTL region) is exposed to the opening 112 and is lower than the top surface of the non-FTL region. In some embodiments, the dummy gate structure 130 includes a void 131 adjacent to a sidewall of the dummy gate structure. The void 131 includes a surface S3 that intersects the sidewall S1. Surface S3 can include one or more surfaces having any shape; for example, surface S3 can be curved or include multiple facets. In some embodiments, as shown in FIG. 3C , the void 131 does not pass through the dummy gate structure 130. In some other embodiments, the void 131 horizontally spans the dummy gate structure 130. In the cross-sectional view of FIG. 3D , the void 131 has a maximum width W along the Y direction. The void 131 can be disposed between the dielectric fin 105 and the fin 104. The void 131 can be formed during the formation of the dummy gate structure 130 (e.g., during deposition of the dummy gate layer). 1 and 4A-4E , method 10 includes step 14, wherein the exposed surfaces of fin 104 and dummy gate structure 130 are oxidized to form oxide layer 10. FIG4A illustrates a partial top view of workpiece 100, and FIG4B-4E illustrate partial cross-sectional views of workpiece 100 taken along lines BB, CC, DD, and EE shown in FIG4A . In some embodiments, the oxide layer 110 is formed by performing an oxidizing process (or oxidation process) on the workpiece 100. In some embodiments, the exposed surfaces of the fin 104 and the dummy gate structure 130 include the sidewall S1 of the dummy gate structure 130, the top surface S2 of the fin 104a exposed to the opening 112, the surface S3 of the void 131, or any combination thereof. In some embodiments, the footing portion 120 is also oxidized to form a portion of the oxide layer 110 (also referred to as the oxidized footing portion 120'). Any suitable method can be used to form the oxide layer 110. In some embodiments, the oxidation process includes a rapid thermal oxidation (RTO) process, a high pressure oxidation (HPO) process, a chemical oxidation process, an in-situ stream generation (ISSG) process, or an enhanced in-situ stream generation (EISSG) process. In some embodiments, oxygen (O) is used. 2) and ozone (O 3) performing an RTO process at a temperature of about 400°C to about 700°C for about 1 second to about 30 seconds. In other embodiments, O 2. O 2 with nitrogen (N 2) or N 2 process gases are used to perform HPO at a pressure of about 1 atm to about 25 atm and a temperature of about 300° C. to about 700° C. for about 1 minute to about 10 minutes. Examples of chemical oxidation processes include wet SPM (sulfuric acid (H 2SO 4) and / or hydrogen peroxide (H 2O 2) Cleaning, wet O 3 / H 2O, etc. In some embodiments, ozone-deionized water (DIO3) may be applied to the workpiece 100. The DIO3 may have an ozone concentration of 1 ppm to about 100 ppm, or about 30 ppm to about 50 ppm. Thereafter, an oxidation annealing may be performed on the workpiece 100 (i.e., in a process chamber containing an oxygen-containing gas). The oxidation process results in an oxide layer having a predetermined thickness. The thickness of the oxide layer 110 may be in a range of about 0.1 nm to about 5 nm, or in a range of about 1 nm to about 3 nm. The oxide layer 110 formed on different exposed surfaces may have different thicknesses. In the embodiment shown in FIG. 4C , the void 131 may have relatively small dimensions, and the oxide layer 110 formed up to the surface S3 of the void 131 may have a thickness T3 along the Y direction, while the oxide layer 110 formed up to the sidewall S1 of the dummy gate structure 130 may have a thickness T1 along the X direction, with thickness T3 being less than thickness T1. In some embodiments, the oxide layer 110 may not be formed on all exposed surfaces of the fin 104 and the dummy gate structure 130. For example, when the DIO3 solution is applied, the DIO3 may not contact all surfaces S3 of the void 131, so only a portion of the surface S3 of the void 131 is oxidized or not oxidized. In some embodiments, the oxide layer 110 formed to the surface S2 of the fin 104a has a thickness T2 along the Z direction. T2 may be similar to T1. T2 and T1 may be in the range of approximately 0.3 nm to approximately 5 nm. If T1 and T2 are too small, the footing portion 120 may not be fully oxidized. If T1 and T2 are too large, too much of the dummy gate structure 130 and / or the top of the fin 104a exposed in the opening 112 may be oxidized, which increases the difficulty of the subsequent step of removing the oxide layer 110 (to be described below) and may cause defects in the dummy gate structure 130 and / or the fin 104a; in addition, too many epitaxial layers will have to be grown in the subsequent steps (to be described below), resulting in unnecessary material and time costs. 1 and 5A-5E, method 10 includes step 16 of removing oxide layer 110. FIG5A shows a partial top view of workpiece 100, and FIG5B-5E show partial cross-sectional views of workpiece 100 taken along lines BB, CC, DD, and EE shown in FIG5A. In some embodiments, this step also removes the exposed portions of the fin oxide layer 108 that are not covered by the dummy gate structure 130 (i.e., not directly below the dummy gate structure 130). After removing the exposed portions of the oxide layer 110 and the fin oxide layer 108, the unoxidized surfaces of the fin 104 and the dummy gate structure 130 are exposed. The unoxidized surfaces may include the unoxidized sidewalls S1' of the dummy gate structure 130, the unoxidized top surface S2' of the FTL region of the fin 104a, the unoxidized top surface S5' of the non-FTL regions of the fins 104a and 104b, the unoxidized surface S3' of the void 131, or any combination thereof. In some embodiments, the oxidized footing portion 120' is removed in this step. S5' may be higher than S2'. The exposed portions of oxide layer 110 and fin oxide layer 108 can be removed using any suitable method. In one example, the removal process (step 16) can be performed using a wet etch process. In some embodiments, the removal process can be performed using a cycle of a high temperature sulfuric peroxide mixture (HTSPM) and dilute hydrofluoric acid (dHF), ozone (O3) and dHF, or a combination thereof. Referring to FIG. 1 and FIGS. 6A-6E , method 10 includes step 18 , wherein an epitaxial layer 115 (also referred to as a cap layer 115 ) is grown on the unoxidized surfaces of the fin 104 and the dummy gate structure 130 . FIG. 6A illustrates a partial top view of the workpiece 100 , while FIGS. 6B-6E illustrate partial cross-sectional views of the workpiece 100 taken along lines BB, CC, DD, and EE shown in FIG. 6A . In some embodiments, the epitaxial layer 115 is grown directly from the unoxidized surfaces of the fin 104 and the dummy gate structure 130. In some embodiments, the epitaxial layer 115 is not grown directly from the unoxidized surfaces of the fin 104 and the dummy gate structure 130. In these embodiments, a seed layer (not shown) can be formed on the unoxidized surfaces of the fin 104 and the dummy gate structure 130, and then the epitaxial layer 115 is formed on the seed layer. In some embodiments, the epitaxial layer 115 includes silicon, carbon, germanium, or a combination thereof. In some embodiments, the epitaxial layer 115 includes silicon. In some embodiments, the epitaxial layer 115 includes a different composition than the fin 104. In the described embodiment, the epitaxial layer 115 includes the same composition as the fin 104 and is separated by the dotted fin 104. For illustration purposes, the following describes an example where the epitaxial layer 115 is formed of silicon. Using a material such as silane (SiH 4) Silicon tetrachloride (SiCl 4) trichlorosilane (TCS) or dichlorosilane (SiH 2Cl 2or DSC) source gas to epitaxially grow the epitaxial layer 115. Hydrogen (H 2) as a reaction gas for reducing the above-mentioned source gas. Depending on the gas used, the deposition temperature during the formation of the epitaxial layer 115 can be in the range of about 700°C to about 1250°C. For example, with a source gas having more chlorine atoms (such as SiCl 4 or TCS), a source gas with fewer chlorine atoms (e.g., DSC) can be used at a lower formation temperature. The aforementioned gas ranges and types are provided as examples and are not limiting. In an embodiment, the growth rates of the epitaxial layer 115 on the unoxidized surfaces of the fin 104 and the dummy gate structure 130 may be different, which may result in different thicknesses of the epitaxial layer 115 on the unoxidized surfaces of the fin 104 and the dummy gate structure 130. Forming the epitaxial layer 115 may be a time-controlled process such that the final thickness of the epitaxial layer 115 is achieved at the end of the process. The fin 104 and the epitaxial layer 115 above the fin 104 together form a new fin including the fin 104a' and the fin 104b', and may be individually or collectively referred to as the fin 104'. Therefore, along the Y direction, the top of the fin 104' above the top surface of the isolation feature 106 is wider than the bottom of the fin 104' below the top surface of the isolation feature 106. In some embodiments, the thickness of the epitaxial layer 115 is in the range of about 0.1 nm to about 5 nm. If the thickness is too small, the fin top loss may not be recovered, so that the gap may be too large, affecting the overall performance of the semiconductor structure, and / or the width of the dummy gate 130 along the X direction may be too narrow, thereby being more susceptible to collapse in subsequent steps. If the thickness is too large, adjacent fins 104' may be too close to each other, and / or adjacent dummy gate structures 130 may be too close to each other. In some embodiments, the epitaxial layer 115 on different unoxidized surfaces is different. This may be due to the different shapes, materials, and orientations of the different unoxidized surfaces, as well as the operating conditions of the epitaxial growth process (such as the seed material, etc.). In some embodiments, the epitaxial layer 115 has a thickness T1' on the unoxidized sidewall S1' of the dummy gate structure 130, a thickness T2' on the unoxidized top surface S2' of the FTL region, a thickness T5' on the unoxidized top surface S5' of the non-FTL region, a thickness T3' on the unoxidized surface S3' of the void 131, and a thickness T4' on the unoxidized sidewall S4' of the fin 104. In some embodiments, T2' is equal to or greater than T5'. In some embodiments, T2' and T5' are each equal to or greater than T1' and T2', and T5' is each equal to or greater than T4'. In some embodiments, T3' is equal to or greater than T1' and / or T4'. In some embodiments, T1' is approximately the same as the thickness T1 of the oxide layer 110 formed up to the sidewall S1 of the dummy gate structure 130. In some embodiments, T2' is greater than the thickness T2 of the oxide layer 110 formed up to the top surface S2 of the fin 104a. Therefore, in the cross-sectional view of FIG6E , the lowest top surface of the fin 104a' exposed to the opening 112 is higher than the lowest top surface of the fin 104a exposed to the opening 112. In other words, the fin top loss of the FTL region of the fin 104a is restored, and the top surface of the FTL region is elevated in the Z direction by approximately (T2'-T2). A portion of the top surface S2'' of the epitaxial layer 115 in the FTL region may be lower than a portion of the top surface S5'' of the epitaxial layer 115 in the non-FTL region, and may be higher than the unoxidized top surface S5' of the non-FTL region of the fin 104 before the epitaxial layer 115 is formed. In some embodiments, T3' is greater than the thickness T3 of the oxide layer 110 formed up to the surface S3 of the void 131. Therefore, in the cross-sectional view of FIG6D , the void 131 has a maximum width W' along the Y direction, which is smaller than the maximum width W before the oxidation process shown in FIG3D . In other words, the size of the void 131 is reduced by approximately (W - W'). In embodiments where the epitaxial layer 115 completely fills the void 131, W' is equal to 0. In the FTL region and between two adjacent epitaxial layers 115 on two opposing unoxidized sidewalls S1' of the dummy gate structure 130, the widths of the fins 104a' and 104b' along the Y direction are (Wa + 2*T4') and (Wb + 2*T4'), respectively. Note that the portion of the fin 104 directly beneath the dummy gate structure 130 can maintain the same widths Wa and Wb along the Y direction during the fabrication process. Referring to FIG6A , from a top view, each fin 104' does not have a constant width, but rather has junctions with varying widths, a feature known as a fin jog structure. The fin step structure includes two wider portions and a narrower portion extending between the two wider portions. The two wider portions each have a width of (Wa+2*T4') or (Wb+2*T4') along the Y direction. The two wider portions are not directly beneath the gate hard mask layer 132. In some embodiments, the narrower portion is beneath the gate hard mask layer 132 and has a width of Wa or Wb along the Y direction. In subsequent processes, after gate replacement (e.g., step 26), the narrower portion will be directly beneath the metal gate structure (described later). After step 18, the top portion of the fin 104' above the top surface of the isolation feature 106 and not directly below the dummy gate structure 130 is expanded in the Z and Y directions. The bottom portion of the fin 104' below the top surface of the isolation feature 106 maintains the size of the fin 104. In the expanded portion, the current driving capability of the fin 104' during operation of the semiconductor structure 100 can be increased. 1 , the method 10 further includes step 18, wherein an annealing process is performed on the workpiece 100. The annealing process may include rapid thermal annealing (RTA), millisecond annealing (MSA), microsecond annealing (µSA), microwave annealing, laser annealing, spike annealing, immersion annealing, furnace annealing, other suitable annealing processes, or combinations thereof. 1 and 7A-7E , method 10 includes step 22 of forming gate spacers 125 on epitaxial layer 115 on unoxidized sidewalls S1′ of dummy gate structure 130. FIG7A illustrates a partial top view of workpiece 100, and FIG7B-7E illustrate partial cross-sectional views of workpiece 100 taken along lines BB, CC, DD, and EE shown in FIG7A . The gate spacer 125 can have a thickness of from about 2 nm to about 10 nm. In some embodiments where the epitaxial layer 115 does not completely fill the gap 131, the gate spacer 125 fills the remaining gap 131, as shown in Figures 7C and 7D, thereby forming a bump 126 of the gate spacer 125. In some examples, the gate spacer 125 can include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-k material, and / or combinations thereof. In some embodiments, the gate spacer 125 includes multiple layers, such as a liner spacer layer and a main spacer layer. For example, the gate spacers 125 can be formed by conformally depositing a dielectric material over the workpiece 100 using a process such as a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. After conformally depositing the dielectric material, a portion of the dielectric material used to form the gate spacers 125 can be etched back to expose a portion of the fin 104 ′ (e.g., in the source / drain region 104sd, as described below). In some cases, the etch-back process removes a portion of the dielectric material forming the gate spacers 125 along the top surface of the dummy gate structure 130, thereby exposing the gate hard mask layer 132. In some embodiments, the etch-back process can include a wet etch process, a dry etch process, a multi-step etch process, and / or a combination thereof. It is noteworthy that after the etch-back process, the gate spacer 125 is still disposed on the epitaxial layer 115 located on the unoxidized sidewall S1' of the dummy gate structure 130. The width and height of the fin 104' directly below the gate spacer 125 can be respectively greater than the width and height of the fin 104' directly below the dummy gate structure 130. In some embodiments, on both sides of the dummy gate structure 130, the top surface S5'' of the epitaxial layer 115 is higher than a portion of the top surface S2'' of the epitaxial layer 115. Therefore, the gate spacers 125 located on both sides of the dummy gate structure 130 and connecting the top surface S5'' and the portion of the top surface S2'' have different heights. The region of the fin 104' directly below the gate hard mask layer 132 and the gate spacer 125 can be referred to as the channel region 104c. The region of the fin 104' that is not directly beneath the gate hard mask layer 132 or the gate spacer 125 can be referred to as the source / drain region 104sd. Depending on the context, the source / drain region 104sd can be referred to individually or collectively as the source region or the drain region. The FTL region can be wider than the source / drain region 104sd along the X direction, as shown in FIG7B . 1 and 8A-8E , method 10 includes step 24 in which source / drain features 135 are formed in source / drain regions 104sd of fins 104 ′. FIG. 8A illustrates a partial top view of workpiece 100 , while FIG. 8B-8E illustrate partial cross-sectional views of workpiece 100 taken along lines BB, CC, DD, and EE shown in FIG. 8A . The source / drain features 135 can be formed using any suitable technique, such as an etching process followed by one or more epitaxial growth processes. In one example, one or more etching processes are performed to remove a portion of the fin 104', thereby forming a recess in the source / drain region 104sd. The recess can be cleaned using hydrofluoric acid (HF) or another suitable, easily performed cleaning process. Subsequently, one or more epitaxial growth processes are performed to grow epitaxial source / drain features in the recess. The top surface of the source / drain features 135 can be higher than the top surface of the fin 104'. The source / drain features 135 can be grown from the top surface and sidewalls of the fin 104' exposed in the recess. Because the width and height of the fin 104' directly below the gate spacer (i.e., the portion of the fin 104' laterally exposed in the recess) in step 18 of the fin 104 increases, the area of ​​the exposed surface of the fin 104' (also referred to as the exposed fin area) where the source / drain features 135 are grown increases. In the depicted embodiment, the recess extends into the bottom portion of the fin 104' below the top surface of the isolation feature 106. In some other embodiments, the bottom surface of the recess is above the top surface of the isolation feature 106. Because the top of the fin 104' is wider than the bottom of the fin 104' in the Y direction, the recess can have a larger surface area. Each source / drain feature 135 can be suitable for forming a p-type FinFET device or an n-type FinFET device. The p-type source / drain features can include one or more epitaxial layers of silicon germanium (epi SiGe) doped with a p-type dopant, such as boron, germanium, indium, and / or other p-type dopants. The n-type source / drain features can include one or more epitaxial layers of silicon (epi Si) or silicon carbon (epi SiC) doped with an n-type dopant, such as arsenic, phosphorus, and / or other n-type dopants. In some embodiments, as shown in Figures 8B, 8C, and 8E, a contact etch stop layer (CESL) 145 and an interlayer dielectric (ILD) layer 140 are formed over the workpiece 100. The CESL 145 can be formed of silicon nitride, silicon carbonitride, or the like. For example, the CESL 145 can be formed using a conformal deposition method such as ALD or CVD. The ILD layer 140 can include a dielectric material, which can be formed using, for example, FCVD, spin coating, CVD, or other deposition methods. The ILD layer 140 may also be formed from an oxygen-containing dielectric material, such as a silicon oxide-based material, such as tetraethyl orthosilicate (TEOS) oxide, plasma-enhanced CVD (PECVD) oxide (SiO2), phospho-silicate glass (PSG), boro-silicate glass (BSG), or boron-doped phospho-silicate glass (BPSG). A planarization step, such as chemical mechanical polishing (CMP) or mechanical grinding, is performed to level the top surfaces of the CESL 145, ILD layer 140, dummy gate structure 130, and gate spacer 125. In some embodiments, the planarization step may remove the gate hard mask layer 132. 1 and 9A-10F , the method 10 includes step 26 , wherein the metal gate structure 155 replaces the dummy gate structure 130 , the epitaxial layer 115 on the unoxidized sidewall S1 ′ of the dummy gate structure 130 , and the fin oxide layer 108 . 9A-9E , the dummy gate structure 130, the epitaxial layer 115 on the unoxidized sidewalls S1′ of the dummy gate structure 130, and the fin oxide layer 108 are removed to form a gate trench 150. The resulting structure is shown in FIG9A-9E . FIG9A shows a partial top view of the workpiece 100, and FIG9B-9E show partial cross-sectional views of the workpiece 100 taken along lines BB, CC, DD, and EE shown in FIG9A . In some embodiments, the top surface and sidewalls of the fin 104' in the channel region 104c, the top surface and sidewalls of the dielectric fin 105, and the sidewalls of the gate spacer 125 including the bump 126 are exposed in the gate trench 150. In the illustrated embodiment, the dummy gate structure 130 and the epitaxial layer 115 on the unoxidized sidewalls S1' of the dummy gate structure 130 are completely removed. In some other embodiments, a portion of the dummy gate structure 130 and / or the epitaxial layer 115 on the unoxidized sidewalls S1' of the dummy gate structure 130 directly below the bump 126 remains. However, because the size of the gap 131 has been reduced in this method, the remaining portion is negligible. The fin oxide layer 108 may be further removed. In some embodiments, the top surface of the fin 104' has a stepped profile in the channel region 104c. In some embodiments, the top surface of the central portion 104cc of the fin 104' along a centerline (e.g., line GG) in the Y direction is lower than the top surfaces of the side portions 104ca and 104cb of the fin 104'. The side portion 104ca may have a stepped top surface, with the bottom surface of the side portion 104ca being at the same level as the top surface of the side portion 104cb. This step may include one or more etching processes that are selective to the materials in the dummy gate structure 130 and the fin oxide layer 108, respectively. For example, a selective etching process such as a selective wet etch, a selective dry etch, or a combination thereof may be used to recess the dummy gate structure 130 and the epitaxial layer 115 on the unoxidized sidewalls S1' of the dummy gate structure 130. In some embodiments, a solution containing a fluoride compound is used as an etchant to recess the fin oxide layer 108 to remove the fin oxide layer 108. Fluorides can effectively remove silicon oxide materials. Referring to Figures 10A-10F, a metal gate structure 155 is deposited in the gate trench 150. Figure 10A illustrates a partial top view of the workpiece 100, while Figures 10B-10E illustrate partial cross-sectional views of the workpiece 100 taken along lines BB, CC, DD, and EE shown in Figure 10A. Figure 10F illustrates a partial cross-sectional view of the workpiece 100 in region FF, taken along lines F'-F' shown in Figures 10A and 10B, respectively. Line F'-F' is slightly higher than the top surface of the isolation structure 106, so that any remaining footing portion in region FF is reflected in the cross-sectional view of Figure 10F. In some embodiments, gate structure 155 conforms to the shape of trench 150 . Gate structure 155 may have an uneven bottom surface. In some embodiments, gate structure 155 includes a central portion 155 c along a centerline (e.g., line GG) in the Y direction and two side portions 155 a located on either side of central portion 155 c. The bottom surface of central portion 155 c is lower than the bottom surfaces of the two side portions 155 a. In some embodiments, gate structure 155 is connected to bump 126 . In some embodiments, the gate structure 155 includes a high-k dielectric layer 156 and a gate electrode 165, as shown in FIG. 10F. The high-k dielectric layer 156 is formed of a high-k (dielectric constant greater than about 3.9) dielectric material, which may include hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium oxide, silicon zirconium oxide, aluminum oxide (AlO), or the like. 2O 3), lanthanum oxide, yttrium oxide, strontium titanate, combinations thereof, or other suitable materials. High-k dielectric layer 156 can be deposited using CVD, ALD, and / or other suitable methods. Gate electrode 165 can include one or more work function layers 158 and 160 and a metal fill layer 162. Depending on the device type (PFET or NFET), one or more work function layers 158 and 160 can include p-type or n-type work function layers. Example n-type work function layers can be formed from aluminum, titanium aluminum, titanium aluminum carbide, tantalum silicon carbide, tantalum aluminum silicon, tantalum silicide, or hafnium carbide. Example p-type work function layers can be formed from titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbonitride, or molybdenum. Metal fill layer 162 can be formed from a metal such as tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu). Gate electrode 165 can be deposited using methods such as CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, the gate structure 155 further includes an interfacial layer (not shown), which may include a dielectric material such as a silicon oxide layer. The interfacial layer may be formed using chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. Referring to FIG. 10F , in some embodiments, the oxidized footing portion 120 ′ is removed from the dummy gate structure 130 in step 16 . The replacement metal gate structure 155 conforms to the shape and / or contour of the dummy gate structure 130 and thus has corners without footing effects, such as clean corners 170 . In some other embodiments, a portion of the oxidized footing portion 120 ′ is retained during this process. In such embodiments, the metal gate structure 155 includes footing corners 175 extending toward the remaining oxidized footing portion 120 ′. A gap 157 may be formed in the metal gate structure 155 . The gap 157 may be located between the high-k dielectric layer 156 and the gate electrode 165 . The gap 157 may comprise air. Although three clean corners 170 and one footing corner 175 are depicted, it should be understood that the metal gate structure 155 may include at least one clean corner 170 and any number of footing corners 175 . In some embodiments, a metal gate structure 155 includes four clean corners 170 and no footing corners 175 . As shown, the source / drain features 135 may include a source / drain feature 135a adjacent to a clean corner 170 and a source / drain feature 135b adjacent to a footing corner 175. A distance D1 between the gate electrode 165 at the clean corner 170 and the adjacent source / drain feature 135a is greater than a distance D2 between the gate electrode 165 at the footing corner 175 and the adjacent source / drain feature 135b. Therefore, electrical shorting between the gate electrode 165 at the clean corner 170 and the adjacent source / drain feature 135a can be avoided. Furthermore, the metal gate structure 155 having the clean corner 170 can improve various operating parameters of the semiconductor structure 100, such as speed performance and power consumption. Referring to FIG. 1 , method 10 includes step 28 , in which further processing is performed to complete the fabrication of workpiece 100 . For example, subsequent processing may form contact openings, contact metallization, and various contacts / vias / lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics), configured to connect the various features to form functional circuits that may include one or more multi-gate devices. The various interconnect features may be fabricated from a variety of conductive materials, including copper, tungsten, and / or silicide. In one example, a damascene and / or dual damascene process is used to form a copper-based multi-layer interconnect structure. Those skilled in the art will appreciate that although FinFET devices are shown as examples in Figures 2-10F, various aspects of the present disclosure are also beneficial to other examples of semiconductor devices, such as GAA devices. While not intended to be limiting, one or more embodiments of the present disclosure provide numerous benefits to semiconductor devices and their formation. For example, embodiments of the present disclosure can reduce and / or eliminate the footing portion of the dummy gate structure, thereby preventing electrical shorts in the device, reducing short channel effects (SCEs), and improving device operating parameters. Furthermore, embodiments of the present disclosure can increase current drive capability by vertically and horizontally expanding the fins not covered by the dummy gate structure during device fabrication. Furthermore, overall device performance can be improved by reducing the dimensions of the dummy gate structure and / or eliminating voids in the dummy gate structure in the methods disclosed herein. In an exemplary embodiment, the present disclosure relates to a method. The method includes providing a workpiece. The workpiece includes a substrate, a fin protruding from the substrate, and a dummy gate structure above the fin. The method also includes performing an oxidation process on the exposed surfaces of the fin and the dummy gate structure to form an oxide layer above the exposed surfaces of the fin and the dummy gate structure; removing the oxide layer to expose an unoxidized top surface and a plurality of unoxidized sidewalls of the fin and a plurality of unoxidized sidewalls of the dummy gate; epitaxially growing a cap layer on the unoxidized top surface and the unoxidized sidewalls of the fin and the unoxidized sidewalls of the dummy gate; forming a source / drain feature on the fin; and replacing the dummy gate structure with a metal gate structure. In some embodiments, the dummy gate includes a footing portion intersecting the fin, wherein performing the oxidation process includes oxidizing the footing portion, and removing the oxide layer includes removing the oxidized footing portion. In some embodiments, the oxide layer is a first oxide layer, the workpiece further includes a second oxide layer disposed on a plurality of sidewalls of the fin, and removing the oxide layer includes removing a first portion of the first oxide layer and the second oxide layer not covered by the dummy gate structure, thereby leaving a second portion of the second oxide layer directly beneath the dummy gate structure. In some embodiments, before performing the oxidation process, a second oxide layer is further disposed on the top surface of the fin, the second oxide layer having a first thickness on the sidewalls of the fin and a second thickness on the top surface of the fin, wherein the thickness of the capping layer on the unoxidized sidewalls of the fin is equal to or greater than the first thickness, and wherein the thickness of the capping layer on the unoxidized top surface of the fin is greater than the second thickness. In some embodiments, the dummy gate structure includes a void, wherein the exposed surfaces of the fin and the dummy gate include the exposed surface of the void, wherein removing the oxide layer further exposes the unoxidized surface of the void, and wherein epitaxially growing the capping layer includes epitaxially growing the capping layer on the unoxidized surface of the void. In some embodiments, after the epitaxial growth of the cap layer, the size of the gap is smaller than the size before the oxidation process is performed. In some embodiments, the workpiece further includes a dielectric fin, the dielectric fin is located above the substrate and adjacent to the fin, and the gap is disposed between the fin and the dielectric fin. In some embodiments, before forming the source / drain features on the fin, the method further includes forming a plurality of gate spacers on the cap layer on the unoxidized sidewalls of the dummy gate structure. In some embodiments, the cap layer and the fin comprise the same composition. In some embodiments, the cap layer is epitaxially grown on the unoxidized top surface of the fin at a first rate, and wherein a second rate at which the cap layer is epitaxially grown on the unoxidized sidewalls of the fin and the dummy gate is less than the first rate. In another exemplary embodiment, the present disclosure relates to a method. The method includes providing a workpiece. The workpiece includes a fin above a substrate, a first oxide layer disposed above a sidewall of the fin, and a dummy gate structure above the fin and directly above a first portion of the first oxide layer, wherein the first oxide layer also includes a second portion not covered by the dummy gate structure. The method also includes oxidizing multiple exposed surfaces of the fin and the dummy gate structure to form a second oxide layer; removing the second portion of the first oxide layer and the second oxide layer to expose multiple unoxidized surfaces of the fin and the dummy gate structure; and forming an epitaxial layer on the unoxidized surfaces of the fin and the dummy gate structure; wherein a thickness of the epitaxial layer is greater than or equal to the second oxide layer. Preferably, the method also includes forming multiple gate spacers on the epitaxial layer on the unoxidized surfaces of the dummy gate structure; forming source / drain features on the fin; and replacing the dummy gate structure with a metal gate structure. In some embodiments, the workpiece further includes an isolation feature adjacent to the fin and located below the dummy gate structure, wherein the dummy gate structure includes a footing portion that intersects the fin and the isolation feature, and wherein the exposed surface of the fin and the dummy gate structure is oxidized, including the footing portion, to form a portion of a second oxide layer. In some embodiments, the exposed surface of the fin and the dummy gate structure includes a top surface of the fin. In some embodiments, the method further includes annealing the workpiece after forming the epitaxial layer. Preferably, the first portion of the first oxide layer is further disposed on the top surface of the fin, wherein the top surface of the epitaxial layer of the fin is higher than the top surface of the first oxide layer. In another exemplary embodiment, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate; a fin is located on the substrate and extends longitudinally along a first direction; a gate structure is located above the fin and extends longitudinally along a second direction perpendicular to the first direction; and a plurality of gate spacers are located on a plurality of sidewalls of the gate structure. The fin has a first portion and a second portion, the first portion is located directly below the gate structure, and the second portion is located directly below the sidewall of the gate structure, wherein the width of the second portion along the second direction is greater than the width of the first portion. In some embodiments, the height of the second portion of the fin is equal to or greater than the height of the first portion of the fin. In some embodiments, a portion of the gate spacer protrudes into the gate structure. In some embodiments, the first portion of the fin includes two first sub-portions and a second sub-portion, the first sub-portion is adjacent to the second portion of the fin, and the second sub-portion is inserted between the two first sub-portions along the first direction; wherein the top surfaces of the two first sub-portions are higher than the top surface of the second sub-portion. The above summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that the present disclosure can be easily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and modifications herein. 10: Method 12, 14, 16, 18, 20, 22, 24, 26, 28: Step 100: Workpiece 102: Substrate 104, 104', 104a, 104b, 104a', 104b': Fin 104c: Channel region 104ca, 104cb: Side portion 104cc: Center portion 104sd: Source / Drain region 105: Dielectric fin / Dummy gate 106: Isolation structure / isolation feature 108: Fin oxide layer 110: Oxide layer 115: Epitaxial layer 120: Footing portion 120': Oxide footing portion 125: Gate spacer 126: Bump 130: Dummy gate structure 131: Gap 132: Gate hard mask layer 135, 135a, 135b: Source / drain features 140: ILD layer 145: CESL 150: Gate trench 155: Metal gate structure 155a: Side portion 155c: Center portion 156: High-k dielectric layer 158: Work function layer 157: Gap 160: Work function layer 162: Metal fill layer 165: Gate electrode 170: Corner 175: Footing corner BB, CC, DD, EE, F'-F', GG: Line FF: Region D1, D2: Distance S1: Sidewall S1': Unoxidized sidewall S2, S2'': Top surface S2': Unoxidized top surface S3: Surface S3': Unoxidized surface S4': Unoxidized sidewall S5': Unoxidized top surface S5'': Top surface T1, T2, T2', T3', T4', T5': Thickness W, W', Wa, Wb: Width X, Y, Z: Direction The various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of discussion. FIG1 shows a flow chart for forming a semiconductor structure according to one or more aspects of the present disclosure. FIG2 shows a partial perspective view of an exemplary workpiece according to various aspects of the present disclosure. FIG3A, 4A, 5A, 6A, 7A, 8A, 9A and 10A show partial top views of an exemplary workpiece during various manufacturing stages in the method of FIG1 according to various aspects of the present disclosure. FIG3B, 4B, 5B, 6B, 7B, 8B, 9B and 10B show partial cross-sectional views of the workpiece along line BB in FIG3A, 4A, 5A, 6A, 7A, 8A, 9A and 10A, respectively, during various manufacturing stages in the method of FIG1 according to various aspects of the present disclosure. Figures 3C, 4C, 5C, 6C, 7C, 8C, 9C, and 10C illustrate partial cross-sectional views of a workpiece taken along lines CC in Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A, respectively, during various stages of fabrication in the method of Figure 1, according to various aspects of the present disclosure. Figures 3D, 4D, 5D, 6D, 7D, 8D, 9D, and 10D illustrate partial cross-sectional views of a workpiece taken along lines DD in Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A, respectively, during various stages of fabrication in the method of Figure 1, according to various aspects of the present disclosure. Figures 3E, 4E, 5E, 6E, 7E, 8E, 9E, and 10E illustrate partial cross-sectional views of a workpiece taken along lines EE in Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A, respectively, during various stages of fabrication in the method of Figure 1, according to various aspects of the present disclosure. FIG. 10F illustrates a partial cross-sectional view of the workpiece in the area of ​​line FF in FIG. 10A and along lines FF′ in FIGs. 10B, 10C, 10D, and 10E during a manufacturing stage in the method of FIG. 1 according to various aspects of the present disclosure. Domestic deposit information (please note in the order of deposit organization, date, and number) None Foreign deposit information (please note in the order of deposit country, organization, date, and number) None 10: Method 12,14,16,18,20,22,24,26,28: Steps

Claims

1. A method for manufacturing a semiconductor structure, comprising: A workpiece is provided comprising: a substrate; a fin protruding from the substrate; and a dummy gate structure above the fin; performing an oxidation process on an exposed surface of the fin and the dummy gate structure to form an oxide layer above the exposed surface of the fin and the dummy gate structure; removing the oxide layer to expose an unoxidized top surface of the fin and a plurality of unoxidized sidewalls and a plurality of unoxidized sidewalls of the dummy gate; epitaxially growing a capping layer on the unoxidized top surface of the fin and the unoxidized sidewalls and the unoxidized sidewalls of the dummy gate; forming a source / drain feature on the fin; and replacing the dummy gate structure with a metal gate structure.

2. The method as claimed in claim 1, wherein the dummy gate includes a base portion intersecting with the fin, wherein performing the oxidation process includes oxidizing the base portion, and wherein removing the oxide layer includes removing the oxidized base portion.

3. The method as described in claim 1, wherein the oxide layer is a first oxide layer, wherein the working element further includes a second oxide layer disposed on a plurality of sidewalls of the fin, and wherein removing the oxide layer includes removing a first portion of the first oxide layer and the second oxide layer not covered by the dummy gate structure, thereby retaining a second portion of the second oxide layer directly below the dummy gate structure.

4. The method as described in claim 1, wherein the top cover layer and the fin comprise the same composition.

5. A method for manufacturing a semiconductor structure, comprising: A workpiece is provided comprising: a fin on a substrate; a first oxide layer disposed on a plurality of sidewalls of the fin; and a dummy gate structure located above the fin and directly above a first portion of the first oxide layer; wherein the first oxide layer further comprises a second portion not covered by the dummy gate structure; oxidizing a plurality of exposed surfaces of the fin and the dummy gate structure to form a second oxide layer; removing the second portion of the first oxide layer and the second oxide layer to expose a plurality of unoxidized surfaces of the fin and the dummy gate structure; and forming an epitaxial layer on the unoxidized surfaces of the fin and the dummy gate structure; wherein a thickness of the epitaxial layer is greater than or equal to that of the second oxide layer.

6. The method as described in claim 5, further comprising: A plurality of gate spacers are formed on the epitaxial layer of the unoxidized surfaces of the dummy gate structure; A source / drain feature is formed on the fin; the dummy gate structure is replaced with a metal gate structure.

7. A semiconductor structure comprising: One substrate; A fin is located above the substrate and extends longitudinally along a first direction; A dielectric fin is located above the substrate and extends longitudinally along the first direction; a gate structure is located above the fin and extends longitudinally along a second direction perpendicular to the first direction; and a plurality of gate spacers are located on a plurality of sidewalls of the gate structure; wherein the fin has a first portion and a second portion, the first portion being located directly below the gate structure, and the second portion being located directly below the sidewalls of the gate structure, wherein the width of the second portion along the second direction is greater than the width of the first portion.

8. The semiconductor structure as claimed in claim 7, wherein a height of the second portion of the fin is equal to or greater than a height of the first portion of the fin.

9. The semiconductor structure as claimed in claim 7, wherein a portion of the gate spacers protrudes into the gate structure.

10. The semiconductor structure of claim 7, wherein the first portion of the fin includes two first sub-parts and a second sub-part, the first sub-parts being adjacent to the second portion of the fin, the second sub-part being inserted between the two first sub-parts along the first direction, wherein the top surfaces of the two first sub-parts are higher than the top surface of the second sub-part.

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