Package structure and method for manufacturing the same

Abstract

A packaging structure and a method of forming the same are provided. The packaging structure includes a first rewiring structure, and first packaging members and second packaging members attached to a first side of the first rewiring structure and separated from each other in a first direction. The packaging structure further includes a first semiconductor die attached to a second side of the first rewiring structure, and a sealant. The packaging structure further includes a heat dissipation layer formed on the first semiconductor die, wherein the thermal conductivity of the heat dissipation layer is greater than that of the sealant. The packaging structure further includes a conductive structure passing through the heat dissipation layer; and a second rewiring structure formed on the heat dissipation layer. Furthermore, the second rewiring structure is electrically connected to the first semiconductor die via the conductive structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to a packaging structure, and more particularly to a configuration for reducing the temperature of the packaging structure. Prior Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Continuous advancements in semiconductor manufacturing processes have resulted in semiconductor devices with smaller structures and / or higher levels of integration. Functional density (i.e., the number of interconnect devices per unit chip area) generally increases as feature size (i.e., the smallest component that can be produced by the manufacturing process) decreases. This process size reduction generally increases production capacity and reduces associated costs.

[0003] Chip packaging not only protects semiconductor devices from environmental contamination, but also provides a connection interface for the semiconductor devices packaged therein. Currently, smaller packaging structures with smaller spaces or lower heights have been developed to package semiconductor devices.

[0004] New packaging technologies are being developed to further improve the density and functionality of semiconductor dies. These new packaging technologies for semiconductor dies face manufacturing challenges. Summary of the Invention

[0005] One embodiment of the present invention provides a packaging structure. The packaging structure includes a first redistribution structure; a first packaging component and a second packaging component attached to a first side of the first redistribution structure and separated from each other in a first direction. The packaging structure further includes a first semiconductor die attached to a second side of the first redistribution structure; and an encapsulant formed around the first semiconductor die. The packaging structure further includes a heat sink layer formed on the first semiconductor die, wherein the heat sink layer has a thermal conductivity greater than that of the encapsulant. The packaging structure further includes a conductive structure extending through the heat sink layer; and a second redistribution structure formed on the heat sink layer. Furthermore, the second redistribution structure is electrically connected to the first semiconductor die via the conductive structure.

[0006] One embodiment of the present invention provides a packaging structure. The packaging structure includes a first semiconductor die having a first projected area in a top view; and a first redistribution structure attached to a first side of the first semiconductor die. The packaging structure further includes a heat dissipation layer attached to a second side of the first semiconductor die, the heat dissipation layer having a second projected area in a top view, and the second projected area of the heat dissipation layer is larger than the first projected area of the first semiconductor die. The packaging structure further includes a second redistribution structure formed on the heat dissipation layer; and a conductive structure passing through the heat dissipation layer and electrically connecting the first semiconductor die and the second redistribution structure. The packaging structure further includes a first packaging component and a second packaging component attached to the first redistribution structure. In addition, the first semiconductor die partially overlaps with the first packaging component and the second packaging component.

[0007] One embodiment of the present invention provides a method for forming a packaging structure. The method includes placing a first semiconductor die on a first carrier substrate; and forming a first redistribution structure on a first side of the first semiconductor die. The method further includes placing a first packaging component and a second packaging component on the first redistribution structure. Furthermore, the first packaging component and the second packaging component are separated in a first direction. The method further includes attaching a second carrier substrate to the first packaging component and the second packaging component, and removing the first carrier substrate from the second side of the first semiconductor die. The method further includes forming a heat dissipation layer to cover the second side of the first semiconductor die, the heat dissipation layer being composed of a carbon-containing material, and the width of the heat dissipation layer in the first direction being greater than the width of the first semiconductor die. The method further includes forming a first conductive structure to pass through the heat dissipation layer, and forming a second redistribution structure to cover the heat dissipation layer and the first conductive structure. Simple diagram description

[0008] 1A to 1C are top views of the packaging structure in some embodiments. 2A to 2P are cross-sectional views of intermediate stages of manufacturing a package structure in some embodiments. FIG2N-1 is an enlarged cross-sectional view of region R_2N shown in FIG2N in some embodiments. FIG. 2O-1 is a diagram illustrating a conductive structure formed in an opening in some embodiments. FIG. 2O-2 is a diagram illustrating a conductive structure 134 - 2 formed in an opening in some embodiments. FIG. 2P-1 is a diagram of a package structure including the conductive structure shown in FIG. 2O-1 in some embodiments. FIG. 2P-2 is a diagram of a package structure including the conductive structure shown in FIG. 2O-2 in some embodiments. FIG3 is a cross-sectional view of a packaging structure in some embodiments. FIG4A is an enlarged cross-sectional view of region R_3a shown in FIG3 in some embodiments. FIG4B is an enlarged cross-sectional view of region R_3b shown in FIG3 in some embodiments. FIG5A is an enlarged cross-sectional view of region R_3a shown in FIG3 in some other embodiments. FIG5B is an enlarged cross-sectional view of region R_3b viewed in FIG3 in some embodiments. FIG6 is a top view of the packaging structure in some embodiments. FIG7A is a top view of the packaging structure in some embodiments. FIG7B is a cross-sectional view of the package structure along the section line X7A-X7A′ in FIG7A in some embodiments. FIG8 is a top view of the packaging structure in some embodiments. FIG9A is a top view of the package structure in some embodiments. FIG9B is a cross-sectional view of the package structure along the section line X9A-X9A′ in some embodiments. FIG9C is a cross-sectional view of a packaging structure in some embodiments. FIG10 is a top view of the packaging structure in some embodiments. FIG. 11A is a top view of the packaging structure in some embodiments. FIG. 11B is a top view of the packaging structure in some embodiments. FIG12A is a top view of the packaging structure in some embodiments. FIG12B is a top view of the packaging structure in some embodiments. FIG13A is a top view of the packaging structure in some embodiments. FIG13B is a cross-sectional view of the package structure along the section line X13A-X13A′ in some embodiments. FIG13C is a cross-sectional view of a packaging structure in some embodiments. FIG14 is a top view of the packaging structure in some embodiments. FIG15 is a top view of the packaging structure in some embodiments. FIG16 is a top view of the packaging structure in some embodiments. FIG17 is a top view of the packaging structure in some embodiments. FIG18 is a top view of the packaging structure in some embodiments. FIG19 is a top view of the packaging structure in some embodiments. FIG20 is a top view of the packaging structure in some embodiments. FIG21 is a top view of the packaging structure in some embodiments. FIG22 is a top view of the packaging structure in some embodiments. FIG23 is a top view of the packaging structure in some embodiments. FIG24 is a top view of the packaging structure in some embodiments. Implementation Method

[0009] The following detailed description may be accompanied by accompanying drawings to facilitate an understanding of various aspects of the present invention. It should be noted that the various structures are for illustrative purposes only and are not drawn to scale, as is common practice in the industry. In practice, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of illustration.

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the present invention. The following disclosure describes specific examples of various components and their arrangements for ease of description. These specific examples are not intended to limit the embodiments of the present invention. For example, if an embodiment of the present invention describes a first structure formed above a second structure, this means that the first structure may be in direct contact with the second structure, or that an additional structure may be formed between the first and second structures, preventing the first and second structures from directly contacting each other. Furthermore, reference numerals may be repeated across various embodiments of the present invention to simplify or clarify the description, and this does not imply that structures with the same reference numerals in various embodiments and / or configurations have the same relative relationships.

[0011] Some variations of the embodiments are described herein. Similar reference numbers are used to designate similar elements in various exemplary embodiments. It should be understood that additional steps may be provided before, during, or after the method, and that other embodiments of the method may replace or omit some of the described steps.

[0012] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or similar terms are used to describe the relationship of one element or structure to another element or structure in the drawings. These spatially relative terms encompass different orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated 90 degrees or otherwise, the spatially relative terms are interpreted based on the orientation.

[0013] Embodiments of the present invention may be related to packaging structures such as three-dimensional packages, three-dimensional integrated circuit devices, or two-and-a-half-dimensional packages. The package structures formed by the embodiments of the present invention include a substrate (supporting one or more dies or packages) and a protective element (such as a protective cover) positioned adjacent to the die or package. The protective element may also serve as a warpage control element and / or a heat sink.

[0014] Embodiments of the present invention may also include other structures and processes. For example, test structures may be included to facilitate verification testing of 3D packages, 3D integrated circuit devices, and / or 2.5D packages. For example, the test structures may include test pads formed in a redistribution layer or on a substrate, allowing testing using probes or probe cards. Verification testing can be performed on intermediate structures as well as final structures. Furthermore, the structures and methods disclosed herein can be combined with intermediate verification using known-good die to increase yield and reduce costs.

[0015] A packaging structure may include various packaging components and semiconductor dies electrically connected to the packaging components. These semiconductor dies may generate heat during operation and may be considered hot spots in the device. In summary, a heat dissipation layer is formed on the semiconductor dies, allowing the temperature of the semiconductor dies to be dispersed (e.g., dissipated) through the heat dissipation layer. Furthermore, this reduces the temperature of the packaging components during operation.

[0016] Figures 1A through 1C are top views of a package structure 100 in some embodiments. To facilitate understanding of the structure, the following figures provide XYZ reference coordinates. Furthermore, the following figures are simplified to provide clarity and facilitate understanding of the inventive concepts of the present embodiments. Additional structures may be included, and some of the following structures may be replaced, adjusted, or omitted.

[0017] More specifically, FIG1A illustrates the layout of package components 10 and 20 within a package structure 100 in some embodiments. In some embodiments, package components 10 and 20 are semiconductor dies with different functions. In some embodiments, package component 10 comprises a memory device, such as a hybrid memory cube module, a high-bandwidth memory module, or the like, comprising multiple memory dies. In some embodiments, package component 20 comprises a system-on-chip (SoC) die, a wafer-level package, or a combination thereof. In some embodiments, package component 10 is a high-bandwidth memory die, while package component 20 is a SoC die.

[0018] In some embodiments, one of the package components 20 is sandwiched between two package components 10 in the X direction, as shown in the top view of FIG1A . In some embodiments, one of the package components 20 and both package components 10 are aligned in the X direction. In some embodiments, the package components 10 are aligned in the Y direction, and the package components 20 are aligned in the Y direction. Package components 10 and 20 can be formed on a redistribution structure (not shown in FIG1A ), and the process details are described below.

[0019] FIG1B illustrates the layout of semiconductor dies 30 and 40 in package structure 100 in some embodiments. More specifically, semiconductor dies 30 and 40 are embedded active dies and are electrically coupled to package components 10 and 20 via a redistribution structure. In some embodiments, semiconductor dies 30 and 40 are embedded local interconnect dies.

[0020] In some embodiments, each semiconductor die 30 is disposed to provide electrical connection between two package components 10 and one package component 20 in the X direction. In some embodiments, each semiconductor die 30 partially overlaps with both package components 10 and one package component 20 in a top view, as shown in FIG1B . In some embodiments, each semiconductor die 30 in a top view partially overlaps with two adjacent sidewall surfaces of both package components 10 and one sidewall surface of one package component 20. In some embodiments, each semiconductor die 40 is disposed to provide electrical connection between two package components 20 in the Y direction. In some embodiments, as shown in FIG1B , each semiconductor die 40 in a top view vertically overlaps with both package components 20.

[0021] Figure 1C shows the layout of the heat dissipation layer 130 in the package structure 100 in some embodiments. In some embodiments, the heat dissipation layer 130 is a carbon-containing heat dissipation layer. More specifically, the heat dissipation layer 130 is formed on the semiconductor dies 30 and 40 to dissipate heat generated by the semiconductor dies 30 and 40 during operation and reduce device temperature. In some embodiments, the heat dissipation layer 130 extends continuously from the semiconductor die 30 to the semiconductor die 40. In some embodiments, the heat dissipation layer 130 completely covers the semiconductor dies 30 and 40. In some embodiments, the width of the heat dissipation layer 130 in the X and Y directions is greater than the width of the semiconductor dies 30 and 40, respectively. In some embodiments, the heat dissipation layer 130 in the top view can completely cover the package components 10 and 20. In some embodiments, the width of the heat dissipation layer 130 in the X and Y directions is greater than the width of the package components 10 and 20, respectively.

[0022] Figures 2A through 2P are cross-sectional views of intermediate stages in the fabrication of package structure 100 in some embodiments. More specifically, the cross-section of some embodiments is taken along line X1C-X1C' in Figure 1C. As shown in Figure 2A , in some embodiments, through-insulation vias 104 are formed in carrier substrate 102.

[0023] The carrier substrate 102 can be configured to provide structural support during the manufacturing process of the package structure 100. In some embodiments, the carrier substrate 102 is composed of silicon, a polymer, a polymer composite, metal foil, ceramic, glass, glass and epoxy, barium oxide, ribbon, or other suitable materials for structural support. In some embodiments, the carrier substrate 102 is a sapphire glass substrate.

[0024] In some embodiments, the through-insulation via 104 is formed of a conductive material such as copper, titanium, tungsten, aluminum, or the like. In some embodiments, a seed layer (not shown) may be formed before forming the through-insulation via 104. The through-insulation via 104 may be formed by the following process. A photoresist layer may be formed on the carrier substrate 102 by spin coating or a similar method. The photoresist layer may then be exposed to pattern the photoresist layer and form an opening therein. After the opening is formed, a conductive material may be filled into the opening by plating, such as electroplating, electroless plating, or the like, to form the through-insulation via 104 in the opening. The photoresist layer may be removed by ashing or stripping, such as using an oxygen plasma or the like.

[0025] In some embodiments, as shown in FIG2B , after forming TIB vias 104, semiconductor dies 30 and 40 (not shown in FIG2B , see FIG1B ) are placed on a carrier substrate 102. Although FIG2B does not show semiconductor die 40, the structure of semiconductor die 40 can be similar or identical to the structure of semiconductor die 30 shown in FIG2B through 2P , as described below. In some embodiments, TIB vias 104 are sandwiched between and separated from semiconductor dies 30 and 40. In some embodiments, some semiconductor dies 30 and 40 are immediately adjacent to each other, without TIB vias 104 formed between them. In some embodiments, the closest distance between two adjacent semiconductor dies 30 and 40 is approximately 50 microns to approximately 150 microns.

[0026] In some embodiments, semiconductor dies 30 and 40 each include a substrate 202, conductive vias 204 extending through substrate 202, and an interconnect structure 206 formed on substrate 202. In some embodiments, interconnect structure 206 includes multiple metallization layers, including a dielectric layer 208 and conductive structures 210 formed within dielectric layer 208. Conductive structures 210 may include metal lines and metal vias formed within dielectric layer 208. Furthermore, in some embodiments, conductive vias 204 are electrically connected to conductive structures 210 within interconnect structure 206. In some embodiments, conductive connectors 212 are formed on interconnect structure 206 and electrically connected to conductive structures 210 within interconnect structure 206. The layouts of conductive structures 210 within interconnect structures 206 of semiconductor dies 30 and 40 may be the same or different.

[0027] Substrate 202 can be a semiconductor substrate such as silicon, which can be doped or undoped, and can be a silicon wafer, an active layer of a semiconductor-on-insulator substrate, or the like. Substrate 202 can also include other semiconductor materials such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, or combinations thereof. Other substrates such as multilayer or graded substrates can also be used. In some embodiments, conductive vias 204 are formed through substrate 202 to electrically connect two sides of substrate 202. In some embodiments, conductive vias 204 are composed of tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, nickel, other suitable conductive materials, or combinations thereof.

[0028] The interconnect structure 206 can be formed using a damascene process, such as a single damascene process, a dual damascene process, or the like. In some embodiments, the dielectric layer 208 includes multiple layers composed of a low-k dielectric material having a dielectric constant less than 7. In some embodiments, the dielectric layer 208 is composed of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or the like. The dielectric layer 208 can be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes. In some embodiments, the conductive structure 210 is composed of tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, nickel, other suitable conductive materials, or combinations thereof. The conductive structure 210 can be formed using chemical vapor deposition, physical vapor deposition, plasma-assisted chemical vapor deposition, plasma-assisted physical vapor deposition, atomic layer deposition, or any other suitable deposition process.

[0029] The conductive connector 212 may include a bonding pad, a microbump, a copper pillar, a copper layer, a nickel layer, a lead-free layer, an electroless nickel-electroless palladium-immersion gold layer, a tin / silver layer, a tin / lead layer, or the like. In some embodiments, the conductive connector 212 is electrically connected to the conductive structure 210 in the interconnect structure 206.

[0030] In some embodiments, as shown in FIG2C , after semiconductor dies 30 and 40 are placed on carrier substrate 102, encapsulant 106 is formed on carrier substrate 102. More specifically, encapsulant 106 is formed to laterally seal TIV 104 and semiconductor dies 30 and 40. In some embodiments, encapsulant 106 in this step covers TIV 104 and the top surfaces of semiconductor dies 30 and 40. In some embodiments, encapsulant 106 comprises a molding compound such as a resin, polyimide, polyphenylene sulfide, polyetheretherketone, polyethersulfone, epoxy molding compound, or combinations thereof.

[0031] In some embodiments, as shown in FIG. 2D , after forming the encapsulant 106, a planarization process is performed on the encapsulant 106 until the TIV 104 and the conductive connector 212 are exposed. The planarization process can be performed using a mechanical polishing process, a chemical mechanical polishing process, or a similar process to remove excess portions of the encapsulant 106. In some embodiments, the planarization process also slightly polishes the TIV 104 and / or the conductive connector 212. After the planarization process, in some embodiments, the upper surfaces of the TIV 104 and the conductive connector 212 are substantially flush with the upper surface of the encapsulant 106.

[0032] In some embodiments, as shown in FIG2E , a redistribution structure 108 is then formed on the semiconductor dies 30 and 40, the through-insulation vias 104, and the encapsulant 106, and a conductive pad 114 is formed on the redistribution structure 108. In some embodiments, the redistribution structure 108 includes multiple insulating layers 110 and redistribution layers 112, and the redistribution layers 112 are electrically connected to the through-insulation vias 104 and the conductive connectors 212 of the semiconductor dies 30 and 40. The redistribution layers 112 can be considered a fan-out structure. The number of insulating layers 110 and redistribution layers 112 shown in FIG2E is for example only and does not limit the present invention. For example, the number of insulating layers 110 and redistribution layers 112 can be from about 1 to about 15.

[0033] In some embodiments, the insulating layer 110 is composed of one or more suitable dielectric materials, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a polymer material, a polyimide material, a low-k dielectric material, a molding material (e.g., an epoxy molding compound or the like), another dielectric material, or a combination thereof. The insulating layer 110 can be formed by spin coating, lamination, chemical vapor deposition, a similar process, or a combination thereof. In some embodiments, the redistribution layer 112 is composed of a conductive material such as copper, titanium, tungsten, aluminum, or a combination thereof. The conductive material can be formed by a deposition process such as electroplating, electroless plating, or a similar process.

[0034] In some embodiments, as shown in FIG2E , after forming the redistribution structure 108, a conductive pad 114 is formed on the redistribution structure 108. In some embodiments, the conductive pad 114 is physically connected to the redistribution layer 112 in the redistribution structure 108. Furthermore, in some embodiments, the conductive pad 114 is electrically connected to the through-insulation vias 104 and the conductive connector 212 of the semiconductor dies 30 and 40 via the redistribution layer 112 of the redistribution structure 108. In some embodiments, the conductive pad 114 is composed of a conductive material such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, nickel, aluminum, other suitable conductive materials, or combinations thereof. In some embodiments, the conductive pad 114 and the redistribution layer 112 are composed of different conductive materials.

[0035] As shown in some embodiments in Figures 2F and 1B , package components 10 and 20 can then be placed on the redistribution structure 108. More specifically, in some embodiments, package components 10 and 20 are bonded to conductive pads 114 on the redistribution structure 108 via conductive connectors 116. As described above, package components 10 and 20 can be placed on the redistribution structure 108 having the layout shown in Figures 1A to 1C. Furthermore, in some embodiments, package component 10 is a high-bandwidth memory die, while package component 20 is a system-on-a-chip die. Furthermore, in some embodiments, package components 10 and 20 include conductive pads 118 electrically connected to the devices within package components 10 and 20. In some embodiments, conductive pads 114 are composed of a conductive material such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, nickel, aluminum, other suitable conductive materials, or combinations thereof.

[0036] In some embodiments, conductive connectors 116 are bonded to conductive pads 118 of package components 10 and 20. In some embodiments, conductive connectors 116 are solder balls, metal pillars, controlled-collapse die-attachment bumps, microbumps, bumps formed using electroless nickel-electroless palladium-immersion gold technology, or the like. In some embodiments, conductive connectors 116 are microbumps vertically sandwiched between conductive pads 114 and 118. In some embodiments, conductive connectors 116 are composed of a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, conductive connectors 116 are initially formed by forming a solder layer via evaporation, electroplating, printing, solder transfer, ball placement, or the like, and a reflow process may be performed to shape the material into the desired bump shape. In some embodiments, conductive connectors 116 include metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or the like. The metal pillars may be free of solder and have substantially vertical sidewalls.

[0037] In some embodiments, as shown in FIG. 2G , after bonding the package components 10 and 20 to the redistribution structure 108, an underfill layer 120 may be formed around the package components 10 and 20. More specifically, in some embodiments, the underfill layer 120 surrounds and covers the lower surfaces and sidewalls of the package components 10 and 20. Furthermore, in some embodiments, the conductive pads 114 and 118 and the conductive connector 116 are embedded in the underfill layer 120. In some embodiments, the underfill layer 120 does not cover (i.e., exposes) the upper surfaces of the package components 10 and 20. In some embodiments, the underfill layer 120 does not cover (i.e., exposes) the upper portions of the sidewall surfaces of the package components 10 and 20.

[0038] In some embodiments, the underfill layer 120 is composed of a polymer, epoxy, molded underfill, or the like. The underfill layer 120 may be formed by performing a capillary flow process after laminating the packaging components 10 and 20 to the redistribution structure 108. In some embodiments, a curing process may be performed after forming the underfill layer 120. The curing process may include heating the underfill layer 120 to a predetermined temperature and maintaining it for a predetermined period of time. The heating step may employ an annealing process or other heating process. The curing process may also include an ultraviolet light exposure process, an infrared energy exposure process, a combination thereof, or a combination thereof in combination with a heating process.

[0039] In some embodiments, as shown in FIG2H , a sealant 122 is then formed around the underfill layer 120. More specifically, in some embodiments, the sealant 122 covers and surrounds the package components 10 and 20 and the underfill layer 120. In some embodiments, the sealant 122 comprises an epoxy, an organic polymer, a polymer with or without silicon-based fillers or glass fillers, or the like. In some embodiments, the sealant 122 comprises a liquid molding compound that may be a colloidal liquid when applied. The sealant 122 may be in a liquid or solid state when applied. The sealant 122 may alternatively comprise other insulating and / or sealing materials. The sealant 122 may be applied using a wafer-level molding process. For example, the sealant 122 may be molded using compression molding, transfer molding, molded underfill, or other methods. In some embodiments, the sealant 122 and the underfill layer 120 are composed of different materials. The sealant 122 may be subjected to a curing process. The curing process may include heating the sealant 122 to a predetermined temperature and maintaining it for a predetermined period of time. The heating step may be an annealing process or other heating process. The curing process may also include an ultraviolet light exposure process, an infrared energy exposure process, a combination thereof, or a combination thereof in combination with a heating process.

[0040] In some embodiments, as shown in FIG. 2I , a planarization process may be performed after forming encapsulant 122 until the top surfaces of package components 10 and 20 are exposed. The planarization process may be performed using a mechanical polishing process, a chemical mechanical polishing process, or a similar process to remove excess encapsulant 122. In some embodiments, the planarization process also slightly etches package components 10 and 20. After the planarization process, in some embodiments, the top surfaces of package components 10 and 20 are substantially flush with the top surface of encapsulant 122.

[0041] In some embodiments, as shown in FIG2J , a carrier substrate 124 is then attached to the encapsulant 122 and the package components 10 and 20. The carrier substrate 124 may be provided to provide structural support during the manufacturing process of the package structure 100. In some embodiments, the carrier substrate 124 may be composed of silicon, a polymer, a polymer composite, metal foil, ceramic, glass, glass and epoxy, barium oxide, tape, or other suitable materials for structural support. In some embodiments, the carrier substrate 124 is a sapphire glass substrate. In some embodiments, the carrier substrates 102 and 124 may be composed of the same material but have different thicknesses.

[0042] In some embodiments, as shown in FIG2K , after attaching the carrier substrate 124 to the encapsulant 122, the package structure is flipped over and the carrier substrate 102 is removed. In some embodiments, the carrier substrate 102 is removed by a carrier separation process. The carrier separation process can employ any suitable process, such as etching, grinding, and mechanical stripping, to remove the carrier substrate 102. In some embodiments, after removing the carrier substrate 102, residues, such as adhesive, may remain on the exposed surfaces of the semiconductor dies 30 and 40. In some embodiments, as shown in FIG2L , a cleaning process 126 is then performed to clean the exposed surfaces of the semiconductor dies 30 and 40.

[0043] In some embodiments, as shown in FIG. 2M , a heat sink layer 130 is then formed over the encapsulant 106, the through-insulation vias 104, and the semiconductor dies 30 and 40. The heat sink layer 130 can be configured to diffuse (e.g., dissipate) heat generated by the semiconductor dies 30 and 40. In some embodiments, the heat sink layer 130 directly contacts the substrate 202 of the semiconductor dies 30 and 40. In some embodiments, the heat sink layer 130 and the interconnect structure 206 are located on opposite sides of the substrate 202 of the semiconductor dies 30 and 40.

[0044] In some embodiments, heat dissipation layer 130 is a carbon-containing layer with high lateral thermal conductivity. In some embodiments, the thermal conductivity of heat dissipation layer 130 is greater than the thermal conductivity of sealant 106. In some embodiments, heat dissipation layer 130 is composed of graphene or diamond-like carbon. In some embodiments, the thermal conductivity of heat dissipation layer 130 is approximately 1 W / mK to approximately 1000 W / mK. In some embodiments, the thickness of heat dissipation layer 130 is approximately 10 microns to approximately 30 microns. The thickness of heat dissipation layer 130 is sufficient to provide adequate thermal conductivity, but not so thick that it is difficult to form a material layer.

[0045] In some embodiments, as shown in FIG2N , after forming the heat dissipation layer 130, an opening 132 is formed through the heat dissipation layer 130. FIG2N-1 is an enlarged cross-sectional view of region R_2N shown in FIG2N , in some embodiments. In some embodiments, as shown in FIG2N and FIG2N-1 , the opening 132 exposes the through-insulation via 104 and the conductive via 204 in the semiconductor dies 30 and 40.

[0046] The opening 132 can be formed by forming a mask layer on the heat dissipation layer 130, performing an etching process to transfer the mask layer pattern to the heat dissipation layer 130, and then removing the mask layer. In some embodiments, the exposed portions of the through-insulation layer via 104 and the conductive via 204 are also slightly etched, resulting in the through-insulation layer via 104 and the conductive via 204 exposed in the opening 132 having curved upper surfaces. In some embodiments, the heat dissipation layer 130 located in the opening 132 has rounded corners and sloped sidewall surfaces.

[0047] In some embodiments as shown in Figure 2O, after forming the opening 132, a conductive structure 134 is formed in the opening 132. Figures 2O-1 and 2O-2 are enlarged cross-sectional views of the region R_2O shown in Figure 2O in some embodiments.

[0048] More specifically, FIG. 2O-1 illustrates a conductive structure 134-1 formed within the opening 132 in some embodiments. The conductive structure 134-1 can be formed by forming a conductive material within the opening 132 and above the heat dissipation layer 130, and performing a planarization process on the conductive material until the upper surface of the heat dissipation layer 130 is exposed. The planarization process can be performed using a mechanical polishing process, a chemical mechanical polishing process, or a similar method to remove excess conductive material. In some embodiments, the conductive material includes tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, nickel, other suitable conductive materials, or combinations thereof. In some embodiments, the upper surface of the conductive structure 134-1 after the planarization process is substantially flush with the upper surface of the heat dissipation layer 130. In some embodiments, the tip of at least one conductive structure 134-1 vertically overlaps the heat dissipation layer 130 and the sealant 106. In some embodiments, the tip portion 134 - 1T of the at least one conductive structure 134 - 1 vertically overlaps the heat dissipation layer 130 and the semiconductor die 30 or 40 .

[0049] FIG2O-2 illustrates a conductive structure 134-2 formed in an opening 132 in some embodiments. The conductive structure 134-2 may be formed by selectively depositing a conductive material in the opening 132 until the upper surface of the conductive material is substantially flush with the upper surface of the heat dissipation layer 130. In some embodiments, the conductive material includes tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, nickel, aluminum, other suitable conductive materials, or combinations thereof. As shown in FIG2O-O , each conductive structure 134-2 has a raised upper surface. In some embodiments, the middle portion of each conductive structure 134-2 is thicker than the edge portion.

[0050] As shown in Figures 20-1 and 20-2, because heat dissipation layer 130 located in opening 132 has slanted sidewall surfaces, the slanted sidewall surfaces of conductive structures 134, including conductive structures 134-1 and 134-2, directly contact heat dissipation layer 130. Furthermore, in some embodiments, the upper surface of each conductive structure 134 is wider than the lower surface (in the X direction). In some embodiments, the upper portion of conductive structure 134 is wider than the bottom portion (in the X direction).

[0051] In some embodiments, as shown in FIG2P , after forming the conductive structure 134, a redistribution structure 140 is formed on the heat dissipation layer 130. In some embodiments, the redistribution structure 140 includes multiple insulating layers 142 and redistribution layers 144 (labeled in FIG2P-1 ), and the redistribution layers 144 are electrically connected to the conductive structures 134 in the heat dissipation layer 130. The redistribution layers 144 can be considered a fan-out structure. The number of insulating layers 142 and redistribution layers 144 shown in FIG2F is for example only and does not limit the present invention. For example, the number of insulating layers 142 and redistribution layers 144 can be from about 1 to about 15.

[0052] In some embodiments, the thermal conductivity of the heat dissipation layer 130 is greater than the thermal conductivity of the insulating layer 142. In some embodiments, the insulating layer 142 is composed of one or more suitable dielectric materials, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a polymer material, a polyimide material, a low-k dielectric material, a molding material (e.g., an epoxy molding compound or the like), another dielectric material, or a combination thereof. The insulating layer 142 can be formed by a suitable process such as spin coating, lamination, chemical vapor deposition, or the like, or a combination thereof. In some embodiments, the redistribution layer 144 is composed of a conductive material such as copper, titanium, tungsten, aluminum, another metal, or a combination thereof. The conductive material can be formed by a deposition process such as electroplating, electroless plating, or the like.

[0053] In some embodiments, as shown in FIG. 2P , after forming the redistribution structure 140, a conductive connector 146 is formed on the redistribution structure 140, and the package structure 100 is formed. The conductive connector 146 may include a bonding pad, a microbump, a copper pillar, a copper layer, a nickel layer, a lead-free layer, an electroless nickel-electroless palladium-immersion gold layer, a tin / silver layer, a tin / lead layer, or the like. In some embodiments, the conductive connector 146 includes a conductive pillar 148, and a solder ball 150 is formed on the conductive pillar 148. In some embodiments, the conductive connector 146 is electrically connected to the redistribution layer 144 in the redistribution structure 140.

[0054] Figures 2P-1 and 2P-2 are enlarged cross-sectional views of region R_2P shown in Figure 2P in some embodiments. More specifically, Figure 2P-1 shows a package structure 100 including the conductive structure 134-1 shown in Figure 2O-1 in some embodiments. In some embodiments, the bottom surface of the bottommost insulating layer 142 is substantially flush with the top surface of the conductive structure 134-1.

[0055] FIG2P-2 illustrates a package structure 100 including the conductive structure 134-2 shown in FIG2O-2 in some embodiments. In some embodiments, the concave lower surface of the redistribution layer 144 on the conductive structure 134-2 directly contacts the convex upper surface of the conductive structure 134-2. In some embodiments, the lower surface of the bottommost insulating layer 142 is uneven. In some embodiments, the convex portion of the bottommost insulating layer 142 is laterally interposed (e.g., in the X direction) between the conductive structure 134-2 and the heat dissipation layer 130. In some embodiments, the bottommost portion of the bottommost insulating layer 142 is lower than the topmost portion of the upper surface of the heat dissipation layer 130.

[0056] In package structure 100, semiconductor dies 30 and 40 generate significant heat during operation, potentially impacting the performance of package components 10 and 20. Therefore, a heat dissipation layer 130 with high thermal conductivity is formed on semiconductor dies 30 and 40 to laterally diffuse the heat generated by these dies. Consequently, the temperature of package structure 100 (particularly the hot spots around semiconductor dies 30 and 40) can be reduced, for example, by approximately 8°C for semiconductor dies 30 and 40, approximately 10°C for package component 10, and approximately 3°C for package component 20, thereby improving the performance of package structure 100.

[0057] In some embodiments, package structure 100 includes a redistribution structure 108, and all package components 10 and 20 shown in Figures 1A to 1C are located on a first side of the redistribution structure 108. Furthermore, in some embodiments, as shown in Figure 2P, all semiconductor dies 30 and 40 shown in Figures 1A to 1C are located on a second side of the redistribution structure 108. Furthermore, in some embodiments, as shown in Figures 1A to 1C, package components 10 and 20 are separated from each other in the X and Y directions, and semiconductor dies 30 and 40 are separated from each other in the X and Y directions. As described above, semiconductor dies 30 and 40 can be arranged to electrically connect package components 10 and 20. Therefore, each semiconductor die 30 partially overlaps with package components 10 and 20, meaning that portions of package components 10 and 20 are within the projection of semiconductor die 30.

[0058] Furthermore, in some embodiments, the heat dissipation layer 130 is formed on the semiconductor dies 30 and 40 and is vertically sandwiched between the semiconductor dies 30 and 40 and the redistribution structure 140. In some embodiments, the conductive structure 134, including conductive structures 134-1 and 134-2, passes through the heat dissipation layer 130, electrically connecting the through-insulation vias 104 and the conductive vias 204 of the semiconductor dies 30 and 40 to the redistribution structure 140 via the conductive structures 134. In some embodiments, the projected area of the heat dissipation layer 130 is larger than the projected areas of the semiconductor dies 30 and 40 and the projected areas of the package components 10 and 20. In some embodiments, the projected areas of the semiconductor dies 30 and 40 and the projected areas of the package components 10 and 20 are within the projected area of the heat dissipation layer 130.

[0059] FIG3 is a cross-sectional view of a package structure 100' in some embodiments. In some embodiments, package structure 100' may be similar to package structure 100 described above, except that conductive structures 134'a, 134'b, and 134'c formed in heat dissipation layer 130 are wider than through-insulation vias 104 and conductive vias 204 in semiconductor dies 30 and 40. Package structure 100' may also have the layout described above, as shown in FIG1A through 1C. The process and materials used to form package structure 100' may be similar or identical to those used to form package structure 100 described above, and therefore will not be repeated here.

[0060] FIG4A is an enlarged cross-sectional view of region R_3a shown in FIG3 in some other embodiments. In some embodiments shown in FIG4A , a conductive structure 134′a-1 is formed in heat dissipation layer 130 and electrically connected to through-insulation vias 104 and conductive vias 204 in semiconductor dies 30 and 40. The structure and material of conductive structure 134′a-1 are substantially similar or identical to those of conductive structure 134-1 shown in FIG2P-1 , except that conductive structure 134′a-1 is wider.

[0061] In some embodiments, at least one conductive structure 134'a-1 is wider in the X-direction than one of the through-insulation vias 104. In some embodiments, at least one conductive structure 134'a-1 is wider in the X-direction than one of the conductive vias 204. In some embodiments, the conductive structure 134'a-1 laterally protrudes from the sidewall surfaces of the through-insulation via 104 below the conductive structure 134'a-1. In some embodiments, the lower surface of the conductive structure 134'a-1 directly contacts the upper surface of the encapsulant 106. In some embodiments, the conductive structure 134'a-1 laterally protrudes from the sidewall surfaces of the conductive via 204 below the conductive structure 134'a-1. In some embodiments, the lower surface of the conductive structure 134'a-1 directly contacts the upper surface of the substrate 202 of the semiconductor dies 30 and 40.

[0062] FIG4B is an enlarged cross-sectional view of region R_3b shown in FIG3 in some other embodiments. In some embodiments shown in FIG4B , conductive structures 134'b-1 and 134'c-1 are formed in heat dissipation layer 130 and electrically connected to TIV 104 and conductive via 204 in semiconductor dies 30 and 40, respectively. The structure and materials of conductive structures 134'b-1 and 134'c-1 are substantially similar or identical to those of conductive structure 134-1 shown in FIG2P-1 , except that conductive structures 134'b-1 and 134'c-1 are wider. In some embodiments, at least one conductive structure 134'b-1 protrudes laterally from one of the sidewall surfaces of TIV 104 below conductive structure 134'b-1. In some embodiments, the bottom surface of conductive structure 134'b-1 directly contacts the top surface of encapsulant 106. In some embodiments, the conductive structure 134'c-1 protrudes laterally from one of the sidewall surfaces of the conductive via 204 below the conductive structure 134'c-1. In some embodiments, the lower surface of the conductive structure 134'c-1 directly contacts the upper surface of the substrate 202 of the semiconductor dies 30 and 40.

[0063] FIG5A is an enlarged cross-sectional view of region R_3a shown in FIG3 in some other embodiments. In some embodiments shown in FIG5A , a conductive structure 134'a-2 is formed in the heat dissipation layer 130 and electrically connected to the through-insulation vias 104 and the conductive vias 204 in the semiconductor dies 30 and 40. The structure and material of the conductive structure 134'a-2 are substantially similar or identical to those of the conductive structure 134-2 shown in FIG2P-2 , except that the conductive structure 134'a-2 is wider. In some embodiments, the spatial relationship between the conductive structure 134'a-2 and adjacent cells is the same as the spatial relationship between the conductive structure 134'a-1 and adjacent cells shown in FIG4A , and the shape of the conductive structure 134'a-2 is the same as the shape of the conductive structure 134-2 shown in FIG2P-2 . Therefore, the details of the conductive structure 134'a-2 are not repeated here.

[0064] FIG5B is an enlarged cross-sectional view of region R_3b shown in FIG3 in some other embodiments. In some embodiments shown in FIG5B , conductive structures 134'b-2 and 134'c-2 are formed in heat dissipation layer 130 and electrically connected to through-insulation vias 104 and conductive vias 204 in semiconductor dies 30 and 40, respectively. The structure and material of conductive structures 134'b-2 and 134'c-2 are substantially similar or identical to those of conductive structure 134-2 shown in FIG2P-2 , except that conductive structures 134'b-2 and 134'c-2 are wider. In some embodiments, the spatial relationship between conductive structures 134'b-2 and 134'c-2 and adjacent cells is the same as the spatial relationship between conductive structures 134'b-1 and 134'c-1 and adjacent cells shown in FIG4B , and the shapes of conductive structures 134'b-2 and 134'c-2 are the same as those of conductive structure 134-2 shown in FIG2P-2 . Therefore, the details of the conductive structures 134 ′ b - 2 and 134 ′ c - 2 are not repeated here.

[0065] FIG6 is a top view of a package structure 200 in some embodiments. In some embodiments, package structure 200 may be similar to package structure 100 described above, differing in the size of the semiconductor die. The processes and materials used to form package structure 200 may be similar or identical to those used to form package structure 100 described above, and therefore are not reiterated here.

[0066] In some embodiments, as shown in FIG6 , package structure 200 includes package components 10 and 20 and semiconductor die 40, with semiconductor die 30 replaced by semiconductor die 30a and 30b. More specifically, in some embodiments, semiconductor die 30a and 30b are each configured to connect electrical signals between one of package components 10 and one of package components 20. The functions and formation methods of semiconductor die 30a and 30b can be similar to those of semiconductor die 30 and are therefore not reiterated here.

[0067] Similar to package structure 100, heat dissipation layer 130 in package structure 200 is formed on semiconductor dies 30a, 30b, and 40. This dissipates heat generated by semiconductor dies 30a, 30b, and 40 during operation, thereby reducing device temperature. In some embodiments, heat dissipation layer 130 completely covers semiconductor dies 30a, 30b, and 40, meaning that semiconductor dies 30a, 30b, and 40 are located within the projection of heat dissipation layer 130. In some embodiments, the width of heat dissipation layer 130 in the X and Y directions may be greater than the width of semiconductor dies 30a, 30b, and 40 in the X and Y directions, respectively.

[0068] FIG7A is a top view of a package structure 300 in some embodiments. FIG7B is a cross-sectional view of the package structure 300 along the section line X7A-X7A' in FIG7A in some embodiments. In some embodiments, the package structure 300 may be similar to the package structure 100 described above, except that a semiconductor die 50 is disposed along with the semiconductor dies 30 and 40. The processes and materials used to form the package structure 300 may be similar or identical to those used to form the package structure 100 described above, and therefore will not be repeated here.

[0069] In some embodiments, as shown in FIG7A , package structure 300 includes package components 10 and 20, semiconductor dies 30 and 40, and an additional semiconductor die 50 is also located within package structure 300. Semiconductor die 50 may be configured to control the power supply of package component 10. More specifically, in some embodiments, as shown in FIG7B , semiconductor dies 30, 40, and 50 are located on a carrier substrate 102, and the processes shown in FIG2C through FIG2P may be performed to form package structure 300. In some embodiments, each semiconductor die 50 partially overlaps one of package components 10.

[0070] Similar to the package structure 100 , the heat dissipation layer 130 in the package structure 300 is formed on the semiconductor dies 30 , 40 , and 50 , so that the heat generated by the semiconductor dies 30 , 40 , and 50 during operation can be dissipated and the device temperature can be reduced.

[0071] In some embodiments, the heat dissipation layer 130 completely covers the semiconductor dies 30, 40, and 50, that is, the semiconductor dies 30, 40, and 50 are located within the projection area of the heat dissipation layer 130. In some embodiments as shown in FIG7A , the width of the heat dissipation layer 130 in the X and Y directions may be greater than the widths of the semiconductor dies 30, 40, and 50 in the X and Y directions, respectively.

[0072] FIG8 is a top view of a package structure 400 in some embodiments. In some embodiments, package structure 400 may be similar to package structure 200 described above, except for the placement of semiconductor die 50. The processes and materials used to form package structure 400 may be similar or identical to those used to form package structures 100, 200, and 300 described above, and therefore are not reiterated here.

[0073] In some embodiments, as shown in FIG8 , a package structure 400 includes package components 10 and 20 and semiconductor dies 30 a, 30 b, 40, and 50. Similar to package structure 200 , a heat dissipation layer 130 in package structure 400 is formed on semiconductor dies 30 a, 30 b, 40, and 50 to dissipate heat generated by semiconductor dies 30 a, 30 b, 40, and 50 during operation and reduce device temperature. In some embodiments, heat dissipation layer 130 completely covers semiconductor dies 30 a, 30 b, 40, and 50, meaning that semiconductor dies 30 a, 30 b, 40, and 50 are located within the projection of heat dissipation layer 130. In some embodiments, the width of heat dissipation layer 130 in the X and Y directions may be greater than the respective widths of semiconductor dies 30 a, 30 b, 40, and 50 in the X and Y directions, as shown in FIG8 .

[0074] FIG9A is a top view of a package structure 100A in some embodiments. FIG9B is a cross-sectional view of the package structure 100A along the line X9A-X9A' in some embodiments. In some embodiments, the package structure 100A may be similar to the package structure 100 described above, differing in the size of the heat dissipation layer. The process and materials used to form the package structure 100A may be similar or identical to those used to form the package structure 100 described above, and therefore will not be repeated here.

[0075] In some embodiments, as shown in FIG9A , a package structure 100A includes package components 10 and 20 and semiconductor dies 30 and 40. Furthermore, a heat dissipation layer 130A is formed on the semiconductor dies 30 and 40 to dissipate heat generated by the semiconductor dies 30 and 40 during operation and reduce device temperature. In some embodiments, the heat dissipation layer 130A completely covers the semiconductor dies 30 and 40, meaning that the semiconductor dies 30 and 40 are located within the projection of the heat dissipation layer 130A. In some embodiments, the width of the heat dissipation layer 130A in the X and Y directions may be greater than the respective widths of the semiconductor dies 30 and 40 in the X and Y directions. In some embodiments, the heat dissipation layer 130A completely covers the package component 20, meaning that the package component 20 is located within the projection of the heat dissipation layer 130A. In some embodiments, the heat dissipation layer 130A partially covers the package component 10, meaning that the package component 10 is partially located outside the projection of the heat dissipation layer 130A.

[0076] More specifically, the process shown in Figures 2A to 2L is performed to form a dielectric layer 131 on the sealant 106, and a heat dissipation layer 130A is located on the dielectric layer 131, as shown in some embodiments in Figure 9B. In addition, in some embodiments, a conductive structure 134A is formed in the dielectric layer 131.

[0077] In some embodiments, the method for forming the dielectric layer 131 and the heat dissipation layer 130A includes forming the dielectric layer 131 to cover the encapsulant 106, forming an opening in the dielectric layer 131, and forming the heat dissipation layer 130A in the opening. In some other embodiments, the method for forming the dielectric layer 131 and the heat dissipation layer 130A includes forming the heat dissipation layer 130A to cover the encapsulant 106, patterning the heat dissipation layer 130A, and forming the dielectric layer 131 around the heat dissipation layer 130A.

[0078] In some embodiments, dielectric layer 131 is composed of a dielectric material having a dielectric constant less than 7. In some embodiments, dielectric layer 131 is composed of silicon oxide, nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or the like. Dielectric layer 131 is formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes. The process and materials used to form heat dissipation layer 130A may be substantially similar or identical to the process and materials used to form conductive structure 134A described above, and therefore are not reiterated here.

[0079] In some embodiments, as shown in FIG9B , after forming dielectric layer 131 and heat dissipation layer 130A, the process shown in FIG2P may be performed to form package structure 100A. Although not clearly shown in FIG9B , in some embodiments, conductive structure 134A of package structure 100A may have a structure similar to that shown in FIG2P-1 or 2P-2.

[0080] FIG9C is a cross-sectional view of a package structure 100A′ in some embodiments. In some embodiments, package structure 100A′ may be similar to package structure 100A described above, except that its conductive structures are wider than those in package structure 100A. The processes and materials used to form package structure 100A′ may be similar or identical to those used to form package structure 100A described above, and therefore are not reiterated here. Furthermore, package structure 100A′ in some embodiments also has the layout shown in FIG9A .

[0081] More specifically, in some embodiments, the heat dissipation layer 130A is formed in the dielectric layer 131, while the conductive structures 134'a and 134'b (similar to the conductive structures 134'a and 134'b shown in FIG3 ) are formed in the heat dissipation layer 130A. Furthermore, in some embodiments, the package structure 100A' further includes a conductive structure 134A'a, which is substantially similar or identical to the conductive structure 134'a shown in FIG3 , except that the conductive structure 134A'a is formed in the dielectric layer 131. Although not clearly shown in FIG9C , the conductive structure 134A'a of the package structure 100A' may have a structure similar to that shown in FIG4A or 5A .

[0082] FIG10 is a top view of a package structure 200A in some embodiments. In some embodiments, package structure 200A may be similar to package structure 200 described above, differing in the size of the heat dissipation layer. The process and materials used to form package structure 200A may be similar or identical to those used to form package structure 200 described above, and therefore will not be repeated here.

[0083] As shown in FIG10 , in some embodiments, a package structure 200A includes package components 10 and 20 and semiconductor dies 30 a, 30 b, and 40. Furthermore, a heat dissipation layer 130A is formed on the semiconductor dies 30 a, 30 b, and 40 to dissipate heat generated by the semiconductor dies 30 a, 30 b, and 40 during operation and reduce device temperature. In some embodiments, the heat dissipation layer 130A completely covers the semiconductor dies 30 a, 30 b, and 40, meaning that the semiconductor dies 30 a, 30 b, and 40 are within the projection of the heat dissipation layer 130A. In some embodiments, the width of the heat dissipation layer 130A in the X and Y directions may be greater than the widths of the semiconductor dies 30 a, 30 b, and 40 in the X and Y directions, respectively. In some embodiments, the heat dissipation layer 130A also completely covers the package component 20, meaning that the package component 20 is within the projection of the heat dissipation layer 130A. In some embodiments, the heat dissipation layer 130A partially covers the packaging component 10 , that is, the packaging component 10 is partially located outside the projection area of the heat dissipation layer 130A.

[0084] FIG11A is a top view of a package structure 300A in some embodiments. In some embodiments, package structure 300A may be similar to package structure 300 described above, differing in the size of the heat dissipation layer. The process and materials used to form package structure 300A may be similar or identical to those used to form package structure 300 described above, and therefore will not be repeated here.

[0085] In some embodiments, as shown in FIG11A , a package structure 300A includes package components 10 and 20 and semiconductor dies 30 , 40 , and 50 . Furthermore, a heat dissipation layer 130A is formed on semiconductor dies 30 and 40 to dissipate heat generated by semiconductor dies 30 a , 30 b , and 40 during operation, thereby reducing device temperature. Meanwhile, heat dissipation layer 130A does not cover semiconductor die 50; that is, semiconductor die 50 is completely outside the projection of heat dissipation layer 130A because semiconductor die 50 generates less heat than semiconductor dies 30 and 40. In some embodiments, heat dissipation layer 130A completely covers semiconductor dies 30 and 40, while heat dissipation layer 130A does not cover semiconductor die 50.

[0086] FIG11B is a top view of a package structure 300A' in some embodiments. In some embodiments, package structure 300A' may be similar to package structure 300 described above, differing in the size of the heat dissipation layer. The process and materials used to form package structure 300A' may be similar or identical to those used to form package structure 300 described above, and therefore will not be repeated here.

[0087] In some embodiments, as shown in FIG11B , a package structure 300A′ includes package components 10 and 20 and semiconductor dies 30 , 40 , and 50 . Furthermore, a heat dissipation layer 130A′ is formed on the semiconductor dies 30 and 40 . In some embodiments, the heat dissipation layer 130A′ completely covers the semiconductor dies 30 and 40 , meaning that the semiconductor dies 30 and 40 are located within the projection of the heat dissipation layer 130A′. The heat dissipation layer 130A′ partially covers the semiconductor die 50 , meaning that the semiconductor die 50 is partially located outside the projection of the heat dissipation layer 130A′. The process and materials used to form the heat dissipation layer 130A′ may be similar or identical to the process and materials used to form the heat dissipation layer 130A described above, and therefore are not reiterated here.

[0088] FIG12A is a top view of a package structure 400A in some embodiments. In some embodiments, package structure 400A may be similar to package structure 400 described above, differing in the size of the heat dissipation layer. The process and materials used to form package structure 400A may be similar or identical to those used to form package structure 300 described above, and therefore will not be repeated here.

[0089] In some embodiments, as shown in FIG12A , a package structure 400A includes package components 10 and 20 and semiconductor dies 30 a, 30 b, 40, and 50. Furthermore, a heat dissipation layer 130A is formed on the semiconductor dies 30 a, 30 b, and 40 to dissipate heat generated by the semiconductor dies 30 a, 30 b, and 40 during operation. The heat dissipation layer 130A does not cover the semiconductor die 50 because the heat generated by the semiconductor die 50 is less than that generated by the semiconductor dies 30 a, 30 b, and 40. In some embodiments, the heat dissipation layer 130A completely covers the semiconductor dies 30 a, 30 b, and 40, meaning that the semiconductor dies 30 a, 30 b, and 40 are within the projection of the heat dissipation layer 130A. The heat dissipation layer 130A does not cover the semiconductor die 50, meaning that the semiconductor die 50 is outside the projection of the heat dissipation layer 130A.

[0090] FIG12B is a top view of a package structure 400A' in some embodiments. In some embodiments, package structure 400A' can be similar to package structure 400 described above, differing in the size of the heat dissipation layer. The process and materials used to form package structure 400A' can be similar or identical to those used to form package structure 400 described above, and therefore are not reiterated here.

[0091] In some embodiments, as shown in FIG12B , a package structure 400A′ includes package components 10 and 20 and semiconductor dies 30 a, 30 b, 40, and 50. Furthermore, a heat dissipation layer 130A′ is formed on the semiconductor dies 30 a, 30 b, and 40, and the heat dissipation layer 130A′ does not completely cover the semiconductor dies 50. In some embodiments, the heat dissipation layer 130A′ completely covers the semiconductor dies 30 a, 30 b, and 40, meaning that the semiconductor dies 30 a, 30 b, and 40 are located within the projection of the heat dissipation layer 130A′. The heat dissipation layer 130A′ partially covers the semiconductor dies 50, meaning that the semiconductor dies 50 are partially located outside the projection of the heat dissipation layer 130A′.

[0092] FIG13A is a top view of a package structure 100B in some embodiments. FIG13B is a cross-sectional view of the package structure 100B along the line X13A-X13A' in some embodiments. In some embodiments, the package structure 100B may be similar to the package structure 100 described above, differing in the size of the heat dissipation layer. The process and materials used to form the package structure 100B may be similar or identical to those used to form the package structures 100 and 100A described above, and therefore will not be repeated here.

[0093] In some embodiments, as shown in FIG13A , a package structure 100B includes package components 10 and 20 and semiconductor dies 30 and 40. Furthermore, heat dissipation layers 130B-1 and 130B-2 are formed on semiconductor dies 30 and 40, respectively, and are slightly larger than the semiconductor dies 30 and 40. This allows heat generated by the semiconductor dies 30 and 40 during operation to dissipate and reduce device temperature. In some embodiments, heat dissipation layers 130B-1 and 130B-2 completely cover the semiconductor dies 30 and 40, meaning that the semiconductor dies 30 and 40 are located within the projections of heat dissipation layers 130B-1 and 130B-2. In some embodiments, the widths of heat dissipation layers 130B-1 and 130B-2 in the X and Y directions may be greater than the widths of the semiconductor dies 30 and 40, respectively, in the X and Y directions. In some embodiments, heat dissipation layer 130B-1 partially covers package component 10. In some embodiments, heat dissipation layers 130B-1 and 130B-2 partially cover package component 20.

[0094] The process for forming heat dissipation layers 130B-1 and 130B-2 can be similar or identical to the process for forming heat dissipation layer 130A described above, with the difference being that heat dissipation layers 130B-1 and 130B-2 are primarily formed on semiconductor dies 30 and 40, respectively. In some embodiments, heat dissipation layers 130B-1 and 130B-2 are separated from each other in the X and Y directions in the top view shown in FIG13A. Although not clearly shown in FIG13B, the conductive structure 134A of the package structure 100B can have a structure similar to that shown in FIG2P-1 or 2P-2.

[0095] FIG13C is a cross-sectional view of a package structure 100B′ in some embodiments. In some embodiments, package structure 100B′ may be similar to package structure 100B described above, except that its conductive structures are wider than those in package structure 100B. The processes and materials used to form package structure 100B′ may be similar or identical to those used to form package structure 100B described above, and therefore are not reiterated here. Furthermore, package structure 100B′ in some embodiments also has the layout shown in FIG13A . More specifically, in some embodiments, heat dissipation layers 130B-1 and 130B-2 are formed in dielectric layer 131, while conductive structures 134′a and 134′b are formed in heat dissipation layers 130B-1 and 130B-2. Furthermore, in some embodiments, any heat dissipation layers 130B-1 and 130B-2 do not cover the central portion of package component 20.

[0096] FIG14 is a top view of a package structure 200B in some embodiments. In some embodiments, package structure 200B may be similar to package structure 200A described above, differing in the size of the heat dissipation layer. The process and materials used to form package structure 200B may be similar or identical to those used to form package structures 200 and 200A described above, and therefore will not be repeated here.

[0097] In some embodiments, as shown in FIG14 , heat dissipation layers 130B-1a, 130B-1b, and 130B-2 are formed on semiconductor dies 30a, 30b, and 40, respectively, and are slightly larger than semiconductor dies 30a, 30b, and 40. In some embodiments, the process for forming heat dissipation layers 130B-1a, 130B-1b, and 130B-2 can be similar or identical to the process for forming heat dissipation layer 130A described above, with the difference that heat dissipation layers 130B-1a, 130B-1b, and 130B-2 are primarily formed on semiconductor dies 30a, 30b, and 40, respectively. In some embodiments, heat dissipation layers 130B-1a, 130B-1b, and 130B-2 are separated from each other in the top view shown in FIG14 . Furthermore, in some embodiments, any heat dissipation layer 130B-1a, 130B-1b, and 130B-2 does not cover the middle portion of the package component 20.

[0098] FIG15 is a top view of a package structure 300B in some embodiments. In some embodiments, package structure 300B may be similar to package structure 300A described above, differing in the size of the heat dissipation layer. The process and materials used to form package structure 300B may be similar or identical to those used to form package structures 300 and 300A described above, and therefore will not be repeated here.

[0099] In some embodiments, as shown in FIG15 , heat dissipation layers 130B-1, 130B-2, and 130B-3 are formed on semiconductor dies 30, 40, and 50, respectively. In some embodiments, the process for forming heat dissipation layers 130B-1, 130B-2, and 130B-3 can be similar or identical to the process for forming heat dissipation layer 130A described above, with the difference that heat dissipation layers 130B-1, 130B-2, and 130B-3 are primarily formed on semiconductor dies 30, 40, and 50, respectively, and are slightly larger than semiconductor dies 30, 40, and 50. In some embodiments, heat dissipation layers 130B-1, 130B-2, and 130B-3 are separated from each other in the top view shown in FIG15 . Furthermore, in some embodiments, any heat dissipation layer 130B-1, 130B-2, and 130B-3 does not cover the middle portion of the package component 20.

[0100] FIG16 is a top view of a package structure 400B in some embodiments. In some embodiments, package structure 400B may be similar to package structure 400A described above, differing in the size of the heat dissipation layer. The process and materials used to form package structure 400B may be similar or identical to those used to form package structures 400 and 400A described above, and therefore will not be repeated here.

[0101] In some embodiments shown in FIG16 , heat dissipation layers 130B-1a, 130B-1b, 130B-2, and 130B-3 are formed on semiconductor dies 30a, 30b, 40, and 50, respectively. In some embodiments, the process for forming heat dissipation layers 130B-1a, 130B-1b, 130B-2, and 130B-3 can be similar to or the same as the process for forming heat dissipation layer 130A described above, with the difference that heat dissipation layers 130B-1a, 130B-1b, 130B-2, and 130B-3 are primarily formed on semiconductor dies 30a, 30b, 40, and 50, respectively, and are slightly larger than semiconductor dies 30a, 30b, 40, and 50. In some embodiments, heat dissipation layers 130B-1a, 130B-1b, 130B-2, and 130B-3 are separated from each other in the top view shown in FIG16 . In addition, any of the heat dissipation layers 130B-1a, 130B-1b, 130B-2, and 130B-3 of some embodiments do not cover the middle portion of the packaging component 20.

[0102] FIG17 is a top view of a package structure 100C in some embodiments. In some embodiments, package structure 100C may be similar to package structure 100 described above, differing in the shape of the heat dissipation layer. The process and materials used to form package structure 100C may be similar or identical to those used to form package structures 100, 100A, and 100B described above, and therefore will not be repeated here.

[0103] In some embodiments, as shown in FIG17 , a package structure 100C includes package components 10 and 20 and semiconductor dies 30 and 40. Furthermore, a heat dissipation layer 130C is formed on the semiconductor dies 30 and 40 to dissipate heat generated by the semiconductor dies 30 and 40 during operation and reduce device temperature. In some embodiments, the heat dissipation layer 130C completely covers the semiconductor dies 30 and 40. In some embodiments, a first portion of the heat dissipation layer 130C vertically overlaps the semiconductor die 30, a second portion of the heat dissipation layer 130C vertically overlaps the semiconductor die 40, and the first and second portions of the heat dissipation layer 130C are connected to each other.

[0104] In the top view shown in FIG17 , in some embodiments, heat dissipation layer 130C does not cover the central portion of each package component 20, and instead covers the peripheral portion of each package component 20. In some embodiments, heat dissipation layer 130C has a first width W1-17, a second width W2-17, and a third width W3-17 along the X-direction. Furthermore, in some embodiments, the second width W2-17 is greater than the first width W1-17 and the third width W3-17. In some embodiments, the first width W1-17 is greater than the third width W3-17.

[0105] In some embodiments, the heat dissipation layer 130C partially covers the package components 10 and 20. The process for forming the heat dissipation layer 130C can be similar or the same as the process for forming the heat dissipation layer 130A, except that the heat dissipation layer 130C is mainly formed on the semiconductor dies 30 and 40.

[0106] FIG18 is a top view of a package structure 200C in some embodiments. In some embodiments, package structure 200C may be similar to package structure 200A described above, differing in the shape of the heat dissipation layer. The process and materials used to form package structure 200C may be similar or identical to those used to form package structures 200, 200A, and 200B described above, and therefore will not be repeated here.

[0107] In some embodiments, as shown in FIG18 , a heat dissipation layer 130C is formed on semiconductor dies 30 a, 30 b, and 40. The process for forming heat dissipation layer 130C can be similar or identical to the process for forming heat dissipation layer 130A described above, with the difference that heat dissipation layer 130C is primarily formed on semiconductor dies 30 a, 30 b, and 40. In some embodiments, heat dissipation layer 130C completely covers semiconductor dies 30 a, 30 b, and 40. Furthermore, in some embodiments, heat dissipation layer 130C does not cover the middle portion of package component 20.

[0108] FIG19 is a top view of a package structure 300C in some embodiments. In some embodiments, package structure 300C may be similar to package structure 300A described above, differing in the shape of the heat dissipation layer. The process and materials used to form package structure 300C may be similar or identical to those used to form package structures 300, 300A, and 300B described above, and therefore are not reiterated here.

[0109] In some embodiments, as shown in FIG19 , a heat dissipation layer 130C′ is formed on semiconductor dies 30, 40, and 50. The process for forming the heat dissipation layer 130C′ can be similar or identical to the process for forming the heat dissipation layer 130A described above, with the difference being that the heat dissipation layer 130C′ is primarily formed on the semiconductor dies 30, 40, and 50. Furthermore, in some embodiments, the heat dissipation layer 130C′ does not cover the middle portion of the package component 20.

[0110] FIG20 is a top view of a package structure 400C in some embodiments. In some embodiments, package structure 400C may be similar to package structure 400A described above, differing in the shape of the heat dissipation layer. The process and materials used to form package structure 400C may be similar or identical to those used to form package structures 400, 400A, and 400B described above, and therefore are not reiterated here. In some embodiments, as shown in FIG20 , heat dissipation layer 130C′ is formed on semiconductor dies 30a, 30b, 40, and 50. Furthermore, in some embodiments, heat dissipation layer 130C′ does not cover the central portion of package component 20.

[0111] FIG21 is a top view of a package structure 300D in some embodiments. In some embodiments, package structure 300D may be similar to package structure 300 described above, differing in the shape of the heat dissipation layer. The process and materials used to form package structure 300D may be similar or identical to those used to form package structures 300, 300A, 300B, and 300C described above, and therefore are not reiterated here.

[0112] In some embodiments, as shown in FIG21 , a package structure 300D includes package components 10 and 20 and semiconductor dies 30, 40, and 50. Furthermore, in some embodiments, heat dissipation layers 130B-1 and 130B-2 are formed on semiconductor dies 30 and 40, but not on semiconductor die 50. Furthermore, in some embodiments, any heat dissipation layers 130B-1 and 130B-2 do not cover the middle portion of package component 20.

[0113] FIG22 is a top view of a package structure 400D in some embodiments. In some embodiments, package structure 400D may be similar to package structure 400 described above, differing in the shape of the heat dissipation layer. The process and materials used to form package structure 400D may be similar or identical to those used to form package structures 400, 400A, 400B, and 400C described above, and therefore will not be repeated here.

[0114] In some embodiments, as shown in FIG22 , a package structure 400D includes package components 10 and 20 and semiconductor dies 30 a, 30 b, 40, and 50. Furthermore, in some embodiments, heat dissipation layers 130B-1 a, 130B-1 b, and 130B-2 are formed on semiconductor dies 30 a, 30 b, and 40, but not on semiconductor die 50. Furthermore, in some embodiments, any heat dissipation layers 130B-1 a, 130B-1 b, and 130B-2 do not cover the middle portion of package component 20.

[0115] FIG23 is a top view of a package structure 300E in some embodiments. In some embodiments, package structure 300E may be similar to package structure 300 described above, differing in the shape of the heat dissipation layer. The process and materials used to form package structure 300E may be similar or identical to those used to form package structures 300, 300A, 300B, 300C, and 300D described above, and therefore are not reiterated here.

[0116] As shown in FIG23 , in some embodiments, a package structure 300E includes package components 10 and 20 and semiconductor dies 30, 40, and 50. Furthermore, in some embodiments, a heat dissipation layer 130C is formed on semiconductor dies 30 and 40, but not on semiconductor die 50. Furthermore, in some embodiments, the heat dissipation layer 130C does not cover the middle portion of the package component 20.

[0117] FIG24 is a top view of a package structure 400E in some embodiments. In some embodiments, package structure 400E may be similar to package structure 400 described above, differing in the shape of its heat dissipation layer. The process and materials used to form package structure 400E may be similar or identical to those used to form package structures 400, 400A, 400B, 400C, and 400D described above, and therefore are not reiterated here.

[0118] In some embodiments, as shown in FIG. 24 , a package structure 400E may also include package components 10 and 20 and semiconductor dies 30 a, 30 b, 40, and 50. Furthermore, in some embodiments, a heat dissipation layer 130C is formed on semiconductor dies 30 a, 30 b, and 40, but not on semiconductor die 50. Furthermore, in some embodiments, the heat dissipation layer 130C does not cover the middle portion of the package component 20.

[0119] As described above, semiconductor dies (such as semiconductor dies 30, 30a, 30b, 40, and 50) can be formed to be electrically connected to package components (such as package components 10 and 20) via redistribution structures (such as redistribution structures 108). However, during operation, the semiconductor dies may generate heat. Therefore, heat dissipation layers (such as heat dissipation layers 130, 130A, 130A', 130B-1, 130B-2, 130B-1a, 130B-1b, 130B-3, 130C, and 130C') are formed on the semiconductor dies to laterally diffuse (i.e., dissipate) the heat generated by the semiconductor dies. In summary, the temperature of the package structure (particularly the hot spots around the semiconductor dies) can be reduced, thereby improving the performance of the package structure.

[0120] It should be understood that the units shown in the package structures 100, 100', 200, 300, 400, 100A, 100A', 200A, 300A, 300A', 400A, 400A', 100B, 100B', 200B, 300B, 400B, 100C, 100C', 200C, 300C, 400C, 300D, 400D, 300E, and 400E may be combined and / or interchanged. For example, the heat dissipation layer formed in the packaging structure (such as heat dissipation layers 130, 130A, 130A', 130B-1, 130B-2, 130B-1a, 130B-1b, 130B-3, 130C, and 130C') may have the structure shown in Figures 2P-1, 2P-2, 4A, 4B, 5A, or 5B, but the layout of the packaging structure may be different.

[0121] It is also worth noting that identical elements in Figures 1A through 24 may be designated by identical reference numerals and may comprise identical or similar materials and be formed by identical or similar processes. Therefore, detailed descriptions thereof are omitted for simplicity. Furthermore, while the descriptions of Figures 1A through 24 relate to a method, it should be understood that the structures illustrated in Figures 1A through 24 are not limited to the method and may exist independently of the method. Similarly, the methods illustrated in Figures 1A through 24 are not limited to the disclosed structures and may exist independently of the structures.

[0122] Furthermore, while the methods described above are described as a series of steps or events, it should be understood that some other embodiments may vary the order of these steps or events. For example, some steps may be performed in a different order and / or concurrently with other steps, rather than in the order described herein. Furthermore, not all steps need to be performed in one or more embodiments described herein. Furthermore, one or more steps described herein may be performed in one or more separate steps and / or aspects.

[0123] Furthermore, the terms "approximately," "substantially," "substantially," and "about" may vary slightly between technologies and are within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or circumstance, these terms may refer to both an exact example of the event or circumstance and an example that is very similar to the event or circumstance.

[0124] Embodiments of a packaging structure are provided. The packaging structure may include a packaging component and a semiconductor die located on opposite sides of a redistribution structure. Furthermore, a heat dissipation layer is formed on the semiconductor die, allowing heat generated by the semiconductor die to be dissipated laterally through the heat dissipation layer. In summary, the device temperature during operation can be reduced, thereby improving performance.

[0125] One embodiment of the present invention provides a packaging structure. The packaging structure includes a first redistribution structure; a first packaging component and a second packaging component attached to a first side of the first redistribution structure and separated from each other in a first direction. The packaging structure further includes a first semiconductor die attached to a second side of the first redistribution structure; and an encapsulant formed around the first semiconductor die. The packaging structure further includes a heat sink layer formed on the first semiconductor die, wherein the heat sink layer has a thermal conductivity greater than that of the encapsulant. The packaging structure further includes a conductive structure extending through the heat sink layer; and a second redistribution structure formed on the heat sink layer. Furthermore, the second redistribution structure is electrically connected to the first semiconductor die via the conductive structure.

[0126] In some embodiments, the heat dissipation layer is composed of graphene or diamond-like carbon.

[0127] In some embodiments, the first semiconductor die overlaps with the first sidewall of the first packaging component and the first sidewall of the second packaging component in a top view.

[0128] In some embodiments, the packaging structure further includes a second semiconductor die adhered to the second side of the first redistribution structure; and a third packaging component adhered to the first side of the first redistribution structure, and the third packaging component and the second packaging component are separated from each other in a first direction, wherein the second semiconductor die overlaps with the second side wall of the second packaging component, the second side wall of the third packaging component, and the heat dissipation layer.

[0129] In some embodiments, the heat dissipation layer continuously extends from the first semiconductor die to the second semiconductor die.

[0130] In some embodiments, the heat dissipation layer has a first portion for covering the first semiconductor die and a second portion for covering the second semiconductor die, and the first portion and the second portion are separated in a first direction.

[0131] In some embodiments, the packaging structure further includes a through-insulation layer via, which is attached to the second side of the first redistribution structure, and the sealant surrounds the through-insulation layer via; and a second conductive structure that passes through the heat dissipation layer and contacts the through-insulation layer via.

[0132] In some embodiments, the width of the second conductive structure in the first direction is greater than the width of the through-insulation via.

[0133] One embodiment of the present invention provides a packaging structure. The packaging structure includes a first semiconductor die having a first projected area in a top view; and a first redistribution structure attached to a first side of the first semiconductor die. The packaging structure further includes a heat dissipation layer attached to a second side of the first semiconductor die, the heat dissipation layer having a second projected area in a top view, and the second projected area of the heat dissipation layer is larger than the first projected area of the first semiconductor die. The packaging structure further includes a second redistribution structure formed on the heat dissipation layer; and a conductive structure passing through the heat dissipation layer and electrically connecting the first semiconductor die and the second redistribution structure. The packaging structure further includes a first packaging component and a second packaging component attached to the first redistribution structure. In addition, the first semiconductor die partially overlaps with the first packaging component and the second packaging component.

[0134] In some embodiments, a first projection area of the first semiconductor die is within a second projection area of the heat dissipation layer, and portions of the first packaging component and the second packaging component are located outside the second projection area of the heat dissipation layer.

[0135] In some embodiments, the second projection area of the heat dissipation layer has a first width and a second width along the first direction, and the first width is different from the second width.

[0136] In some embodiments, the packaging structure further includes a third packaging component and a fourth packaging component adhered to the first redistribution structure, wherein the first packaging component, the second packaging component, and the third packaging component are aligned in a first direction, the fourth packaging component and the second packaging component are aligned in a second direction, and the second direction is different from the first direction; the second semiconductor die is adhered to the first redistribution structure and overlaps with the second packaging component and the third packaging component; and the third semiconductor die is adhered to the first redistribution structure and overlaps with the second packaging component and the fourth packaging component, wherein the first semiconductor die, the second semiconductor die, and the third semiconductor die are located in the second projection area of the heat dissipation layer in the top view.

[0137] In some embodiments, the packaging structure further includes a fifth packaging component adhered to the first redistribution structure, wherein the fifth packaging component is aligned with the first packaging component in the second direction, and the fifth packaging component is located in the second projection area of the heat dissipation layer in the top view and partially overlaps with the first projection area of the first semiconductor grain.

[0138] In some embodiments, the packaging structure further includes a fourth semiconductor die adhered to the first redistribution structure and separated from the first semiconductor die in a first direction, wherein the fourth semiconductor die is located outside the second projection area of the heat dissipation layer in a top view and vertically overlaps with the first packaging component.

[0139] In some embodiments, the heat dissipation layer is formed in the dielectric layer.

[0140] One embodiment of the present invention provides a method for forming a packaging structure. The method includes placing a first semiconductor die on a first carrier substrate; and forming a first redistribution structure on a first side of the first semiconductor die. The method further includes placing a first packaging component and a second packaging component on the first redistribution structure. Furthermore, the first packaging component and the second packaging component are separated in a first direction. The method further includes attaching a second carrier substrate to the first packaging component and the second packaging component, and removing the first carrier substrate from the second side of the first semiconductor die. The method further includes forming a heat dissipation layer to cover the second side of the first semiconductor die, the heat dissipation layer being composed of a carbon-containing material, and the width of the heat dissipation layer in the first direction being greater than the width of the first semiconductor die. The method further includes forming a first conductive structure to pass through the heat dissipation layer, and forming a second redistribution structure to cover the heat dissipation layer and the first conductive structure.

[0141] In some embodiments, the method further includes forming an opening through the heat dissipation layer, wherein the opening exposes a through hole in the first semiconductor die, and a first conductive structure is formed in the opening.

[0142] In some embodiments, the method further includes forming a through-insulation layer via on the first carrier substrate; and forming a sealant around the through-insulation layer via and the first semiconductor die, wherein the sealant is sandwiched between the heat dissipation layer and the first redistribution structure.

[0143] In some embodiments, the method further includes forming a second conductive structure in the heat dissipation layer, wherein the second conductive structure directly contacts the arc-shaped upper surface of the through-insulation via.

[0144] In some embodiments, the method further includes placing a second semiconductor die, a third semiconductor die, and a fourth semiconductor die on a first carrier substrate, wherein the first semiconductor die, the second semiconductor die, the third semiconductor die, and the fourth semiconductor die vertically cover a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall of the first packaging component, respectively, and a heat dissipation layer covers the first semiconductor die, the second semiconductor die, the third semiconductor die, and the fourth semiconductor die.

[0145] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, and modifications may be made without departing from the spirit and scope of the present invention.

[0146] R_2N,R_2O,R_2P,R_3a,R_3b: Region W 1-17: First width W 2-17: Second width W 3-17: Third width X 1C-X 1C',X 7A-X 7A',X 9A-X 9A',X 13A-X 13A': Section line 10,20: Encapsulation components 30,30a,30b,40,50: semiconductor grains 100,100',100A,100A',100B,100B',100C,100C',200,200A,200B,200C,300,300A,300A',300B,300C,300D,300E,400,400A,400A',400B,400C,400D,400E: Package structure 102,124: Carrier substrate 104: Through-insulation hole 106,122:Sealants 108,140: Rewiring structure 110,142:Insulation layer 112,144: Rewiring layer 114,118: Conductive pad 116,146,212: Conductive connector 120: bottom fill layer 126: Cleaning process 130,130A,130A',130B-1,130B-2,130B-1a,130B-1b,130B-3,130C,130C': heat dissipation layer 131,208: Dielectric layer 132: Opening 134,134-1,134-2,134'a,134'a-1,134'a-2,134'b,134'b-1,134'b-2,134'c,134'c-1,134'c-2,134A,134A'a,210: Conductive structure 134-1T: Tip part 148: Conductive column 150:Solder balls 202:Substrate 204: conductive through hole 206:Internal connection structure

Claims

1. A packaging structure, comprising: First layer of wiring structure; A first packaging component and a second packaging component are attached to a first side of the first rewiring structure and separated from each other in a first direction; a first semiconductor die and a second semiconductor die are attached to a second side of the first rewiring structure; a sealant is formed around the first semiconductor die and the second semiconductor die; a heat dissipation layer is formed on the first semiconductor die but not on the second semiconductor die, wherein the thermal conductivity of the heat dissipation layer is greater than that of the sealant; a conductive structure passes through the heat dissipation layer; and a second rewiring structure is formed on the heat dissipation layer, wherein the second rewiring structure is electrically connected to the first semiconductor die via the conductive structure.

2. The packaging structure as described in claim 1, wherein the heat dissipation layer is composed of graphene or diamond-like carbon.

3. The packaging structure as described in claim 1 or 2, wherein the first semiconductor die overlaps with the first sidewall of the first packaging member and the first sidewall of the second packaging member in the top view.

4. The encapsulation structure as described in claim 3, further comprising: A third encapsulation component is attached to a first side of the first rewiring structure, and the third encapsulation component is separated from the second encapsulation component in the first direction.

5. A packaging structure, comprising: A first semiconductor die, having a first projection area in the top view; a second semiconductor die; A first rewiring structure is attached to a first side of the first semiconductor die and the second semiconductor die; a heat dissipation layer is attached to a second side of the first semiconductor die but not to a second side of the second semiconductor die, wherein the heat dissipation layer has a second projection area in the top view, and the second projection area of ​​the heat dissipation layer is larger than the first projection area of ​​the first semiconductor die; a second rewiring structure is formed on the heat dissipation layer; a conductive structure passes through the heat dissipation layer and electrically connects the first semiconductor die and the second rewiring structure; and a first packaging member and a second packaging member are attached to the first rewiring structure, wherein the first semiconductor die partially overlaps with the first packaging member and the second packaging member.

6. The packaging structure as claimed in claim 5, wherein the first projection area of ​​the first semiconductor die is in the second projection area of ​​the heat dissipation layer, and portions of the first packaging member and the second packaging member are located outside the second projection area of ​​the heat dissipation layer.

7. The packaging structure as described in claim 5 or 6, wherein the second projection area of ​​the heat dissipation layer has a first width and a second width along a first direction, and the first width is different from the second width.

8. A method for forming a packaging structure, comprising: A first semiconductor die and a second semiconductor die are placed on a first carrier substrate; A first rewiring structure is formed on a first side of the first semiconductor die and the second semiconductor die; a first packaging component and a second packaging component are placed on the first rewiring structure, wherein the first packaging component and the second packaging component are separated in a first direction; a second carrier substrate is attached to the first packaging component and the second packaging component; the first carrier substrate is removed from a second side of the first semiconductor die and the second semiconductor die; a heat dissipation layer is formed to cover the second side of the first semiconductor die but not the second side of the second semiconductor die, wherein the heat dissipation layer is composed of a carbon-containing material, and the width of the heat dissipation layer in the first direction is greater than the width of the first semiconductor die; a first conductive structure is formed to pass through the heat dissipation layer; and a second rewiring structure is formed to cover the heat dissipation layer and the first conductive structure.

9. The method of forming the packaging structure as described in claim 8 further includes: An opening is formed through the heat dissipation layer, wherein the opening exposes a through-hole in the first semiconductor die, and the first conductive structure is formed in the opening.

10. The method of forming the packaging structure as described in claim 8 or 9 further includes: A through-insulation layer via is formed on the first carrier substrate; and a sealant is formed around the through-insulation layer via and the first semiconductor die, wherein the sealant is sandwiched between the heat dissipation layer and the first rewiring structure.

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