Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures located above a substrate and a plurality of second nanostructures adjacent to the first nanostructures. The semiconductor structure includes a protective layer located above the first nanostructures and a first gate structure formed above the first nanostructures. The semiconductor structure includes a second gate structure formed on the second nanostructures. The semiconductor structure includes a first dielectric wall layer located between the first gate structure and the second gate structure, wherein the upper surface of the first dielectric wall layer is higher than the upper surface of the protective layer.

Description

Semiconductor structure and method for forming the same Embodiments of the present invention relate to a semiconductor technology, and more particularly to a semiconductor structure and a method for forming the same. The electronics industry is experiencing a growing demand for smaller and faster electronic devices capable of performing a multitude of increasingly complex and sophisticated functions. Consequently, there is a continuing trend within the semiconductor industry toward manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking semiconductor IC dimensions (e.g., minimum feature size), thereby increasing production efficiency and reducing associated costs. However, this miniaturization has introduced greater complexity to the semiconductor manufacturing process. Consequently, achieving continued advancements in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies. Recently, multi-gate devices have been introduced in an attempt to improve gate control, reduce off-state current, and mitigate short-channel effects (SCE) by increasing gate-channel coupling. However, the integration of multi-gate devices can be challenging. In some embodiments, a semiconductor structure is provided, comprising: a plurality of first nanostructures located above a substrate and a plurality of second nanostructures adjacent to the first nanostructures. The semiconductor structure includes a protective layer located above the first nanostructures and a first gate structure formed on the first nanostructures. The semiconductor structure includes a second gate structure formed on the second nanostructures. The semiconductor structure includes a first dielectric wall layer located between the first gate structure and the second gate structure, wherein the upper surface of the first dielectric wall layer is higher than the upper surface of the protective layer. In some embodiments, a semiconductor structure is provided, comprising: a plurality of first nanostructures located above a substrate and a plurality of second nanostructures adjacent to the first nanostructures. The semiconductor structure includes a first protective layer located above the first nanostructures and a first gate structure formed on the first and second nanostructures. The semiconductor structure also includes a first dielectric wall layer located between the first and second nanostructures, with the upper surface of the first gate structure being higher than the upper surface of the first dielectric wall layer. In some embodiments, a method for forming a semiconductor structure is provided, comprising: forming a first fin structure and a second fin structure above a substrate, the first fin structure comprising alternating layers of a first semiconductor material and a second semiconductor material, and the second fin structure comprising alternating layers of a first semiconductor material and a second semiconductor material. The method includes forming a first protective layer on the first fin structure and a second protective layer on the second fin structure, and forming a dummy gate structure spanning the first and second fin structures. The method also includes forming a first spacer layer and a second spacer layer on sidewall surfaces of the dummy gate structure, and removing a portion of the dummy gate structure to expose the first spacer layer. The method also includes removing a portion of the first spacer layer to expose a portion of the second spacer layer, and removing a portion of the first semiconductor material layer to form a first nanostructure and a second nanostructure. The method also includes forming a gate dielectric layer on the first and second nanostructures, with the gate dielectric layer being located on the first and second spacer layers. The method includes forming a gate electrode layer on the gate dielectric layer and removing a portion of the gate electrode layer. The method includes removing a portion of the gate dielectric layer to expose a second spacer layer and forming a dielectric spacer layer between the first nanostructure and the second nanostructure. The following disclosure provides many different embodiments or examples to implement the different characteristic components of the present invention. The following disclosure describes specific examples of each component and its arrangement in order to simplify the disclosure. Of course, these are only examples and are not used to define the present invention. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which additional characteristic components can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the disclosure will repeat numbers and / or text in each different example. The repetition is for the purpose of simplicity and clarity, rather than to list the relationship between the different embodiments and / or configurations being discussed. Some variations of embodiments of the present invention are described below. Similar reference numerals are used to designate similar elements throughout the various views and illustrative embodiments. It should be understood that additional operations may be provided before, during, and after this method, and that some of the operations described may be replaced or removed for other embodiments of this method. The gate all around (GAA) transistor structure described below can be patterned by any suitable method. For example, the structure can be patterned using one or more optical lithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine optical lithography and self-alignment processes, allowing the formation of patterns having, for example, a smaller pitch than that obtainable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern out the gate all around (GAA) structure. The fins described below can be patterned using any suitable method. For example, the fins can be patterned using one or more optical lithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine optical lithography and self-alignment processes, allowing the formation of patterns with, for example, smaller pitches than can be achieved using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fins. The following provides an embodiment of a semiconductor structure and a method for forming the same. The semiconductor structure includes a first nanostructure and a second nanostructure formed above a substrate. A protective layer is formed on the first nanostructure and the second nanostructure to protect the first nanostructure and the second nanostructure. A gate structure is formed on the nanostructure, and a first spacer layer and a second spacer layer are formed on opposite sidewall surfaces of the gate structure. A dielectric wall layer is located between the first nanostructure and the second nanostructure. Because a portion of the gate electrode layer of the gate structure is replaced by the dielectric wall layer, the area of ​​the gate electrode layer is reduced. Unnecessary capacitance between the gate structure and the source / drain (S / D) contact structure of the semiconductor structure is reduced. In addition, due to the protection of the protective layer, each nanostructure has substantially the same thickness. When the thickness uniformity of each nanostructure is improved, the performance of the semiconductor structure can be improved. The source / drain (S / D) structure or source / drain (S / D) region may be individually or collectively referred to as a source or a drain, depending on the context. 1A to 12B are perspective views illustrating intermediate stages of forming a semiconductor structure 100 a according to some embodiments. Referring to FIG. 1A , a first semiconductor material layer 106 and a second semiconductor material layer 108 are formed along a first direction (e.g., the x-axis) over a substrate 102. Next, a protective layer 110 and a hard mask layer 112 are formed over the first semiconductor material layer 106 and the second semiconductor material layer 108. The second semiconductor material layer 108 includes an uppermost second semiconductor material layer 108T. The thickness of the uppermost second semiconductor material layer 108T is smaller than that of the other second semiconductor material layers 108. Because the thickness of the uppermost second semiconductor material layer 108T is very small, the uppermost second semiconductor material layer 108T is removed along with the first semiconductor material layer 106 in the step of FIG. 1R . The substrate 102 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 102 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In some embodiments, first semiconductor material layers 106 and second semiconductor material layers 108 are alternately stacked above substrate 102. In some embodiments, first semiconductor material layers 106 and second semiconductor material layers 108 are made of different semiconductor materials. In some embodiments, first semiconductor layer 106 is made of silicon germanium (SiGe), and second semiconductor layer 108 is made of silicon (Si). In some embodiments, the first semiconductor layer 106 and the second semiconductor layer 108 each include silicon (Si), germanium (Ge), silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), or other suitable materials. The first semiconductor layer 106 and the second semiconductor layer 108 are made of different materials with different lattice constants. In some embodiments, the first semiconductor layer 106 is made of silicon (Si), and the second semiconductor layer 108 is made of silicon germanium (SiGe). In some embodiments, each first semiconductor layer 106 has a thickness in the range of approximately 3 nm to 8 nm. In some embodiments, each second semiconductor layer 108 has a thickness in the range of approximately 3 nm to 8 nm. In some embodiments, the thickness of the topmost second semiconductor material layer 108T is in the range of approximately 1 nm to 2 nm. It should be noted that although four first semiconductor material layers 106 and four second semiconductor material layers 108 are formed, the semiconductor structure may include more or fewer first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure may include two to five first semiconductor material layers 106 and second semiconductor material layers. The first semiconductor material layer 106 and the second semiconductor material layer 108 can be formed by low-pressure chemical vapor deposition (LPCVD), epitaxial growth processes, other suitable methods, or combinations thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE). The protective layer 110 has a high etch selectivity relative to the first semiconductor material layer 106. When the first semiconductor material layer 106 is removed, the protective layer 110 is not removed in the step of Figure 1R. In some embodiments, the protective layer 110 is made of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or other suitable materials. The protective layer 110 can be formed by thermal oxidation or chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the thickness of the protective layer 110 is approximately in the range of 2 nm to 20 nm. In some embodiments, the thickness of the protective layer 110 is greater than the thickness of the first semiconductor material layer 106 and the thickness of the second semiconductor material layer 108. In some embodiments, the hard mask layer 112 is made of silicon nitride (SiN) and formed by chemical vapor deposition (CVD), such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). Next, as shown in FIG. 1B , according to some embodiments, the hard mask layer 112 is patterned to form a patterned hard mask layer 112. The protective layer 110 is then patterned using the patterned hard mask layer 112 as a mask. According to some embodiments, after patterning the protective layer 110, the semiconductor material stack is patterned to form the fin structures 104 a / 104 b / 104 c. In some embodiments, the fin structures 104 a / 104 b / 104 c include a base fin structure 105 and a semiconductor material stack consisting of a first semiconductor material layer 106 and a second semiconductor material layer 108. 1B-T illustrate top views of a semiconductor structure 100 a at intermediate stages according to some embodiments, and block A1 shown in FIG. 1B-T corresponds to the structure in FIG. 1B . The hard mask layer 112 and the protective layer 110 are patterned through a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process. Then, as shown in FIG. 1C , according to some embodiments, after forming the fin structures 104 a / 104 b / 104 c, an isolation material 115 is formed on the hard mask layer 112 and the protective layer 110. Next, a planarization process is performed on the isolation material 115 until the hard mask layer 112 is exposed. Thus, the upper surface of the isolation material 115 is substantially coplanar with the upper surface of the hard mask layer 112. In some embodiments, isolation material 115 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, isolation material 115 is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), another suitable method, or a combination thereof. 1D , according to some embodiments, the hard mask layer 112 is removed to expose the protection layer 110. In some embodiments, the hard mask layer 112 is removed by an etching process (eg, dry etching or wet etching). 1E , according to some embodiments, after removing the hard mask layer 112, the top portion of the isolation material 115 is removed to form an isolation structure 116. The upper surface of the isolation structure 116 is lower than the upper surface of the fin structures 104a / 104b / 104c. According to some embodiments, the isolation structure 116 is used to electrically isolate the active regions (eg, the fin structures 104 a / 104 b / 104 c ) of the semiconductor structure 100 a and is also referred to as a shallow trench isolation (STI) feature. In some embodiments, the isolation structure 116 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, a dielectric liner (not shown) is formed before forming the isolation structure 116. The dielectric liner is made of silicon nitride, and the isolation structure formed over the dielectric liner is made of silicon oxide. As shown in FIG. 1F , according to some embodiments, after forming the isolation structure 116, a dummy gate structure 118 is formed across the fin structures 104a / 104b / 104c and extends above the isolation structure 116. The dummy gate structure 118 can be used to define the source / drain (S / D) regions and the channel region of the resulting semiconductor structure 100a. The dummy gate structure 118 is formed along the Y-axis. 1F-T illustrate top views of a semiconductor structure at an intermediate stage according to some embodiments, and block A1 shown in FIG1F-T corresponds to the structure shown in FIG1F . In some embodiments, the dummy gate structure 118 includes a dummy gate dielectric layer 120 and a dummy gate electrode layer 122. In some embodiments, the dummy gate dielectric layer 120 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO 2. HfZrO, HfSiO, HfTiO, HfAlO, or a combination thereof. In some embodiments, the dummy gate dielectric layer 120 is formed using thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), another suitable method, or a combination thereof. In some embodiments, the dummy gate electrode layer 122 includes polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal, or a combination thereof. In some embodiments, the dummy gate electrode layer 122 is formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination thereof. The formation of the dummy gate structure 118 may include conformally forming a dielectric material as a dummy gate dielectric layer 120. Subsequently, a conductive material may be formed over the dielectric material as a dummy gate electrode layer 122, and a hard mask layer (not shown) may be formed over the conductive material. Next, the dielectric material and the conductive material may be patterned through the hard mask layer (not shown) to form the dummy gate structure 118. As shown in FIG. 1G , according to some embodiments, after forming the dummy gate structure 118, a first gate spacer layer 126 and a second gate spacer layer 128 are formed along two opposite sidewalls of the dummy gate structure 118 and cover the two opposite sidewalls, and also cover two opposite sidewalls of the source / drain regions of the fin structures 104 a / 104 b / 104 c. The first gate spacer layer 126 and the second gate spacer layer 128 may be used to separate the source / drain (S / D) structure from the dummy gate structure 118 and support the dummy gate structure 118. The first gate spacer layer 126 and the second gate spacer layer 128 may be used to limit the lateral growth of the subsequently formed source / drain structure and support the fin structures 104a / 104b / 104c. The first gate spacer layer 126 and the second gate spacer layer 128 are made of different materials. The second gate spacer layer 128 has a high etching selectivity relative to the first gate spacer layer 126. When the first gate spacer layer 126 is removed by an etching process, the second gate spacer layer 128 is not removed by the etching process. In some embodiments, the first gate spacer layer 126 is made of a dielectric material, such as silicon oxide (SiO 2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxide carbonitride (SiOCN), and / or combinations thereof. In some embodiments, the second gate spacer layer 128 is made of a dielectric material, such as silicon oxide (SiO 2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon oxide carbonitride (SiOCN), and / or combinations thereof. In some embodiments, the thickness of the first gate spacer layer 126 is approximately in a range of 1 nm to 5 nm. In some embodiments, the thickness of the second gate spacer layer 128 is approximately in a range of 1 nm to 5 nm. The formation of the first gate spacer layer 126 and the second gate spacer layer 128 may include conformally depositing a dielectric material to cover the dummy gate structure 118, the protective layer 110, the fin structure 104a / 104b / 104c and the isolation layer 116 located on the substrate 102, and performing an anisotropic etching process (e.g., dry plasma etching) to remove the dielectric layer covering the upper surface of the dummy gate structure 118, the protective layer 110 and the local isolation structure 116. Next, as shown in FIG. 1H , according to some embodiments, after forming the first gate spacer layer 126 and the second gate spacer layer 128, the source / drain (S / D) regions of the fin structures 104a / 104b / 104c are recessed to form source / drain (S / D) grooves 130. More specifically, according to some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 not covered by the dummy gate structure 118, the first gate spacer layer 126, and the second gate spacer layer 128 are removed. In some embodiments, the fin structures 104 a / 104 b / 104 c are recessed by performing an etching process. The etching process may be an anisotropic etching process, such as a dry plasma etch, and the dummy gate structure 118 , the first gate spacer layer 126 , and the second gate spacer layer 128 are used as an etching mask during the etching process. In some embodiments, the first gate spacer layer 126 and the second gate spacer layer 128 in the source / drain (S / D) region are also recessed to form a lowered first gate spacer layer 126 and a lowered second gate spacer layer 128 . Thereafter, as shown in FIG. 1I , according to some embodiments, the first semiconductor material layer 106 exposed through the source / drain (S / D) groove 130 is laterally recessed to form a notch 132 . In some embodiments, an etching process is performed on the semiconductor structure 100a to laterally recess the first semiconductor material layer 106 of the fin structures 104a / 104b / 104c from the source / drain recesses 130. In some embodiments, during the etching process, the first semiconductor material layer 106 has a greater etch rate (or etch amount) than the second semiconductor material layer 108, thereby forming a notch 132 between adjacent second semiconductor material layers 108. 1J , according to some embodiments, an inner spacer layer 134 is formed in the recess 132 between the second semiconductor material layers 108. In some embodiments, since the protection layer 110 and the inner spacer layer 134 are formed in different steps, the inner spacer layer 134 and the protection layer 110 are made of different materials. According to some embodiments, the internal spacer layer 134 is used to separate the source / drain structure and the gate structure formed in subsequent manufacturing processes. In some embodiments, the inner spacer layer 134 is made of a dielectric material, such as silicon oxide (SiO 2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN). In some embodiments, the inner spacer layer 134 is formed by a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, another suitable process, or a combination thereof. Next, as shown in FIG. 1K , according to some embodiments, after forming the inner spacer layer 134, a source / drain (S / D) structure 136 is formed within the source / drain (S / D) recess 130. The uppermost surface of the protection layer 110 is higher than the uppermost surface of the source / drain (S / D) structure 136. Furthermore, the lowermost surface of the protection layer 110 is higher than the uppermost surface of the source / drain (S / D) structure 136. In some embodiments, the source / drain (S / D) structure 136 is formed using an epitaxial growth process, such as molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), another suitable epitaxial growth process, or a combination thereof. In some embodiments, the source / drain (S / D) structure 136 is made of any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof. In some embodiments, the source / drain (S / D) structure 136 is doped in situ during the epitaxial growth process. For example, the source / drain (S / D) structure 136 may be epitaxially grown SiGe doped with boron (B). For example, the source / drain (S / D) structure 136 may be epitaxially grown Si doped with carbon to form a silicon:carbon (Si:C) source / drain (S / D) feature; epitaxially grown Si doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain (S / D) feature; or epitaxially grown Si doped with carbon and phosphorus to form a silicon carbon phosphorus (SiCP) source / drain (S / D) feature. In some embodiments, the doping of the source / drain (S / D) structure 136 is performed in one or more implantation processes after the epitaxial growth process. 1L , according to some embodiments, after forming the source / drain (S / D) structure 136, an etch stop layer 138 is conformally formed to cover the source / drain (S / D) structure 136, and an interlayer dielectric (ILD) layer 140 is formed above the contact etch stop layer 138. In some embodiments, etch stop layer 138 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material used for etch stop layer 138 can be conformally deposited over the semiconductor structure by chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof. In some embodiments, etch stop layer 138 has a thickness in a range of approximately 1 nm to 5 nm. The interlayer dielectric (ILD) layer 140 may include a multilayer structure made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and / or other suitable low-k dielectric materials. The ILD layer 140 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. According to some embodiments, after depositing the etch stop layer 138 and the interlayer dielectric (ILD) layer 140, a planarization process (e.g., chemical mechanical polishing (CMP) or an etch-back process) may be performed until the dummy gate layer 120 of the dummy gate structure 118 is exposed, as shown in FIG. 1I . Figures 1M-1ZB illustrate schematic perspective views of the semiconductor structure 100a along line AA' in Figure 1L along the dummy gate structure 118 according to some embodiments. Figures 1M-T illustrate schematic top views of the semiconductor structure 100a at intermediate stages according to some embodiments, and block B1 shown in Figures 1M-T corresponds to the structure shown in Figure 1M. As shown in FIG. 1M , according to some embodiments, a dummy gate structure 118 including a dummy gate dielectric layer 120 and a dummy gate electrode layer 122 is formed on the fin structures 104 a / 104 b / 104 c . Next, as shown in FIG. 1N , according to some embodiments, a portion of the dummy gate structure 118 is removed to form a trench 141. More specifically, the top portion of the dummy gate electrode layer 122 and a portion of the dummy gate dielectric layer 120 are removed using the protective layer 110 as an etch stop layer. Alternatively, a portion of the protective layer 110 may be removed. In some other embodiments, the protective layer 110 is not removed. When part of the dummy gate electrode layer 122 is removed, the fin structure 104a / 104b / 104c protected by the protective layer 110 is not removed. In this way, the upper surface of the isolation structure 116 is exposed. In addition, the sidewall surface of the fin structure 104a / 104b / 104c is exposed. Since the protective layer 110 protects the film layer located below, the groove 141 is formed in a self-aligned manner. If there is no protective layer on the fin structure 104a / 104b / 104c, the fin structure 104a / 104b / 104c will be damaged due to the overlay offset (misalignment) of the optical lithography during the etching process for forming the groove 141. The overlay offset (misalignment) can be solved by forming the protective layer 110. Next, as shown in FIG. 10 , according to some embodiments, a liner layer 143 and a filling layer 144 are formed into the trench 141. The dielectric wall layer 142 is formed by the liner layer 143 and the filling layer 144. The liner layer 143 directly contacts the protection layer 110, the first semiconductor layer 106, and the second semiconductor layer 108 of the fin structures 104 a / 104 b / 104 c. It should be noted that dielectric wall layer 142 is located between two adjacent fin structures, specifically, between fin structure 104a and fin structure 104b. Furthermore, dielectric wall layer 142 penetrates protective layer 110. Protective layer 110 directly contacts liner 143 of dielectric wall layer 142. Dielectric wall layer 142 has a top and a bottom, with the top being wider than the bottom. Dielectric wall layer 142 has a T-shaped structure. Since a portion of protective layer 110 has been removed as shown in FIG. 1N , a portion of dielectric wall layer 142 is buried within protective layer 110. In some embodiments, the liner 143 is made of silicon oxide (SiO), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or a suitable material. In some embodiments, the liner 143 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, the filler layer 144 is made of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or a combination thereof. In some embodiments, the filler layer 144 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. Next, as shown in FIG. 1P , according to some embodiments, another portion of the dummy gate electrode layer 122 of the dummy gate structure 118 is removed to form a trench 147 . Thus, the trench 147 exposes a portion of the first gate spacer layer 126 . More specifically, a portion of the gate electrode layer 122 is removed through a removal process. This exposes a portion of the dummy gate dielectric layer 120. It should be noted that when a portion of the dummy gate structure 118 is removed, the dielectric wall layer 142 including the liner layer 143 and the filling layer 144 is not removed. The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 122 is polysilicon, a wet etchant (eg, tetramethylammonium hydroxide (TMAH) solution) may be used to selectively remove the dummy gate electrode layer 122 . Then, as shown in FIG. 1Q , according to some embodiments, the exposed first gate spacer layer 126 is removed to expose a portion of the second gate spacer layer 128. After the removal process, the outer sidewall surface of the first gate spacer layer 126 is substantially flush with the outer sidewall surface of the dummy gate dielectric layer 122. In some embodiments, the exposed first gate spacer layer 126 is removed by an etching process (e.g., a dry etching process or a wet etching process). 1R , according to some embodiments, the exposed dummy gate dielectric layer 120 is removed. Thereafter, according to some embodiments, the first semiconductor material layer 106 is removed to form a nanostructure 108 ′ composed of the second semiconductor material layer 108 . Because the thickness of the topmost second semiconductor material layer 108T is smaller than that of the other second semiconductor material layers 108, the topmost second semiconductor material layer 108T is removed together with the first semiconductor material layer 106. This exposes the top, bottom, and sidewall surfaces of the protective layer 110. The dummy gate dielectric layer 120 can be removed using plasma dry etching, dry chemical etching, and / or wet etching. It should be noted that when the first semiconductor material layer 106 is removed, the protection layer 110 is not removed because the protection layer 110 has a high etching selectivity relative to the first semiconductor material layer 106 . The nanostructure 108' serves as a channel layer of the semiconductor structure 100a. The source / drain (S / D) structure 136 is connected to the nanostructure 108'. In addition, when the first semiconductor material layer 106 is removed, a portion of the liner 143 is exposed. It should be noted that after removing the exposed dummy gate dielectric layer 120, the outer sidewall surface of the first gate spacer layer 126 extends beyond the sidewall surface of the protective layer 110 and the sidewall surface of the nanostructure 108'. Therefore, a gap exists between the outer sidewall surface of the first gate isolation layer 126 and the outer sidewall surface of the protective layer 110. In other words, the first gate spacer layer 126 protrudes from the top surface and sidewall surface of the protective layer 110. A step height exists between the first gate spacer layer 126 and the protective layer 110. The first semiconductor material layer 106 may be removed by performing a selective wet etching process, such as an APM (eg, ammonium hydroxide-hydrogen peroxide-water mixture) etching process. For example, the wet etching process uses an etchant such as ammonium hydroxide (NH 4OH), TMAH, ethylenediamine pyrocatechol (EDP) and / or potassium hydroxide (KOH) solution. In some embodiments, the upper portion of the gate spacer layer 126 is also removed. Next, as shown in FIG. 1S , according to some embodiments, after forming nanostructure 108′, the exposed portion of liner 143 is removed. The remaining liner 143 is located between nanostructure 108′ and filler layer 144 and in direct contact therewith. After removing the exposed portion of liner 143, liner 143 has multiple, disconnected, and separate portions. Next, as shown in FIG. 1T , according to some embodiments, an interfacial layer 152 is formed to surround the nanostructure 108 ′, and then a gate dielectric layer 154 is formed over the interfacial layer 152 , the isolation structure 116 , the dielectric wall layer 142 , and the protective layer 110 . More specifically, the gate dielectric layer 154 is in direct contact with the protective layer 110 , the dielectric wall layer 142 , the isolation structure 116 , and the interfacial layer 152 . In other words, the protective layer 110 is surrounded by the gate dielectric layer 154 . The gate dielectric layer 154 is in direct contact with the liner 143 of the dielectric wall layer 142 . It should be noted that the gate dielectric layer 154 is conformally formed on the interface layer 152, the isolation structure 116, the dielectric wall layer 142, and the protective layer 110. Therefore, the trench 147 is not completely filled with the gate dielectric layer 154. It should be noted that the gate dielectric layer 154 is in direct contact with the filling layer 144 of the dielectric wall layer 142. In addition, the gate dielectric layer 154 is in direct contact with the sidewall surface of the protective layer 110. Furthermore, because the first gate spacer layer 126 protrudes from the top surface and sidewall surfaces of the protection layer 110 (as shown in FIG1R ), the gate dielectric layer 154 directly above the first gate isolation layer 126 still protrudes from the gate dielectric layer 154 directly above the protection layer 110. Due to the height difference between the first gate spacer layer 126 and the protection layer 110, a gap is still retained. In some embodiments, the interface layer 152 is an oxide layer formed around the nanostructure 108 ′ and on top of the base fin structure 105 . In some embodiments, a gate dielectric layer 154 is formed over the interface layer 152 such that the nanostructure 108′ is surrounded (e.g., enclosed) by the gate dielectric layer 154. Furthermore, according to some embodiments, the gate dielectric layer 154 also covers the sidewalls of the first gate spacer layer 126 and the second gate spacer layer 128. In some embodiments, the gate dielectric layer 154 is made of one or more layers of dielectric materials, such as HfO 2. HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide alloy (HfO 2-Al 2O 3) Another suitable high-k dielectric material or a combination thereof. In some embodiments, the gate dielectric layer 154 is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable method, or a combination thereof. Next, as shown in FIG. 1U , according to some embodiments, a gate electrode layer 156 is formed on the gate dielectric layer 154. The gate structure 150 is composed of the interface layer 152, the gate dielectric layer 154, and the gate electrode layer 156. It should be noted that the gate electrode layer 156 is conformally formed on the gate dielectric layer 154, so the trench 147 remains and is not filled by the gate electrode layer 156. In some embodiments, the gate electrode layer 156 is formed on the gate dielectric layer 154. In some embodiments, the gate electrode layer 156 is made of one or more layers of a conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, another suitable material, or a combination thereof. In some embodiments, the gate electrode layer 156 is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, another suitable method, or a combination thereof. Although other conductive layers, such as work function metal layers, are not shown in the figures, they may also be formed within the gate structure 150. In some embodiments, the work function metal layer includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), tungsten nitride, tungsten nitride (WN), ruthenium (Ru), or combinations thereof. Then, as shown in FIG. 1V , according to some embodiments, a portion of the gate electrode layer 156 is removed. As a result, after the portion of the gate electrode layer 156 is removed, the trench 147 has a T-shaped structure. Because a gap is formed between the outer wall surface of the first gate spacer layer 126 and the outer wall surface of the protective layer 110 in the step of FIG. 1R , the outer wall surface of the gate electrode layer 156 is substantially flush with the outer wall surface of the gate dielectric layer 154 . In other words, due to the height difference between the first gate spacer layer 126 and the protective layer 110 , the outer wall surface of the gate electrode layer 156 can be substantially coplanar with the outer wall surface of the gate dielectric layer 154 . Therefore, the amount of gate electrode layer 156 removed can be controlled by defining the height difference between the first gate spacer layer 126 and the protective layer 110 . In some embodiments, a portion of the gate electrode layer 156 is removed through an etching process (eg, dry etching or wet etching). It should be noted that in order to reduce unnecessary capacitance between the gate electrode layer 156 and the source / drain (S / D) contact structure, the area of ​​the gate electrode layer 156 is reduced by removing a portion of the gate electrode layer 156 . Next, as shown in FIG. 1W , according to some embodiments, the exposed portion of the gate dielectric layer 154 is removed to expose the second gate spacer layer 128. After removing the exposed portion of the gate dielectric layer 154, a trench 147 remains. The second gate spacer layer 128 is exposed through the trench 147. In some embodiments, the exposed portion of the gate dielectric layer 154 is removed by an etching process (e.g., dry etching or wet etching). It should be noted that since a gap is formed between the outer wall surface of the first gate spacer layer 126 and the outer wall surface of the protection layer 110 in the step of Figure 1R, the outer wall surface of the gate electrode layer 156 is substantially flush with the outer wall surface of the gate dielectric layer 154. The gate structure 150 includes a first gate structure 150a and a second gate structure 150b. The first gate structure 150a is separated from the second gate structure 150b by the dielectric wall layer 142. The first gate structure 150a and the second gate structure 150b are formed on two opposite sidewall surfaces of the dielectric wall layer 142. The first gate structure 150a includes an interface layer 152 surrounding the nanostructure 108′ of the first fin structure 104a, a gate dielectric layer 154 formed on the interface layer 152, and a gate electrode layer 156 formed on the gate dielectric layer 154. The second gate structure 150b includes an interface layer 152 surrounding the nanostructure 108′ of the second fin structure 104b and the third fin structure 104c, a gate dielectric layer 154 formed on the interface layer 152, and a gate electrode layer 156 formed on the gate dielectric layer 154. Next, as shown in FIG. 1X , according to some embodiments, a liner 163 and a filling layer 164 are formed into trench 147. Dielectric wall layer 162 is formed from liner 163 and filling layer 164. Liner 163 is in direct contact with gate electrode layer 156. Liner 163 prevents filling layer 164 from oxidizing gate electrode layer 156. Liner 163 and filling layer 164 are made of different materials. It should be noted that the dielectric wall layer 162 is located between two adjacent fin structures 104b and 104c. The dielectric wall layer 162 has a top and a bottom, and the top is wider than the bottom. The dielectric wall layer 162 has a T-shaped structure. In some embodiments, liner 163 is made of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or other suitable materials. In some embodiments, liner 163 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, liner 163 has a thickness in a range of approximately 1 nm to 10 nm. In some embodiments, the filler layer 164 is made of silicon oxide (SiO), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or a combination thereof. In some embodiments, the filler layer 164 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. Next, as shown in FIG. 1Y , according to some embodiments, the top portion of the filling layer 164 of the dielectric wall layer 162 is removed to form a recess 165. Thus, recess 165 exposes a portion of the liner layer 163. The uppermost surface of the filling layer 164 of the dielectric wall layer 162 is higher than the upper surface of the protective layer 110. In some embodiments, a portion of the filling layer 164 of the dielectric wall layer 162 is removed by an etching process (eg, a dry etching process or a wet etching process). Next, as shown in FIG. 1Z , according to some embodiments, the horizontal portion of the liner 163 of the dielectric wall layer 162 is removed. This results in a recess 165 exposing the vertical portion of the gate electrode layer 156. Note that while the gate electrode layer 156 is exposed by removing the horizontal portion of the liner 163 directly above the gate electrode layer 156, the sidewall portion of the liner 163 remains above the gate electrode layer 156. In some embodiments, the horizontal portion of the liner 163 of the dielectric wall layer 162 is removed by an etching process (eg, a dry etching process or a wet etching process). Next, as shown in FIG. 12A , according to some embodiments, a conductive layer 168 is formed within the recess 165 . The recess 165 is not completely filled with the conductive layer 168 . The conductive layer 168 directly contacts and is electrically connected to the gate electrode layer 156 . The lower surface of the conductive layer 168 directly contacts the gate electrode layer 156 , but the sidewall surfaces of the conductive layer 168 are separated from the gate electrode layer 156 by the liner 163 . It should be noted that the conductive layer 168 is formed by a selective deposition process, and thus the conductive layer 168 is selectively formed on the gate electrode layer 156. Although the conductive layer 168 is primarily formed on the surface of the conductive material, the conductive layer 168 may extend to a position directly above the upper surface of the dielectric wall layer 162. The conductive layer 168 and the gate electrode layer 156 are made of different materials. An interface exists between the conductive layer 168 and the gate electrode layer 156 . In some embodiments, conductive layer 168 is made of a conductive material including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof. In some embodiments, conductive layer 168 is made of tungsten (W) that does not contain fluorine (F). The conductive layer 168 may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), plasma enhanced physical vapor deposition (PEPVD), or atomic layer deposition (ALD). Then, as shown in FIG. 12B , according to some embodiments, a dielectric layer 170 is formed on the conductive layer 168 and within the recess 165 . A planarization process (e.g., chemical mechanical polishing (CMP) or an etch-back process) may be performed. Next, according to some embodiments, an etch-stop layer 172 is formed on the dielectric wall layer 162 , the protective layer 110 , and the dielectric layer 170 , and a dielectric layer 174 is formed on the etch-stop layer 172 . In some embodiments, dielectric layer 170 is made of silicon oxide, silicon nitride, silicon oxynitride, or a suitable dielectric material. Dielectric layer 170 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, the etch stop layer 172 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the etch stop layer 172 can be conformally deposited over the semiconductor structure by chemical vapor deposition (CVD), atomic layer deposition (ALD), other deposition methods, or a combination thereof. Dielectric layer 174 may include a multilayer structure made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other suitable low-k dielectric materials. Dielectric layer 174 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. Next, a gate contact structure 178 is formed on the conductive layer 168. The gate contact structure 178 is formed through the conductive layer 168. The gate contact structure 178 passes through the dielectric layer 170 and directly contacts the conductive layer 168. The gate contact structure 178 is electrically connected to the gate electrode layer 156 through the conductive layer 168. In some embodiments, the gate contact structure 178 is made of a conductive material, including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof. The gate contact structure 178 may be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process. As shown in FIG. 12B , a first gate structure 150a is separated from a second gate structure 150b by a dielectric wall layer 142. The first gate structure 150a and the second gate structure 150b are formed on opposite sidewall surfaces of the dielectric wall layer 142. The top surface of the first gate structure 150a is substantially coplanar with the top surface of the dielectric wall layer 142. The top surface of the second gate structure 150b is substantially coplanar with the top surface of the dielectric wall layer 142. The gate electrode layer 156 of the second gate structure 150b extends from a first location to a second location. The first location is located on the nanostructure 108' of the second fin structure 104b, while the second location is located on the nanostructure 108' of the third fin structure 104c. A portion of the gate electrode layer 156 of the second gate structure 150b is located directly below the dielectric wall layer 162. The upper surface of the dielectric wall layer 142 is higher than the upper surface of the protective layer 110. Furthermore, the upper surface of the dielectric wall layer 162 is higher than the upper surface of the protective layer 110. The upper surface of the dielectric wall layer 162 is lower than the upper surface of the dielectric wall layer 142. The upper surface of the dielectric wall layer 162 is lower than the uppermost surfaces of the gate electrode layers 156 of the first gate structure 150a and the second gate structure 150b. If the protective layer 110 is not formed on the nanostructure 108', when the step of removing a portion of the gate electrode layer 156 through a chemical mechanical polishing (CMP) process is performed, the height uniformity of the gate electrode layer 156 will be poor due to CMP process variation. If the height of the gate electrode layer 156 is designed to be high enough to reduce the influence of CMP process variation, another unnecessary capacitance problem may occur. To improve height uniformity and prevent unnecessary capacitance problems, the protective layer 110 is formed on the nanostructure 108'. Furthermore, if the protective layer 110 is not formed on the nanostructure 108', the topmost nanostructure 108' will be slightly removed, and the thickness of the topmost nanostructure 108' will be different from the thickness of the second topmost nanostructure 108'. As a result, the performance of the semiconductor structure 100a will be reduced. Therefore, the protective layer 110 is formed on the nanostructure 108'. The protective layer 110 protects the underlying nanostructure 108' from being etched during manufacturing, thereby maintaining the thickness of each nanostructure 108'. Due to the protection of the protective layer 110, each nanostructure 108' has substantially the same thickness. When the thickness uniformity of each nanostructure 108' is improved, the performance of the semiconductor structure 100a is improved. The protection layer 110 is used to protect the underlying nanostructure 108 ′ from being etched or damaged. A gate dielectric layer 154 and a gate electrode layer 156 are formed on the protection layer 110 . The uppermost surface of the gate electrode layer 156 is higher than the upper surface of the protection layer 110 . As shown in FIG12B , a first width W1 is defined between one end of the gate electrode layer 156 and one end of the nanostructure 108 ′ along the horizontal direction. In some embodiments, the first width W1 is approximately in a range of 2 nm to 12 nm. If the thickness of the first width W1 is less than 2 nm, the threshold voltage (Vth) of the semiconductor structure 100a is difficult to control. If the thickness of the first width W1 is greater than 12 nm, the area of ​​the gate electrode layer 156 is too large, which increases the unnecessary capacitance generated between the nanostructure 108' of the second fin structure 104b and the nanostructure 108' of the third fin structure 104c. In other words, the gate electrode layer 156 between the nanostructure 108' of the second fin structure 104b and the nanostructure 108' of the third fin structure 104c is partially replaced by the dielectric wall layer 162. Therefore, reducing the area of ​​the gate electrode layer 156 reduces the unnecessary capacitance between the nanostructure 108' of the second fin structure 104b and the nanostructure 108' of the third fin structure 104c. Furthermore, the unnecessary capacitance between the gate electrode layer 156 and the contacts above the source / drain (S / D) structure 136 can also be reduced. Therefore, the performance of the semiconductor structure 100 a is improved. The first recess distance D1 of the gate dielectric layer 154 is measured from the upper surface of the interface layer 152 and the upper surface of the liner 143. In some embodiments, the first recess distance D1 of the gate dielectric layer 154 is approximately in the range of 0.1 nm to 5 nm. When the first recess distance D1 of the gate dielectric layer 154 is within this range, the coverage of the nanostructure 108' by the gate dielectric layer 154 is increased, and the controllability of the gate structure 150 is enhanced. Consequently, the performance of the semiconductor structure 100a is improved. FIG. 2 is a schematic cross-sectional view of the semiconductor structure 100 a along line BB′ of FIG. 12B according to some embodiments. As shown in FIG2 , a second width W2 is defined between two adjacent second gate spacers 128. This second width W2 is achieved by performing the step of FIG1Q , removing the exposed first gate spacers 126 to expose a portion of the second gate spacers 128. Since a substantial portion of the first gate spacers 126 has been removed, the remaining first gate spacers 126 remain beneath the liner 163 of the dielectric wall layer 162. In addition, the lower surface of the first gate spacer layer 126 and the lower surface of the second spacer layer 128 are in direct contact with the upper surface of the protection layer 110 . FIG3 is a schematic cross-sectional view of the semiconductor structure 100 a taken along line CC′ of FIG12B according to some embodiments. As shown in FIG3 , the remaining first gate spacer layer 126 is located directly below the dielectric wall layer 162. The upper surface of the second spacer layer 128 is higher than the upper surface of the first spacer layer 126. In addition, the upper surface of the second spacer layer 128 is higher than the lower surface of the conductive layer 168. Note that the second width W2 is located between two adjacent second spacers 128. This second width W2 is achieved by performing the step in FIG. 1Q, removing the exposed first gate spacer layer 126 to expose a portion of the second gate spacer layer 128. Since a substantial portion of the first gate spacer layer 126 has been removed, the remaining first gate spacer layer 126 remains beneath the liner 163 of the dielectric wall layer 162. Furthermore, the second width W2 is greater than the distance between two adjacent first spacers 126. Figures 4A-4B illustrate schematic cross-sectional views of a semiconductor structure 100b according to some embodiments. The semiconductor structure 100b of Figures 4A-4B includes components similar to or identical to the components of the semiconductor structure 100a of Figure 12B. The materials and processes used to form the semiconductor structure 100b may be similar to or identical to those used to form the semiconductor structure 100a described above and are not further described herein. The difference between the semiconductor structure 100 b in FIG4A and the semiconductor structure 100 a in FIG1R is that the liner layer 143 of the dielectric wall layer 142 is not removed. The liner layer 143 is a continuous layer and is exposed through the trench 147 . Next, as shown in FIG. 4B , an interface layer 152 is formed on the nanostructure 108 ′, and a gate dielectric layer 154 is formed on the interface layer 152. It should be noted that the gate dielectric layer 154 is formed on the sidewall surfaces of the liner 143 of the dielectric wall layer 142. Compared to the semiconductor structure 100 a shown in FIG. 12B , the first recess distance D1 of the gate dielectric layer 154 is not observed in FIG. 4B . Figures 5A-5B illustrate schematic cross-sectional views of a semiconductor structure 100c according to some embodiments. The semiconductor structure 100c of Figures 5A-5B includes components similar to or identical to the components of the semiconductor structure 100a of Figure 12B. The materials and processes used to form the semiconductor structure 100b may be similar to or identical to those used to form the semiconductor structure 100a described above and are not further described herein. The difference between the semiconductor structure 100 c of FIG5A and the semiconductor structure 100 a of FIG15B is that no liner is formed between the gate electrode layer 156 and the filling layer 164. The dielectric wall layer 162 is made of the filling layer 164. Next, as shown in FIG5B , a conductive layer 168 is formed on the dielectric wall layer 162 having the filling layer 164 but not the liner layer 163. Furthermore, the sidewall surface of the conductive layer 168 directly contacts the gate electrode layer 156. However, in FIG12B , the sidewall surface of the conductive layer 168 does not directly contact the gate electrode layer 156. Figures 6A-6B illustrate schematic cross-sectional views of a semiconductor structure 100d according to some embodiments. The semiconductor structure 100d in Figures 6A-6B includes components similar to or identical to the components of the semiconductor structure 100a in Figure 12B. The materials and processes used to form the semiconductor structure 100d may be similar to or identical to those used to form the semiconductor structure 100a described above and are not further described herein. The difference between the semiconductor structure 100d in FIG6A and the semiconductor structure 100a in FIG1N is that the protection layer 110 is not recessed while the dummy gate electrode layer 122 is removed, and the protection layer 110 still has a rectangular structure. Thereafter, as shown in FIG. 6B , a dielectric wall layer 142 is formed in the trench 141 . FIG7 illustrates a schematic cross-sectional view of a semiconductor structure 100e according to some embodiments. The semiconductor structure 100e in FIG7 includes components similar to or identical to those of the semiconductor structure 100b in FIG4B . The materials and processes used to form the semiconductor structure 100e may be similar to or identical to those used to form the semiconductor structure 100b described above and are not further described herein. The difference between the semiconductor structure 100e of FIG7 and the semiconductor structure 100b of FIG4B is that the protection layer 110 is not recessed while the dummy gate electrode layer 122 is removed. The protection layer 110 still has a rectangular structure. FIG8 illustrates a schematic cross-sectional view of a semiconductor structure 100 f according to some embodiments. The semiconductor structure 100 f in FIG8 includes components similar to or identical to the components of the semiconductor structure 100 c in FIG5B . The materials and processes used to form the semiconductor structure 100 f may be similar to or identical to those used to form the semiconductor structure 100 c described above and are not further described herein. The difference between the semiconductor structure 100f of FIG8 and the semiconductor structure 100c of FIG5B is that the protection layer 110 is not recessed while the dummy gate electrode layer 122 is removed. The protection layer 110 still has a rectangular structure. To improve the height uniformity of the gate structures 150a / 150b and prevent unnecessary capacitance problems, a protection layer 110 is formed on the nanostructure 108'. The protection layer 110 protects the underlying nanostructure 108' from damage, thereby maintaining the thickness of the nanostructure 108'. Furthermore, the portion of the gate electrode layer 156 located between the nanostructure 108' of the second fin structure 104b and the nanostructure 108' of the third fin structure 104c is replaced by a dielectric wall layer 162. Consequently, the area of ​​the gate electrode layer 156 is reduced, thereby reducing unnecessary capacitance between the nanostructure 108' of the second fin structure 104b and the nanostructure 108' of the third fin structure 104c. Furthermore, unnecessary capacitance between the gate electrode layer 156 and the contact above the source / drain (S / D) structure 136 is reduced. Consequently, the performance of the semiconductor structure 100a is improved. Furthermore, although the disclosed methods are depicted and described below as a series of actions or events, it should be understood that in some other embodiments, the order of the actions or events depicted may be changed. For example, some actions may occur in a different order and / or concurrently with other actions or events beyond those depicted and / or described above. Furthermore, not all depicted actions are required to implement one or more of the above-described configurations or embodiments. Furthermore, one or more of the above-described actions may be performed within one or more individual actions and / or stages. Furthermore, the terms "approximately," "substantially," "substantially," and "about" described above take into account small variations and can vary in different technologies and have a range of error understood by a person of ordinary skill in the art. For example, when used in conjunction with an event or circumstance, these terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs very nearly. The above provides an embodiment for forming a semiconductor structure. An embodiment of a semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first nanostructure and a second nanostructure formed above a substrate. A protective layer is formed on the first nanostructure and the second nanostructure. A gate structure is formed on the nanostructure, and a first spacer layer and a second spacer layer are formed on opposite sidewall surfaces of the gate structure. A dielectric wall layer is located between the first nanostructure and the second nanostructure. Since part of the gate electrode layer of the gate structure is replaced by the dielectric wall layer, the area of ​​the gate electrode layer is reduced. Unnecessary capacitors in the semiconductor structure are reduced. In addition, due to the protection of the protective layer, each nanostructure has substantially the same thickness. The thickness uniformity of each nanostructure is improved. Therefore, the performance of the semiconductor structure is improved. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of first nanostructures located above a substrate and a plurality of second nanostructures adjacent to the first nanostructures. The semiconductor structure includes a protective layer located above the first nanostructures and a first gate structure formed on the first nanostructures. The semiconductor structure includes a second gate structure formed on the second nanostructures. The semiconductor structure includes a first dielectric wall layer located between the first gate structure and the second gate structure, wherein the upper surface of the first dielectric wall layer is higher than the upper surface of the protective layer. In some embodiments, the first gate structure is separated from the second gate structure by a first dielectric wall layer. In some embodiments, the semiconductor structure further includes a plurality of third nanostructures adjacent to the second nanostructure and a second dielectric wall layer located between the second nanostructure and the third nanostructure, wherein the upper surface of the second dielectric wall layer is lower than the upper surface of the first dielectric wall layer. In some embodiments, a portion of the second gate structure is located directly below the second dielectric wall layer. In some embodiments, the semiconductor structure further includes a conductive layer formed on the second dielectric wall layer and the second gate structure, and a contact structure formed on the conductive layer. In some embodiments, the first dielectric wall layer includes a liner and a filling layer located on the liner, the liner being in direct contact with the first nanostructure. In some embodiments, the first gate structure includes a gate dielectric layer and a gate electrode layer, the gate dielectric layer of the first gate structure being in direct contact with the filling layer. In some embodiments, the first gate structure is formed on a sidewall surface of the first dielectric wall layer. In some embodiments, the protective layer is in direct contact with the first dielectric wall layer. In some embodiments, a portion of the first dielectric wall layer is buried in the protective layer. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of first nanostructures located above a substrate and a plurality of second nanostructures adjacent to the first nanostructures. The semiconductor structure includes a first protective layer located above the first nanostructures and a first gate structure formed on the first and second nanostructures. The semiconductor structure also includes a first dielectric wall layer located between the first and second nanostructures, with an upper surface of the first gate structure being higher than an upper surface of the first dielectric wall layer. In some embodiments, the semiconductor structure further includes a conductive layer formed on the first dielectric wall layer and the first gate structure, and a contact structure formed on the conductive layer. In some embodiments, a portion of the first gate structure is located directly below the first dielectric wall layer. In some embodiments, the semiconductor structure further includes a plurality of third nanostructures adjacent to the second nanostructure and a second dielectric wall layer located between the second nanostructure and the third nanostructure, wherein the upper surface of the second dielectric wall layer is higher than the upper surface of the first dielectric wall layer. In some embodiments, the semiconductor structure further includes a second protective layer formed on the third nanostructure, wherein a portion of the second dielectric wall layer is buried in the second protective layer. In some embodiments, the semiconductor structure further includes a first spacer layer adjacent to the first gate structure and a second spacer layer formed on the first spacer layer, wherein a portion of the first spacer layer is located directly below the first dielectric wall layer. In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first fin structure and a second fin structure above a substrate, respectively, wherein the first fin structure includes alternating stacks of first and second semiconductor material layers, and the second fin structure includes alternating stacks of first and second semiconductor material layers. The method includes forming a first protective layer on the first fin structure and a second protective layer on the second fin structure, and forming a dummy gate structure spanning the first and second fin structures. The method also includes forming a first spacer layer and a second spacer layer on the sidewall surface of the dummy gate structure, and removing a portion of the dummy gate structure to expose the first spacer layer. The method includes removing a portion of the first spacer layer to expose a portion of the second spacer layer, and removing a portion of the first semiconductor material layer to form a first nanostructure and a second nanostructure. The method includes forming a gate dielectric layer on the first and second nanostructures, and the gate dielectric layer is located on the first and second spacer layers. The method includes forming a gate electrode layer on the gate dielectric layer and removing a portion of the gate electrode layer. The method includes removing a portion of the gate dielectric layer to expose a second spacer layer and forming a dielectric spacer layer between the first nanostructure and the second nanostructure. In some embodiments, the method further includes forming a gate dielectric layer on the protective layer; forming a gate electrode layer on the protective layer, wherein the upper surface of the gate electrode layer is higher than the upper surface of the protective layer. In some embodiments, the method further includes removing a top portion of the dielectric wall layer to expose the gate electrode layer; forming a conductive layer on the dielectric wall layer and the gate electrode layer; and forming a contact structure on the conductive layer. In some embodiments, a portion of the gate electrode layer is located directly below the dielectric wall layer. The above briefly describes the characteristic components of several embodiments of the present invention, so that those with ordinary skill in the art can more easily understand the types of the present disclosure. Anyone with ordinary skill in the art should understand that this disclosure can be easily used as a basis for changes or designs of other processes or structures to achieve the same purposes and / or obtain the same advantages as the embodiments described herein. Anyone with ordinary skill in the art will also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and that changes, substitutions, and modifications can be made without departing from the spirit and scope of the present disclosure. 100a, 100b, 100c, 100d, 100e, 100f: semiconductor structure 102: substrate 104a, 104b, 104c: fin structure 105: base fin structure 106: first semiconductor material layer 108: second semiconductor material layer 108': nanostructure 108T: top second semiconductor material layer 110: protective layer 112: hard mask layer 115: isolation material 116: isolation structure 118: dummy gate structure 120: dummy gate dielectric layer 122: dummy gate electrode layer 126: first gate spacer layer 128: second gate spacer layer 130: source / drain recess 132: notch 134: inner spacer layer 136: source / drain (S / D) structure 138, 172: etch stop layer 140: interlayer dielectric ( ILD) layer 141, 147: trench 142, 162: dielectric wall layer 143, 163: liner 144, 164: filling layer 150: gate structure 150a: first gate structure 150b: second gate structure 152: interface layer 154: gate dielectric layer 156: gate electrode layer 165: recess 168: conductive layer 170, 174: dielectric layer 178: gate contact structure A1, B1: block D1: first recess distance W1: first width W2: second width Figures 1A to 1Z illustrate schematic perspective views of intermediate stages of forming a semiconductor structure according to some embodiments. Figures 1ZA to 1ZB illustrate schematic perspective views of intermediate stages of forming a semiconductor structure according to some embodiments. Figures 1B-T illustrate schematic top views of intermediate stages of a semiconductor structure according to some embodiments, with block A1 shown in Figures 11B-T corresponding to the structure shown in Figure 1B. Figures 1F-T illustrate schematic top views of intermediate stages of a semiconductor structure according to some embodiments, with block A1 shown in Figures 1F-T corresponding to the structure shown in Figure 1F. Figures 1M-T illustrate schematic top views of intermediate stages of a semiconductor structure according to some embodiments, with block B1 shown in Figures 1M-T corresponding to the structure shown in Figure 1M. Figure 2 illustrates a schematic cross-sectional view of the semiconductor structure taken along line BB' of Figure 1ZB according to some embodiments. Figure 3 illustrates a schematic cross-sectional view of the semiconductor structure taken along line CC' of Figure 1ZB according to some embodiments. Figures 4A-4B illustrate schematic cross-sectional views of a semiconductor structure according to some embodiments. Figures 5A-5B illustrate schematic cross-sectional views of semiconductor structures according to some embodiments. Figures 6A-6B illustrate schematic cross-sectional views of semiconductor structures according to some embodiments. Figure 7 illustrates a schematic cross-sectional view of a semiconductor structure according to some embodiments. Figure 8 illustrates a schematic cross-sectional view of a semiconductor structure according to some embodiments. 100a: Semiconductor structure 102: Base 104a, 104b, 104c: Fin structure 105: Base fin structure 108':Nanostructure 110: Protective layer 116: Isolation Structure 126: first gate spacer layer 128: second gate spacer layer 138,172: Etch stop layer 140: Interlayer dielectric (ILD) layer 142,162: Dielectric wall layer 143,163: Lining 144,164: Filling layer 150a: first gate structure 150b: second gate structure 152: Interface layer 154: Gate dielectric layer 156: Gate electrode layer 168: conductive layer 170,174: Dielectric layer 178: Gate contact structure D1: first concave distance W1: first width

Claims

1. A semiconductor structure, comprising: Multiple first nanostructures are located on a substrate; A plurality of second nanostructures are adjacent to the first nanostructures; A protective layer is located above the first nanostructures, wherein the first nanostructures are located between the substrate and the protective layer; a first gate structure is formed on the first nanostructures; a second gate structure is formed on the second nanostructures; and a first dielectric wall layer is located between the first gate structure and the second gate structure, wherein an upper surface of the first dielectric wall layer is higher than an upper surface of the protective layer.

2. The semiconductor structure of claim 1, wherein the first gate structure is separated from the second gate structure through the first dielectric wall layer.

3. The semiconductor structure as described in claim 1 or 2 further includes: Multiple third nanostructures are adjacent to the second nanostructure; And a second dielectric wall layer, located between the second nanostructure and the third nanostructure, wherein an upper surface of the second dielectric wall layer is lower than the upper surface of the first dielectric wall layer.

4. The semiconductor structure of claim 1 or 2, wherein the first dielectric wall layer includes a liner and a fill layer located on the liner, and the liner is in direct contact with the first nanostructure.

5. A semiconductor structure, comprising: Multiple first nanostructures are located on a substrate; A plurality of second nanostructures are adjacent to the first nanostructures; A first protective layer is located above the first nanostructures, wherein the first nanostructures are located between the substrate and the first protective layer; a first gate structure is formed on the first nanostructures and the second nanostructures; and a first dielectric wall layer is located between the first nanostructures and the second nanostructures, wherein an upper surface of the first gate structure is higher than an upper surface of the first dielectric wall layer.

6. The semiconductor structure as described in claim 5 further includes: A conductive layer is formed on the first dielectric wall layer and the first gate structure; And a contact structure is formed on the conductive layer.

7. The semiconductor structure of claim 5 or 6, wherein a portion of the first gate structure is located directly below the first dielectric wall layer.

8. The semiconductor structure as described in claim 5 or 6 further includes: A plurality of third nanostructures are adjacent to the second nanostructures; And a second dielectric wall layer, located between the second nanostructures and the third nanostructures, wherein an upper surface of the second dielectric wall layer is higher than an upper surface of the first dielectric wall layer.

9. The semiconductor structure of claim 8 further includes: a second protective layer formed on the third nanostructure, wherein a portion of the second dielectric wall layer is embedded in the second protective layer.

10. A method for forming a semiconductor structure, comprising: A first fin structure and a second fin structure are formed on a substrate, wherein the first fin structure includes a plurality of alternately stacked first semiconductor material layers and a plurality of alternately stacked second semiconductor material layers, and the second fin structure includes a plurality of alternately stacked first semiconductor material layers and a plurality of alternately stacked second semiconductor material layers; a first protective layer is formed on the first fin structure and a second protective layer is formed on the second fin structure; a dummy gate structure is formed across the first fin structure and the second fin structure; a first spacer layer and a second spacer layer are formed on the sidewall surface of the dummy gate structure; a portion of the dummy gate structure is removed to expose the first spacer layer; a portion of the first spacer layer is removed to expose a portion of the second spacer layer; a portion of the first semiconductor material layers is removed to form a plurality of first nanostructures and a plurality of second nanostructures; A gate dielectric layer is formed on the first nanostructure and the second nanostructure, and the gate dielectric layer is located on the first spacer layer and the second spacer layer; a gate electrode layer is formed on the gate dielectric layer; a portion of the gate electrode layer is removed; a portion of the gate dielectric layer is removed to expose the second spacer layer; and a dielectric wall layer is formed between the first nanostructure and the second nanostructure.

11. The method for forming the semiconductor structure as described in claim 10 further includes: The gate dielectric layer is formed on the protective layer; And forming the gate electrode layer on the protective layer, wherein an upper surface of the gate electrode layer is higher than an upper surface of the protective layer.

12. The method for forming the semiconductor structure as described in claim 10 further includes: Remove one top of the dielectric wall layer to expose the gate electrode layer; And forming a conductive layer on the dielectric wall layer and the gate electrode layer; and forming a contact structure on the conductive layer.

13. The method of forming a semiconductor structure as claimed in claim 10, wherein a portion of the gate electrode layer is located directly below the dielectric wall layer.

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