Semiconductor device test system, method of testing semiconductor device, and method of adjusting thermal environment of semiconductor structure

Abstract

A test method and system for testing a semiconductor device are provided. The method includes placing a packaged semiconductor device on a tester and bonding a thermal management component to the upper surface of the packaged semiconductor device. The tester is used to test the packaged semiconductor device, and during the test, a first thermal condition is applied to a first region of the thermal management component, while a second thermal condition is applied to a second region of the thermal management component. The first thermal condition is different from the second thermal condition.

Description

[Technical Field]

[0001] This disclosure relates to thermal management components, and more particularly to thermal management components for multi-wafer or bare die devices. [Previous Technology]

[0002] Testing is a critical step in ensuring the reliability, integrity, and performance of integrated circuits. Thermal management during testing, such as that of semiconductor structures, has become a challenge. This is especially true when dealing with packaged semiconductor devices with multiple wafers or bare dies within the package (e.g., 2.5D and 3D structures). While existing thermal management techniques are generally adequate for their intended purpose, they are not entirely satisfactory in all respects. [Summary of the Invention]

[0003] This disclosure provides a semiconductor device testing system, including a packaged multi-die semiconductor device, a tester, a thermal management component, a coolant handling system, and a control system. The packaged multi-die semiconductor device has a surface. The tester has a socket in which the packaged multi-die semiconductor device is disposed. The thermal management component engages the packaged multi-die semiconductor device in the socket, wherein the surface of the packaged multi-die semiconductor device is connected to the thermal management component. The coolant handling system is operable to provide a coolant to the thermal management component. The control system is operable to control the supply of coolant from the coolant handling system to the thermal management component.

[0004] This disclosure provides a semiconductor device testing system and a method for testing a semiconductor device, the method comprising: placing a packaged semiconductor device on a tester; bonding a thermal management component to an upper surface of the packaged semiconductor device; and testing the packaged semiconductor device using the tester, and during the test, delivering a first thermal condition to a first region of the thermal management component and simultaneously delivering a second thermal condition to a second region of the thermal management component, wherein the first thermal condition is different from the second thermal condition.

[0005] This disclosure provides a semiconductor device testing system and a method for regulating a thermal environment of a semiconductor structure. The method includes: providing a multi-die packaged semiconductor device; providing a thermal management component connected to an upper surface of the multi-die packaged semiconductor device; during an operation of the multi-die packaged semiconductor device, delivering a first liquid coolant to a first region of the thermal management component, wherein the first region covers a first die of the multi-die packaged semiconductor device; and delivering a second liquid coolant to a second region of the thermal management component, wherein the second region covers a second die of the multi-die packaged semiconductor device, and wherein the delivery of the second liquid coolant is performed simultaneously with the delivery of the first liquid coolant.

Implementation Method

[0007] This disclosure relates generally to semiconductor devices, and more particularly to integrated circuits (ICs) included in multi-die package devices (also known as multi-wafer packages or modules), including thermal management during the testing and operating conditions of said devices.

[0008] The following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, spatially related terms, such as “down,” “up,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upper,” “lower,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontal,” “downward,” “upward,” etc.), are used to facilitate understanding of the relationship between one feature and another in this disclosure. Spatially related terms are intended to cover different orientations of the means including the features. Reference numerals and / or letters may also be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, when numbers or ranges of numbers are described using terms such as "about," "approximately," etc., the term is intended to cover numbers within a reasonable range that takes into account variations inherent during manufacturing, as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics related to numbers, a number or range of numbers covers a reasonable range including the described number, such as within + / -10% of the described number. For example, a material layer having a thickness of "about 5 nm" can cover a size range from 4.5 nm to 5.5 nm, where a manufacturing tolerance associated with the deposited material layer is known to one of ordinary skill in the art to be + / -10%. Furthermore, taking into account variations inherent in any manufacturing process, when device features are described as having "substantial" characteristics and / or features, the term is intended to capture characteristics and / or features within the tolerances of the manufacturing process. For example, a "substantially vertical" or "substantially horizontal" feature is intended to cover features that are approximately vertical and horizontal within a given tolerance of the manufacturing process used to manufacture such features, but not necessarily mathematically or perfectly vertical and horizontal.

[0010] This disclosure presents certain discussions regarding thermal management during testing of packaged semiconductor structures. Those skilled in the art will understand that the thermal management components and methods discussed herein are not only solutions or improvements for thermal management of devices under test (DUTs), but can also be applied to the thermal management of devices in use, including, but not limited to, packaged semiconductor structures implemented in electronic systems such as computers or other information processing systems.

[0011] Thermal management during IC testing (or use), such as thermal management of ICs tested after packaging, has become a challenge. For example, as devices become more complex and expand to packaged semiconductor structures comprising multiple wafers or bare dies, addressing their power and heat generation becomes more challenging. Thermal management of the DUT is crucial for ensuring the quality and reliability of both the DUT and the test equipment. Some cooling mechanisms implemented in the tester may provide low cooling efficiency (e.g., air-cooled heat sinks) and / or do not allow for independent control of areas or regions of the DUT, such as independent control of the temperature around each die of a multi-die DUT. In further embodiments, it may be necessary to test the dies of a multi-die package at different test temperatures. Therefore, the lack of independent control over multi-die package regions necessitates performing single-temperature tests multiple times.

[0012] This disclosure addresses some or all of these challenges in at least some of its embodiments by providing an improved thermal management system for devices such as multi-die packages operating under test conditions or otherwise. In various embodiments, the thermal management system of this disclosure provides interfaces to different regions or blocks of thermal management components to independently control (through the introduction of coolant) the multi-die package element. Therefore, the thermal conditions of regions of the multi-die element can be controlled independently; for example, the thermal conditions around one die of the multi-die package can be controlled independently from the thermal conditions around another die of the multi-die package. By providing flexibility in the thermal conditions of regions within the package element, test time can be reduced and binning efficiency improved. In some embodiments, certain dies of the multi-die package (e.g., high-power components) can undergo targeted, improved cooling.

[0013] Further benefits of this disclosure include the opportunity to remove the thermal interface material (TIM) that serves as the interface between the die and thermal management components. Instead, in some embodiments, direct heat exchange can be provided between the device (e.g., the exposed surface of a 3D IC) and the coolant. In some implementations, the removal of the TIM provides greater efficiency in transferring thermal energy from the device. This offers particular benefit in removing heat from high-power devices in multi-die packages during operation or testing.

[0014] The discussion of this benefit is provided for ease of understanding only. Different embodiments may have different advantages, and no particular embodiment requires a specific advantage.

[0015] The multi-die or wafer packaging disclosed herein is exemplary. Various packaging technologies can integrate multiple wafers or dies into a single semiconductor device. Depending on the stacking level, modern semiconductor packaging can have so-called 2.5D or 3D structures. In a 2.5D structure, at least two wafers are coupled to a redistribution layer (RDL) structure or an interposer layer providing chip-to-chip communication. At least two dies in a 2.5D structure can be stacked non-perpendicularly on top of each other. In a 3D structure, at least two dies are stacked on top of each other and interact through through silicon vias (TSVs). Depending on the process used, 2.5D and 3D structures can have an integrated fan-out (InFO) structure or a chip-on-wafer-on-substrate (CoWoS®) structure. Various configurations including 2.5D and 3D structures are included within the multi-die packaging devices discussed in this disclosure.

[0016] Figure 1 is a block diagram of a thermal management system 11, which includes a device 10 connected to a thermal management component 12, which is operatively coupled to a control system 14 and a coolant handling system 16. The thermal management system 11 may be included in a tester, product system (such as a computer or information processing system), etc.

[0017] Device 10 may be a packaged semiconductor device containing one or more wafers or dies within a package (i.e., a multi-wafer or multi-die package). Device 10 may include at least three wafers or dies within a package. In some embodiments, device 10 has a 2.5D or 3D structure. Exemplary embodiments of device 10 will be discussed in more detail below with reference to Figures 2A through 7.

[0018] Control system 14 is provided for implementing various aspects of this disclosure. Control system 14 includes a hardware processor and a non-transitory computer-readable storage medium encoded with (i.e., stored) a program (i.e., a set of executable instructions). These instructions may be adapted to perform one or more of the functions discussed in this disclosure, including the method of FIG8. Control system 14 may be operatively coupled to thermal management component 12 and / or coolant handling system 16. As described below, control system 14 receives data from thermal management component 12, such as data received from thermal sensors disposed on or therein of thermal management component 12. In some embodiments, the data received from thermal management component 12 is used to calculate the desired output of coolant handling system 16, and therefore, instructions are transmitted from control system 14 to coolant handling system 16. In one embodiment, instructions are transmitted from control system 14 to coolant handling system 16, wherein instructions are generated based on stored or received data (such as design data, device performance data, simulation data, etc.). In one embodiment, instructions are transmitted from the control system 14 to the coolant handling system 16, wherein the instructions are generated based on the desired test conditions (e.g., temperature) of the device 10.

[0019] The coolant handling system 16 may provide a series of pumps, valves, pipes, reservoirs, and / or other features suitable for supplying coolant to the thermal management component 12 and receiving coolant (i.e., used coolant) from the thermal management component 12 after use. In some embodiments, the coolant handling system 16 supplies coolant according to instructions from the control system 14, such as operating valves of the coolant handling system. In one embodiment, the coolant of the coolant handling system 16 (particularly the coolant supplied to the thermal management component 12) is a liquid coolant. In some embodiments, the coolant returned from the thermal management component 12 to the coolant handling system 16 (i.e., waste coolant) is still liquid. However, in some variations, the coolant received from the thermal management component 12 to the coolant handling system 16 is gaseous. Various configurations of the coolant handling system 16 are possible, including multiple supply pipes (e.g., lines) extending to the thermal management component 12, and multiple return pipes (e.g., lines) extending from the thermal management component 12 to the coolant handling system 16. In one embodiment, the number of coolant supply pipes extending from the coolant handling system 16 to the thermal management component 12 is the same as the number of temperature zones of the thermal management component 12 (e.g., A, B, C as described below). In other embodiments, the number of supply pipes may be less than the number of temperature zones. Of course, the coolant handling system includes various valves that control the supply of coolant to the thermal management component 12, and in some cases, these valves are controlled by instructions provided by the control system 14.

[0020] The thermal management component 12 is connected to the device 10. The thermal management component 12 may be directly connected to the device 10, making it physically contact the upper surface of the device 10. In one embodiment, the thermal management component 12 may be part of a test head for electrical testing of the device 10. In one embodiment, the thermal management component 12 may be attached to the device 10 installed in an operating system (e.g., a computer or other message processing system). The thermal management component 12 may include a housing providing a manifold that receives a supply line from the coolant handling system 16 and provides a return line. The thermal management component 12 may include various compartments or chambers that operate to accommodate the received coolant. As described below, these compartments may be sealed compartments that directly contact the upper surface of the device 10 to directly supply coolant (e.g., liquid coolant) to the device 10 to enhance heat transfer.

[0021] As shown in the figures, the thermal management component 12 includes multiple thermal zones or blocks, shown here as A, B, and C. In some embodiments, each thermal zone may be independently controlled by the control system 14 and have an independent connection from the coolant handling system 16 (e.g., coolant delivery). Although three zones are shown in the figures, any number of zones is possible. In some embodiments, the number of zones is at least equal to the number of bare dies or wafers in the multi-die package provided as device 10. In one embodiment, a target thermal condition setpoint (e.g., temperature) is selected for zones A, B, and C respectively. And each zone A, B, and C may be provided with a temperature sensor. In one embodiment, one or more sensors measure the thermal conditions (e.g., temperature) of each zone A, B, and C respectively. In one embodiment, the control system 14 delivers different coolant conditions (e.g., different temperatures, different coolants, different flow rates) to each zone A, B, and C via the coolant handling system 16. Referring to Figures 2A through 7, the exemplary thermal management component 12 will be discussed in further detail below.

[0022] Referring now to Figures 2A and 2B, a packaged multi-chip device 200 is shown. The packaged multi-chip device 200 may be generally similar to the device 10 described in Figure 1. A thermal management component 202 is disposed on and interconnected with the packaged multi-chip device 200. The thermal management component 202 may be generally similar to the thermal management component 12 described above in Figure 1.

[0023] A cross-sectional view of the packaged multi-wafer device 200 shows three wafers or dies 204A, 204B, and 204C. However, any number of wafers or dies can be included in the packaged multi-wafer device 200, including additional wafers 204A and 204C, as shown in the top view of FIG2A. In one embodiment, wafers 204A and / or 204C are memory devices such as high-bandwidth memory (HBM) dies. In one embodiment, device 204B is a logic element. Exemplary bare dies may include a variety of semiconductor devices, such as diode-based devices, resistor-capacitor-based devices, transistor-based devices, silicon controller rectifiers, PNP transistors, NPN transistors, n-channel metal-oxide-semiconductor (NMOS) transistors, p-channel metal-oxide-semiconductor (PMOS) transistors, field oxide devices, gate-triggered devices, base-triggered devices, substrate-triggered devices, zener diodes, metal-oxide rheostats, transient voltage suppression diodes, complementary metal-oxide-semiconductor (CMOS) diodes, bipolar clamp diodes, and combinations thereof. Therefore, each of the first die 204A, the second die 204B, and the third die 204C may include multiple transistors, such as planar transistors, fin-type field effect transistors (FinFETs), gate-all-around (GAA) transistors, nanowire transistors, nanosheet transistors, or other multi-gate transistors.

[0024] The packaged multichip device 200 has a package substrate 206. The package substrate 206 may include a printed circuit board (PCB) or a suitable substrate. For electrical contact of the devices in the packaged multichip device 200, connectors 207, such as controlled collapse chip connection (C4) bumps, solder bumps, or other features, are provided on the package substrate 206.

[0025] The first die 204A, the second die 204B, and the third die 204C (and any additional dies) are physically and electrically connected to the interposer substrate 208 via a plurality of microbumps or other interconnects. The space between each of the first die 204A, the second die 204B, and the third die 204C (and / or the space between the die and the interposer 208) may be filled with underfill 210. A molding compound 212 (also referred to as an encapsulation layer) may be disposed around the die to provide structural support and environmental protection. The molding compound 212 may include polymers, resins, epoxy resins, silicon dioxide, alumina, and / or other suitable materials. In embodiments, the interposer 208 may include semiconductor materials such as silicon (Si) substrates. In some alternative embodiments, the interposer 208 includes silicon germanium (SiGe), silicon carbon (SiC), glass, and / or other suitable materials. Interposer 208 includes interconnect layers, such as redistribution layers, connected to each of the first die 204A, the second die 204B, and the third die 204C. Furthermore, through-substrate vias (TSVs) can transmit corresponding signals through interposer 208 to connectors (e.g., microbumps, pillars, C4 bumps, and other suitable connections) between interposer 208 and package substrate 206. Underfill 210 may be located between package substrate 206 and interposer 208. The underfill 210 between interposer substrate 208 and package substrate 206 may be the same as or different from the underfill 210 between dies 204A, 204B, and 204C. Underfill 210 may include polymers, epoxy resins, and / or other suitable materials.

[0026] In one embodiment, one or more of the bare dies 204A, 204B, and 204C are oriented in a flip-chip direction such that the device layer (e.g., Epistar) faces downwards, and the back side of the device substrate is exposed on the top surface of the packaged multi-chip device 200. In one embodiment, the device substrate is a silicon substrate. In some embodiments, the substrate may be a bulk silicon substrate, while in other embodiments, other semiconductor materials including Group III, Group IV, and Group V elements may be used. Alternatively, the substrate may be a silicon insulator (SOI) substrate. Thus, in one embodiment, the silicon substrate surface is exposed on the top surface of the bare dies 204A, 204B, and / or 204C. In some embodiments, a dielectric layer or other protective layer is formed on the back side of the device substrate and exposed on the top surface of the packaged multi-chip device 200. The exposed upper surface of the device 200 between the bare dies 204A, 204B, and 204C may include underfill 210.

[0027] Attached to the upper surface of the packaged multi-wafer device 200 is a thermal management component 202. The thermal management component 202 may be generally similar to the thermal management component 12 described above with reference to FIG. 1. The thermal management component 202 includes a manifold 214 that provides an assembly for receiving conduits for a coolant inlet conduit 218 leading to the thermal management component 202 and conduits for a coolant outlet conduit 220 from the thermal management component 202. The coolant inlet conduit 218 and the coolant outlet conduit 220 may be connected to a coolant handling system, such as the coolant handling system 16 discussed above with reference to FIG. 1.

[0028] In the illustrated embodiment of the thermal management component 202, direct cooling compartments 216 (labeled 216A, 216B, and 216C respectively in FIG. 2B) are located within manifold 214. The direct cooling compartment may be a chamber in which fluid (e.g., a liquid) can be contained, for example, fluid can flow from one side of the compartment to the other. During the flow from one side of the compartment to the other, coolant flows across the upper surface of the device 200 that engages with the compartment. A sealant 222 is disposed along the periphery of the direct cooling compartment 216 and between the compartment 216 and the upper surface of the packaged multi-wafer device 200. The sealant 222 may be a non-permeable adhesive, such as epoxy, resin, or other materials. The sealant 222 may also include mechanical attachment devices, gaskets, clamps, etc. In some embodiments, the sealant 222 is adapted to provide a sealed connection between the packaged element (e.g., the surface of the bare die 204A / B / C) and the direct cooling compartment 216. In one embodiment, a gap is provided between the encapsulated multi-wafer device 200 and the sealant 222, manifold 214, and compartments 216A / 216B / 216C.

[0029] As shown in Figures 2A and 2B, in the embodiments, a single direct cooling compartment 216A, 216B, or 216C is located above each die 204A, 204B, and 204C, respectively. A first inlet pipe 218A, having a first control valve 224A, is configured to supply coolant to the first direct cooling compartment 216A located above the first die 204A. A second pipe 218B, having a second control valve 224B, supplies coolant to the second direct cooling compartment 216B located above the second die 204A. A third pipe 218C, having a third control valve 224C, supplies coolant to the third direct cooling compartment 216C located above the third die 204C. The coolant delivery to each direct cooling compartment can be individually controlled by a control system (e.g., control system 14 discussed above with reference to Figure 1). In some embodiments, in the direct cooling compartments 216A, 216B, 216C, coolant supplied from the corresponding conduits 218A, 218B, 218C is directly provided to the upper exposed surfaces of the device 200, and particularly to the upper exposed surfaces of the respective bare wafers 204A, 204B, 204C. That is, in one embodiment, the coolant is directly provided to the back side of the device substrate (e.g., a silicon substrate) of the corresponding wafer. In further embodiments, the provided coolant may be a liquid coolant. Exemplary coolant compositions include deionized water, alcohols, polymeric liquids, and / or other thermally conductive liquids.

[0030] The outlet pipes remove coolant (i.e., used coolant) from the direct cooling compartments 216A, 216B, 216C. In one embodiment, the coolant moves through the compartments via a pump, pressure, or other suitable mechanism. In some embodiments, the coolant (e.g., used coolant) supplied in the outlet pipes 220A, 220B, 220C is gaseous. In other embodiments, the coolant (e.g., used coolant) is liquid. Due to heat transfer from the corresponding bare crystals 204A, 204B, 204C, the temperature of the coolant (e.g., used coolant) in the outlet pipes 220A, 220B, 220C is higher than the temperature of the corresponding inlet pipes 218A, 218B, 218C. Of course, the configuration of the piping routes of the inlet pipes 218 and the outlet pipes 220 is merely exemplary and different routes may be used to supply the compartments depending on the design shape and environmental factors (e.g., adjacent temperatures of adjacent pipes).

[0031] Because the coolant supply to each direct cooling compartment 216A, 216B, 216C is individually controlled, the thermal conditions for each bare die 204A, 204B, and 204C can be individually controlled. For example, a first coolant at a first flow rate can be supplied at a first inlet pipe 218A to the first direct cooling compartment 216A located above the first bare die 204A to provide a first level of cooling. A second coolant at a second flow rate can be supplied at a second inlet pipe 218B to the second direct cooling compartment 216B located above the second bare die 204B to provide a second level of cooling. The second flow rate, coolant type, and / or cooling level may differ from the first flow rate, coolant type, and / or cooling level. A third coolant at a third flow rate can be supplied at a third pipe 218C to the third direct cooling compartment 216B located above the third bare die 204B to provide a third level of cooling. The third flow rate, coolant type, and / or cooling level may differ from the first flow rate, coolant type, and / or cooling level and / or the second flow rate, coolant type, and / or cooling level. In one embodiment, the second die 204B is a die with properties that generate additional heat (e.g., high power), which is addressed by additional cooling provided by the second direct cooling compartment 216B. During device operation, such as during testing, the thermal conditions of each area of ​​the thermal management components can be adjusted. In one embodiment, the diameter of the conduit leading to one compartment (e.g., 216 covering the logic device 204B) may be larger than the diameter of the other conduits.

[0032] Referring now to Figures 3A and 3B, a packaged multi-chip device 200 is shown, which may be substantially similar to that discussed above. A thermal management component 302 is disposed on and connected to the packaged multi-chip device 200. The thermal management component 302 is substantially the same as the thermal management component 202 shown in Figure 1, and has similarities to, but differences from, the thermal management component 202 discussed above with reference to Figures 2A and 2B. Similar reference numerals indicate features of similar configurations.

[0033] Thermal management component 302 includes a manifold 214 that provides conduit for a single coolant inlet conduit 218D and conduit for a single coolant outlet conduit 220D. A single direct cooling compartment 216D is located within the manifold 214. The direct cooling compartment 216D is a compartment or chamber in which fluid (e.g., liquid coolant) may be contained, wherein the compartment extends over one or more dies of the packaged multi-wafer device 200 (e.g., over dies 204A, 204B, and 204C). A sealant 222 is disposed between the periphery of the direct cooling compartment 216D and the upper surface of the packaged multi-wafer device 200. In some embodiments, the sealant 222 is adapted to provide a sealed connection between the surface of the packaged multi-wafer device 200 and the direct cooling compartment 216D. In one embodiment, the edge of the direct cooling compartment 216D is located above the die of the packaged multi-wafer device 200. For example, a first sealant location may be located on the upper surface of the die 204A, and a second sealant location may be located on the upper surface of the die 204A.

[0034] As shown in Figures 3A and 3B, a single direct cooling compartment 216D is located above all bare crystals 204A, 204B, and 204C. The coolant delivery to the direct cooling compartment 216D can be controlled by a control system, such as the control system 14 discussed above with reference to Figure 1. In some embodiments, in the direct cooling compartment 216D, coolant delivered from inlet conduit 218D is directly supplied to the upper surfaces of the bare crystals 204A, 204B, and 204C. In one embodiment, the temperature of the coolant above the bare crystal 204C is lower than the temperature of the coolant above the bare crystal 204B, and the temperature of the coolant above the bare crystal 204B is lower than the temperature of the coolant above the bare crystal 204A. Therefore, the thermal management component 302 can provide enhanced cooling to the bare crystal 204C compared to the bare crystals 204B and 204A. As described above, outlet conduit 220D removes coolant (i.e., waste coolant with elevated temperature) from the direct cooling compartment 216D. The inlet point of inlet pipe 218D can be varied, as shown by comparing Figures 3A and 3B.

[0035] Referring now to Figures 4A and 4B, a packaged multi-chip device 200 is shown, which may be substantially similar to those discussed above. A thermal management component 402 is disposed on and connected to the packaged multi-chip device 200. The thermal management component 402 may be substantially similar to the thermal management component 12 described in Figure 1 above, and has similarities to, but differences from, the thermal management component 202 described in Figure 2 above. Similar reference numerals indicate features of similar configurations.

[0036] The thermal management component 402 includes a manifold 214 that provides an assembly of conduits for two coolant inlet lines 218E, 218F and two coolant outlet lines 220E, 220F. Three direct cooling compartments 216E, 216F, 216G are located within the manifold 214. The direct cooling compartments 216E, 216F, and 216G may be substantially similar to the direct cooling compartments 216A, 216B, and 216C described above with reference to FIG. 2, respectively. Each of the direct cooling compartments 216E, 216F, and 216G provides a chamber in which fluid (e.g., liquid coolant) can be contained, and the chamber extends to one of the bare dies of the packaged multi-wafer device 200 (e.g., extending over bare dies 204A, 204B, or 204C, respectively).

[0037] As shown in FIG. 4, a first inlet coolant conduit 218E is connected to a direct cooling compartment 216F to supply coolant, and a second inlet coolant conduit 218F is connected to a direct cooling compartment 216G to supply coolant. The coolant delivery to the direct cooling compartments 216G and 216F can be controlled by a control system (e.g., the control system 14 discussed above with reference to FIG. 1). In an implementation of the embodiment of FIG. 4, an outlet coolant conduit 220E' extends from the direct cooling compartment 216G to the direct cooling compartment 216E. That is, in one embodiment, coolant that has already received some heat transfer from the bare die 204C within compartment 216G is then supplied to compartment 216E for heat treatment (e.g., cooling) of the bare die 204A. The coolant has a first temperature at the inlet of the direct cooling compartment 216G, a second temperature higher than the first temperature at the outlet of the direct cooling compartment 216G, and a third temperature higher than the second temperature at the outlet 220E of the direct cooling compartment 216G. In one embodiment, the bare dies 204C and 204A are memory devices. In the illustrated embodiment, the inlet coolant conduit 218E supplies coolant to the direct cooling compartment 216F, and the outlet coolant conduit 220F supplies coolant from the direct cooling compartment 216F. Therefore, the thermal conditions of one bare die 204B can be controlled separately from the thermal conditions of the other bare dies in the system (e.g., 204A and 204C), while bare dies 204A and 204C are controlled together.

[0038] Referring now to FIG. 5A, a packaged multi-chip device 200 is shown, which may be substantially similar to that discussed above. A thermal management component 502 is disposed on and connected to the packaged multi-chip device 200. The thermal management component 502 is generally similar to the thermal management component 202 shown in FIG. 1, and has similarities to, but differences from, the thermal management component 202 discussed above with reference to FIGS. 2A to 4. Similar reference numerals indicate features of similar configurations.

[0039] The thermal management component 502 includes a manifold 214 that provides an assembly of conduits for a coolant inlet conduit 218G and two coolant outlet conduits 220G, 220H. Three direct cooling compartments 216H, 216I, 216J are located within the manifold 214. The direct cooling compartments 216H, 216I, and 216J may be substantially similar to the direct cooling compartments 216A, 216B, and 216C described above with reference to Figures 2A and 2B, respectively. Each of the direct cooling compartments 216H, 216I, and 216J provides a compartment or chamber therein for containing fluid, such that coolant may extend over the portion of the device 200 exposed in the compartment (e.g., one or more bare dies of the packaged multi-wafer device 200 (e.g., one or each of bare dies 204A, 204B)).

[0040] As shown in FIG. 5, a first inlet coolant conduit 218G is connected to a direct cooling compartment 216I to supply coolant. The coolant delivery to the direct cooling compartment 216I can be controlled by a control system (e.g., the control system 14 discussed above with reference to FIG. 1). In the implementation of the embodiment of FIG. 5, an outlet coolant conduit 220I extends from the direct cooling compartment 216I to the direct cooling compartment 216H, and an outlet coolant conduit 220I extends from the direct cooling compartment 216I to the direct cooling compartment 216J. Outlet coolant conduits 220G and 220H extend from the direct cooling compartments 216H and 216J, respectively.

[0041] In other embodiments, the number of inlet pipes is greater than the number of outlet pipes, for example, when hot coolant from one compartment is delivered to another compartment and the outlet pipes do not extend beyond the thermal management component itself. In other embodiments, the number of inlet pipes may be less than the number of outlet pipes.

[0042] Referring now to Figures 6A and 6B, a packaged multi-chip device 200 is shown, which may be substantially similar to those discussed above. A thermal management component 602 is disposed on and connected to the packaged multi-chip device 200. The thermal management component 602 is substantially the same as the thermal management component 12 shown in Figure 1, and has similarities to, but differences from, the thermal management component 202 discussed above with reference to Figure 2. Similar reference numerals indicate features of similar configurations.

[0043] The thermal management component 602 includes a manifold 214 that provides an assembly of conduits for a coolant inlet conduit 218J and a coolant outlet conduit 220J. Similar to the embodiments described above, a valve 224 is provided to control the coolant supplied by the coolant inlet conduit 218J, for example, through a control system (as shown in control system 14 of FIG1). Within the manifold 214, three distinct regions or blocks are provided, each corresponding to a die 204A, 204B, or 204C, respectively. A nozzle 604 is provided in each region. The nozzle 604 is operable to deliver coolant 606 to the upper surface of the packaged multi-wafer device 200. In one embodiment, coolant 606 is delivered to the top surface of each die 204A, 204B, and 204C (e.g., the exposed portion of the device substrate of each die). The coolant 606 can be delivered in a liquid phase. While independent control of cooling for each region may not be provided in this embodiment, cooling efficiency can be improved. Figure 6B illustrates that a nozzle 604 above a die (e.g., 204B) can provide a greater quantity of coolant 606. Of course, including Figure 6A, each nozzle 604 can include multiple nozzles to deliver coolant. The illustration in Figure 6B merely suggests that the number of nozzles / heads delivering coolant on one die is greater than the number of nozzles / heads delivering coolant on another die.

[0044] Referring now to FIG. 7, a packaged multi-chip device 200 is shown, which may be substantially similar to that discussed above. A thermal management component 702 is disposed on and connected to the packaged multi-chip device 200. The thermal management component 702 may be substantially the same as the thermal management component 12 shown in FIG. 1, and has similarities to the thermal management component 202 discussed with reference to FIG. 2B and the thermal management component 602 discussed with reference to FIG. 6. Similar reference numerals indicate features of similar configurations. As shown, die 204B experiences thermal conditions defined by coolant 606 (e.g., liquid coolant) supplied from nozzle 604 in manifold 214 arranged above die 204B. Dies 204A and 204C experience thermal conditions defined by coolant (e.g., liquid coolant) supplied to direct cooling compartments 216K and 216L, respectively. Inlet pipes 218L, 218K and 218M deliver coolant to the corresponding direct cooling compartment or nozzle via control valve 224; outlet pipes 220K, 220L and 220M remove coolant from manifold 214.

[0045] The embodiment of FIG. 7 can provide enhanced cooling efficiency in the desired region (e.g., bare die 204B). The embodiment of FIG. 7 also provides individual control over each region of the thermal management component 702 and therefore each bare die 204A, 204B, and 204C. The embodiment of FIG. 7 can be used when the test conditions for each device vary during a single test, for example, when it is desired that one bare die maintain a lower target temperature than the others during a single test.

[0046] Referring now to FIG8, a method 800 for testing multi-wafer packaged semiconductor devices is shown, and is particularly suitable for testing multi-wafer packaged semiconductor devices. Method 800 can be implemented using the thermal management system 11 described above with reference to FIG1. ​​Method 800 can also be implemented using one or more aspects of the embodiments of FIG2 through 7 as described above. For clarity, FIG8 has been simplified to better understand the inventive concept disclosed herein. Additional steps can be added to method 800, and some steps described below can be substituted, modified, or eliminated in other embodiments of the testing method.

[0047] In block 802, the pick and place (PnP) arm places the device under test (DUT) into the test socket of the tester. In one embodiment, the device may be substantially similar to the packaged multi-wafer device 200 discussed above with reference to FIG. 2. This tester may be substantially similar to the tester discussed below with reference to FIG. 9. In block 804, a thermal test head may engage the DUT. In one embodiment, the thermal test head includes one or more of the thermal management components 12, 202, 302, 402, 502, 602, or 702 discussed above with reference to FIGS. 1, 2, 3, 4, 5, 6, and 7. For example, in one embodiment, the test head may be selected to provide the same number of thermal areas (e.g., individually controllable areas or blocks) as the bare die in the DUT (e.g., the bare die exposed at the top surface of the DUT). The engagement of the test head and the DUT may be sufficient to prevent leakage by any seal (see, for example, sealant 222 discussed above).

[0048] In block 806, a coolant path is established to the test head, and in particular, the thermal management components of the test head. As described above, the coolant can be supplied through piping. In one embodiment, a control system, such as control system 14, is used to determine the coolant, and the control system can provide instructions to the valves of the cooling treatment system (coolant treatment system 16). The coolant can be a liquid coolant.

[0049] Method 800 then continues to block 808, where the DUT is tested. (In some embodiments, the testing at block 808 may begin before coolant is provided in block 806.) The testing of the DUT may cause the DUT to generate heat. During the testing of the DUT at block 808 and the resulting heat, feedback on the DUT's state (block 808A) (e.g., feedback on the temperature of each zone of a multi-zone thermal test head (e.g., thermal management component) may be provided to the control system. The feedback may be provided by a temperature sensor, voltage or power reading, and / or other suitable feedback mechanism. The feedback may be provided to the control system, such as control system 14 discussed above in FIG. 1. During the test, the thermal conditions provided by the thermal test head and its thermal management component may be adjusted in block 808B based on the feedback on the thermal conditions provided in block 808A. In one embodiment, adjusting the thermal conditions includes adjusting the coolant supplied to one or more zones of the thermal management component of the test head, for example by manipulating a valve in the inlet pipe to increase the flow rate of coolant to a first zone of the thermal management component of the test head. Adjustments can be performed individually for each region of the thermal management component, for example, increasing the first coolant rate to a first region and decreasing the second coolant rate to a second region. In one embodiment, feedback from block 808A is compared with the desired test temperature to determine the adjustment of block 808B. This feedback and adjustment can control the thermal conditions of one or more regions of the test head, so the DUT can continue throughout the test. Note that in some implementations, different tests with different thermal setpoints can be performed. Therefore, the adjustment of the thermal conditions in block 808B can be based on the desired test conditions.

[0050] In block 810, the DUT test is terminated. Based on the test results of block 808, the DUTs can be classified and / or sorted, also known as grading. The test can evaluate the electrical characteristics, reliability, behavior, other characteristics and / or behaviors, or combinations thereof of the DUT in response to various inputs and / or conditions (e.g., a specific temperature). After the test is completed, coolant delivery can be stopped. In an embodiment, a vacuum operation removes residual liquid coolant from the top surface of the DUT. Method 800 continues to block 812, where the thermal test head is disengaged, and in block 814, the PnP arm removes the DUT from the test socket.

[0051] Referring now to FIG. 9, a block diagram of a partial or complete exemplary test system 900 for IC testing according to various aspects of the present disclosure is shown. For clarity, FIG. 9 has been simplified to better understand the inventive concept of the present disclosure. Additional features may be added to the test system 900 and / or its components, and some features described below may be replaced, modified, or eliminated in other embodiments of the test system 900 and / or its components. The test system 900 may perform the method 800 discussed above with reference to FIG. 8.

[0052] The test system 900 includes a tester 902 (also known as automatic / automated test equipment (ATE)). The test system 900 is configured to test the quality and / or functionality of a device under test (DUT) such as DUT 904. A test processor (such as a pick-and-place (PnP) assembly, not shown) can position the DUT 904 to make mechanical and / or electrical contact with the tester 902 via a test interface 906 (such as a load plate or socket). The tester 902 performs tests on the DUT 904 and evaluates its performance and / or characteristics. Based on the test results, the DUT 904 is classified and / or sorted by the test processor (not shown), also known as grading. The test system 900 can evaluate the electrical characteristics, reliability, behavior, other characteristics and / or behaviors, or combinations thereof of the DUT in response to various inputs and / or conditions (e.g., a specific temperature). In some embodiments, the test system 900 evaluates the electrical characteristics and / or operation of the DUT at high temperatures. In some embodiments, the test system 900 subjectes the DUT to reliability tests, such as thermal cycling and / or thermal shock tests. These tests can be performed under desired thermal conditions (e.g., temperature) by controlling thermal conditions through the thermal management component 910, as described below.

[0053] The DUT 904 has surfaces 904A and 904B, which may be referred to as the top surface and bottom surface, respectively. DUT contacts are formed on surface 904B of conductive material. The DUT contacts may be arranged on surface 904B to form a contact array / pattern, such as a ball grid array. In some embodiments, the DUT contacts are solder balls, such as those shown above with reference to connector 207, as described with reference to FIG. 2. These contacts are connected to the tester. Specifically, test interface 906 provides a mechanical and electrical interface between tester 902 and DUT 904, and test interface 906 transmits signals between tester 902 and DUT 904, such as test signals from tester 902 to DUT 904 and response signals from DUT 904 to DUT 904. Test interface 906 may include a load board, such as a printed circuit board (PCB), a socket mounted on the load board, a test head or a portion thereof, and / or other configurations. The configuration of the test interface 906 depends on the type and / or configuration of the DUT 904 being tested and is not limited to this disclosure. An exemplary socket 908 is shown, which includes a cavity for receiving the DUT 904. In some embodiments, the socket 908 also includes contacts, such as probe cards with probe pins, spring-loaded pins (e.g., pogo pins), contacts of various shapes embedded in an elastomer, particle interconnects, other suitable types of contacts and / or interconnects, or combinations thereof.

[0054] A thermal management component 910 for the test head may also be provided, configured to connect to surface 904A of device 904. Thermal management component 910 may be substantially similar to thermal management components 12, 202, 302, 402, 502, 602 and / or 702 discussed above with reference to Figures 2 to 7. Thermal management component 910 is coupled to control system 14, which may be substantially similar to that discussed above with reference to Figure 1. Thermal management component 910 may also be connected to coolant handling system 16, as described above. Specifically, thermal management component 910 may be connected to coolant handling system 16 via inlet and outlet coolant pipes. Thermal management component 910 may include one or more zones or blocks that can be controlled to provide suitable thermal conditions for DUT 904 during testing by tester 902.

[0055] This disclosure provides a semiconductor device testing system, including a packaged multi-die semiconductor device, a tester, a thermal management component, a coolant handling system, and a control system. The packaged multi-die semiconductor device has a surface. The tester has a socket in which the packaged multi-die semiconductor device is disposed. The thermal management component engages the packaged multi-die semiconductor device in the socket, wherein the surface of the packaged multi-die semiconductor device is connected to the thermal management component. The coolant handling system is operable to provide a coolant to the thermal management component. The control system is operable to control the supply of coolant from the coolant handling system to the thermal management component.

[0056] In one embodiment, the coolant handling system includes a plurality of conduits extending to a thermal management component. In one embodiment, the thermal management component includes a sealed compartment connected to the surface of a packaged multi-die semiconductor device. In one embodiment, the thermal management component includes a first compartment and a second compartment, wherein a conduit extends from the first compartment to the second compartment. In one embodiment, in a top view, a sealed compartment of the thermal management component is centered on and included within a boundary defined by a die of the packaged multi-die semiconductor device. In one embodiment, the thermal management component includes a plurality of sealed compartments for receiving coolant. In one embodiment, each sealed compartment is engaged with the surface of the packaged multi-die semiconductor device. In one embodiment, the thermal management component includes at least one jet delivery member.

[0057] This disclosure provides a semiconductor device testing system and a method for testing a semiconductor device, the method comprising: placing a packaged semiconductor device on a tester; bonding a thermal management component to an upper surface of the packaged semiconductor device; and testing the packaged semiconductor device using the tester, and during the test, delivering a first thermal condition to a first region of the thermal management component and simultaneously delivering a second thermal condition to a second region of the thermal management component, wherein the first thermal condition is different from the second thermal condition.

[0058] In one embodiment, a first thermal condition is delivered by supplying a first liquid coolant to a first region of the thermal management component, and a second thermal condition is delivered by supplying a second liquid coolant to a second region of the thermal management component. In one embodiment, the first liquid coolant is delivered by a spray, and the second liquid coolant is delivered to a sealed compartment connected to a portion of the packaged semiconductor device. In one embodiment, the first region is a sealed compartment connected to a first region of the upper surface of the packaged semiconductor device, and the second region is another sealed compartment connected to a second region of the upper surface of the packaged semiconductor device. In one embodiment, the first region of the upper surface of the packaged semiconductor device is a first die, and the second region of the upper surface of the packaged semiconductor device is a second die. In one embodiment, the method further includes: determining a first temperature associated with the first region and determining a second temperature associated with the second region, wherein the second temperature is different from the first temperature. In one embodiment, the method further includes: setting a first target temperature for the first region and setting a second target temperature for the second region.

[0059] This disclosure provides a semiconductor device testing system and a method for regulating a thermal environment of a semiconductor structure. The method includes: providing a multi-die packaged semiconductor device; providing a thermal management component connected to an upper surface of the multi-die packaged semiconductor device; during an operation of the multi-die packaged semiconductor device, delivering a first liquid coolant to a first region of the thermal management component, wherein the first region covers a first die of the multi-die packaged semiconductor device; and delivering a second liquid coolant to a second region of the thermal management component, wherein the second region covers a second die of the multi-die packaged semiconductor device, and wherein the delivery of the second liquid coolant is performed simultaneously with the delivery of the first liquid coolant.

[0060] In one embodiment, a first region of the thermal management component is a first sealed compartment, wherein one side of the first sealed compartment is defined by an upper surface of a first die. In one embodiment, a second region of the thermal management component includes a nozzle disposed above an upper surface of a second die. In one embodiment, a second region of the thermal management component includes a second sealed compartment, wherein one side of the second sealed compartment is defined by an upper surface of a second die. In one embodiment, the method further includes: delivering a third liquid coolant to a third region of the thermal management component, wherein the third region covers a third die of a multi-die packaged semiconductor device.

[0061] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0006] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG1 is a cross-sectional view of a thermal management component connected to a multi-die package element according to aspects of this disclosure. FIG2A is a top view of an embodiment of a thermal management component positioned above a device according to aspects of this disclosure. FIG2B, FIG3A, FIG3B, FIG4, FIG5, FIG6A, FIG6B and FIG7 show cross-sectional views of embodiments of thermal management components with various coolant path configurations according to aspects of this disclosure. FIG8 shows an embodiment of a test device implementing thermal management control according to aspects of this disclosure. FIG9 shows a block diagram of a device under test (DUT) in a test system with a thermal management component according to aspects of this disclosure.

Claims

1. A semiconductor device testing system, comprising: A packaged multi-die semiconductor device having a surface; A tester having a socket in which the packaged multi-die semiconductor device is disposed; A thermal management component, engaging the packaged multi-die semiconductor device in the socket, wherein the surface of the packaged multi-die semiconductor device is connected to the thermal management component; a coolant handling system operable to provide a coolant to the thermal management component, wherein the coolant in the thermal management component is in direct contact with the surface of the packaged multi-die semiconductor device; and a control system operable to control the supply of coolant from the coolant handling system to the thermal management component.

2. The system as claimed in claim 1, wherein the thermal management component includes a first compartment and a second compartment, wherein a conduit extends from the first compartment to the second compartment.

3. The system as claimed in claim 1, wherein, in a top view, a sealed compartment of the thermal management component is centered on and included within a boundary defined by a die of the packaged multi-die semiconductor device.

4. The system as claimed in claim 1, wherein the thermal management component includes a plurality of sealed compartments for receiving the coolant.

5. The system as claimed in claim 4, wherein each of the hermetically sealed compartments is coupled to the surface of the packaged multi-die semiconductor device.

6. A method for testing a semiconductor device, the method comprising: A packaged semiconductor device is placed on a tester; A thermal management component is attached to an upper surface of the packaged semiconductor device; The tester is used to test the packaged semiconductor device, and during the test, a first thermal condition is applied to a first region of the thermal management component, and a second thermal condition is applied to a second region of the thermal management component, wherein the first thermal condition is different from the second thermal condition, wherein the first thermal condition is applied by supplying a first liquid coolant to the first region of the thermal management component, and the second thermal condition is applied by supplying a second liquid coolant to the second region of the thermal management component, wherein the first liquid coolant and the second liquid coolant in the thermal management component are in direct contact with the upper surface of the packaged semiconductor device.

7. The method as described in claim 6, wherein the first liquid coolant is delivered via a spray and the second liquid coolant is delivered to a sealed compartment connected to a portion of the packaged semiconductor device.

8. The method as described in claim 6, wherein the first region is a sealed compartment connected to a first region of the upper surface of the packaged semiconductor device, and wherein the second region is another sealed compartment connected to a second region of the upper surface of the packaged semiconductor device.

9. The method as described in claim 8, wherein the first region of the upper surface of the packaged semiconductor device is a first die, and the second region of the upper surface of the packaged semiconductor device is a second die.

10. The method as described in claim 6, further comprising: A first temperature associated with the first region is determined and a second temperature associated with the second region is determined, wherein the second temperature is different from the first temperature.

11. A method for regulating a thermal environment of a semiconductor structure, the method comprising: Provide a multi-die packaged semiconductor device; A thermal management component is provided that is connected to an upper surface of the multi-die packaged semiconductor device; During an operation of the multi-die packaged semiconductor device, a first liquid coolant is delivered to a first region of the thermal management component, wherein the first region covers a first die of the multi-die packaged semiconductor device; and a second liquid coolant is delivered to a second region of the thermal management component, wherein the second region covers a second die of the multi-die packaged semiconductor device, and wherein the delivery of the second liquid coolant is simultaneous with the delivery of the first liquid coolant, wherein the first liquid coolant and the second liquid coolant in the thermal management component are in direct contact with the upper surface of the multi-die packaged semiconductor device.

12. The method as described in claim 11, wherein the first region of the thermal management component is a first sealed compartment, wherein one side of the first sealed compartment is defined by an upper surface of the first bare die.

13. The method as described in claim 12, wherein the second region of the thermal management component includes a nozzle disposed above an upper surface of the second bare die.

14. The method as described in claim 12, wherein the second region of the thermal management component includes a second sealing compartment, wherein one side of the second sealing compartment is defined by an upper surface of the second bare die.

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