Plasma etching in semiconductor processing

Abstract

Semiconductor processing methods may include forming a plasma effluent containing various precursors, such as etchant precursors, oxygen-containing precursors, and silicon- and fluorine-containing precursors, such as silicon tetrafluoride. The plasma effluent may then contact a silicon-containing material and a masking material on a substrate in a processing area of ​​a semiconductor processing chamber. The masking material may have one or more pores to allow the plasma effluent to reach the silicon-containing material. Contact between the silicon-containing material and the masking material and the plasma effluent may result in (i) etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material, and (ii) simultaneously etching the masking material with the plasma effluent and depositing silicon- and oxygen-containing material on the masking material.

Description

Technical Field

[0001] Cross - Reference to Related Applications: This application claims the benefit and priority of U.S. Non - Provisional Application No. 18 / 234,685, filed on August 16, 2023, with the title "PLASMA ETCHING IN SEMICONDUCTOR PROCESSING", the content of which is hereby incorporated by reference in its entirety for all purposes.

[0002] The present technology relates to semiconductor processing methods and components. More specifically, the present technology relates to systems and methods for etching silicon - containing materials. Background Art

[0003] Integrated circuits are realized through a process of generating complex patterned material layers on a substrate surface. Generating patterned materials on a substrate requires controlled methods to remove the exposed materials. Chemical etching is used for various purposes, including transferring patterns in photoresist to underlying layers, thinning layers, or reducing the lateral dimensions of existing features on a surface. Generally, an etching process that can etch one material faster than another is desired to facilitate, for example, a pattern transfer process. Due to the diversity of materials, circuits, and processes, etching processes have evolved to be selective for various materials.

[0004] Depending on the materials used in the process, etching processes can be classified into wet etching and dry etching. Wet HF etching preferentially removes silicon oxide rather than other dielectrics and materials. However, wet processes may be difficult to penetrate some confined trenches and may sometimes deform the remaining materials. Dry etching, which occurs in a local plasma formed within a substrate processing region, can penetrate more confined trenches and cause less deformation to fine remaining structures. However, local plasmas may generate arcs during discharge, thereby damaging the substrate.

[0005] Therefore, there is a need for improved systems and methods in order to produce high - quality components and structures. The present technology can meet these and other needs. Summary of the Invention

[0006] Exemplary methods of semiconductor processing may include forming a plasma effluent of various precursors (e.g., an etchant precursor, an oxygen-containing precursor, and a silicon- and fluorine-containing precursor). An example of the silicon- and fluorine-containing precursor is silicon tetrafluoride. The plasma effluent may then contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. More specifically, the silicon-containing material may be disposed on the substrate, and the mask material (e.g., a dielectric material) may be disposed on the silicon-containing material. The mask material may have one or more apertures to allow the plasma effluent to reach the silicon-containing material. Contacting the silicon-containing material and the mask material with the plasma effluent may result in (i) etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material, and (ii) simultaneously etching the mask material with the plasma effluent and depositing a silicon- and oxygen-containing material on the mask material.

[0007] In some embodiments, the etchant precursor may include one or more of the following: a chlorine-containing precursor, a bromine-containing precursor, and a fluorine-containing precursor other than silicon tetrafluoride. In some embodiments, the volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursor may be less than or about 50:1. Additionally, the volume ratio of the etchant precursor to the oxygen-containing precursor may be less than or about 20:1. In some cases, a carrier gas may be present when forming the plasma effluent, and the volume ratio of the carrier gas to the oxygen-containing precursor may be less than or about 10:1.

[0008] In some embodiments, the silicon-containing material may include one or more of the following: crystalline silicon, amorphous silicon, doped silicon, silicon nitride, silicon carbide, boron silicide, tungsten silicide, tungsten carbide boride, and silicon germanium. The semiconductor processing method may selectively remove the silicon-containing material relative to the mask material. For example, the semiconductor processing method may remove the silicon-containing material with a selectivity greater than or about 4 relative to the mask material.

[0009] In some cases, the one or more apertures are characterized by a critical dimension less than or about 1000 nm, or preferably less than or about 50 nm, such as 5 nm to 25 nm. After etching the silicon-containing material, the one or more features are characterized by a depth greater than or about 100 nm. After etching the silicon-containing material, the one or more features are characterized by an aspect ratio greater than or about 5:1.

[0010] In some embodiments, the pressure in the processing region may be maintained at about 5 Torr or lower. In some embodiments, the temperature in the processing region may be maintained at about 100°C or lower. In some embodiments, the plasma effluent may be generated at a plasma power of about 5000 W or lower.

[0011] Some embodiments of the present technology may cover semiconductor processing methods. The method may include forming a plasma effluent of a plurality of precursors (such as an etchant precursor, an oxygen-containing precursor, and a silicon- and fluorine-containing precursor) in the presence of a carrier gas. An example of the silicon- and fluorine-containing precursor is silicon tetrafluoride. The volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursor may be less than or about 50:1; the volume ratio of the etchant precursor to the oxygen-containing precursor may be less than or about 20:1; the volume ratio of the carrier gas to the oxygen-containing precursor may be less than or about 10:1. Then, the plasma effluent may contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. More specifically, the silicon-containing material may be disposed on the substrate, and the mask material (such as a dielectric material) may be disposed on the silicon-containing material. The mask material may have one or more pores to allow the plasma effluent to reach the silicon-containing material. The contact of the silicon-containing material and the mask material with the plasma effluent may result in (i) etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material, and (ii) simultaneously etching the mask material with the plasma effluent and depositing a silicon- and oxygen-containing material on the mask material.

[0012] The semiconductor processing method may selectively remove the silicon-containing material relative to the mask material. For example, the semiconductor processing method may remove the silicon-containing material with a selectivity greater than or about 4 relative to the mask material. In some cases, the features of one or more pores are characterized by a critical dimension less than or about 1000 nm, or preferably less than or about 50 nm, such as 5 nm to 25 nm. After etching the silicon-containing material, the features of one or more features are characterized by a depth greater than or about 100 nm. After etching the silicon-containing material, the features of one or more features are characterized by an aspect ratio greater than or about 5:1.

[0013] Some embodiments of the present technology may cover semiconductor processing methods. The method may include forming a plasma effluent of a plurality of precursors (such as an etchant precursor, an oxygen-containing precursor, and silicon tetrafluoride, wherein the volume ratio of the oxygen-containing precursor to silicon tetrafluoride is less than or about 50:1). Then, the plasma effluent may contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. More specifically, the silicon-containing material may be disposed on the substrate, and the mask material (such as a dielectric material) may be disposed on the silicon-containing material. The mask material may have one or more pores to allow the plasma effluent to reach the silicon-containing material. Contacting the silicon-containing material and the mask material with the plasma effluent may result in (i) etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material, and (ii) simultaneously etching the mask material with the plasma effluent and depositing a silicon- and oxygen-containing material on the mask material.

[0014] In some embodiments, the plasma effluent can be a first plasma effluent of a first plurality of precursors, and the method can further include forming a second plasma effluent from a second plurality of precursors that do not include silicon tetrafluoride. The second plasma effluent can etch a silicon-containing material to form and / or deepen one or more features in the silicon-containing material.

[0015] A semiconductor processing method can selectively remove a silicon-containing material relative to a masking material. For example, a semiconductor processing method can remove a silicon-containing material with a selectivity greater than or about 4 relative to a masking material. In some cases, one or more features of the pores are characterized by a critical dimension less than or about 1000 nm, or preferably less than or about 50 nm, such as 5 nm to 25 nm. After etching the silicon-containing material, one or more features are characterized by a depth greater than or about 100 nm. After etching the silicon-containing material, one or more features are characterized by an aspect ratio greater than or about 5:1.

[0016] This technique can provide many advantages over conventional systems and techniques. For example, embodiments of the present technique can enhance the formation and deepening of features in a semiconductor structure. These and other embodiments, as well as many of their advantages and features, are described in more detail in conjunction with the following description and the accompanying drawings. Brief Description of the Drawings

[0017] Reference to the remainder of the specification and the drawings can further understand the nature and advantages of the disclosed technique.

[0018] FIG. 1 shows a schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technique.

[0019] FIG. 2 shows operations in a semiconductor processing method according to some embodiments of the present technique.

[0020] FIGS. 3A to 3C show exemplary schematic cross-sectional structures produced according to some embodiments of the present technique.

[0021] Some of the figures are incorporated by way of illustration. It should be understood that these figures are for illustrative purposes only and should not be considered drawn to scale unless explicitly stated to be so. Additionally, as schematic diagrams, these figures are used to aid understanding and may not include all aspects or information equivalent to the actual object and may include exaggerated materials for illustrative purposes.

[0022] In the accompanying drawings, like parts and / or features may have the same reference numerals. Additionally, various parts of the same type can be distinguished by adding a letter to the reference numeral to differentiate the like parts. If only the first reference numeral is used in the specification, the description applies to any of the like parts having the same first reference numeral, regardless of the letter. Embodiment

[0023] As the dimensions of semiconductor structures decrease, the feature sizes on such structures also decrease and generally become more dense. Multiple methods can be used to form features on semiconductor structures, including etching, which can use a masking material to protect underlying silicon-containing material, where pores in the masking material allow the underlying silicon-containing material to be etched at desired locations. Conventional techniques use plasma etching and masking to increase the feature depth on semiconductor structures. However, the etchant can damage the mask, resulting in irregular feature sizes. Additionally, as the critical dimension (or width) at the feature opening decreases, reactions at the mask or at the top of the feature are more likely to clog or seal the opening and prevent the etchant from entering the feature. One way to overcome this problem is to use a thicker mask, where the cost and time to produce the mask increase with increasing thickness.

[0024] This technique overcomes these problems using a silicon- and fluorine-containing precursor (such as silicon tetrafluoride). In a plasma etching method, the silicon- and fluorine-containing precursor can produce a silicon-containing plasma effluent and a fluorine-containing plasma effluent. As described in more detail herein, the silicon-containing plasma effluent can promote the regeneration of the masking material being etched simultaneously during the process. Overall, this simultaneous action results in minimal change in the mask thickness during the processes disclosed herein, thus facilitating the use of a thinner mask.

[0025] Furthermore, the fluorine-containing plasma effluent has a relatively high electronegativity, which enables the fluorine-containing plasma effluent to impede the deposition of unwanted materials, particularly at the openings of the features, thereby alleviating the clogging of the openings.

[0026] Although the remainder of the disclosure will routinely identify specific semiconductor processing methods that utilize the disclosed technology and will describe one type of semiconductor processing chamber, it should be readily understood that the processes can be performed in any number of semiconductor processing chambers. Accordingly, the technology should not be considered limited to these specific deposition processes or chambers. Before describing a semiconductor processing method in accordance with the present technology, the present disclosure will discuss one possible chamber that can be used to perform the processes of embodiments in accordance with the present technology.

[0027] [Figure] [1] shows a schematic cross-sectional view of an exemplary processing chamber 100, which is suitable for patterning a material layer on a substrate 102 located in the processing chamber 100. The exemplary processing chamber 100 is suitable for performing a patterning process. However, it should be understood that aspects of the present technology can be performed in any number of chambers, and the substrate support according to the present technology can be incorporated into an etching chamber, a deposition chamber, a treatment chamber, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 that defines a chamber space 101 in which a substrate can be processed. The chamber body 105 may have a sidewall 112 and a bottom 118 coupled to a ground terminal 126. The sidewall 112 may have a liner 115 to protect the sidewall 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and the related components of the plasma processing chamber 100 are not limited and are generally scalable to be larger than the size of the substrate 102 to be processed therein. Examples of substrate sizes include a diameter of 200 mm, a diameter of 250 mm, a diameter of 300 mm, and a diameter of 450 mm, etc., such as display or solar cell substrates.

[0028] The chamber body 105 may support a chamber lid assembly 110 to enclose the chamber space 101. The chamber body 105 may be made of aluminum or other suitable materials. A substrate access port 113 may be formed through the sidewall 112 of the chamber body 105 to facilitate the transfer of the substrate 102 into and out of the plasma processing chamber 100. The access port 113 may be coupled to a transfer chamber and / or other chambers of the substrate processing system as described above. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber space 101. A pumping device may be coupled to the chamber space 101 through the pumping port 145 to evacuate and control the pressure within the processing space. The pumping device may include one or more pumps and throttle valves.

[0029] The gas panel 160 can be coupled to the chamber body 105 through a gas pipeline 167 to supply process gas into the chamber space 101. The gas panel 160 can include one or more process gas sources 161, 162, 163, 164, and can additionally include inert gases, non-reactive gases, and reactive gases, such as those available for various processes. Examples of process gases that the gas panel 160 can provide include but are not limited to: hydrocarbon gases containing carbon such as methane, silicon tetrafluoride, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon gases, argon, chlorine, nitrogen, helium, or oxygen, as well as a variety of additional materials. In addition, the process gas can include gases containing nitrogen, chlorine, fluorine, oxygen, and hydrogen, such as H2, NH3, H2O, H2O2, NF3, HF, F2, CF4, CHF3, C2F6, C2F4, C3F6, C4F6, C4F8, BrF3, ClF3, SF6, CH3F, CH2F2, BCl3, PF3, PH3, SO2, and COS, as well as any number of additional precursors.

[0030] The valve 166 can control the flow of process gas from the sources 161, 162, 163, 164 of the gas panel 160 and can be managed by the controller 165. The flow of gas supplied from the gas panel 160 to the chamber body 105 can include a combination of gases from one or more sources. The lid assembly 110 can include a nozzle 114. The nozzle 114 can be one or more ports for introducing process gas from the sources 161, 162, 164, 163 of the gas panel 160 into the chamber space 101. After introducing the process gas into the plasma processing chamber 100, the gas can be energized to form a plasma. An antenna 148 (such as one or more inductive coils) can be provided near the plasma processing chamber 100. The antenna power supply 142 can supply power to the antenna 148 through a matching circuit 141 to inductively couple energy (such as RF energy) to the process gas, thereby maintaining the plasma formed by the process gas in the chamber space 101 of the plasma processing chamber 100. As an alternative, or in addition to the antenna power supply 142, a process electrode located below and / or above the substrate 102 can be used to capacitively couple RF power to the process gas, thereby maintaining the plasma within the chamber space 101. The operation of the power supply 142 can be controlled by a controller (such as the controller 165), which also controls the operation of other components in the plasma processing chamber 100.

[0031] The substrate support base 135 can be disposed in the chamber space 101 to support the substrate 102 during processing. The substrate support base 135 can include an electrostatic chuck 122 for holding the substrate 102 during processing. The electrostatic chuck (「ESC」) 122 can hold the substrate 102 to the substrate support base 135 using electrostatic attraction. The ESC 122 can be powered by an RF power supply 125 integrated with a matching circuit 124. The ESC 122 can include an electrode 121 embedded in a dielectric body. The electrode 121 can be coupled to the RF power supply 125 and can provide a bias voltage that attracts plasma ions formed from the process gas in the chamber space 101 to the ESC 122 and the substrate 102 on the base. During processing of the substrate 102, the RF power supply 125 can cycle between on and off (or pulsed). The ESC 122 can have an isolator 128 to make the sidewalls of the ESC 122 less attractive to the plasma, thereby extending the maintenance life cycle of the ESC 122. Additionally, the substrate support base 135 can have a cathode pad 136 to protect the sidewalls of the substrate support base 135 from the plasma gas and to extend the maintenance interval of the plasma processing chamber 100.

[0032] The electrode 121 can be coupled to a power supply 150. The power supply 150 can provide an adsorption voltage of about 5000 volts to about -5,000 volts to the electrode 121. The power supply 150 can also include a system controller for controlling the operation of the electrode 121 by directing a direct current to the electrode 121 to adsorb and desorb the substrate 102. For example, similar to the RF power supply 125, the power supply 150 can provide a bias voltage to attract plasma ions formed from the process gas in the chamber space 101 to the ESC 122 and the substrate 102 located on the base. During processing of the substrate 102, the power supply 150 can cycle on and off or pulse. In an embodiment, the power supply 150 can supply RF power, a direct current or voltage for adsorption and / or bias, or a combination of the above. In additional embodiments, multiple power supplies can be configured to supply RF power and direct current or voltage for adsorption and / or bias. The ESC 122 can include a heater disposed within the base and connected to a power supply for heating the substrate, and the cooling base 129 that supports the ESC 122 can include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC 122 and the substrate 102 disposed on the ESC 122. The ESC 122 can be configured to operate within a temperature range required by the thermal budget of the components fabricated on the substrate 102. For example, the ESC 122 can be configured to hold the substrate 102 at a temperature of about -150°C or lower to about 500°C or higher, depending on the process being performed.

[0033] The cooling base 129 can be used to assist in controlling the temperature of the substrate 102. To mitigate process drift and time, the temperature of the substrate 102 can be kept substantially constant by the cooling base 129 throughout the time the substrate 102 is in the cleaning chamber. In some embodiments, the temperature of the substrate 102 can be maintained at a temperature between about -150°C and about 500°C during subsequent cleaning processes, although any temperature can be employed. The cover ring 130 can be disposed on the ESC 122 and along the perimeter of the substrate support base 135. The cover ring 130 can be configured to confine the etching gas to the desired portion of the exposed top surface of the substrate 102 while shielding the top surface of the substrate support base 135 from the plasma environment within the plasma processing chamber 100. The lift pins can be selectively transferred through the substrate support base 135 to raise the substrate 102 above the substrate support base 135 for access to the substrate 102 by a transfer robot or other suitable transfer mechanism, as previously described.

[0034] The controller 165 can be used to control the process sequence, regulate the gas flow rate into the plasma processing chamber 100 from the gas panel 160, and other process parameters. When the CPU executes the software routine, the CPU is transformed into a dedicated computer (e.g., a controller) that can control the plasma processing chamber 100 to perform processes in accordance with the disclosure herein. The software routine can also be stored and / or executed by a second controller associated with the plasma processing chamber 100.

[0035] The previously discussed chamber can be used to perform exemplary methods, including an etching method and a processing method. Turning to [FIG.] [2], which shows exemplary operations in a method 200 according to an embodiment of the present technology. Before the first operation of the method, the substrate can be processed in one or more ways (e.g., front-end processing, deposition, etching, polishing, cleaning, or any other operation) before being placed in the processing area of a chamber that can perform method 200. Some or all of these operations can be performed in the previously described chamber or system tool, or can be performed in different chambers on the same system tool, which can include the chamber that performs the operations of method 200.

[0036] Method 200 can include several optionally selected operations that may or may not be specifically related to some embodiments of the method according to the present technology. For example, many operations are described to provide a broader range of structure formation but are not critical to the technology or can be performed by alternative methods, as will be further discussed below. Method 200 describes [FIG.] The operations schematically illustrated in [3A-3C] will be described in conjunction with the operations of method 200 with reference to the schematic diagrams of these operations. It should be understood that FIGS. 3A-3B only show partial schematic diagrams, and the substrate may include any number of structural segments having the aspects shown in the figures, as well as alternative structural aspects that may still benefit from the operations of the present technology.

[0037] Method 200 may (or may not) involve optional operations, as the case may be, to develop the semiconductor structure 300 for a particular manufacturing operation. It should be understood that method 200 may be performed on any number of semiconductor structures 300, and FIG. 3A shows an exemplary structure in which a contact cleaning or etching process may be performed. As shown in FIG. 3A, the processed semiconductor structure 300 may include a substrate 305, on which a silicon-containing material 310 is disposed, and a patterned mask material 315 is disposed on the substrate 305 itself. The substrate 305 may be or may include a dielectric material, such as an oxide or nitride of any number of materials. For example, the silicon-containing material 310 may be or may include crystalline silicon, amorphous silicon, doped silicon, silicon nitride, silicon carbide, boron silicide, tungsten silicide, tungsten carbide boron, silicon germanium, or any combination thereof.

[0038] Although the mask material 315 is shown as a single layer material, the mask material 315 may include one or more material layers. The mask material 315 may be a hard mask, a photoresist mask, or a combination thereof. For example, the mask material 315 may include a hard mask with a photoresist mask disposed thereon. Alternatively, the mask material 315 may include only a hard mask. The hard mask may be composed of one or more material layers (e.g., up to 10 layers). Each layer of the hard mask may include materials such as silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous carbon, or any combination thereof. The mask material 315 may be or include a patterned photoresist layer, such as a photolithographically patterned mask or made of other materials. The photoresist layer may be a positive photoresist, a negative photoresist, an ultraviolet photoresist, an i-line photoresist, an electron beam photoresist (e.g., a chemically amplified resist (CAR)), or other suitable photoresist. The mask may be characterized by a thickness less than or about 2000 nm, such as 10 nm to 2000 nm, 10 nm to 500 nm, 50 nm to 1000 nm, 500 nm to 1500 nm, or 1000 nm to 2000 nm.

[0039] The masking material 315 can be patterned to form pores 320 through the masking material 315, exposing portions 325 of the underlying silicon-containing material 310. The pores 320 can be characterized by a critical dimension 330 (or the width of the pores 320) that is less than or about 1000 nm, such as 5 nm to 1000 nm, 5 nm to 25 nm, 5 nm to 50 nm, 10 nm to 20 nm, 50 nm to 250 nm, 50 nm to 500 nm, 250 nm to 750 nm, or 500 nm to 1000 nm. It should be understood that the structures are not intended to be limiting and similarly encompass any of a variety of other semiconductor structures. Although the method 200 of the present disclosure can be applied to small and large pores, advantageously, the method of the present disclosure is related to pores having a small critical dimension 330 that is less than or about 50 nm, such as 5 nm to 50 nm, 5 nm to 25 nm, 10 nm to 20 nm, or 25 nm to 50 nm. Other exemplary structures can include two-dimensional and three-dimensional structures common in semiconductor manufacturing, within which silicon-containing material is to be removed.

[0040] Method 200 can include forming, in operation 205, a plasma effluent 335, 340, 345, and 350 from a plurality of precursors, the plurality of precursors including silicon- and fluorine-containing precursors, etchant precursors, and oxygen-containing precursors. For example, the silicon- and fluorine-containing precursor can include silicon tetrafluoride (SiF4). For example, the etchant precursor can include one or more materials that include chlorine-containing precursors, bromine-containing precursors, or fluorine-containing precursors. For example, the chlorine-containing precursor can include one or more materials that include diatomic chlorine (Cl2) or hydrogen chloride (HCl). For example, the bromine-containing precursor can include hydrogen bromide (HBr). For example, the fluorine-containing precursor can include one or more materials that include nitrogen trifluoride (NF3), hydrogen fluoride (HF), diatomic fluorine (F2), carbon tetrafluoride (CF4), trifluoromethane (CHF3), hexafluoroethane (C2F6), hexafluoropropene (C3F6), bromine trifluoride (BrF3), chlorine trifluoride (ClF3), sulfur hexafluoride (SF6), additional fluorine-substituted hydrocarbons, or fluorine-containing materials. For example, the oxygen-containing precursor can include one or more materials that include oxygen (O2), carbon dioxide (CO2), carbon monoxide (CO), nitrous oxide (N2O), nitrogen dioxide (NO2), ozone (O3), or water (H2O).

[0041] The precursors can also include any number of carrier gases, which can include nitrogen, helium, argon, or other rare, inert, or useful precursors. The carrier gas can be used to dilute the precursors, thereby further reducing the etching rate and / or allowing sufficient diffusion through the pores 320.

[0042] The plasma effluents 335, 340, 345, and 350 formed from precursors may be formed in situ in the processing region or may be formed in a remote plasma system. That is, the plasma effluents 335, 340, 345, and 350 may be generated in the processing region of a semiconductor processing chamber that houses the semiconductor structure 300. Alternatively, the plasma effluents 335, 340, 345, and 350 may be generated remotely and provided to the processing region of a semiconductor processing chamber that houses the semiconductor structure 300. For example, plasma processing may be generated by a remote plasma source (RPS), capacitively coupled plasma (CCP), or inductively coupled plasma (ICP), which may or may not include one or more carrier gases such as argon (Ar), helium (He), NH3, nitrogen (N2), H2, or a mixture thereof. The plasma effluents 335, 340, 345, 350 may be low-level plasmas to limit the amount of bombardment, sputtering, and surface modification. In embodiments, the plasma power may be less than or about 5,000 W, less than or about 4,500 W, less than or about 4,000 W, less than or about 3,500 W, less than or about 3,000 W, less than or about 2,500 W, less than or about 2,000 W, less than or about 1,500 W, less than or about 1,000 W, less than or about 750 W, less than or about 500 W, or less, but the plasma power may also include ranges between any two of the aforementioned numbers, or any smaller ranges encompassed by the aforementioned ranges. By utilizing low-level plasma power, the plasma effluents 335, 340, 345, 350 can be better controlled to transport through the pores 320 of the mask material 315 while limiting the sputtering of the mask material 315 and other exposed surfaces.

[0043] Method 200 may include contacting the silicon-containing material 310 and the mask material 315 with the plasma effluents 335, 340, 345, 350 in the processing region of a semiconductor processing chamber in operation 210. As shown in FIG. 3B, in operation 215, the contact of the silicon-containing material 310 with the plasma effluents 335, 340, 345, 350 may cause etching of the silicon-containing material 310, which may form and / or deepen the feature 355 in the silicon-containing material 310. Additionally, in operation 215, the contact of the mask material 315 with the plasma effluents 335, 340, 345, 350 may cause simultaneous etching of the mask material 315 and deposition of silicon- and oxygen-containing materials on the mask material 315.

[0044] Without being bound by theory, it is believed that a silicon-containing plasma effluent 335 from a silicon- and fluorine-containing precursor (e.g., silicon tetrafluoride) and an oxygen-containing plasma effluent 345 from an oxygen-containing precursor can cause a silicon- and oxygen-containing material to deposit on the mask material 315. At the same time, a plasma effluent 350 from an etchant precursor and / or a silicon- and fluorine-containing precursor can etch the mask material 315 as well as the silicon-containing material 350. A fluorine-containing plasma effluent 340 from an etchant precursor and / or a silicon- and fluorine-containing precursor (e.g., silicon tetrafluoride) can preferentially contact the silicon-containing material because it has a higher electronegativity relative to other plasma effluents 335, 345, 350 (especially the oxygen-containing plasma effluent 345 from the oxygen-containing precursor and the silicon-containing plasma effluent 335 from the silicon- and fluorine-containing precursor). By preferentially contacting the silicon-containing material 310, the fluorine-containing plasma effluent 340 can reduce the formation of the silicon- and oxygen-containing material on the silicon-containing material 310, thereby reducing the width (or critical dimension) of the feature 355, especially near the interface between the mask material 315 and the silicon-containing material 310. The reduction in feature width reduces the entry of the plasma effluent 350 from the etchant precursor into the feature 355, thereby reducing the etching of the silicon-containing material 310 that deepens the feature 355. Thus, while the silicon-containing material 310 can be etched, the mask material 315 can be etched and replenished (by deposition) simultaneously, which results in the selective removal of the silicon-containing material 310 relative to the mask material 315. Advantageously, the method 200 of the present disclosure can result in a minimal change in the thickness of the mask material 315 while still forming deep features 355, which can allow for the use of a thinner mask material 315 at the start of the method.

[0045] Although the illustrated method 200 and semiconductor structure 300 show the use of plasma effluents 335, 340 from silicon- and fluorine-containing precursors to form the feature 355, in an alternative embodiment, the feature 355 may already be formed (or started), and the plasma effluents 335, 340 from the silicon- and fluorine-containing precursors may be used only to deepen the feature 355. For example, the method can include: forming a first plasma effluent from a first precursor including a first etchant precursor; contacting the mask material and the silicon-containing material with the first plasma effluent to cause etching of the silicon-containing material, thereby forming and deepening a feature (e.g., deepening by about 5 nm to 100 nm); then forming a second plasma effluent from a second precursor including a silicon- and fluorine-containing precursor, an oxygen-containing precursor, and a second etchant precursor (which may be the same as or different from the first etchant precursor); and contacting the silicon-containing material and the mask material with the second plasma effluent to etch the silicon-containing material to deepen the feature and simultaneously etch and deposit the mask material, as described herein.

[0046] The silicon-containing material 310 can define sidewalls 360 and a bottom 365 of the feature 355, and each pore 320 defines an opening 370 at the top of each feature 355, where the mask material 315 interfaces with the silicon-containing material 310. After completing the method 200 shown in FIG. 3C, the feature 355 can be characterized by: a critical dimension 375 at the opening 370 at the top of the feature 355, a depth 380 from the opening 370 to the bottom 365 of the feature 355, an aspect ratio (depth 380 relative to the critical dimension 375), or any combination thereof. After completing the method 200, the feature 355 can be characterized by a critical dimension 375 that is less than or about 1000 nm, such as 5 nm to 1000 nm, 5 nm to 25 nm, 5 nm to 50 nm, 10 nm to 20 nm, 50 nm to 250 nm, 50 nm to 500 nm, 250 nm to 750 nm, or 500 nm to 1000 nm, and preferably less than or about 50 nm, such as 5 nm to 50 nm, 5 nm to 25 nm, 10 nm to 20 nm, or 25 nm to 50 nm. After completing the method 200, the feature 355 can be characterized by a depth 380 that is greater than or about 100 nm, such as 100 nm to 50,000 nm, 100 nm to 1000 nm, 500 nm to 5000 nm, 1000 nm to 10,000 nm, or 5000 nm to 50,000 nm. After completing the method 200, the feature 355 can be characterized by an aspect ratio that is greater than or about 5:1, such as greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35:1, greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 60:1, greater than or about 70:1, greater than or about 80:1, greater than or about 90:1, greater than or about 100:1 or greater, or 5:1 to 200:1, 5:1 to 50:1, 25:1 to 100:1, 50:1 to 200:1 or greater.

[0047] The mask material 315 may be characterized by a thickness less than or about 2000 nm, such as 10 nm to 2000 nm, 10 nm to 500 nm, 50 nm to 1000 nm, 500 nm to 1500 nm, or 1000 nm to 2000 nm, before contacting the plasma effluent. After operations 210 and 215, the mask material 315 may be characterized by a thickness less than or about 2000 nm, such as 10 nm to 2000 nm, 10 nm to 500 nm, 50 nm to 1000 nm, 500 nm to 1500 nm, or 1000 nm to 2000 nm. Comparing the thickness of the mask material 315 before and after operations 210 and 215, the mask material 315 may be characterized by a thickness change less than or about 200 nm, such as 0 nm to 10 nm, 0 nm to 20 nm, 1 nm to 50 nm, 25 nm to 100 nm, or 50 nm to 200 nm. The thickness of the mask material 315 after operations 210 and 215 may depend on various factors, including but not limited to precursor gas ratio, applied RF power, chamber pressure, etc.

[0048] Method 200 is characterized by the preferential (or selective) removal of the silicon-containing material 310 relative to the mask material 315. Selectivity is defined as the depth 380 of feature 355 divided by the difference between the starting thickness (MT S) and the final thickness (MT F) of the mask material 315, as shown in the following formula. Selectivity = Feature depth / (MT S - MT F)

[0049] For example, method 200 may be performed, where (i) in FIG. 3A, before etching, the thickness of the mask material 315 may be 100 nm, and (ii) in FIG. 3C, after etching, the thickness of the mask material 315 may be 60 nm, and the depth 380 of feature 355 may be 300 nm. In the example, the selective removal of the silicon-containing material 310 relative to the mask material 315 will be 300 nm / (100 nm – 60 nm) = 7.5. Method 200 may be characterized by a selectivity of removing the silicon-containing material 310 relative to the mask material 315 that is greater than or about 4, such as greater than or about 6, greater than or about 8, greater than or about 10, greater than or about 12, greater than or about 14, greater than or about 16, greater than or about 18, greater than or about 20, or greater than or about 22, or greater, or 4 to 30, 4 to 15, 10 to 20, or 15 to 30. Selectivity may depend on various factors, including but not limited to precursor gas ratio, RF power, chamber pressure, etc.

[0050] The volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursors can be less than or about 50:1, such as 10:1 to 50:1, 10:1 to 30:1, 15:1 to 40:1, or 20:1 to 50:1. Without being bound by theory, it is believed that an increase in the SiF4 flow rate relative to the O2 flow rate (i.e., a lower volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursors) may lead to an increase in mask deposition, thereby resulting in an increase in clogging. However, there may be an inflection point in the O2:SiF4 volume ratio at which there is not enough O2 to support the increased deposition, and the mask material deposition rate decreases.

[0051] During operation 205, the volume ratio of the etchant precursor to the oxygen-containing precursor can be less than or about 20:1, such as 1:1 to 20:1, or 1:1 to 15:1, or 5:1 to 20:1. Without being bound by theory, the oxygen-containing precursor (such as O2) can be used both as a precursor for mask material deposition (in conjunction with SiF4) and as a precursor for passivating the sidewalls 360 of feature 355. Although it is believed that reducing the oxygen-containing precursor (i.e., a higher volume ratio of the etchant precursor to the oxygen-containing precursor) can reduce clogging, it may also lead to an increase in feature width and an increase in feature bowing. The appropriate volume ratio of the etchant precursor to the oxygen-containing precursor may highly depend on the composition of the silicon-containing material 310. Therefore, clogging can be more effectively controlled or alleviated by the amount of silicon- and fluorine-containing precursors used (i.e., the volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursors, rather than the volume ratio of the etchant precursor to the oxygen-containing precursor).

[0052] During operation 205, the volume ratio of the carrier gas (such as nitrogen, helium, argon) to the oxygen-containing precursor can be less than or about 10:1, such as 1:1 to 10:1, 1:1 to 5:1, 3:1 to 7:1, or 5:1 to 10:1. Without being bound by theory, it is believed that most inert carrier gases have a minimal impact on the overall process performance and are used to dilute highly electronegative plasmas, providing higher plasma stability by reducing the reflected power observed in the RF system. However, diatomic inert gases (such as, N2) may have a significant impact on the plasma chemistry by increasing the fluorine signal (observed in the optical emission spectrum), thereby resulting in a decrease in selectivity and an increase in mask damage.

[0053] During any of operations 205, 210, and / or 215 of method 200, a bias power may be applied to substrate 305. The bias power may provide a directional flow of plasma effluent to substrate 305. Thus, etchant may be directed into pores 320, which may assist the plasma effluent in passing through the material being etched and reaching substrate 305. In an embodiment, the plasma power may be greater than or about 500 W, and may be greater than or about 750 W, greater than or about 1,000 W, greater than or about 1,500 W, greater than or about 2,000 W, greater than or about 2,500 W, greater than or about 2,750 W, greater than or about 3,000 W, greater than or about 3,250 W, greater than or about 3,500 W, greater than or about 4,000 W, greater than or about 4,500 W, greater than or about 5,000 W or more, although the bias power may also include a range between any two of these recited numbers or any smaller range encompassed by any of the recited ranges. By applying the bias power, a narrow ion angular distribution may be generated and better profile control (e.g., without bending and / or distortion) and etching verticality may be provided. The narrow ion angular distribution may reduce sidewall erosion, increase the etching rate, and make the etching front more square.

[0054] In an embodiment, the bias power may be applied through an RF power source (e.g., RF power source 125) and / or a power source for directing a DC current or voltage to the ESC (e.g., power source 150). As previously discussed with respect to FIG. 1, the RF power source and / or the power source for directing a DC current or voltage may be cycled on and off or pulsed during processing. By pulsing, better control of ion energy and ion flux may be achieved, and a lower angular spread of the plasma effluent may be realized. Additionally, pulsing may neutralize the charge of the plasma effluent at the etch front, which may improve the etching uniformity. In an embodiment where the bias power is applied by an RF power source and a power source for directing a DC current or voltage to the ESC, the power sources may be synchronous or asynchronous. The DC current or voltage may be pulsed in the microsecond range and may be characterized by a duty cycle between 0% and 100%. In some embodiments, there may be an additional electrode in the ESC for pulsing the DC current or voltage, while other embodiments may utilize the same electrode for both adsorption and pulsing. In some embodiments, RF and pulsed DC may be supplied only to the cooling pedestal 129, while a separate DC adsorption power source 150 may be connected to the adsorption electrode (grid) within the ceramic ESC.

[0055] In an embodiment, each operation of method 200 can be performed at a constant temperature, while in some embodiments, the temperature can be adjusted during different operations. For example, during method 300, the substrate, pedestal, or chamber temperature can be maintained at a temperature less than or about 100°C, less than or about 80°C, less than or about 60°C, less than or about 40°C, less than or about 20°C, less than or about 0°C, and in some embodiments, the temperature can be maintained at a temperature less than or about -20°C, less than or about -40°C, less than or about -50°C, less than or about -60°C, less than or about -70°C, less than or about -80°C, less than or about -90°C, less than or about -100°C, less than or about -110°C, less than or about -120°C or lower, although the temperature can also include a range between any two of these recited numbers or within any smaller range encompassed by any of the recited ranges.

[0056] During method 300, the pressure inside the processing chamber can be controlled. For example, while forming a plasma effluent and contacting a material with the plasma effluent, the pressure inside the semiconductor processing chamber can be maintained at less than or about 5 Torr. Additionally, in an embodiment, the pressure inside the semiconductor processing chamber can be maintained at less than or about 4 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr, less than or about 500 mTorr, less than or about 250 mTorr, less than or about 200 mTorr, less than or about 150 mTorr, less than or about 100 mTorr, less than or about 80 mTorr, less than or about 60 mTorr, less than or about 50 mTorr, less than or about 45 mTorr, less than or about 40 mTorr, less than or about 35 mTorr, less than or about 30 mTorr, less than or about 25 mTorr, less than or about 20 mTorr, less than or about 15 mTorr, less than or about 10 mTorr or lower, although the pressure can also include a range between any two of these recited numbers, or any smaller range encompassed by any of the recited ranges. The pressure inside the processing chamber affects the ability to flow into the pores. For example, as the pressure increases, it may be more difficult for the plasma effluent to penetrate the pores 320 to reach the silicon-containing material 310. Thus, in some embodiments, the pressure can be kept at less than or about 1 Torr to allow the effluent to flow into the pores 320 and the features 355 etched in the silicon-containing material 310 on the substrate 305.

[0057] In the foregoing description, many details have been set forth in order to explain the various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments can be practiced without these details or with additional details.

[0058] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. Additionally, to avoid unnecessarily obscuring the technology, many well-known processes and elements have not been described. Therefore, the foregoing description should not be regarded as limiting the scope of the technology. Further, a method or process may be described in sequential or step-by-step terms, but it should be understood that the operations may be performed concurrently or in an order different from that listed.

[0059] When a numerical range is provided, it is understood that unless the context clearly dictates otherwise, each intermediate value (to the smallest fraction of a unit of the lower limit) between the upper and lower limits of the range is also specifically disclosed. Any stated value or unstated intermediate value within the range, and any narrower range between any other stated or intermediate value within the range, are encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded from the range, and each range (where either, neither, or both of the limits are included within the smaller range) is also covered by the technology, except for any explicitly excluded limits within the range. When the range includes one or both of the limits, ranges excluding either or both of the included limits are also included.

[0060] As used herein and in the appended claims, the singular forms "a" and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, reference to "the layer" includes reference to one or more layers and equivalents known to those skilled in the art, and so forth.

[0061] Furthermore, when used in this specification and the appended claims below, the terms "comprising," "including," and "having," and the like are intended to specify the presence of the stated features, integers, components, or operations, but do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups thereof.

[0062] 100: Plasma processing chamber 102: Substrate 105: Chamber body 110: Chamber lid assembly 112: Sidewall 113: Substrate access port 114: Nozzle 115: Gasket 118: Bottom 121: Electrode 122: Electrostatic chuck 124: Matching Circuit 125: RF Power Supply 126: Ground Terminal 129: Cooling Base 130: Cover Ring 135: Substrate Support Base 136: Cathode Pad 141: Matching Circuit 142: Antenna Power Supply 145: Pumping Port 148: Antenna 150: Power Supply 160: Gas Panel 161: Process Gas Source 162: Process Gas Source 163: Process Gas Source 164: Process Gas Source 165: Controller 166: Valve 167: Gas Pipeline 200: Method 205, 210, 215: Operations 300: Semiconductor Structure 305: Substrate 310: Silicon-Containing Material 315: Masking Material 320: Pores 325: Portion 330: Critical Dimension 335: Plasma Effluent 340: Plasma Effluent 345: Plasma Effluent 350: Plasma Effluent 355: Feature 360: Sidewall 365: Bottom 370: Opening 375: Critical Dimension 380: Depth

[0063] Domestic Deposit Information (Please note in the order of deposit institution, date, and number) None Foreign Deposit Information (Please note in the order of deposit country, institution, date, and number) None

Claims

1. A semiconductor processing method, comprising: i) forming a plasma effluent containing multiple precursors, including an etchant precursor, an oxygen-containing precursor, and a silicon- and fluorine-containing precursor, wherein the silicon- and fluorine-containing precursor includes silicon tetrafluoride; ii) contacting a silicon-containing material and a masking material with the plasma effluent in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support in the processing region, wherein the silicon-containing material is disposed on the substrate, and the masking material is disposed on the silicon-containing material, wherein the masking material has one or more apertures to allow the plasma effluent to reach the silicon-containing material, wherein the masking material includes a dielectric material; iii) etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material; and iv) simultaneously etching the masking material with the plasma effluent and depositing a silicon- and oxygen-containing material on the masking material.

2. The semiconductor processing method as claimed in claim 1, wherein the etchant precursor comprises one or more of the following: a chlorine-containing precursor, a bromine-containing precursor, and a fluorine-containing precursor that is not silicon tetrafluoride.

3. The semiconductor processing method as claimed in claim 1, wherein the volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursor is less than or about 50:

1.

4. The semiconductor processing method as claimed in claim 1, wherein the volume ratio of the etchant precursor to the oxygen-containing precursor is less than or about 20:

1.

5. The semiconductor processing method as claimed in claim 1, wherein a carrier gas is present when plasma effluent is formed.

6. The semiconductor processing method as described in claim 5, wherein the volume ratio of the carrier gas to the oxygen-containing precursor is less than or about 10:

1.

7. The semiconductor processing method as claimed in claim 1, wherein the silicon-containing material comprises one or more of the following: crystalline silicon, amorphous silicon, doped silicon, silicon nitride, silicon carbide, boron silicon, tungsten silicon, and germanium silicon.

8. The semiconductor processing method as claimed in claim 1, wherein the method selectively removes the silicon-containing material relative to the masking material.

9. The semiconductor processing method as claimed in claim 1, wherein the method removes the silicon-containing material relative to the masking material with a selectivity greater than or about 4.

10. The semiconductor processing method as claimed in claim 1, wherein one or more pores are characterized by a critical dimension of less than or about 1000 nm.

11. The semiconductor processing method as claimed in claim 1, wherein after etching the silicon-containing material, the one or more features are characterized by a depth greater than or about 100 nm.

12. The semiconductor processing method as claimed in claim 1, wherein after etching the silicon-containing material, the one or more features are characterized by an aspect ratio greater than or about 5:

1.

13. The semiconductor processing method as claimed in claim 1, wherein a pressure in the processing region is maintained at about 5 Torr or lower.

14. The semiconductor processing method as claimed in claim 1, wherein a temperature in the processing region is maintained at about 100 degrees Celsius or lower.

15. The semiconductor processing method as claimed in claim 1, wherein the plasma effluent is generated at a plasma power of about 5000W or less.

16. A semiconductor processing method, comprising: i) A plasma effluent forming multiple precursors in the presence of a carrier gas, wherein the multiple precursors include an etchant precursor, an oxygen-containing precursor, and a silicon- and fluorine-containing precursor, wherein the silicon- and fluorine-containing precursor includes silicon tetrafluoride, wherein the volume ratio of the oxygen-containing precursor to the silicon- and fluorine-containing precursor is less than or about 50:1, wherein the volume ratio of the etchant precursor to the oxygen-containing precursor is less than or about 20:1, and wherein the volume ratio of the carrier gas to the oxygen-containing precursor is less than or about 10:1; ii) Contacting a silicon-containing material and a masking material with the plasma effluent in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support in the processing region, wherein the silicon-containing material is disposed on the substrate and the masking material is disposed on the silicon-containing material, wherein the masking material has one or more pores to allow the plasma effluent to reach the silicon-containing material, wherein the masking material includes a dielectric material; iii) Etching the silicon-containing material with the plasma effluent to form and / or deepen one or more features in the silicon-containing material, wherein the silicon-containing material defines a plurality of sidewalls and a bottom along the one or more features of the substrate, and each of the one or more pores defines an opening at a top of each of the one or more features; and iv) Simultaneously etching the masking material with the plasma effluent and depositing a silicon- and oxygen-containing material on the masking material, wherein the method selectively removes the silicon-containing material relative to the masking material.

17. The semiconductor processing method as claimed in claim 16, wherein the method removes the silicon-containing material relative to the masking material with a selectivity greater than or about 4.

18. A semiconductor processing method, comprising: i) A plasma effluent forming multiple precursors, including an etchant precursor, an oxygen-containing precursor, and silicon tetrafluoride, wherein the volume ratio of the oxygen-containing precursor to the silicon tetrafluoride is less than or about 50:1; ii) The plasma effluent contacts a silicon-containing material and a masking material in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support in the processing region, wherein the silicon-containing material is disposed on the substrate and the masking material is disposed on the silicon-containing material, wherein the masking material has one or more pores to allow the plasma effluent to pass to the silicon-containing material, wherein the masking material includes a dielectric material; iii) Etching the silicon-containing material with the plasma effluent to deepen one or more features in the silicon-containing material, wherein the silicon-containing material defines a plurality of sidewalls and a bottom along the one or more features of the substrate, and each of the one or more pores defines an opening at a top of each of the one or more features; and iv) Simultaneously etching the masking material with the plasma effluent and depositing a silicon and oxygen-containing material on the masking material, wherein the method selectively removes the silicon-containing material relative to the masking material.

19. The semiconductor processing method of claim 18, wherein the plasma effluent is a first plasma effluent of a first plurality of precursors, and wherein the method further comprises: A second plasma effluent is formed from a second plurality of precursors, the second plurality of precursors not including silicon tetrafluoride; and the silicon-containing material is etched with the second plasma effluent to form and / or deepen the one or more features in the silicon-containing material.

20. The semiconductor processing method as claimed in claim 18, wherein the method removes the silicon-containing material relative to the masking material with a selectivity greater than or about 4.

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