Semiconductor device structure and method for forming the same

Abstract

This embodiment provides a semiconductor device structure and a method for forming the same. The structure includes a gate electrode layer disposed above a substrate; a first source / drain region disposed above the substrate; a conductive contact disposed above the first source / drain region; a first dielectric layer disposed above the gate electrode layer and the conductive contact; a first conductive component disposed in the first dielectric layer; a second conductive component disposed in the first dielectric layer; and a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer contacts a portion of the side surface of the second conductive component.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor technology, and more particularly to the structure of a semiconductor device and a method for forming the same. Prior Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuitry than the previous one. Throughout the history of IC development, functional density (the number of interconnected devices per die area) has increased, while geometric dimensions (the smallest components or lines produced during manufacturing) have shrunk. This miniaturization of device size offers the benefits of increased production efficiency and reduced costs. However, this miniaturization has also increased the complexity of processing and manufacturing ICs.

[0003] Therefore, it is necessary to improve the processing and manufacturing of integrated circuits. Summary of the Invention

[0004] In some embodiments, a semiconductor device structure is provided, the semiconductor device structure including a gate electrode layer disposed above a substrate; a first source / drain region disposed above the substrate; a conductive contact disposed above the first source / drain region; a first dielectric layer disposed above the gate electrode layer and the conductive contact; a first conductive component disposed in the first dielectric layer; a second conductive component disposed in the first dielectric layer; and a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer contacts a portion of the side surface of the second conductive component.

[0005] In some embodiments, a semiconductor device structure is provided, the semiconductor device structure including a gate electrode layer disposed above a substrate; a source / drain region disposed above the substrate; a conductive contact disposed above the source / drain region; a first dielectric layer disposed above the gate electrode layer and the conductive contact; a first conductive component disposed in the first dielectric layer; a second conductive component disposed in the first dielectric layer; a third conductive component disposed on and in contact with the first conductive component; a fourth conductive component disposed on and in contact with the second conductive component; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer contacts a portion of a side surface of the second conductive component and a first portion of a side surface of the third conductive component; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer contacts a portion of a side surface of the fourth conductive component and a second portion of a side surface of the third conductive component.

[0006] In other embodiments, a method for forming a semiconductor device structure is provided, the method comprising forming a first dielectric layer over a substrate, wherein the substrate includes a gate electrode layer, a source / drain region, and conductive contacts disposed over the source / drain region; forming a first conductive component in the first dielectric layer; depositing a second dielectric layer on the first conductive component and the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; forming a second conductive component in the first, second, and third dielectric layers; and performing a chemical mechanical polishing process to expose the second dielectric layer and the second conductive component, wherein during the chemical mechanical polishing process, the second dielectric layer covers the first conductive component. Simple Explanation of the Diagram

[0007] The embodiments of the present invention can be better understood from the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Figures 1, 2, 3, 4, 5, and 6 are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments. Figures 7A, 8A, 9A, 10A, 11A, and 12A are schematic cross-sectional views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6, according to some embodiments. Figures 7B, 8B, 9B, 10B, 11B, and 12B are schematic cross-sectional views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6, according to some embodiments. Figures 7C, 8C, 9C, 10C, 11C, and 12C are schematic cross-sectional views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6, according to some embodiments. Figures 13A, 13B, 13C, 13D, 13E, 13F, 13G, 13H, and 13I are schematic cross-sectional views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6, according to some embodiments. Figures 14A and 14B are schematic cross-sectional views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6, based on some alternative embodiments. Figures 15A, 15B, 15C, 15D, 15E, 15F, and 15G are schematic cross-sectional views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6, based on some alternative embodiments. Figures 16A and 16B are schematic cross-sectional views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6, based on some alternative embodiments. Figures 17A, 17B, 17C, 17D, and 17E are schematic cross-sectional views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6, based on some alternative embodiments. Figure 18 is a cross-sectional view of one of the stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6, according to some alternative embodiments. Implementation

[0008] It is important to understand that the following content provides many different embodiments or examples of implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the explanation. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment disclosed herein, but may depend on the processing conditions and / or required nature of the components. Furthermore, in the following description, embodiments in which the first component is formed above or on the second component include those where the first and second components are in direct contact, and embodiments in which additional components may be formed between the first and second components, such that the first and second components are not in direct contact. Additionally, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0009] Furthermore, to facilitate the description of the relationship between one element or component and another (or multiple elements or components) in the diagram, spatially related terms such as "below," "under," "lower part," "above," "upper part," and similar terms may be used. In addition to the orientation shown in the diagram, spatially related terms also cover different orientations of the device during use or operation. The device may also be positioned elsewhere (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly.

[0010] While embodiments of the invention are discussed with reference to nanostructured channel field-effect transistors (e.g., gate all-around (GAA) field-effect transistors, such as horizontal gate all-around (HGAA) or vertical gate all-around (VGAA) field-effect transistors), embodiments of some aspects herein can be used with other processes and / or other devices, such as planar field-effect transistors, fin field-effect transistors, and other suitable devices. Those skilled in the art will understand that other modifications that can be made are considered within the scope of embodiments of the invention. In the case of employing a gate all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, these structures can be patterned using one or more photolithography processes (including dual patterning or multiple patterning processes). Generally, dual or multiple patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than those achievable using a single direct photolithography process. For instance, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the full-wrap gate structure.

[0011] Figures 1 through 13I illustrate exemplary processes for manufacturing a semiconductor device structure 100 according to embodiments of the present invention. It should be understood that additional operations may be provided before, during, and after the processes shown in Figures 1 through 13I, and for additional embodiments of the method, some of the operations described below may be substituted or eliminated. The order of these operations / processes is not limited and is interchangeable.

[0012] Figures 1, 2, 3, 4, 5, and 6 are perspective views of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a stack of semiconductor layers 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may contain crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is an insulating-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers to enhance the insulating layer. In one aspect, the insulating layer is an oxygen-containing layer.

[0013] The substrate 101 may include regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field-effect transistor (NFET) and boron for a p-type field-effect transistor (PFET).

[0014] The stack of semiconductor layers 104 comprises alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel field-effect transistors. In some embodiments, the stack of semiconductor layers 104 comprises a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the stack of semiconductor layers 104 comprises alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of silicon, while the second semiconductor layer 108 may be made of silicon germanium. In some examples, the first semiconductor layer 106 may be made of silicon germanium, while the second semiconductor layer 108 may be made of silicon. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or contain other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0015] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of each layer of the stack of semiconductor layers 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0016] The first semiconductor layer 106, or a portion thereof, may form a nanostructure channel of the semiconductor device structure 100 during subsequent manufacturing stages. The term nanostructure is used herein to refer to any material portion having nanometer or even micrometer-scale dimensions and being elongated, regardless of its cross-sectional shape. Thus, the term refers to elongated material portions with circular or substantially circular cross-sections, as well as beam-shaped or rod-shaped material portions comprising, for example, cylindrical or substantially rectangular cross-sections. The nanostructure channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructure transistor. A nanostructure transistor may be referred to as a nanosheet transistor, a nanowire transistor, a fully wound gate (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define channels or multiple channels of the semiconductor device structure 100 is further discussed below.

[0017] Each first semiconductor layer 106 may have a thickness ranging from about 5 nm to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 may have a thickness ranging from about 2 nm to about 50 nm. Figure 1 shows three alternating first semiconductor layers 106 and three second semiconductor layers 108 for illustrative purposes and is not intended to limit the scope beyond what is specifically referenced in the request. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the stack of semiconductor layers 104, and the number of these layers depends on the predetermined number of channels in the semiconductor device structure 100.

[0018] In Figure 2, the fin structure 112 is formed from a stack of semiconductor layers 104. Each fin structure 112 has an upper portion comprising a first semiconductor layer 106 and a second semiconductor layer 108, and a base portion 116 formed from a substrate 101. The fin structure 112 can be formed by patterning a hard mask layer using multiple patterning operations including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element comprising the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element can be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 in unprotected areas through a hard mask layer, through the stack of semiconductor layers 104, and into the substrate 101, leaving a plurality of extending fin structures 112. The trenches 114 extend in the X direction. The trenches 114 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or a combination thereof.

[0019] In Figure 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Next, a planarization operation (e.g., chemical mechanical polishing (CMP) and / or etch-back method) is performed to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-dielectric-constant dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0020] In Figure 4, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes a portion of fin structure 112, such as a stack of semiconductor layers 104. The recess in insulating material 118 exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 contacting the substrate portion 116 formed by the substrate 101.

[0021] In Figure 5, one or more sacrificial gate structures 130 are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 includes a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 can be formed by sequentially depositing a blanket layer of sacrificial gate dielectric layer 132, sacrificial gate electrode layer 134, and masking layer 136, and then patterning these layers into the sacrificial gate structure 130. Next, spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. For example, the spacers 138 can be formed by sequentially depositing one or more layers of spacers 138 without isotropic etching. In some embodiments, the spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. In some embodiments, although one sacrificial gate structure 130 is shown, two or more sacrificial gate structures 130 may be arranged along the X direction. In some embodiments, the contact poly pitch (CPP) (the minimum center-to-center distance between adjacent sacrificial gate electrode layers 134) is in the range of about 35 nm to about 100 nm.

[0022] The sacrificial gate dielectric layer 132 may comprise one or more dielectric materials, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may comprise silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may comprise more than one layer, such as an oxide layer and a nitride layer. The spacer wall 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0023] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 is used as a channel region of the semiconductor device structure 100.

[0024] In Figure 6, the portion of fin structure 112 not covered by sacrificial gate structure 130 and spacer wall 138 is recessed to a horizontal level above, flush with, and below the top surface of isolation region 120. This recess (forming notch 119) of fin structure 112 can be achieved through an isotropic or anisotropic etching process, and this etching process is selective for one or more crystal planes of substrate 101. The etching process can be dry etching (e.g., reactive ion etching, neutron beam etching, or similar methods) or wet etching (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any etchant).

[0025] Figures 7A, 7B, and 7C are schematic cross-sectional views of the semiconductor device structure 100 along lines AA, BB, and CC of Figure 6, respectively.

[0026] Figures 8A, 8B, and 8C are schematic cross-sectional views of one of the stages of fabricating a semiconductor device structure 100 along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments. As shown in Figure 8A, edge portions of each second semiconductor layer 108 of the stack of semiconductor layers 104 are horizontally removed along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, this portion of the second semiconductor layer 108 is removed by a selective wet etching process. In cases where the second semiconductor layer 108 is made of silicon germanium and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 is selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH₄OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0027] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the recesses to form dielectric spacers 144. The dielectric spacers 144 may be made of a low-dielectric-constant dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers 144 may be formed by first forming a compliant dielectric layer using a compliant deposition process (e.g., atomic layer deposition), followed by removing the portion of the compliant dielectric layer except for the dielectric spacers 144 using anisotropic etching. The dielectric spacers 144 are protected by the first semiconductor layer 106 during the anisotropic etching process. The remaining second semiconductor layers 108 cover the spacers 144 along the X-direction.

[0028] Figures 9A, 9B, and 9C are schematic cross-sectional views of one of the stages of fabricating a semiconductor device structure 100 according to some embodiments, along lines AA, BB, and CC of Figure 6, respectively. As shown in Figures 9A and 9C, a source / drain (S / D) region 146 is formed from a substrate portion 116. The source / drain region 146 can be grown vertically and horizontally to form facets that correspond to the crystal surfaces of the material applied to the substrate portion 116. In this document, the terms source region and drain region are used interchangeably, and the structures of the source region and drain region are substantially the same. Furthermore, individually or collectively, depending on the context, a source / drain region may refer to either a source or a drain. The source / drain region 146 may be made of one or more layers of Si, SiP, SiC, and SiCP for n-type channel field-effect transistors or Si, SiGe, and Ge for p-type channel field-effect transistors. For p-type channel field-effect transistors, p-type dopants (e.g., boron (B)) can also be included in the source / drain regions 146. The source / drain regions 146 can be formed by epitaxial growth methods using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy.

[0029] Figures 10A, 10B, and 10C are schematic cross-sectional views illustrating one of the stages of fabricating a semiconductor device structure 100 along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments. In Figures 10A, 10B, and 10C, a contact etch stop layer (CESL) 162 is compliantly formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the source / drain region 146. The CESL 162 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or similar materials or combinations thereof, and may be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. In some embodiments, the contact etch stop layer 162 comprises SiC, SiN, SiOCN, SiOC, SiCN, SiO, AlO, AlON, or AlN. Next, an interlayer dielectric (ILD) layer 164 is formed on the contact etch stop layer 162 above the semiconductor device structure 100. The material used for the interlayer dielectric layer 164 may comprise compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for the interlayer dielectric layer 164. The interlayer dielectric layer 164 may be deposited using plasma-assisted chemical vapor deposition or other suitable deposition techniques. In some embodiments, after the formation of the interlayer dielectric layer 164, the semiconductor device structure 100 may undergo a thermal process to anneal the interlayer dielectric layer 164.

[0030] After forming the interlayer dielectric layer 164, the semiconductor device structure 100 is planarized (e.g., chemical mechanical polishing) until the sacrificial gate electrode layer 134 is exposed, as shown in Figures 10A and 10B.

[0031] Figures 11A, 11B, and 11C are schematic cross-sectional views illustrating one of the stages of fabricating a semiconductor device structure 100 along lines AA, BB, and CC of Figure 6, according to some embodiments. As shown in Figures 11A and 11B, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the second semiconductor layer 108 creates openings between the spacer walls 138 and between the first semiconductor layer 106. The interlayer dielectric layer 164 protects the source / drain regions 146 during the removal process. The sacrificial gate structure 130 can be removed by plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132 by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant (e.g., a tetramethylammonium hydroxide (TMAH) solution) may be used to selectively remove the sacrificial gate electrode layer 134 without removing the spacer wall 138, the interlayer dielectric layer 164, and the contact etch stop layer 162.

[0032] The second semiconductor layer 108 can be removed using a selective wet etching process. In the case where the second semiconductor layer 108 is made of silicon-germanium and the first semiconductor layer 106 is made of silicon, the chemicals used in the selective wet etching process remove the silicon-germanium but do not substantially affect the dielectric material of the silicon, spacer walls 138, and dielectric spacer walls 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant or a dry etchant. Wet etchants include, but are not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), and phosphoric acid (H3PO4), while dry etchants include, but are not limited to, fluorine-based gases (e.g., F2) or chlorine-based gases (e.g., Cl2) or any suitable isotropic etchant.

[0033] After forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed around the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as the gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, high dielectric constant dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high dielectric constant dielectric materials include HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloys, other high dielectric constant dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. The gate electrode layer 172 can comprise one or more layers of conductive material, such as polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 172 can be formed by chemical vapor deposition, atomic layer deposition, electroplating, or other suitable deposition techniques. Gate electrode layer 172 may also be deposited on the upper surface of interlayer dielectric layer 164. Then, the gate dielectric layer 170 and gate electrode layer 172 formed on the interlayer dielectric layer 164 are removed by means of, for example, chemical mechanical polishing, until the top surface of interlayer dielectric layer 164 is exposed.

[0034] Figures 12A, 12B, and 12C are schematic cross-sectional views illustrating one of the stages of fabricating the semiconductor device structure 100 according to some embodiments, along lines AA, BB, and CC of Figure 6, respectively. As shown in Figures 12A and 12C, conductive contacts 180 are formed in the interlayer dielectric layer 164 and the contact etch stop layer 162. The conductive contacts 180 are electrically connected to the corresponding source / drain regions 146 through the silicon layer 182. The conductive contacts 180 may be conductive and may contain one or more materials having Ru, Mo, Co, Ir, W, Ti, Ta, Cu, TiN, or TaN. The conductive contacts 180 may be formed by any suitable method, such as electrochemical plating (ECP) or physical vapor deposition. The silicon layer 182 may be formed by any suitable process. In some embodiments, a metal layer (not shown) is first formed on the semiconductor device structure 100. The metal layer may comprise Ti, Ni, Ru, Co, W, or other suitable metals. The metal layer may be deposited using any suitable process, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. After depositing the metal layer, an annealing process is performed to react the source / drain regions 146 with the metal layer, thereby forming a silicon layer 182. The silicon layer 182 may comprise any suitable material, such as NiSi, TiSi, CoSi, RuSi, or WSi. A planarization process (e.g., chemical mechanical polishing) may be performed such that the top surface of the gate electrode layer 172 is substantially coplanar with the top surface of the conductive contact 180, as shown in Figure 12A. In some embodiments, the conductive contact 180 has a critical dimension in the range of about 5 nm to about 50 nm.

[0035] Figures 13A, 13B, 13C, 13D, 13E, 13F, 13G, 13H, and 13I are schematic cross-sectional views of various stages of manufacturing the semiconductor device structure 100, taken along line AA of Figure 6, according to some embodiments. For clarity, various components on the substrate 101 in Figures 13A to 13I are omitted. As shown in Figure 13A, in some embodiments, conductive contacts 180 are formed between pads 202. Pads 202 may contain any suitable dielectric material, such as SiN. In some embodiments, pads 202 contain Co, W, Ru, Al, Mo, Ti, TiN, Cu, TaN, or other suitable materials. In some embodiments, pads 202 are absent, and conductive contacts 180 contact the interlayer dielectric layer 164. Next, as shown in Figure 13B, an etch stop layer 204 and another interlayer dielectric layer 206 are formed on the interlayer dielectric layer 164, the gate structure 174, and the conductive contacts 180. Etch stop layer 204 may comprise the same material as contact etch stop layer 162, and interlayer dielectric layer 206 may comprise the same material as interlayer dielectric layer 164. Conductive component 208 is formed in interlayer dielectric layer 206 and etch stop layer 204. Conductive component 208 may comprise a conductive material, such as Ru, Mo, Co, Ir, W, Ti, Ta, Cu, TiN, TaN, combinations thereof, or other suitable materials. Conductive component 208 may be formed by any suitable process, such as physical vapor deposition or electrochemical plating. In some embodiments, conductive component 208 is electrically connected to gate electrode layer 172. In some embodiments, conductive component 208 is electrically connected to gate electrode layer 172 and conductive contacts 180 located adjacent to one or more gate electrode layers 172, as shown in Figure 13B. In some embodiments, conductive component 208 is in direct contact with gate electrode layer 172.

[0036] As shown in Figure 13C, a planarization process (e.g., chemical mechanical polishing) is performed to make the top surface of the conductive component 208 and the top surface of the interlayer dielectric layer 206 substantially coplanar. The conductive component 208 is electrically connected to the gate electrode layer 172 (and, in some embodiments, adjacent conductive contacts 180). The conductive component 208 electrically connected to the gate electrode layer 172 and the conductive contacts 180 may be referred to as a butted contact. In some embodiments, the conductive component 208 has a critical dimension in the range of about 5 nm to about 50 nm. Next, as shown in Figure 13D, a chemical mechanical polishing stop layer 210 and another interlayer dielectric layer 212 are formed over the interlayer dielectric layer 206 and the conductive component 208. The chemical mechanical polishing stop layer 210 may comprise any suitable material, such as SiC, SiN, SiOCN, SiOC, SiCN, SiO, AlO, AlON, or AlN. The chemical mechanical polishing stop layer 210 can be formed by any suitable process, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The interlayer dielectric layer 212 may contain the same material as the interlayer dielectric layer 206 and can be formed by the same process as the interlayer dielectric layer 206. Next, as shown in Figure 13E, a conductive component 214 is formed in the interlayer dielectric layer 212, the chemical mechanical polishing stop layer 210, the interlayer dielectric layer 206, and the etch stop layer 204. The conductive component 214 may contain a conductive material, such as Ru, Mo, Co, Ir, W, Ti, Ta, Cu, TiN, TaN, combinations thereof, or other suitable materials. In some embodiments, the conductive component 214 contains a material different from that of the conductive component 208. For example, in some embodiments, the conductive component 208 is used to provide a signal or power to the gate electrode layer 172, and the conductive component 208 contains Ti or W, which can result in a higher yield. Conductive component 214 is used to provide signal or power to source / drain region 146, and conductive component 214 contains Ru, Mo, or Ir, which can result in reduced resistance. Conductive component 214 can be formed by any suitable process, such as physical vapor deposition or electrochemical plating. In some embodiments, conductive component 214 contacts conductive contact 180, conductive contact 180 being electrically connected to source / drain region 146 through silicon layer 182 (Figures 12A, 12C).

[0037] As shown in Figure 13F, a chemical mechanical polishing (CMP) process is performed to remove conductive component 214 and a portion of the interlayer dielectric layer 212. The CMP process is stopped when the CMP stop layer 210 is exposed. As described above, in some embodiments, conductive component 208 and conductive component 214 are made of different materials, such as different metals. Therefore, both conductive component 208 and conductive component 214 are exposed to the polishing slurry of the CMP process, which can lead to galvanic corrosion. Galvanic corrosion refers to the corrosive damage caused when two different materials (i.e., conductive components 208, 214) are coupled in a corrosive electrolyte (i.e., the polishing slurry of the CMP process). To avoid galvanic corrosion, the CMP stop layer 210 is used to cover conductive component 208 when conductive component 214 is exposed during the CMP process. In some embodiments, the CMP stop layer 210 has a thickness ranging from about 1 nm to about 10 nm. As shown in Figure 13F, the thickness of the chemical mechanical polishing stop layer 210 defines the additional height of the conductive component 214 along the Z direction relative to the conductive component 208. If the thickness of the chemical mechanical polishing stop layer 210 is less than about 1 nm, it may be insufficient to cover the conductive component 208 during the chemical mechanical polishing process. On the other hand, if the thickness of the chemical mechanical polishing stop layer 210 is greater than about 10 nm, the conductive component 214 may be too close to a conductive component located at a horizontal height above an adjacent conductive component. This may increase the generated capacitance. As shown in Figure 13F, after the chemical mechanical polishing process, the top surface of the chemical mechanical polishing stop layer 210 is substantially coplanar with the top surface of the conductive component 214. In some embodiments, the conductive component 214 has a critical dimension in the range of about 5 nm to about 50 nm.

[0038] In some embodiments, after the chemical mechanical polishing (CMP) process, the CMP stop layer 210 is removed, as shown in Figure 13G. The CMP stop layer 210 can be removed by any suitable process, such as an etching process. The etching process can be a selective etching process that does not substantially affect the conductive component 214. After the CMP stop layer 210 is removed, the conductive component 214 extends to a horizontal height above the top surface of the conductive component 208 and the interlayer dielectric layer 206. A portion of the side surface of each conductive component 214 is exposed, as shown in Figure 13G. In some embodiments, the bottom surface of the conductive component 208 and the bottom surface of the conductive component 214 are substantially coplanar, and the top surface of the conductive component 214 extends to a horizontal height above the top surface of the conductive component 208, as shown in Figure 13G.

[0039] Next, as shown in Figure 13H, another etch stop layer 216 is deposited on the top surface of the conductive component 208, the interlayer dielectric layer 206, and the conductive component 214, and the etch stop layer 216 is also deposited on the exposed portion of the side surface of each conductive component 214. An intermetallic dielectric (IMD) layer 218 is deposited on the etch stop layer 216. The etch stop layer 216 may contain the same material as the etch stop layer 204 and may be formed by the same process as the etch stop layer 204. The intermetallic dielectric layer 218 is made of a dielectric material, such as SiOx, SiOxCyHz, or SiOxCy, where x, y, and z are integers or non-integers. In some embodiments, the intermetallic dielectric layer 218 contains a dielectric material having a dielectric constant value in the range of about 1 to about 5. As shown in Figure 13I, a conductive component 220 is formed in the intermetallic dielectric layer 218 and the etch stop layer 216. In some embodiments, each conductive component 220 includes a barrier layer 222 and a conductive material 224. The barrier layer 222 may comprise Co, W, Ru, Al, Mo, Ti, TiN, Cu, TaN, or other suitable materials, while the conductive material 224 may comprise Co, W, Ru, Al, Mo, Ti, TiN, Cu, TaN, or other suitable materials. In some embodiments, the conductive material 224 comprises a diffusely diffusing metal (e.g., Cu), while the barrier layer 222 may comprise Ti, TiN, or TaN, which prevents metal diffusion from the conductive material 224 to the intermetallic dielectric layer 218. In some embodiments, the conductive material 224 is not easily diffused, and the barrier layer 222 is absent. In some embodiments, the thickness of the barrier layer 222 is in the range of about 0.5 nm to about 10 nm. In some embodiments, a planarization process (e.g., chemical mechanical polishing) is performed such that the top surfaces of the conductive component 220 and the intermetallic dielectric layer 218 are substantially coplanar. In some embodiments, as shown in Figure 13I, the etch stop layer 216 contacts a portion of the side surface of each conductive component 220 and a portion of the side surface of each conductive component 214.

[0040] Figures 14A and 14B are cross-sectional schematic diagrams taken along line AA of Figure 6, according to some alternative embodiments, illustrating various stages of manufacturing the semiconductor device structure 100. As shown in Figure 14A, a chemical mechanical polishing (CMP) process is performed to expose the CMP stop layer 210 and the conductive component 214, which is the same manufacturing stage shown in Figure 13F. Next, instead of removing the CMP stop layer 210, an etch stop layer 216 is deposited on the CMP stop layer 210 and the conductive component 214, as shown in Figure 14B. An intermetallic dielectric layer 218 is deposited on the etch stop layer 216, and a conductive component 220 is formed in the intermetallic dielectric layer 218 and the etch stop layer 216. The conductive component 220 is disposed above the conductive component 208 and is also formed in the CMP stop layer 210, as shown in Figure 14B. In some embodiments, as shown in Figure 14B, a chemical mechanical polishing stop layer 210 contacts a portion of the side surface of each conductive member 220 and a portion of the side surface of each conductive member 214 disposed above the gate electrode layer 172. An etch stop layer 216 contacts a portion of the side surface of each conductive member 220, as shown in Figure 14B.

[0041] Figures 15A, 15B, 15C, 15D, 15E, 15F, and 15G are schematic cross-sectional views of various stages of manufacturing the semiconductor device structure 100, taken along line AA of Figure 6, according to some alternative embodiments. In some embodiments, as shown in Figures 13A to 13H and Figures 14A to 14B, the conductive component 208 is formed before the conductive component 214 is formed. In some embodiments, the conductive component 214 is formed before the conductive component 208 is formed. As shown in Figure 15A, after the conductive contact 180 is formed, an etch stop layer 204 and an interlayer dielectric layer 206 are deposited on the semiconductor device structure 100. Then, the conductive component 214 is formed in the interlayer dielectric layer 206 and the etch stop layer 204. The semiconductor device structure 100 is subjected to a planarization process (e.g., a chemical mechanical polishing process), as shown in Figure 15B.

[0042] As shown in Figure 15C, a chemical mechanical polishing (CMP) stop layer 210 is deposited on the interlayer dielectric layer 206 and the conductive component 214, and an interlayer dielectric layer 212 is deposited on the CMP stop layer 210. Next, a conductive component 208 is formed in the interlayer dielectric layer 212, the CMP stop layer 210, the interlayer dielectric layer 206, and the etch stop layer 204, as shown in Figure 15D. A CMP process is performed to expose the CMP stop layer 210, as shown in Figure 15E. The CMP stop layer 210 covers the conductive component 214 during the CMP process. Therefore, the conductive component 208 is exposed to the polishing slurry of the CMP process, while the CMP stop layer 210 protects the conductive component 214. This prevents electrochemical corrosion. In some embodiments, the CMP stop layer 210 is removed, as shown in Figure 15F. After the chemical mechanical polishing stop layer 210 is removed, the top surface of the conductive component 214 and the top surface of the interlayer dielectric layer 206 are substantially coplanar, and the top surface of the conductive component 208 extends to a horizontal level above the top surfaces of the conductive component 214 and the interlayer dielectric layer 206. A portion of the side surface of each conductive component 208 is exposed, as shown in Figure 15F. In some embodiments, the bottom surface of the conductive component 208 and the bottom surface of the conductive component 214 are substantially coplanar, and the top surface of the conductive component 208 extends to a horizontal level above the top surface of the conductive component 214, as shown in Figure 15F.

[0043] Next, as shown in Figure 15G, an etch stop layer 216 is deposited on the top surfaces of the conductive member 208, the interlayer dielectric layer 206, and the conductive member 214, and the etch stop layer 216 is also deposited on the exposed portions of the side surfaces of each conductive member 208. An intermetallic dielectric layer 218 is deposited on the etch stop layer 216, and a conductive member 220 is formed in the intermetallic dielectric layer 218 and the etch stop layer 216. In some embodiments, a planarization process (e.g., a chemical mechanical polishing process) is performed such that the top surfaces of the conductive member 220 and the intermetallic dielectric layer 218 are substantially coplanar. In some embodiments, the etch stop layer 216 contacts a portion of the side surface of each conductive member 208 and a portion of the side surface of each conductive member 220 disposed above the conductive member 214.

[0044] Figures 16A and 16B are cross-sectional schematic diagrams taken along line AA of Figure 6, according to some alternative embodiments, illustrating various stages of manufacturing the semiconductor device structure 100. As shown in Figure 16A, a chemical mechanical polishing (CMP) process is performed to expose the CMP stop layer 210 and the conductive component 208, which is the same manufacturing stage shown in Figure 15E. Next, instead of removing the CMP stop layer 210, an etch stop layer 216 is deposited on the CMP stop layer 210 and the conductive component 208, as shown in Figure 16B. An intermetallic dielectric layer 218 is deposited on the etch stop layer 216, and a conductive component 220 is formed in the intermetallic dielectric layer 218 and the etch stop layer 216. The conductive component 220, disposed above the conductive component 214, is also formed in the CMP stop layer 210, as shown in Figure 16B. In some embodiments, as shown in Figure 16B, a chemical mechanical polishing stop layer 210 contacts a portion of the side surface of each conductive member 208 and a portion of the side surface of each conductive member 220 disposed above the conductive member 214. An etch stop layer 216 contacts a portion of the side surface of each conductive member 220, as shown in Figure 16B.

[0045] Figures 17A, 17B, 17C, 17D, and 17E are schematic cross-sectional views of various stages of manufacturing the semiconductor device structure 100, taken along line AA of Figure 6, according to some alternative embodiments. In some embodiments, the gate electrode layer 172 and the conductive contact 180 (Figure 12A) comprise different materials. Therefore, in some embodiments, performing a chemical mechanical polishing (CMP) process after forming the conductive contact 180 may result in electrochemical corrosion. During the CMP process, a CMP stop layer can be used to cover the gate electrode layer 172. As shown in Figure 17A, the gate electrode layer 172 is formed in the same manufacturing stages as shown in Figures 11A, 11B, and 11C. Next, as shown in Figure 17B, a CMP stop layer 250 is deposited on the gate electrode layer 172 and the interlayer dielectric layer 164. The CMP stop layer 250 is also deposited on the spacer wall 138, the gate dielectric layer 170, and the contact etch stop layer 162. The chemical mechanical polishing stop layer 250 may contain the same material as the chemical mechanical polishing stop layer 210 and may be formed by the same process as the chemical mechanical polishing stop layer 210. The chemical mechanical polishing stop layer 250 may have the same thickness as the chemical mechanical polishing stop layer 210.

[0046] As shown in Figure 17C, an interlayer dielectric layer 206 is deposited on the chemical mechanical polishing (CMP) stop layer 250, and a pad 202 and a conductive contact 180 are formed within the interlayer dielectric layer 206. The pad 202 and the conductive contact 180 are formed through the interlayer dielectric layer 206, the CMP stop layer 250, the interlayer dielectric layer 164, and the contact etch stop layer 162. Next, a CMP process is performed to remove a portion of the conductive contact 180, the interlayer dielectric layer 206, and the pad 202 until the CMP stop layer 250 is exposed. During the CMP process, the CMP stop layer 250 covers the gate electrode layer 172 (made of a metal different from that of the conductive contact 180). This prevents electrochemical corrosion. As shown in Figure 17D, the top surface of the CMP stop layer 250 and the top surface of the conductive contact 180 are substantially coplanar.

[0047] Next, as shown in Figure 17E, an interlayer dielectric layer 206 is deposited on the chemical mechanical polishing stop layer 250. The processes described in Figures 13B to 13H or Figures 13B to 13F and Figure 14B can be performed to form conductive components 208 and 214, the chemical mechanical polishing stop layer 210, the etch stop layer 216, the intermetallic dielectric layer 218, and the conductive component 220, as shown in Figure 17E. In some embodiments, the chemical mechanical polishing stop layer 210 is retained in the semiconductor device structure 100. In some embodiments, the chemical mechanical polishing stop layer 210 is removed. In some embodiments, the conductive component 214 is formed prior to the formation of the conductive component 208. Therefore, the height of the conductive component 208 is substantially greater than the height of the conductive component 214, as shown in Figure 17E.

[0048] Figure 18 is a cross-sectional schematic diagram of one of the stages of manufacturing the semiconductor device structure 100, taken along line AA of Figure 6, according to some alternative embodiments. In some embodiments, the chemical mechanical polishing stop layer 210 is removed, and the conductive component 208 is formed prior to the formation of the conductive component 214.

[0049] This invention provides a semiconductor device structure 100, which includes a conductive member 208 disposed on and in contact with a gate electrode layer 172, and a conductive member 214 disposed on and in contact with a conductive contact 180. Since a chemical mechanical polishing (CMP) stop layer 210 is formed on either the conductive member 208 or the conductive member 214, the height of the conductive member 208 differs from the height of the conductive member 214, and some embodiments offer numerous advantages. For example, during a CMP process, having a CMP stop layer 210 formed on either the conductive member 208 or the conductive member 214 exposes one of the conductive members 208 or 214 during the CMP process, which prevents electrochemical corrosion.

[0050] One embodiment is a semiconductor device structure, which includes a gate electrode layer disposed above a substrate; a first source / drain region disposed above the substrate; a conductive contact disposed above the first source / drain region; a first dielectric layer disposed above the gate electrode layer and the conductive contact; a first conductive component disposed in the first dielectric layer; a second conductive component disposed in the first dielectric layer; and a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer contacts a portion of the side surface of the second conductive component.

[0051] In some other embodiments, the semiconductor device structure further includes a spacer wall disposed on both sides of the gate electrode layer; and a third dielectric layer disposed on the spacer wall, wherein the first dielectric layer is disposed on the third dielectric layer.

[0052] In some other embodiments, the first conductive component and the second conductive component are disposed in the third dielectric layer.

[0053] In some other embodiments, the top surface of the third dielectric layer and the top surface of the conductive contact are substantially coplanar.

[0054] In some other embodiments, the semiconductor device structure further includes a fourth dielectric layer disposed on the second dielectric layer.

[0055] In some other embodiments, the above-described semiconductor device structure further includes a third conductive component disposed in the fourth dielectric layer and the second dielectric layer, wherein the third conductive component is disposed on the first conductive component and contacts the first conductive component.

[0056] In some other embodiments, the above-described semiconductor device structure further includes a fourth conductive component disposed in the fourth dielectric layer and the second dielectric layer, wherein the fourth conductive component is disposed on and in contact with the second conductive component, and the top surface of the third conductive component and the top surface of the fourth conductive component are substantially coplanar.

[0057] In some other embodiments, the first conductive component is disposed on and in contact with the gate electrode layer, and the second conductive component is disposed on and in contact with the conductive contact.

[0058] In some other embodiments, the first conductive component is disposed on and in contact with the conductive contact, and the second conductive component is disposed on and in contact with the gate electrode layer.

[0059] Another embodiment is a semiconductor device structure, which includes a gate electrode layer disposed above a substrate; a source / drain region disposed above the substrate; a conductive contact disposed above the source / drain region; a first dielectric layer disposed above the gate electrode layer and the conductive contact; a first conductive component disposed in the first dielectric layer; a second conductive component disposed in the first dielectric layer; a third conductive component disposed on and in contact with the first conductive component; a fourth conductive component disposed on and in contact with the second conductive component; and a second dielectric layer disposed on the first dielectric layer, the second dielectric layer contacting a portion of the side surface of the second conductive component and a first portion of the side surface of the third conductive component. This structure further includes a third dielectric layer disposed on the second dielectric layer, the third dielectric layer contacting a portion of the side surface of the fourth conductive component and a second portion of the side surface of the third conductive component.

[0060] In some other embodiments, the semiconductor device structure further includes a fourth dielectric layer disposed on the third dielectric layer, wherein the third conductive component and the fourth conductive component are disposed in the third dielectric layer and the fourth dielectric layer.

[0061] In some other embodiments, the top surfaces of the third conductive component and the fourth conductive component are substantially coplanar.

[0062] In some other embodiments, the semiconductor device structure further includes a spacer wall disposed on both sides of the gate electrode layer; and a fifth dielectric layer disposed on the spacer wall, wherein the first dielectric layer is disposed on the fifth dielectric layer.

[0063] In some other embodiments, the first conductive component and the second conductive component are disposed in the fifth dielectric layer.

[0064] In some other embodiments, the top surface of the fifth dielectric layer and the top surface of the conductive contact are substantially coplanar.

[0065] Another embodiment is a method comprising forming a first dielectric layer over a substrate, wherein the substrate includes a gate electrode layer, a source / drain region, and a conductive contact disposed over the source / drain region. The method further comprises forming a first conductive component in the first dielectric layer; depositing a second dielectric layer on the first conductive component and the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; forming a second conductive component in the first, second, and third dielectric layers; and performing a chemical mechanical polishing process to expose the second dielectric layer and the second conductive component, wherein the second dielectric layer covers the first conductive component during the chemical mechanical polishing process.

[0066] In some other embodiments, the method further includes removing the second dielectric layer to expose a portion of the top surface of the first conductive member and the top surface of the second conductive member and a portion of the side surface of the second conductive member; and depositing a fourth dielectric layer on the first dielectric layer, the first conductive member and the second conductive member, wherein the fourth dielectric layer is deposited on the exposed portion of the side surface of the second conductive member.

[0067] In some other embodiments, the method further includes depositing a fourth dielectric layer on the second dielectric layer and the second conductive component.

[0068] In some other embodiments, the first conductive component is formed on the gate electrode layer, and the second conductive component is formed on the conductive contact.

[0069] In some other embodiments, the first conductive component is formed on the conductive contact, and the second conductive component is formed on the gate electrode layer.

[0070] The foregoing outlines the features of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments of the present invention.

[0071] 100: Semiconductor Device Structure 101: Base 104: Semiconductor layer 106: First semiconductor layer 108: Second semiconductor layer 112: Fin Structure 114: Trench 116: Base portion 118: Insulating materials 119: Notch 120: Isolation Zone 130: Sacrificial gate structure 132: Sacrificial gate dielectric layer 134: Sacrificial gate electrode layer 136: Masking layer 138: Interstitial wall 144: Dielectric spacer wall 146: Source / Drain Region 162: Contact Etching Stop Layer 164,206,212: Interlayer dielectric layer 170: Gate dielectric layer 172: Gate electrode layer 174: Gate Structure 180: Conductive contact 182: Silicon layer 202: Padding 204, 216: Etching stop layer 210, 250: Chemical mechanical grinding stop layer 208, 214, 220: Conductive components 218: Intermetallic dielectric layer 222: Barrier Layer 224: Conductive materials

Claims

1. A semiconductor device structure, comprising: a gate electrode layer disposed above a substrate; a first source / drain region disposed above the substrate; a conductive contact disposed above the first source / drain region; a first dielectric layer disposed above the gate electrode layer and the conductive contact; a first conductive component disposed in the first dielectric layer; a second conductive component disposed in the first dielectric layer, wherein the top surface of the second conductive component and the top surface of the first conductive component are at different horizontal heights; and a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer contacts a portion of one side surface of the second conductive component.

2. The semiconductor device structure of claim 1 further includes: a spacer wall disposed on both sides of the gate electrode layer; and a third dielectric layer disposed on the spacer wall, wherein the first dielectric layer is disposed on the third dielectric layer.

3. The semiconductor device structure of claim 2, wherein the first conductive component and the second conductive component are disposed in the third dielectric layer.

4. The semiconductor device structure of claim 2, wherein the top surface of the third dielectric layer and the top surface of the conductive contact are substantially coplanar.

5. The semiconductor device structure of any one of claims 1 to 4 further includes: a fourth dielectric layer disposed on the second dielectric layer.

6. The semiconductor device structure of claim 5 further includes: a third conductive component disposed in the fourth dielectric layer and the second dielectric layer, wherein the third conductive component is disposed on the first conductive component and contacts the first conductive component.

7. The semiconductor device structure of claim 6 further includes: a fourth conductive member disposed in the fourth dielectric layer and the second dielectric layer, wherein the fourth conductive member is disposed on the second conductive member and contacts the second conductive member, and the top surface of the third conductive member and the top surface of the fourth conductive member are substantially coplanar.

8. The semiconductor device structure of any one of claims 1 to 4, wherein the first conductive component is disposed on the gate electrode layer and contacts the gate electrode layer, and the second conductive component is disposed on the conductive contact and contacts the conductive contact.

9. A semiconductor device structure as claimed in any one of claims 1 to 4, wherein the first conductive component is disposed on and contacts the conductive contact, and the second conductive component is disposed on and contacts the gate electrode layer.

10. A semiconductor device structure, comprising: a gate electrode layer disposed above a substrate; a source / drain region disposed above the substrate; a conductive contact disposed above the source / drain region; a first dielectric layer disposed above the gate electrode layer and the conductive contact; a first conductive component disposed in the first dielectric layer; a second conductive component disposed in the first dielectric layer, wherein the top surface of the second conductive component and the top surface of the first conductive component are at different horizontal heights; a third conductive component disposed on and in contact with the first conductive component; and a fourth conductive component disposed on and in contact with the second conductive component. A second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer contacts a portion of a side surface of the second conductive member and a first portion of a side surface of the third conductive member; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer contacts a portion of a side surface of the fourth conductive member and a second portion of the side surface of the third conductive member.

11. The semiconductor device structure of claim 10 further includes: a fourth dielectric layer disposed on the third dielectric layer, wherein the third conductive component and the fourth conductive component are disposed in the third dielectric layer and the fourth dielectric layer.

12. The semiconductor device structure of claim 11, wherein the top surface of the third conductive component and the top surface of the fourth conductive component are substantially coplanar.

13. A method of forming a semiconductor device structure, comprising: forming a first dielectric layer over a substrate, wherein the substrate includes a gate electrode layer, a source / drain region, and a conductive contact disposed above the source / drain region; forming a first conductive component in the first dielectric layer; depositing a second dielectric layer on the first conductive component and the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; forming a second conductive component in the first dielectric layer, the second dielectric layer, and the third dielectric layer, wherein the top surface of the second conductive component and the top surface of the first conductive component are at different horizontal heights; and performing a chemical mechanical polishing process to expose the second dielectric layer and the second conductive component, wherein during the chemical mechanical polishing process, the second dielectric layer covers the first conductive component.

14. The method of forming a semiconductor device structure as claimed in claim 13 further includes: removing the second dielectric layer to expose a top surface of the first conductive member and a portion of the top surface of the second conductive member and a side surface of the second conductive member; and depositing a fourth dielectric layer on the first dielectric layer, the first conductive member and the second conductive member, wherein the fourth dielectric layer is deposited on the exposed portion of the side surface of the second conductive member.

15. The method of forming a semiconductor device structure as claimed in claim 13 or 14 further includes: depositing a fourth dielectric layer on the second dielectric layer and the second conductive component.

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