Semiconductor structures and methods of forming semiconductor structures

Abstract

The method for forming a semiconductor structure disclosed herein includes the following steps: forming a semiconductor structure comprising a plurality of channel components vertically stacked on a substrate; forming a source / drain feature abutting against the channel components; after the source / drain feature is formed, depositing a dielectric material layer surrounding the channel components, and maintaining gaps between the channel components after the dielectric material layer is deposited; selectively removing the central portion of the dielectric material layer to release the channel components; and forming a metal gate structure surrounding the channel components. The side portions of the dielectric material layer are located between the metal gate structure and the source / drain feature.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to methods for forming semiconductor structures. Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded generation after generation of ICs, each generation smaller and more complex than the last. Throughout IC development, functional density (the number of interconnects per unit wafer area) has generally increased, while geometry (the smallest element or line that can be created using manufacturing processes) has decreased. This downsizing typically benefits production efficiency and reduces associated costs. However, this size reduction also increases the complexity of integrated circuit fabrication and manufacturing.

[0003] For example, as integrated circuit (IC) technology has evolved to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate channel coupling, reducing off-state current, and reducing short-channel effects (SCE). Multi-gate devices generally refer to devices with gate structures or portions thereof positioned on more than one side of the channel region. Gate-around (GAA) transistors are an example of multi-gate devices and have become a popular and promising choice for high-performance and low-leakage applications. GAA transistors have gate structures that can extend partially or completely around the channel region to provide access to both sides or multiple sides of the channel region. As GAA devices continue to expand, challenges arise. For example, in GAA fabrication, the formation of internal spacers can be a crucial process for reducing capacitance and preventing leakage between gate stacks and source / drain regions. However, existing structures and fabrication techniques suffer from various problems, including poor epitaxial growth and crystal dislocations in the source / drain regions. Therefore, although existing structures and manufacturing technologies are generally sufficient to meet their intended purpose, they are not entirely satisfactory in all aspects. Summary of the Invention

[0004] This invention provides a method for forming a semiconductor structure, comprising: forming a stack on a substrate, the stack including staggered channel layers and sacrificial layers; patterning the stack to form a fin structure; forming a dummy gate stack in the channel region of the fin structure; depositing gate spacers on the sidewalls of the dummy gate stack; recessing the source / drain region of the fin structure, the source / drain trench exposing the sidewalls of the channel layers and the sidewalls of the sacrificial layers; epitaxially growing a first epitaxial layer from the sidewalls of the channel layers and the sidewalls of the sacrificial layers; epitaxially growing a second epitaxial layer on the first epitaxial layer; removing the dummy gate stack; selectively removing the sacrificial layer in the channel region to release the channel layer as a channel component; depositing a dielectric material layer covering the channel component; removing the dielectric material layer from the channel region while retaining a portion of the dielectric material layer directly below the gate spacers to form an internal spacer; and forming a metal gate structure covering the channel component, wherein the internal spacer is located between the metal gate structure and the first epitaxial layer.

[0005] This invention also provides a method for forming a semiconductor structure, comprising: forming a structure including channel components vertically stacked on a substrate; forming source / drain features abutting the channel components; after forming the source / drain features, depositing a dielectric material layer covering the channel components, wherein after depositing the dielectric material layer, gaps are maintained between adjacent channel components; selectively removing the central portion of the dielectric material layer to release the channel components; and forming a metal gate structure covering the channel components, wherein the side portions of the dielectric material layer are located between the metal gate structure and the source / drain features.

[0006] This invention also provides a semiconductor structure, comprising: a nanostructure suspended above a substrate; a gate structure surrounding each of the nanostructures; a gate spacer located on the side of the gate structure; a source / drain feature abutting the nanostructure; and an internal spacer between the gate structure and the source / drain feature, extending between adjacent ones in the nanostructure, wherein the internal spacer includes a first sidewall facing the source / drain feature and a second sidewall facing the gate structure, the first sidewall being straight and vertical, and the second sidewall being curved toward the source / drain feature. Simple Explanation of the Diagram

[0007] This disclosure can be best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 illustrates a flowchart of a method for forming a semiconductor device according to one or more aspects of this disclosure. Figures 2, 3, 4, 5A, 5B, 6, 7A, 7B, 8A, 8B, 8C, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B, according to one or more aspects of this disclosure, show partial cross-sectional views of a work-in-progress (WIP) structure during manufacturing according to the method of Figure 1. Implementation

[0008] The following disclosure provides numerous different embodiments or examples to achieve different features of the provided subject matter. Specific components and arrangements will be described below to simplify the content of this disclosure. These are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples in this disclosure. Such repetition is for simplicity and clarity and does not represent a relationship between the various embodiments and / or configurations discussed.

[0009] Spatial relative terms, such as "below," "below," "above," "over," and "above," may be used herein to describe the relationship of one element or feature relative to another element or feature, as illustrated in the figures. In addition to the orientations shown in the figures, these spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be positioned in other orientations (e.g., rotated 90 degrees or other orientations), and therefore the spatial relative descriptors used herein should be interpreted accordingly.

[0010] Furthermore, when using terms such as "about" or "approximately" to describe numbers or ranges of numbers, these terms are intended to encompass a reasonable range of numbers that takes into account inherent variations in the manufacturing process, as understood by those skilled in the art. For example, a number or range of numbers includes a reasonable range of the described number, such as within ±10% of the described number, based on known manufacturing tolerances associated with manufacturing features having said numerical characteristics. For example, a material layer with a thickness of "about 5 nm" may include a dimensional range from 4.25 nm to 5.75 nm, wherein the tolerances in manufacturing the material layer are considered by those skilled in the art to be ±15%.

[0011] This disclosure generally relates to multi-gate transistors and methods of manufacturing the same, and more specifically, to forming internal spacers in the fabrication process of gate-all-around (GAA) transistors. The internal spacers provide isolation between the gate structure and adjacent source / drain regions in a GAA transistor. In this document, a source / drain region(s) refers to a region that provides the source and / or drain of one or more devices. Depending on the context, a source / drain region may also refer to the source or drain of one or more devices.

[0012] Multi-gate transistors include those transistors in which the gate structure is formed on at least two sides of the channel region. These multi-gate devices can include p-type field-effect transistors (PFETs) or n-type field-effect transistors (NFETs). A specific example presented herein is a multi-gate transistor called a gate-all-around (GAA) transistor. The gate structure of a GAA transistor, or a portion thereof, is formed on the four sides of the channel (e.g., surrounding the channel). Devices presented herein also include embodiments having channels in one or more nanostructures, such as nanosheets, nanowires, bar-shaped nanostructures, and / or other suitable configurations. These nanostructures are also referred to as channel members. The device examples presented herein may have one or more channel members (e.g., nanosheets) associated with a single continuous gate structure. However, those skilled in the art will recognize that this teaching can also be applied to a single channel member (e.g., a single nanosheet) or any number of channel members. Those skilled in the art may identify examples of other semiconductor devices that could benefit from certain aspects of this disclosure.

[0013] GAA transistors include internal spacers and gate spacers (also called external spacers), as well as other structures. Internal spacers are typically formed before the source / drain features. In an exemplary GAA fabrication process, after creating source / drain trenches, spaces for the internal spacers are formed by partially removing sacrificial layers that alternate with the channel layers. The internal spacers are then formed in these spaces by depositing dielectric material and performing appropriate etching processes. However, the internal spacers introduce dielectric surfaces on the sidewalls of the source / drain trenches, which intersect with the semiconductor surfaces from the channel layers. Therefore, subsequent epitaxial growth of the source / drain features is limited to those semiconductor surfaces that are exposed on the sidewalls of the source / drain trenches. Source / drain features grown separately from these interrupted semiconductor surfaces merge together after reaching a certain height. However, this epitaxial growth process can result in poor epitaxial quality (e.g., voids at the bottom) and displacement of the source / drain features in the source / drain regions. The purpose of this disclosure is to design an internal spacer formation method to improve the quality of source / drain features epitaxially grown in the source / drain region while maintaining the accuracy of the internal spacer size and position.

[0014] In an example process disclosed herein, to form a GAA transistor, a fin structure having a channel layer and a sacrificial layer is first formed on a substrate. After forming a dummy gate stack on the channel region of the fin structure, gate sidewall spacers are formed on the dummy gate stack. Next, the source / drain regions of the fin structure are recessed. Then, source / drain features are formed on the source / drain recessed regions. After removing the dummy gate stack, the sacrificial layer is selectively removed to release the channel layer as channel components. Next, a dielectric layer is deposited in the space between adjacent channel components. Then, the dielectric layer is etched back and partially recessed to form internal spacers between the channel components. Finally, a gate structure is formed to encapsulate each channel component.

[0015] Various aspects of this disclosure will be further described in detail with reference to the accompanying drawings. Figure 1 is a flowchart illustrating a method 100 for forming a semiconductor structure from a work-in-progress (WIP) structure according to an embodiment of this disclosure. Method 100 is merely an example and is not intended to limit the scope of this disclosure to what is explicitly shown in method 100. Additional steps may be added before, during, and after method 100, and certain steps may be replaced, deleted, or rearranged to suit other embodiments of the method. For simplicity, not all steps are described in detail herein. Method 100 will be described below together with Figures 2 through 16B, which are cross-sectional views of the WIP structure at different manufacturing stages according to an embodiment of method 100 in Figure 1. Since the WIP structure will be manufactured into a semiconductor structure or semiconductor device, the WIP structure will also be referred to herein as a semiconductor structure or semiconductor device 200. For the avoidance of doubt, directions X, Y, and Z in Figures 2 through 16B are perpendicular to each other. In this disclosure, unless explicitly stated otherwise, the same reference numerals denote the same features or steps.

[0016] Referring to Figures 1 and 2, method 100 includes step 102, forming a stack 204 of alternating semiconductor layers on a semiconductor device 200. As shown in Figure 2, the semiconductor device 200 includes a substrate 202. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. As is known in the art, the substrate 202 may include various doping configurations depending on design requirements. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) may be formed on the substrate 202. In some embodiments, the n-type dopant forming the n-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) may be formed on the substrate 202. In some embodiments, the p-type dopant forming the p-type well may include boron (B) or gallium (Ga). Suitable doping methods may include ion implantation and / or diffusion processes of the dopant. The substrate 202 may also include other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon-germanium (SiGe), germanium-tin (GeSn), or diamond. Additionally, the substrate 202 may also include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate 202 may selectively include an epitaxial layer, which can be strained to improve performance, and may include silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structures, and / or have other suitable reinforcing features.

[0017] In some embodiments, the stack 204 on substrate 202 includes alternating channel layers 208 having a first semiconductor compound and sacrificial layers 206 having a second semiconductor compound. Alternatively, the sacrificial layers 206 are alternating with the channel layers 208. The first and second semiconductor compounds may be different. In some embodiments, the sacrificial layers 206 comprise silicon germanium (SiGe) or germanium tin (GeSn), while the channel layers 208 comprise silicon (Si). It should be noted that, as shown in Figure 2, the three sacrificial layers 206 and three channel layers 208 are arranged alternately; this is for illustrative purposes only and is not intended to limit the scope beyond what is specifically described in the claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the performance requirements of the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0018] The sacrificial layer 206 and channel layer 208 in stack 204 can be deposited using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), and / or other suitable epitaxial growth processes. As previously described, in at least some instances, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, while the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and channel layer 208 are substantially doped (i.e., the foreign dopant concentration ranges from about 0 atoms / cm³ to about 1 x 10¹⁷ atoms / cm³), for example, no intentional doping is performed during the epitaxial growth process of stack 204.

[0019] Referring to Figures 1 and 3, method 100 includes step 104, forming a fin structure 212 on the stack 204 and the substrate 202. To pattern the stack 204, a hard mask layer can be deposited on the stack 204 to form an etch mask. The etch mask layer can be single-layer or multi-layer. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer on the pad oxide layer. The fin structure 212 can be patterned from the stack 204 and the substrate 202 by lithography and etching processes. Lithography processes may include photoresist coating (e.g., spin coating), soft baking, mask aligning, exposure, post-exposure bake (PEB), photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching), wet etching and / or other etching methods. As shown in Figure 3, the etching process in step 104 forms trenches extending vertically through the stack 204 and a portion of the substrate 202. These trenches define the fin structure 212. In some embodiments, dual patterning or multiple patterning processes may be used to define the fin structure, for example, structures with smaller pitches than achievable in a single direct lithography process. For example, in one embodiment, a material layer is first formed on the substrate and patterned using a lithography process. Then, spacers are formed next to the patterned material layer using a self-aligned process. Next, the material layer is removed, and the remaining spacers or mandrels can be used to pattern the fin structure 212 by etching the stack 204 and a portion of the substrate 202. As shown in Figure 3, the fin structure 212 extends vertically in the Z direction and along its length in the X direction. The fin structure 212 includes a fin base 212B patterned from the substrate 202 and a patterned stack 204 directly on the fin base 212B. In some cases, the width of the fin structure 212, measured along the Y direction, may be between approximately 3 nanometers and approximately 20 nanometers.

[0020] Referring again to Figures 1 and 3, method 100 includes step 106, forming an isolation feature 214 around the fin base 212B of the fin structure 212. In some embodiments shown in Figure 3, the isolation feature 214 is located on the sidewall of the fin base 212B. In some embodiments, the isolation feature 214 may be formed in a trench to isolate the fin structure 212 from adjacent fin structures. The isolation feature 214 may also be referred to as shallow trench isolation (STI) feature 214. For example, in some embodiments, a dielectric layer is first deposited on the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride oxide, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer can be deposited using chemical vapor deposition (CVD), subatmospheric CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, through chemical-mechanical polishing (CMP). The planarized dielectric layer is then recessed or pulled back using dry etching, wet etching, and / or combinations thereof to form the shallow trench isolation (STI) feature 214 shown in Figure 3. After recessing, the fin structure 212 is raised above the STI feature 214, while the fin base 212B is embedded or buried within the STI feature 214.

[0021] Referring to Figures 1 and 4, method 100 includes step 108, depositing a semiconductor pad layer 210 on the fin structure 212. After forming the isolation feature 214, the semiconductor pad layer 210 can be deposited on the semiconductor device 200, including on the isolation feature 214, on the top surface of the fin structure 212, and along the sidewalls of the fin structure 212. The function of the semiconductor pad layer 210 is to protect the sidewalls of the sacrificial layer 206, as these sidewalls may be subject to undesirable damage during fabrication. In some embodiments, the semiconductor pad layer 210 may comprise silicon (Si). In some embodiments, the semiconductor pad layer 210 can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes.

[0022] Referring to Figures 1, 5A, and 5B, method 100 includes step 110, forming a dummy gate stack 220 on the channel region 212C of the fin structure 212. The dummy gate stack 220 serves as a placeholder to undergo various processes and is eventually removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 5B is a cross-sectional view along the line from point A to point A' in Figure 5A. In some embodiments, as shown in Figure 5B, multiple dummy gate stacks 220 are formed on the fin structure 212, and the fin structure 212 can be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. As shown in Figure 5B, the channel region 212C is located between the two source / drain regions 212SD along the direction X.

[0023] The formation of the dummy gate stack 220 may include depositing layers in the dummy gate stack 220 and patterning these layers. Referring to Figure 5A, a dummy dielectric layer 216, a dummy electrode layer 218, and a gate-top hard mask layer 222 may be uniformly deposited on the semiconductor device 200. The dummy dielectric layer 216 may be formed on the fin structure 212 using CVD, ALD, oxygen plasma oxidation, or other suitable processes. In the illustrated embodiment, the dummy dielectric layer 216 is formed via an oxygen plasma oxidation process, which essentially oxidizes the semiconductor pad layer 210 to form the dummy dielectric layer 216. In some cases, the dummy dielectric layer 216 may comprise silicon oxide. Subsequently, the dummy electrode layer 218 may be deposited on the dummy dielectric layer 216 using CVD, ALD, or other suitable processes. In some cases, the dummy electrode layer 218 may comprise polysilicon. For patterning, an upper gate hard mask layer 222 can be deposited on the dummy electrode layer 218 using CVD, ALD, or other suitable processes. The upper gate hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, as shown in Figure 6. For example, the patterning process may include lithography (e.g., lithography or electron beam lithography) and etching processes. The lithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The lithography process forms a patterned photoresist layer. The patterned photoresist layer is then used as an etch mask in the etching process to pattern the upper gate hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the upper gate hard mask layer 222 may include a silicon oxide layer 222a and a silicon nitride layer 222b located on the silicon oxide layer 222a. As shown in Figure 6, the dummy gate stack 220 is patterned so that it is located only on the channel region 212C and not on the source / drain region 212SD.

[0024] Referring to Figures 1 and 6, method 100 includes step 112, depositing a gate spacer layer 226 on semiconductor device 200 (including on dummy gate stack 220). In some embodiments, the gate spacer layer 226 (including on the top surface and sidewalls of the dummy gate stack 220) is compliantly deposited on semiconductor device 200. For ease of description, the term "compliantly" is used herein to refer to a layer having a substantially uniform thickness across various regions. The gate spacer layer 226 can be deposited on the dummy gate stack 220 using processes such as CVD, sub-atmospheric CVD (SACVD), ALD, or other suitable processes. The gate spacer layer 226 can be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may comprise silicon carbonitride, silicon carbide oxide, silicon oxynitride, or silicon nitride. In some embodiments, the gate spacer layer 226 may include an inner layer 226a of silicon oxide and an outer layer 226b of silicon nitride located on the inner layer 226a.

[0025] Referring to Figures 1, 7A, and 7B, method 100 includes step 114, in which the source / drain regions 212SD of the fin structure 212 are anisotropically trenched to form source / drain trenches 228. The anisotropic etching may include dry etching or a suitable etching process that etches the source / drain regions 212SD and a portion of the substrate 202. The resulting source / drain trenches 228 extend vertically through the depth of the stack 204 and partially into the substrate 202. An example of the dry etching process in step 114 may use oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasmas, and / or combinations thereof. As shown in Figure 7A, the source / drain regions 212SD of the fin structure 212 are trenched to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain trench 228 extends below the substrate 202, it includes a bottom surface and lower sidewalls defined in the substrate 202. See Figure 7B, which shows a partial cross-sectional view of two adjacent source / drain regions 212SD. As shown in Figure 7B, most of the fin structure 212 has been etched away in the source / drain regions 212SD, exposing the top surface of the fin base 212B within the source / drain regions 212SD. Because the gate spacer layer 226 is etched at a slower rate than the fin structure 212, it extends above the top surface of the fin base 212B in the source / drain regions 212SD. The remaining portion of the gate spacer layer 226 on the sidewall of the dummy gate stack 220 (as shown in Figure 7A) is called the gate spacer, and the remaining portion of the gate spacer layer 226 on the top surface of the fin base 212B (as shown in Figure 7B) is also called the fin spacer.

[0026] Referring to Figures 1 and 8A through 8C, method 100 includes step 116, wherein source / drain features 244 are formed on source / drain regions 212SD. Source / drain features 244 include a p-type source / drain feature 244P formed in a PFET region, as shown in Figure 8A, and an n-type source / drain feature 244N formed in an NFET region, as shown in Figure 8B. Figure 8C shows a partial cross-sectional view of two adjacent source / drain regions 212SD, one including the p-type source / drain feature 244P and the other including the n-type source / drain feature 244N.

[0027] The p-type source / drain feature 244P may include silicon-germanium (SiGe) and p-type dopants such as boron (B), gallium (Ga), or combinations thereof. As shown in Figure 8A, in the illustrated embodiment, the p-type source / drain feature 244P may include a multilayer structure. For example, the p-type source / drain feature 244P may include a lightly doped epitaxial layer 244Pa located on the sidewalls and bottom surface of the source / drain trench 228, and a heavily doped epitaxial layer 244Pb located above the lightly doped epitaxial layer 244Pa. The atomic percentages of the dopant concentration (e.g., B%) and germanium concentration (e.g., Ge%) of the lightly doped epitaxial layer 244Pa are smaller than those of the heavily doped epitaxial layer 244Pb to reduce crystal dislocation and other crystal defects. In some embodiments, the germanium concentration (G%) in the lightly doped epitaxial layer 244Pa is between about 10% and about 20%, while the germanium concentration (G%) in the heavily doped epitaxial layer 244Pb is between about 30% and about 60%. It is noteworthy that the germanium concentration (G%) in the lightly doped epitaxial layer 244Pa differs from the germanium concentration (G%) in the sacrificial layer 206, which allows for selective etching of the sacrificial layer 206 in subsequent processes, using the lightly doped epitaxial layer 244Pa as an etch stop layer. For example, the germanium concentration (G%) in the sacrificial layer 206 may be between about 20% and 30%, higher than the germanium concentration in the lightly doped epitaxial layer 244Pa but lower than the germanium concentration in the heavily doped epitaxial layer 244Pb.

[0028] Each lightly doped epitaxial layer 244Pa and heavily doped epitaxial layer 244Pb can be formed using vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), or molecular beam epitaxy (MBE). The doping of the lightly doped epitaxial layer 244Pa and the heavily doped epitaxial layer 244Pb can be achieved through in-situ doping. Since the sidewalls and bottom surface of the source / drain trench 228 comprise continuous semiconductor surfaces derived from the end portions of the sacrificial layer 206, the end portions of the channel layer 208, and the top surface of the substrate 202, the lightly doped epitaxial layer 244Pa is a continuous layer. In the illustrated embodiment, the lightly doped epitaxial layer 244Pa has two vertical portions and one horizontal portion, forming a U-shape. Each vertical portion of the lightly doped epitaxial layer 244Pa conformally covers the sidewalls of the source / drain trench 228 with a uniform thickness T1. In the illustrated embodiment, the outer sidewall of the lightly doped epitaxial layer 244Pa facing the fin structure 212 and the inner sidewall facing the source / drain trench 228 are both substantially flat and vertical. The horizontal portion of the lightly doped epitaxial layer 244Pa has a thickness T2, which is greater than the thickness T1 (i.e., T2 > T1) due to the faster crystal growth rate from the top surface of the substrate 202. The heavily doped epitaxial layer 244Pb includes a lower portion surrounded by the lightly doped epitaxial layer 244Pa and an upper portion covering the lightly doped epitaxial layer 244Pa. The lower portion of the heavily doped epitaxial layer 244Pb has a thickness T3, which is greater than the thickness T1 (i.e., T3 > T1). Therefore, the heavily doped epitaxial layer 244Pb can occupy most of the volume of the p-type source / drain feature 244P to reduce contact resistance. Depending on the epitaxial growth time of the lightly doped epitaxial layer at 244 Pa, the thickness T3 may be less than the thickness T2 (i.e., T3 < T2), as shown in Figure 8A, or in other embodiments, the thickness T3 may be greater than the thickness T2 (i.e., T3 > T2).

[0029] The n-type source / drain feature 244N may comprise silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. In the embodiment shown in Figure 8B, the n-type source / drain feature 244N may comprise a multilayer structure. For example, the n-type source / drain feature 244N may comprise a lightly doped epitaxial layer 244Na covering the sidewalls and bottom surface of the source / drain trench 228, and a heavily doped epitaxial layer 244Nb covering the lightly doped epitaxial layer 244Na. The dopant concentration (e.g., P%) in the lightly doped epitaxial layer 244Na is lower than the dopant concentration in the heavily doped epitaxial layer 244Nb to reduce crystal misalignment and other crystal defects. In some embodiments, the P% in the lightly doped epitaxial layer 244Na is between about 10% and about 20%, while the P% in the heavily doped epitaxial layer 244Nb is between about 30% and about 60%.

[0030] Both the lightly doped epitaxial layer 244Na and the heavily doped epitaxial layer 244Nb can be formed by vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), or molecular beam epitaxy (MBE). The doping of the lightly doped epitaxial layer 244Na and the heavily doped epitaxial layer 244Nb can be achieved through in-situ doping. Since the sidewalls and bottom surface of the source / drain trench 228 comprise continuous semiconductor surfaces derived from the end portions of the sacrificial layer 206, the end portions of the channel layer 208, and the top surface of the substrate 202, the lightly doped epitaxial layer 244Na is a continuous layer. In the illustrated embodiment, the lightly doped epitaxial layer 244Na has two vertical portions and one horizontal portion, forming a U-shape. Each vertical portion of the lightly doped epitaxial layer 244Na conformably covers the sidewalls of the source / drain trench 228 with a uniform thickness T1'. In the illustrated embodiment, the outer sidewall of the lightly doped epitaxial layer 244Na facing the fin structure 212 and the inner sidewall facing the source / drain trench 228 are both substantially flat and vertical. The horizontal portion of the lightly doped epitaxial layer 244Na has a thickness T2', which is greater than the thickness T1' (i.e., T2' > T1'), due to the faster crystal growth rate from the top surface of the substrate 202. The heavily doped epitaxial layer 244Nb includes a lower portion surrounded by the lightly doped epitaxial layer 244Na and an upper portion covering the lightly doped epitaxial layer 244Na. In the illustrated embodiment, the lower portion of the heavily doped epitaxial layer 244Nb has a thickness T3', which is smaller than the thicknesses T1' and T2' (i.e., T3' < T1' < T2'), so the lightly doped epitaxial layer 244Na may occupy a large portion of the volume of the n-type source / drain feature 244N. Alternatively, depending on the epitaxial growth time of the lightly doped epitaxial layer 244Na, the thickness T3' may be greater than the thickness T1' but less than the thickness T2' (i.e., T1' < T3' < T2') or greater than both the thickness T1' and the thickness T2' (i.e., T1' < T2' < T3').

[0031] In the illustrated embodiment, because the lower thickness of the heavily doped epitaxial layer 244Nb is less than the thickness of the heavily doped epitaxial layer 244Pb, during the epitaxial growth process, the upper portion of the heavily doped epitaxial layer 244Nb may protrude beyond the top surface of the lightly doped epitaxial layer 244Na compared to the heavily doped epitaxial layer 244Pb. This results in the uppermost portion of the n-type source / drain feature 244N potentially being higher than the uppermost portion of the p-type source / drain feature 244P. Furthermore, the upper portion of the heavily doped epitaxial layer 244Nb has a wavy top surface compared to the generally flat upper portion of the heavily doped epitaxial layer 244Pb. In other words, the top surface of the n-type source / drain feature 244N may have a greater surface roughness than the top surface of the p-type source / drain feature 244P.

[0032] In some embodiments, as shown in Figure 8C, an n-type source / drain feature 244N may be adjacent to a p-type source / drain feature 244P. The n-type source / drain feature 244N may comprise silicon (Si) and an n-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb). The p-type source / drain feature 244P may comprise silicon-germanium (SiGe) and a p-type dopant such as boron (B). A finned gate spacer layer 226 may be located on the bottom sidewall of each n-type source / drain feature 244N and p-type source / drain feature 244P. For ease of illustration and description, the n-type source / drain feature 244N and p-type source / drain feature 244P may be collectively referred to as source / drain feature 244, as shown in Figure 8C.

[0033] Referring to Figures 1, 9A, and 9B, method 100 includes step 118, forming an inter-layer dielectric (ILD) 248 on the source / drain feature 244. In some embodiments, a contact etch stop layer (CESL) 246 is also formed prior to the formation of the ILD layer 248. In some embodiments, the contact etch stop layer 246 may comprise silicon nitride or aluminum nitride. In some embodiments, the contact etch stop layer 246 may be deposited using a CVD process or atomic layer deposition (ALD). The ILD layer 248 is then deposited on the contact etch stop layer 246. In some embodiments, the ILD layer 248 comprises tetraethyl orthosilicate (TES) oxide, undoped silicate glass, or doped silicate, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. The ILD layer 248 can be deposited using CVD, flow CVD (FCVD), spin coating, or other suitable deposition techniques. After depositing the ILD layer 248, the semiconductor device 200 can be planarized using a planarization process to remove the upper gate hard mask layer 222 and expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. After exposing the dummy gate stack 220, it can be removed.

[0034] Referring to Figures 1, 10A, and 10B, method 100 includes step 120, in which a dummy gate stack 220 is removed to form a gate trench 250, and a plurality of channel layers 208 are released as channel components 2080. The removal of the dummy gate stack 220 may include one or more etching processes selectively applied to the material of the dummy gate stack 220. For example, the removal of the dummy gate stack 220 may be performed using selective wet etching, selective dry etching, or a combination thereof, processes selectively applied to the dummy gate stack 220. After forming the gate trench 250, a sacrificial layer 206 sandwiched between the channel layers 208 in the channel region 212C is selectively removed. The selective removal of the sacrificial layer 206 releases the channel layers 208, forming the channel components 2080. Depending on the design, the channel components 2080 may be embodied as nanowires, nanopillars, nanosheets, or other nanostructures. Selective removal of the sacrificial layer 206 creates voids 252 between and around adjacent channel components 2080. Selective removal of the sacrificial layer 206 can be achieved through selective dry etching, selective wet etching, or other selective etching processes. For example, selective dry etching processes can use one or more fluorine-based etchants, such as fluorine or hydrofluorocarbons. Examples of selective wet etching processes include APM etching (e.g., an ammonia hydroxide-hydrogen peroxide-water mixture). The germanium concentration difference between the outer layer of the source / drain feature 244 and the sacrificial layer 206 creates an etching contrast, allowing the source / drain feature 244 to remain largely intact during the selective removal of the sacrificial layer 206. Notably, as shown in Figures 10A and 10B, the uppermost channel component 2080 may experience some etching loss when directly exposed to the gate trench 250. This causes the top surface at the center of the uppermost channel component 2080 to form a curved profile, exposing part of the bottom surface of the gate spacer layer 226.

[0035] As shown in Figures 1, 11A, and 11B, method 100 includes step 122, depositing a dielectric material layer 254 in and around the void 252 between and around the gate trench 250 and adjacent channel components 2080. As detailed below, the dielectric material layer 254 is etched and formed as an internal spacer. Therefore, the dielectric material layer 254 is also referred to as the internal spacer material layer 254. The internal spacer material layer 254 may include a dielectric material such as SiOC, SiOCN, SiCN, and / or other suitable materials. In various embodiments, at least the inner layer 226a of the gate spacer layer 226 and the internal spacer material layer 254 contain different material compositions. In one embodiment, the inner layer 226a of the gate spacer layer 226 may include silicon dioxide, while the outer layer 226b of the gate spacer layer 226 and the internal spacer material layer 254 both include silicon nitride. In another example, the inner layer 226a of the gate spacer layer 226 comprises silicon dioxide, the outer layer 226b of the gate spacer layer 226 comprises silicon nitride, and the inner spacer material layer 254 comprises silicon carbide. In some embodiments, the inner spacer material layer 254 can be deposited using a cyclic deposition and etching (CDE) process. The CDE process may involve alternating multiple deposition cycles and multiple etching cycles. In some cases, each deposition cycle is immediately followed by an etching cycle. For example, each etching cycle may use a fluorinated etchant, such as sulfur hexafluoride (SF6) or nitrogen trifluoride (NF3). These etching cycles continuously remove dielectric material from the gate spacer layer 226, preventing the dielectric material from accumulating too quickly and thus closing the gate trench 250. The etching cycles also maintain the void 252 as a void between adjacent channel components 2080. These gaps are intentionally left so that the etchant can flow into them during the subsequent etching process, promoting partial removal of the internal spacer material layer 254, thereby forming the internal spacer.

[0036] Referring to Figures 1 and 12A through 12C, method 100 includes step 124, removing the central portion of the internal spacer material layer 254 within the channel region 212C, while the remaining portion directly beneath the gate spacer layer 226 and in contact with the source / drain feature 244 is retained as internal spacer 2540. In some embodiments, the etching process of step 124 includes alternating cycles of surface treatment and selective etching. During this cycle, a portion of the exposed internal spacer material layer 254 in the channel region 212C is repeatedly surface treated and subsequently selectively etched to remove the treated surface portion. The cycle continues until the internal spacer material layer 254 in the channel region 212C is completely removed, while the remaining portion directly beneath the gate spacer layer 226 is retained as internal spacer 2540. In various embodiments, surface treatment (e.g., oxidation or nitriding) is performed through the gate trench 250, using the gate spacer layer 226 as a treatment mask, as shown in Figure 12C, a cross-sectional view along a line from point C to point C in Figure 12A, where the inner spacers 2540 remain beneath the gate spacer layer 226. Referring again to Figures 12A and 12B, the central portions of the inner spacer material layers 254 on either side of the gate spacer layer 226 undergo surface treatment, resulting in a change in material composition that gives this portion a different etch selectivity relative to the rest of the inner spacer material layers 254. A selective etching process is then applied in a cycle to remove the treated (e.g., oxidized or nitrided) surface portions of the inner spacer material layers 254, because the etching process is tuned to be selective for oxides or nitrides and does not substantially etch untreated portions. The remaining voids 252 (or spaces 252) allow the etchant to reach the treated surface portions at different locations, thereby improving the consistency of the etching rate. Selective etching processes may include wet etching, dry etching, reactive ion etching, or other suitable etching methods.

[0037] After the internal spacer material layer 254 is removed from the channel region 212C, the channel component 2080 is released again. The gap 252 between adjacent channel components 2080 is enlarged. As will be described in further detail below, a high-dielectric layer / metal gate (HK MG) structure is formed in the enlarged gap 252 and abuts against the internal spacer 2540. Thus, the internal spacer 2540 provides isolation between the metal gate structure and the epitaxial source / drain features 244. The width of the enlarged gap 252 in the X direction may be greater than the width between the gate spacer layers 226. Therefore, the lower part of the metal gate structure to be formed below the topmost channel component 2080 may have a wider width in the X direction than its upper part between the gate spacer layers 226. In the illustrated embodiment, as shown in Figures 12A and 12B, since the etching process begins from the channel region 212C, the inner sidewall of the internal spacer 2540 faces the enlarged gap 252, exhibiting a concave profile that curves toward the source / drain feature 244, while the outer sidewall of the internal spacer 2540, which is adjacent to the source / drain feature 244, is generally straight.

[0038] In some embodiments of the GAA manufacturing process, the etching process forming the internal spacers begins from the source / drain region 212SD, resulting in an outer wall with a concave profile curving towards the channel region 212C. In contrast, the curved inner sidewalls and generally straight outer walls of the internal spacer 2540, as shown herein, represent one of the characteristics of devices produced through some of the example manufacturing processes described in this disclosure. It is noteworthy that, due to the curvature profile of the top surface of the uppermost channel component 2080, a portion of the internal spacer material layer 254 may remain directly beneath the gate spacer layer 226 in the corner regions of the curvature profile without being removed. These remaining portions of the internal spacer material layers 254, vertically stacked between the uppermost channel component 2080 and the gate spacer layer 226, are referred to as dielectric residue 254R, and may be retained in the final structure. Dielectric residue 254R, having the same material composition as the internal spacer 2540, represents another characteristic of devices produced through some of the example manufacturing processes.

[0039] Referring to Figures 1, 13A, and 13B, method 100 includes step 126, in which a gate structure 260 is formed in the gate trench 250 to enclose the channel component 2080. These gate structures 260 are also referred to as high-k / metal gate (HKMG) structures due to the high-k dielectric layer and the metal gate electrode layer, but other compositions are also possible. As described above, due to the enlargement of the gap 252, the lower portion of the gate structure 260 located below the uppermost channel component 2080 may have a width in the X direction greater than the width of its upper portion between the opposing sidewalls of the gate spacer layer 226, as shown in Figures 13A and 13B. Alternatively, the upper and lower portions of the gate structure 260 may have substantially uniform widths. In the illustrated embodiment, the gate structure 260 includes: an interface layer 262 located at the junction of the channel component 2080 and the substrate 202 in the channel region 212C; a high-k dielectric layer 264 located above the interface layer 262; a work function layer 266 (a p-type work function layer 266P in the PFET region and an n-type work function layer 266N in the NFET region) located above the high-k dielectric layer 264; and a metal filler layer 268 (a metal filler layer 268P in the PFET region and a metal filler layer 268N in the NFET region) surrounded by the work function layer 266. The interface layer 262 and the high-k dielectric layer 264 are collectively referred to as the gate dielectric layer. The work function layer 266 and the metal filler layer 268 are collectively referred to as the gate electrode layer.

[0040] Interface layer 262 may comprise dielectric materials such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. High-k dielectric layer 264 may comprise high-k dielectric materials such as hafnium oxide. Alternatively, the gate dielectric layer may include other high-k dielectric materials, such as titanium dioxide (TiO₂), hafnium calcium oxide (HfZrO₄), niobium oxide (Ta₂O₅), hafnium silicon oxide (HfSiO₄), scandium oxide (ZrO₂), scandium silicon oxide (ZrSiO₂), gallium oxide (La₂O₃), aluminum oxide (Al₂O₃), scandium oxide (ZrO), yttrium oxide (Y₂O₃), hafnium gallium oxide (HfLaO), gallium silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium niobium oxide (HfTaO), hafnium titanium oxide (HfTiO), and combinations thereof, or other suitable materials. The high-k dielectric layer 264 can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation treatment and / or other suitable methods.

[0041] The work function layer 266 may be a p-type or n-type work function layer, depending on the type of device (PFET or NFET). The p-type work function layer 266P contains a metal with a sufficiently large effective work function, including but not limited to titanium nitride (TiN), tantalum nitride (TaN), vanadium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. The n-type work function layer 266N contains a metal with a sufficiently low effective work function, including but not limited to titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), or combinations thereof. Each metal-filled layer 268N and 268P may include aluminum (Al), tungsten (W), cobalt (Co), and / or other suitable materials. In various embodiments, the gate electrode layer may be formed using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam evaporation, or other suitable processes.

[0042] Referring to Figures 14A and 14B, Figures 14A and 14B illustrate another embodiment of the semiconductor device 200 at the end of step 126. The semiconductor device 200 shown in Figures 14A and 14B is similar in many respects to the embodiments shown in Figures 13A and 13B. The difference is the deposition of a buffer epitaxial layer 242 beneath the bottom of the source / drain feature 244. The buffer epitaxial layer 242 is epitaxially grown from the top surface of the fin base 212B prior to the formation of the source / drain feature 244. For example, the epitaxial growth of the buffer epitaxial layer 242 can be performed using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable epitaxial growth processes. In some embodiments, the material of the buffer epitaxial layer 242 is the same as that of the substrate 202, such as silicon. In some alternative embodiments, the buffer epitaxial layer 242 comprises a semiconductor material other than silicon, such as silicon germanium (SiGe), silicon tin (SiSn), or other suitable semiconductor materials. In some embodiments, the buffer epitaxial layer 242 is undoped, for example, without any intentional doping during the epitaxial growth process. In contrast, in one example, the substrate 202 is lightly doped, with a doping concentration higher than that of the buffer epitaxial layer 242. The buffer epitaxial layer 242 provides a high-resistance path from the source / drain region to the semiconductor substrate, thereby suppressing leakage current in the semiconductor substrate.

[0043] Referring to Figures 15A and 15B, which illustrate another embodiment of the semiconductor device 200 after step 126, the semiconductor device 200 in Figures 15A and 15B is similar in many respects to the embodiments in Figures 13A and 13B. The difference lies in the presence of more rectangular internal spacers 2540 in Figures 15A and 15B, whose inner and outer sidewalls are generally straight. The straight inner sidewalls are primarily due to the application of different parameters in the cyclic etching process during step 124.

[0044] Referring to Figures 16A and 16B, which illustrate another embodiment of the semiconductor device 200 after step 126, the semiconductor device 200 in Figures 16A and 16B is similar in many respects to the embodiments in Figures 13A and 13B. The difference lies in the fact that the inner and outer sidewalls of the internal spacer 2540 in Figures 16A and 16B both have a curvature profile that bends towards the source / drain feature 244. Due to the presence of the curved outer sidewalls, a portion of the internal spacer 2540 is partially embedded in the sidewalls of the source / drain feature 244. This curved outer sidewall is primarily caused by etch loss of the outer layer of the source / drain feature 244 due to limited etch contrast during the selective removal of the sacrificial layer 206 in step 120.

[0045] Semiconductor device 200 may undergo further processing to form various features and regions known in the art. For example, subsequent processing may include forming contact openings, contact metals, and various contact / via / wire and multilayer interconnect features (e.g., metal layers and interlayer dielectric layers) on substrate 202, configured to connect various functional elements to form a functional circuit, which may include one or more multi-gate devices. Furthermore, multilayer interconnects may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal wires. Various interconnect features may use a variety of conductive materials, including copper, tungsten, and / or silicates. For example, damascene and / or dual damascene processes may be used to form copper-related multilayer interconnect structures. Additionally, other process steps may be performed before, during, and after method 100, and some of the above-mentioned process steps may be replaced or omitted depending on different embodiments of method 100.

[0046] While not intended to be limiting, embodiments of this disclosure offer one or more of the following advantages. For example, embodiments of this disclosure provide a method for forming internal spacers after forming source / drain features, which effectively reduces crystal defects and other defects in the source / drain regions of GAA transistors. Furthermore, this method of forming internal spacers can be easily integrated into existing semiconductor manufacturing processes.

[0047] In one embodiment, this disclosure relates to a method of forming a semiconductor structure. The method includes forming a stack on a substrate, comprising alternating stacks of multiple channel layers and multiple sacrificial layers; patterning the stack to form a fin-like structure; forming a dummy gate stack in the channel region of the fin-like structure; depositing gate spacers on the sidewalls of the dummy gate stack; recessing the source / drain region of the fin-like structure to form source / drain trenches that expose the sidewalls of the channel layers and the sidewalls of the sacrificial layers; performing a first epitaxial growth on the sidewalls of the channel layers and the sidewalls of the sacrificial layers to form a first epitaxial layer; performing a second epitaxial growth on the first epitaxial layer to form a second epitaxial layer; removing the dummy gate stack; selectively removing the sacrificial layers in the channel region to release the channel layers as channel components; depositing a dielectric material layer covering the channel components; removing the dielectric material layer from the channel region while retaining a portion of the dielectric material layer below the gate spacers to form internal spacers; and forming a metal gate structure covering the channel components, wherein the internal spacers are located between the metal gate structure and the first epitaxial layer. In some embodiments, the internal spacer has a first sidewall in contact with the first epitaxial layer and a second sidewall in contact with the metal gate structure, and the second sidewall of the internal spacer is curved toward the first epitaxial layer. In some embodiments, the first sidewall of the internal isolation layer is substantially straight. In some embodiments, the first sidewall of the internal isolation layer is curved toward the first epitaxial layer. In some embodiments, the operation of depositing the dielectric material layer includes a cycle deposition and etching process. In some embodiments, the operation of removing the dielectric material layer includes a cycle surface treatment and etching process. In some embodiments, after depositing the dielectric material layer, a gap is left between adjacent channel components. In some embodiments, both the first and second epitaxial layers comprise silicon germanium, wherein the percentage concentration of germanium atoms in the first epitaxial layer is less than the percentage concentration of germanium atoms in the second epitaxial layer. In some embodiments, the first epitaxial layer includes a first sidewall in contact with the channel component and a second sidewall in contact with the second epitaxial layer, and the first and second sidewalls of the first epitaxial layer are substantially straight. In some embodiments, the method further includes forming a buffer epitaxial layer between the substrate and the first epitaxial layer.

[0048] In another embodiment, this disclosure relates to a method. The method includes forming a structure in which a plurality of channel components are vertically stacked above a substrate to form source / drain features abutting the channel components; after forming the source / drain features, depositing a dielectric material layer to cover the channel components; leaving gaps between adjacent channel components after depositing the dielectric material layer; selectively removing a central portion of the dielectric material layer to release the channel components; and forming a metal gate structure covering the channel components. Side portions of the dielectric material layer are located between the metal gate structure and the source / drain features. In some embodiments, selectively removing the central portion of the dielectric material layer includes repeating processing steps and selective etching steps until the channel components are released. In some embodiments, the processing step is an oxidation process or a nitriding process. In some embodiments, the side portions of the dielectric material layer include a first sidewall facing the source / drain features and a second sidewall facing the metal gate structure, wherein the second sidewall of the side portion bends toward the source / drain features. In some embodiments, the first sidewall of the side portion of the dielectric material layer is substantially straight. In some embodiments, after selectively removing the central portion of the dielectric material layer, a portion of the dielectric material layer remains on the top surface of the uppermost channel component.

[0049] In another embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a plurality of nanostructures suspended above a substrate; a gate structure surrounding each of the nanostructures; a gate spacer located on the sidewall of the gate structure; a source / drain feature abutting the nanostructure; and an internal spacer between the gate structure and the source / drain feature, extending between two adjacent nanostructures. The internal spacer has a first sidewall facing the source / drain feature and a second sidewall facing the gate structure, wherein the first sidewall is straight and vertical, while the second sidewall curves toward the source / drain feature. In some embodiments, the gate structure includes a lower portion below the uppermost nanostructure and an upper portion above the uppermost nanostructure, wherein the lower portion is wider than the upper portion along the length of the nanostructure. In some embodiments, the source / drain feature includes a first epitaxial layer and a second epitaxial layer surrounded by the first epitaxial layer, wherein the first epitaxial layer has sidewalls facing the gate structure, and the sidewalls of the first epitaxial layer are straight and vertical. In some embodiments, the germanium concentration of the first epitaxial layer is lower than the germanium concentration of the second epitaxial layer.

[0050] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should recognize that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and adjustments without departing from the spirit and scope of this disclosure.

[0051] 100: Method 102,104,106,108,110,112,114,116,118,120,122,124,126: Steps 200: Semiconductor devices 202:Substrate 204: Stacking 206: Sacrifice Layer 208: Channel Layer 2080: Channel Components 210: Semiconductor pad layer 212: Fin-like structure 212B: Fin-shaped base 212C: Channel Area 212SD: Source / Drain Region 214: Isolation Features 216: Virtual Dielectric Layer 218: Dummy Electrode Layer 220: Virtual Gate Stack 222: Upper gate extremely hard shielding layer 222a: Silicon oxide layer 222b: Silicon nitride layer 226: Gate spacer layer 226a: Inner layer 226b: Outer layer 228: Source / Drain Trench 242: Buffer epitaxial layer 244: Source / Drain Characteristics 244P: p-type source / drain characteristics 244N: n-type source / drain characteristics 244Pa, 244Na: Lightly doped epitaxial layer 244Pb, 244Nb: Heavily doped epitaxial layer 246: Contact Etching Stop Layer 248: Interlayer dielectric layer (ILD layer) 250: Gate trench 252: Gap 254: Internal spacer material layer 254R: Dielectric residue 2540: Internal spacers 260: Gate structure 262: Interface Layer 264: High K-value dielectric layer 266: Work Function Layer 266P: p-type work function layer 266N: n-type work function layer 268, 268N, 268P: Metal filler layer A, A', C: Points T1,T1',T2,T2',T3,T3': Thickness X, Y, Z: Direction

Claims

1. A method for forming a semiconductor structure, comprising: A stack is formed on a substrate, the stack including a plurality of channel layers and a plurality of sacrificial layers arranged in an alternating pattern; the stack is patterned to form a fin-like structure; a dummy gate stack is formed on a channel region of the fin-like structure; a plurality of gate spacers are deposited on the plurality of sidewalls of the dummy gate stack; a source / drain region of the fin-like structure is recessed to form a source / drain trench, the source / drain trench exposing the plurality of sidewalls of the channel layers and the plurality of sidewalls of the sacrificial layers; a buffer epitaxial layer is formed in the source / drain trench; a first epitaxial layer is epitaxially grown from the sidewalls of the channel layers and the sacrificial layers and from the buffer epitaxial layer; a second epitaxial layer is epitaxially grown on the first epitaxial layer; the dummy gate stack is removed. Selectively remove the sacrificial layers in the channel region to release the channel layers as a plurality of channel components, wherein the channel components include a bottommost channel component; deposit a dielectric material layer covering the channel components; remove the dielectric material layer from the channel region while retaining portions of the dielectric material layer directly below the gate spacers to form a plurality of internal spacers; And forming a metal gate structure covering the channel components, wherein the internal spacers are located between the metal gate structure and the first epitaxial layer, wherein a top surface of the buffer epitaxial layer is lower than a top surface of the bottommost channel component.

2. The method as claimed in claim 1, wherein the internal spacers have a first sidewall adjacent to the first epitaxial layer and a second sidewall adjacent to the metal gate structure, and the second sidewall of the internal spacers bends toward the first epitaxial layer.

3. The method as described in claim 1, wherein the operation of removing the dielectric material layer includes a cyclic surface treatment and an etching process.

4. The method as described in claim 1, wherein both the first epitaxial layer and the second epitaxial layer comprise silicon germanium, and the percentage concentration of germanium atoms in the first epitaxial layer is less than the percentage concentration of germanium atoms in the second epitaxial layer.

5. The method as described in claim 1, wherein the first epitaxial layer includes a first sidewall connected to the channel components and a second sidewall connected to the second epitaxial layer, and both the first sidewall and the second sidewall of the first epitaxial layer are substantially straight.

6. A method for forming a semiconductor structure, comprising: A structure is formed comprising a plurality of channel components vertically stacked on a substrate, wherein the channel components include a bottommost channel component; A buffer epitaxial layer is formed on the substrate; a source / drain feature is formed on the buffer epitaxial layer and abuts against the channel components, wherein a top surface of the buffer epitaxial layer is lower than a top surface of the bottommost channel component; after forming the source / drain feature, a dielectric material layer is deposited covering the channel components, wherein after depositing the dielectric material layer, a plurality of voids are maintained between adjacent channel components; a central portion of the dielectric material layer is selectively removed to release the channel components; and a metal gate structure is formed covering the channel components, wherein a side portion of the dielectric material layer is located between the metal gate structure and the source / drain feature.

7. The method as described in claim 6, wherein the operation of selectively removing the central portion of the dielectric material layer includes repeatedly performing a processing step and a selective etching step until the channel components are released, wherein the processing step is an oxidation step or a nitriding step.

8. The method as described in claim 6, wherein the side portion of the dielectric material layer includes a first sidewall facing the source / drain feature and a second sidewall facing the metal gate structure, and the second sidewall of the side portion of the dielectric material layer bends toward the source / drain feature, and the first sidewall of the side portion of the dielectric material layer is substantially straight.

9. The method as described in claim 6, wherein after selectively removing the central portion of the dielectric material layer, a portion of the dielectric material layer remains on the top surface of the uppermost of the channel components.

10. A semiconductor structure comprising: A plurality of nanostructures are suspended above a substrate, wherein the nanostructures include a bottommost nanostructure; a gate structure surrounds each of the nanostructures; a gate spacer is located on one side of the gate structure; a source / drain feature is abutted against the nanostructures; and a buffer epitaxial layer is located between the substrate and the source / drain feature, wherein a top surface of the buffer epitaxial layer is lower than a top surface of the bottommost nanostructure. And an internal spacer, located between the gate structure and the source / drain feature, and extending between adjacent ones in the nanostructures, wherein the internal spacer includes a first sidewall facing the source / drain feature and a second sidewall facing the gate structure, the first sidewall being straight and vertical, and the second sidewall being curved toward the source / drain feature.

11. The semiconductor structure as claimed in claim 10, wherein the gate structure includes a lower portion located below one of the uppermost layers of the nanostructure and an upper portion located above one of the uppermost layers of the nanostructure, and the lower portion is wider than the upper portion in the length direction of the nanostructure.

12. The semiconductor structure as claimed in claim 10, wherein the source / drain feature includes a first epitaxial layer and a second epitaxial layer surrounded by the first epitaxial layer, the first epitaxial layer including a sidewall facing the gate structure and the sidewall of the first epitaxial layer being straight and vertical, and the germanium concentration of the first epitaxial layer being lower than the germanium concentration of the second epitaxial layer.

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