Semiconductor structure and method of forming the same

Abstract

The method includes patterning and stacking multiple layers to form first and second multilayer stacks, each including multiple staggered sacrificial layers and multiple nanostructures. The second multilayer stack is wider than the first multilayer stack. A nanosheet transistor is formed based on the first multilayer stack. The nanosheet transistor includes multiple first channel regions having a first width; and a first gate stack located on the first channel regions. A nanowire transistor is formed based on the second multilayer stack. The nanowire transistor includes multiple second channel regions, and the second channel regions are narrower than the first channel regions; and a second gate stack located on the second channel regions.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor structures, and particularly to semiconductor structures employing nanowire transistors and nanosheet transistors. Prior Technology

[0002] Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (such as the number of interconnect devices per unit wafer area) typically increases with shrinking geometry. Shrinking manufacturing processes generally facilitate increased production capacity and reduced associated costs.

[0003] Minimizing size also increases the complexity of processing and manufacturing integrated circuits. To achieve these advancements, the processing and manufacturing of integrated circuits also require similar development. For example, fully wound gate transistors have been introduced to replace planar transistors. The structure of fully wound gate transistors and methods for fabricating them have been developed. Summary of the Invention

[0004] In some embodiments of the present invention, a method for forming a semiconductor structure includes patterning and stacking a plurality of layers to form a first multilayer stack and a second multilayer stack, each of the first multilayer stack and the second multilayer stack including a plurality of interleaved sacrificial layers and a plurality of nanostructures, wherein the second multilayer stack is wider than the first multilayer stack; forming a nanosheet transistor based on the first multilayer stack, wherein the nanosheet transistor includes a plurality of first channel regions having a first width; and a first gate stack located on the first channel regions; forming a nanowire transistor based on the second multilayer stack, wherein the nanowire transistor includes a plurality of second channel regions, and the second channel regions are narrower than the first channel regions; and a second gate stack located on the second channel regions.

[0005] In some embodiments of the present invention, the semiconductor structure includes a substrate semiconductor substrate; a nanoplate transistor located on the substrate semiconductor substrate, wherein the nanoplate transistor includes a plurality of first channel regions, wherein an upper first channel region overlaps with a lower first channel region; a first gate stack located on the first channel regions; and a nanowire transistor located on the substrate semiconductor substrate, wherein the nanowire transistor includes a plurality of second channel regions narrower than the first channel regions, wherein an upper second channel region overlaps with a lower second channel region; and a second gate stack located on the second channel regions.

[0006] In some embodiments of the present invention, the semiconductor structure includes a nanowire transistor, including a protrusion structure, including a plurality of channel regions; and a plurality of dielectric regions located between the channel regions; a first source / drain region and a second source / drain region located on both sides of the channel regions and the dielectric regions and coupled to the channel regions and the dielectric regions; and a gate stack located on the protrusion structure. Simple Explanation of the Diagram

[0007] Figures 1 to 4, 5A-1, 5A-2, 5B-1, 5B-2, 6A-1, 6A-2, 6B-1, 6B-2, 7B-1, 7B-2, 8A-1, 8A-2, 8B-1, 8B-2, 9A-1, 9A-2, 9B-1, 9B-2, 10A-1, 10A-2, 10B-1, 10B-2, 11A-1, 11A-2, 11B-1, 11B-2, 12A-1, 12A-2, 12B-1, 12B-2, 13A-1, 13A-2, 13B-1, 13B-2, 14A-1, 14A-2, 14B-1, and 14B-2 are diagrams of the intermediate stages of forming nanosheet transistors and nanowire transistors in some embodiments. Figures 15A-1, 15A-2, 15B-1, 15B-2, 16A-1, 16A-2, 16B-1, 16B-2, 17A-1, 17A-2, 17B-1, and 17B-2 are diagrams of intermediate stages in forming nanosheet transistors and nanowire transistors in other embodiments. Figures 18 to 21 are top views of some nanowires and nanosheets in some embodiments. Figure 22 is a circuit diagram of a static random access memory unit in some embodiments. Figure 23 shows some nanosheet transistors with different channel widths in some embodiments. Figure 24 shows some nanowire transistors with different channel widths in some embodiments. Figure 25 shows the process flow for forming nanosheet transistors and nanowire transistors in some embodiments. Implementation

[0008] The following detailed description, accompanied by accompanying drawings, will aid in understanding various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity of explanation.

[0009] It is understood that the different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The specific components and arrangements described are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or that the two are separated by other additional components rather than in direct contact. Furthermore, the same reference numerals may be used repeatedly in various embodiments of the present invention for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] In addition, spatial relative terms such as "below," "below," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90 degrees or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0011] A hybrid structure and its formation method are provided, wherein the hybrid structure includes a wafer transistor and a wire transistor. In some embodiments of the invention, the wafer transistor and the wire transistor share some common formation processes. Semiconductor materials can be epitaxially grown to increase the thickness of the nanowires in the wire transistor. By forming a hybrid structure in a circuit, the occupied wafer area can be reduced without sacrificing circuit performance.

[0012] The embodiments described herein provide examples of how the subject matter of the embodiments of the present invention can be implemented or employed, and those skilled in the art will readily understand feasible adjustments and maintain within the scope of the various embodiments. In the various drawings and illustrative embodiments, similar reference numerals may be used to designate similar elements. While embodiments of some methods are described with steps performed in a particular order, embodiments of other methods may have these steps performed in any logical order.

[0013] Figures 1 to 14A-1, 14A-2, 14B-1, and 14B-2 are cross-sectional views of intermediate stages in forming a hybrid structure in some embodiments of the present invention, wherein the hybrid structure contains nanosheet transistors and nanowire transistors. The corresponding process can be the process flow shown in Figure 25.

[0014] Figure 1 is a perspective view of wafer 10. Wafer 10 includes a multilayer structure containing multiple layers stacked 22 on substrate 20. In some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or the like, and may also employ other substrates and / or structures such as semiconductor-on-insulator, strained semiconductor-on-insulator, silicon-germanium-on-insulator, or the like. Substrate 20 may be doped with p-type semiconductor, but in other embodiments, substrate 20 may be doped with n-type semiconductor.

[0015] In some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing interleaved materials. Individual processes may be process 202 in the process flow 200 shown in FIG. 25. In some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material, wherein the first semiconductor material and the second semiconductor material are different.

[0016] In some embodiments, the composition of the first semiconductor material of the first layer 22A may be or include silicon germanium, germanium, silicon, gallium arsenide, indium antimonide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, or the like. In some embodiments, the method for depositing the first layer 22A, such as silicon germanium, is epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy, molecular beam epitaxy, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, ultra-high vacuum chemical vapor deposition, remote plasma chemical vapor deposition, or similar methods. In some embodiments, the thickness of the first layer 22A is between about 30 Å and about 300 Å. However, any suitable thickness may be used, which is still within the scope of the embodiments.

[0017] Once the first layer 22A is deposited on the substrate 20, the second layer 22B can be deposited on the first layer 22A. In some embodiments, the second layer 22B may be composed of or include a second semiconductor material such as silicon, silicon germanium, germanium, gallium arsenide, indium antimonide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, combinations thereof, or the like, and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, in some embodiments, the first layer 22A is silicon germanium, while the second layer 22B may be composed of silicon, and vice versa. It should be understood that any suitable combination of materials may be used for the first layer 22A and the second layer 22B.

[0018] In some embodiments, a second epitaxial layer 22B is grown on the first layer 22A, using a deposition technique similar to that used to form the first layer 22A. In some embodiments, the thickness of the second layer 22B is similar to the thickness of the first layer 22A. The thickness of the second layer 22B may also differ from the thickness of the first layer 22A. In some embodiments, the thickness of the first layer 22A is between about 4 nm and 7 nm, while the thickness of the second layer 22B is between about 8 nm and 12 nm.

[0019] Once the second layer 22B is formed on the first layer 22A, the deposition process can be repeated to form the remaining layers in the multilayer stack 22 until the top layer required to form the multilayer stack 22 is formed. In some embodiments, the thicknesses of the first layers 22A and the second layers 22B may be the same or similar to each other. The thicknesses of the first layers 22A and the second layers 22B may be the same or different. In some embodiments, the first layer 22A is removed in a subsequent process, so the first layer 22A can be considered a sacrificial layer. In other embodiments, the second layer 22B is removed in a subsequent process, so the second layer 22B is a sacrificial layer.

[0020] In some embodiments, pad oxide layers and hard mask layers (not shown) may be formed on the multilayer stack 22. These layers are patterned for subsequent patterning processes of the multilayer stack 22.

[0021] As shown in Figure 2, an etching process patterns a portion of the multilayer stack 22 and the underlying substrate 20 to form a trench 23. This process may be process 204 in the process flow 200 shown in Figure 25. The trench 23 extends into the substrate 20. The retained portion of the multilayer stack 22 can then be considered as a multilayer stack 22'. A portion of the substrate 20 below the multilayer stack 22' can be retained and subsequently considered as a substrate strip 20'. The multilayer stack 22' includes a first layer 22A and a second layer 22B. The first layer 22A can be referred to as a sacrificial layer, and the second layer 22B can be referred to as a nanostructure. The portion of the multilayer stack 22' and the underlying substrate strip 20' can together be considered as a semiconductor strip 24.

[0022] In the above embodiments, the fully wound gate transistor structure can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the structure, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography with a self-aligned process, resulting in a smaller pattern pitch than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A self-aligned process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fully wound gate structure.

[0023] As shown in Figure 3, an isolation region 26 is formed, which can also be considered as a shallow trench isolation region. A specific process may be process 206 in process flow 200 shown in Figure 25. The shallow trench isolation region 26 may include a pad oxide (not shown), which may be a thermal oxide obtained from the surface layer of the thermally oxidized substrate 20. The pad oxide may also be a deposited silicon oxide layer, formed by atomic layer deposition, high-density plasma chemical vapor deposition, chemical vapor deposition, or similar methods. The shallow trench isolation region 26 may also include a dielectric material on the pad oxide, wherein the dielectric material may be formed by flowable chemical vapor deposition, spin coating, high-density plasma chemical vapor deposition, or similar methods. A planarization process, such as chemical mechanical polishing or mechanical polishing, can then be performed to flush the upper surface of the dielectric material, with the retained portion of the dielectric material forming the shallow trench isolation region 26.

[0024] Next, the shallow trench isolation region 26 is recessed, so that the top protrusion of the semiconductor strip 24 is higher than the upper surface 26T of the retained portion of the shallow trench isolation region 26, forming a protruding fin 28. The protruding fin 28 includes the top of the multilayer stack 22' and the substrate strip 20'. The method of recessing the shallow trench isolation region 26 can be a dry etching process, which can use nitrogen trifluoride and ammonia as etching gases. Plasma can be generated during the etching process. The etching gas can also include argon. In other embodiments of the invention, the method of recessing the shallow trench isolation region 26 is a wet etching process, which uses etching chemicals that may include hydrofluoric acid.

[0025] Next, as shown in Figure 4, the two device regions 100-NS and 100-NW are used to form nanosheet transistors and nanowire transistors, respectively, and these transistors can also be considered as fully wound gate transistors. The structures formed in device regions 100-NS and 100-NW can share the same fabrication process, including the process shown in Figures 1 to 3. The width W1 of the multilayer stack 22' in device region 100-NS is greater than the width W2 of the multilayer stack 22' in device region 100-NW. In summary, the material thickness in device region 100-NS can be the same as the material thickness of the corresponding structure in device region 100-NW.

[0026] In some embodiments, the width W1 (see Figure 5A-2) may be between about 8 nm and about 30 nm, and may be between about 8 nm and about 13 nm. The width W2 (see Figure 5B-2) may be between about 4 nm and about 6 nm. In some embodiments, the ratio W1 / W2 may be between about 1.5 and about 7.5.

[0027] As shown in Figure 4, the dummy gate stack 30 and the gate spacer 38 are formed on the upper surface and sidewalls of the protruding fin 28. The individual process may be process 208 in the process flow 200 shown in Figure 25. The dummy gate stack 30 may include a dummy gate dielectric layer 32 and a dummy gate 34 located on the dummy gate dielectric layer 32. The dummy gate dielectric layer 32 may be formed by oxidizing the surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as an oxide layer. For example, the dummy gate 34 may be composed of polycrystalline silicon or amorphous silicon, or other materials such as amorphous carbon.

[0028] The dummy gate stack 30 may also each include one or more hard masking layers 36 on the dummy gate 34. The hard masking layer 36 may be composed of silicon nitride, silicon oxide, silicon carbonitride, silicon carbonitride oxide, or multiple layers of the above. The dummy gate stack 30 may extend beyond one or more protruding fins 28 and the shallow trench isolation region 26 between the protruding fins 28. The length direction of the dummy gate stack 30 may also be perpendicular to the length direction of the protruding fins 28. The method of forming the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate layer on the dummy gate dielectric layer, depositing one or more hard masking layers, and then patterning the formed layered structure using a patterning process.

[0029] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. In some embodiments of the present invention, the gate spacer 38 is composed of a dielectric material such as silicon nitride, silicon oxide, silicon carbide, silicon dioxide, silicon carbonitride, silicon oxynitride, silicon carbonitride, or the like, and may have a single-layer structure or a multilayer structure containing multiple dielectric layers. The formation process of the gate spacer 38 may include depositing one or more dielectric layers, followed by an anisotropic etching process on the dielectric layers. The retained portion of the dielectric layer is the gate spacer 38.

[0030] Figures 5A-1 and 5A-2 are cross-sectional views of the structure shown in device region 100-NS of Figure 4, which will form a nanosheet transistor. Figure 5A-1 shows the reference cross-section CL-CL (CL represents the channel length direction) in Figure 4, which cuts through the protruding fin 28. Figure 5A-2 shows the reference cross-section GL-GL (GL represents the gate longitudinal direction) in Figure 4, which is parallel to the gate length direction. In the description, the figures containing the symbols "A-1" or "A-2" correspond to the cross-sections CL-CL and GL-GL of device region 100-NS, respectively. The figures containing the symbols "B-1" or "B-2" correspond to the cross-sections CL-CL and GL-GL of device region 100-NW, respectively.

[0031] As shown in Figures 5A-1, 5A-2, 5B-1, and 5B-2, an etching process is used to recess the protruding fins 28 (Figure 4) that are not directly located below the dummy gate stack 30 and the gate spacer 38, forming a recess 42. A specific process may be process 210 in process flow 200 shown in Figure 25. For example, a dry etching process may be performed using hexafluoroethane, carbon tetrafluoride, sulfur dioxide, a mixture of hydrogen bromide and chlorine and oxygen, a mixture of hydrogen bromide and chlorine and oxygen and difluoromethane, or similar substances to etch the multilayer stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with or below the multilayer stack 22'. The etching may be anisotropic, so the sidewalls of the multilayer stack 22' facing the recess 42 are vertical and flat.

[0032] Figure 4 shows the X-axis, Y-axis, and Z-axis, and subsequent diagrams will also show the X-axis, Y-axis, and Z-axis to ensure the structural orientation is clear.

[0033] As shown in Figures 6A-1 and 6A-2, a hard mask layer 39 is formed in the device region 100-NS. A specific process may be process 212 in process flow 200 shown in Figure 25. In some embodiments, the hard mask layer 39 is deposited as a blanket layer, and the deposition method may employ compliant deposition processes such as atomic layer deposition, chemical vapor deposition, or similar processes. A patterning process is then performed to remove portions of the hard mask layer 39 in the device region 100-NW, leaving the hard mask layer 39 in the device region 100-NS. The hard mask layer 39 may be composed of alumina, titanium oxide, titanium nitride, or the like, and may be a low-dielectric-constant dielectric material such as silicon carbonitride.

[0034] Next, the sacrificial semiconductor layer, such as the first layer 22A, in the device region 100-NW is removed using an isotropic etching process to obtain the structure shown in Figures 6B-1 and 6B-2. The individual process can be process 214 in process flow 200 shown in Figure 25. Etching is performed via recess 42. The space left after removing the sacrificial semiconductor layer, such as the first layer 22A, is the gap 41 between nanostructures, such as the second layer 22B.

[0035] The sacrificial semiconductor layer, such as the first layer 22A, can be etched using either a dry etching process or a wet etching process. The etchant used has a higher selectivity for the material of the sacrificial semiconductor layer, such as the first layer 22A (e.g., silicon-germanium) than for the material of the nanostructure, such as the second layer 22B, and the substrate 20 (e.g., silicon). For example, in one embodiment, if the sacrificial semiconductor layer, such as the first layer 22A, is composed of silicon-germanium and the nanostructure, such as the second layer 22B, is composed of silicon, a wet etching process can be performed using an etchant such as hydrogen chloride. Wet etching processes can be performed using immersion processes, spray processes, spin coating processes, or similar processes.

[0036] As shown in Figures 7B-1 and 7B-2, an epitaxial semiconductor layer 44 is grown on the exposed semiconductor material via a selective epitaxial process. A specific process may be process 216 in process flow 200 shown in Figure 25. In summary, the semiconductor layer 44 is formed on a nanostructure such as the second layer 22B. The material of the semiconductor layer 44 may be the same as or different from the material of the nanostructure such as the second layer 22B. In summary, the semiconductor layer 44 may or may not be different from the nanostructure such as the second layer 22B. The thickness of the semiconductor layer 44 can be controlled, but it cannot be too thick or too thin. If the semiconductor layer 44 is too thick, there is a risk that adjacent channels will contact each other. If the semiconductor layer 44 is too thin, the subsequently formed displacement gate stack may extend between adjacent semiconductor layers 44, resulting in increased parasitic capacitance. The thickness of the semiconductor layer 44 can be between approximately 1.5 nm and approximately 3.5 nm.

[0037] In some embodiments, semiconductor layer 44 is a silicon layer and contains no or substantially no germanium therein, for example, germanium atomic percentage is less than about 1%. Semiconductor layer 44 may also include germanium, for example, germanium atomic percentage is between 0% and 100%. In the structure shown in FIG7B-2, semiconductor layer 44 is formed on the upper and lower surfaces of the semiconductor nanostructure facing gap 41.

[0038] Epitaxy is selective, and the semiconductor layer 44 is not formed on the exposed dielectric material, which contains gate spacers 38 and a hard mask layer 36. Etching gases such as hydrogen chloride can be added to the precursor gas used in epitaxy to achieve the above effect. A back-etch process can also be performed after deposition for selective deposition. The deposition and back-etch process can also include multiple repeated deposition and back-etch cycles. An etching gas such as hydrogen chloride can also be used for the back-etch process. In summary, the semiconductor layer 44 is not grown on the hard mask layer 39, and the structure of the device region 100-NS during and after epitaxy can be the same as the structures shown in Figures 6A-1 and 6A-2.

[0039] As shown in some embodiments of Figures 8A-1, 8A-2, 8B-1, and 8B-2, a dielectric layer 46 is deposited. Individual processes may include process 218 in process flow 200 shown in Figure 25. The dielectric layer 46 may include silicon oxide, silicon carbide, silicon carbonitride, or the like. Formation processes may include compliant deposition processes such as atomic layer deposition, chemical vapor deposition, or similar processes.

[0040] As shown in Figures 8A-1 and 8A-2, the dielectric layer 46 in the device region 100-NS is compliantly formed on the hard mask layer 36. As shown in Figures 8B-1 and 8B-2, the dielectric layer 46 includes portions filling the recesses / gaps 41 (Figure 7B-1) and also includes portions located on the exposed dielectric layer.

[0041] In subsequent processes, an isotropic etching process is performed to etch the dielectric layer 46. This process may be process 220 in process flow 200 shown in Figure 25. In summary, a portion of the dielectric layer 46 in the device region 100-NS is removed (as shown in Figures 9A-1 and 9A-2), exposing the hard mask layer 39.

[0042] As shown in Figures 9B-1 and 9B-2, in device region 100-NW, the majority or all portions of the dielectric layer 46 in the gap between the semiconductor layer 44 (and the nanostructure such as the second layer 22B) are retained as separate dielectric layers (or can be considered as dielectric layer 46), and portions of the dielectric layer 46 outside the gap are removed. The etching process can be dry etching or wet etching, which can select an etching chemical to etch the dielectric layer 46 without etching the gate spacer 38 and the hard mask layer 36. For example, when the dielectric layer 46 comprises silicon oxide, a mixture of nitrogen trifluoride and ammonia or a mixture of hydrofluoric acid and ammonia can be used for dry etching. When wet etching is used, a hydrofluoric acid solution can be used.

[0043] By controlling the etching process, some portions of the dielectric layer 46 in the gaps between semiconductor layers 44 can be recessed to form a depression. The dashed line 47 in Figure 9B-1 indicates the position of the outer surface of the dielectric layer 46 when the dielectric layer 46 is recessed. The depression of the dielectric layer 46 can be less than, equal to, or greater than the thickness of the sidewall portion of the semiconductor layer 44.

[0044] As shown in Figures 10A-1 and 10A-2, the hard mask layer 39 in device region 100-NS is removed, and the removal method can be a wet etching process or a dry etching process. A specific process can be process 222 in process flow 200 shown in Figure 25. This exposes the sidewalls of the sacrificial layer, such as the first layer 22A, and the nanostructure, such as the second layer 22B. The structure in device region 100-NW is shown in Figures 10B-1 and 10B-2.

[0045] As shown in Figures 11B-1 and 11B-2, a protective layer 51 is formed. The formation process may include depositing the protective layer 51 into device regions 100-NS and 100-NW, and removing a portion of the protective layer 51 in device region 100-NS to retain a portion of the protective layer 51 in device region 100-NW. A specific process may be process 224 in process flow 200 shown in Figure 25. In some embodiments, the protective layer 51 may be composed of silicon nitride or other materials that differ from the exposed materials of the structures shown in Figures 11A-1 and 11A-2. The upper surface of the protective layer 51 may have a height difference between the top surface of the nanostructure, such as the second layer 22B, and this height difference is between approximately 5 nm and approximately 10 nm. If the height difference is too large, subsequent processes may find it difficult to remove the protective layer 51.

[0046] After forming the protective layer 51 to protect the device region 100-NW, an inner spacer 50-NS can be formed, as shown in Figures 11A-1 and 11A-2. An individual process may be process 226 in the process flow 200 shown in Figure 25. In some embodiments, the sacrificial layer in the device region 100-NS, such as the first layer 22A, is recessed to form a lateral recess, for example, using an isotropic etching process such as a dry etching process or a wet etching process. An individual process may be process 228 in the process flow 200 shown in Figure 25.

[0047] The method for laterally recessing the sacrificial semiconductor layer, such as the first layer 22A, can employ an etchant with greater selectivity for the material of the sacrificial semiconductor layer, such as the first layer 22A (e.g., silicon-germanium), than for the material of the nanostructure, such as the second layer 22B, and the substrate 20 (e.g., silicon), to perform a wet etching process. For example, when the sacrificial semiconductor layer, such as the first layer 22A, is composed of silicon-germanium and the nanostructure, such as the second layer 22B, is composed of silicon, an etchant such as hydrogen chloride can be used for a wet etching process. Wet cleaning processes can be performed using immersion processes, spray processes, spin coating processes, or similar processes.

[0048] Next, an inner spacer 50-NS is formed. In some embodiments, the method of forming the inner spacer 50-NS includes depositing a compliant dielectric layer that extends into the lateral recess. An etching process (which can also be considered a spacer trimming process) is then performed to trim portions of the spacer layer outside the lateral recess, leaving portions of the spacer layer within the lateral recess. The retained portions of the spacer layer can be considered the inner spacer 50-NS. The protective layer 51 is then removed. In some embodiments, when the inner spacer 50-NS is formed in the device region 100-NS, no inner spacer is formed in the device region 100-NW.

[0049] After removing the protective layer 51, a cleaning process is performed to prepare the structure for epitaxy. This cleaning process is designed to remove oxides from the subsequent channel regions. Alternatively, the outer portion of the semiconductor layer 44 on the nanostructure, such as the second layer 22B (see Figure 11B-1), can be removed or recessed. For example, hydrofluoric acid gas can be used for the cleaning process. During the cleaning process, the dielectric layer 46 can be slightly recessed, for example, by about 1 nm to about 2 nm. The final structure in the device region 100-NW is shown in Figures 12B-1 and 12B-2.

[0050] During the cleaning process, the structure in the device area 100-NS is as shown in Figures 12A-1 and 12A-2, and the structure is basically the same as that shown in Figures 11A-1 and 11A-2.

[0051] Figures 13A-1 and 13A-2 show the method of forming source / drain regions 48-NS in device region 100-NS, while Figures 13B-1 and 13B-2 show the method of forming source / drain regions 48-NW in device region 100-NW. The source / drain regions can be considered individually or together as sources or drains, depending on the context. An individual process may be process 230 in process flow 200 shown in Figure 25.

[0052] When the source / drain regions 48-NS and 48-NW are n-type regions, they may include silicon or silicon carbide and n-type dopants such as arsenic, phosphorus, antimony, the like, or combinations thereof. For example, the n-type source / drain regions 48-NS and 48-NW may include silicon arsenide, silicon phosphide, silicon carbide phosphide, silicon arsenide phosphide, silicon antimonyide, or the like. When the source / drain regions 48-NS and 48-NW are p-type regions, they may include silicon, silicon germanium, or germanium, and further include p-type dopants such as boron, indium, or combinations thereof. For example, the p-type semiconductor layer such as the source / drain regions 48-NS and 48-NW may include silicon germanium boride, germanium boride, or the like.

[0053] The source / drain regions 48-NS and 48-NW can be formed using an epitaxial process. Furthermore, when the source / drain regions 48-NS and 48-NW have the same conductivity type, they can be grown by epitaxially using the same process. In some embodiments, the source / drain regions 48-NS and 48-NW may include multiple sublayers such as sublayers L0, L1, L2, and the like, and different sublayers may have different compositions. For example, the concentration of n-type or p-type dopant (depending on the conductivity type) in sublayer L0 is lower than the concentration of n-type or p-type dopant in sublayer L1.

[0054] As shown in Figures 13B-1 and 13B-2, the source / drain region 48-NW may contact the dielectric layer 46 to form an interface. In some embodiments, the interface may be recessed and may overlap with the upper nanostructure such as the second layer 22B and / or with the lower nanostructure such as the second layer 22B. In summary, the source / drain region 48-NW (such as sublayer L0) may extend slightly between the upper and lower semiconductor layers 44. The source / drain region 48-NW may extend into the region 54 shown in Figure 13B-1. The extension distance may be equal to, slightly greater than, or slightly less than the lateral distance of the inner spacer 50-NS (Figure 13A-1). In other embodiments, the interface between the source / drain region 48-NW and the dielectric layer 46 may be perpendicularly aligned with the outer edge of the nanostructure such as the second layer 22B.

[0055] In some embodiments, the semiconductor layer 44 and the nanostructure, such as the second layer 22B, can together serve as the channel region of the final transistor in the device region 100-NW, and can be considered together as the nanostructure (or channel region) 22B'. Due to the skin effect, the current density in the semiconductor layer 44 and the nanostructure, such as the second layer 22B, is relatively high. Forming a germanium-containing semiconductor layer 44 is beneficial for conducting higher currents.

[0056] As shown in Figures 14A-1, 14A-2, 14B-1, and 14B-2, a contact etch stop layer 66 and an interlayer dielectric layer 68 are formed. Individual processes may include process 232 in process flow 200 shown in Figure 25. The contact etch stop layer 66 may be composed of silicon oxide, silicon nitride, silicon carbonitride, or similar materials, and its formation method may employ chemical vapor deposition, atomic layer deposition, or similar methods. The interlayer dielectric layer may include a dielectric material, and its formation method may employ flowable chemical vapor deposition, spin coating, chemical vapor deposition, or any other suitable deposition method. The interlayer dielectric layer 68 may be composed of an oxygen-containing dielectric material, which may be silicon oxide, phospholipid glass, borosilicate glass, borosilicate glass, undoped silicate glass, or similar materials.

[0057] A planarization process, such as chemical mechanical polishing or mechanical polishing, is performed to flush the upper surface of the interlayer dielectric layer 68. In some embodiments, the planarization process may remove the hard masking layer 36 to expose the dummy gate 34 (or stop at the hard masking layer 36). In some embodiments, the dummy gate 34 (or hard masking layer 36, see Figures 13A-1, 13A-2, 13B-1, and 13B-2), gate spacer 38, and interlayer dielectric layer 68 are flush after the planarization process (in process variables).

[0058] Next, the dummy gate 34 (and hard mask layer 36, if present) and the dummy gate dielectric layer 32 in the device region 100-NS are removed by one or more etching processes to form a recess. In the device region 100-NS, the recesses each expose a portion of the multilayer stack 22' and / or lie on top of a portion of the multilayer stack 22' (as shown in Figures 13A-1 and 13A-2), and the portion of the multilayer stack 22' includes the channel region in the subsequently completed nanostructure field-effect transistor. The individual process may be process 234 in the process flow 200 shown in Figure 25. The portion of the multilayer stack 22' that serves as the channel region is located between adjacent pairs of epitaxial source / drain regions 48-NS.

[0059] Next, the sacrificial layer, such as the first layer 22A, is etched away, causing the recess to extend downward between the nanostructures, such as the second layer 22B. As shown in Figure 13A-2, after removing the dummy gate dielectric layer 32 and the dummy gate 34, the sidewall of the sacrificial layer, such as the first layer 22A, can be exposed, and therefore the sacrificial layer, such as the first layer 22A, can be removed.

[0060] In device region 100-NW, the dummy gate stack 30 shown in Figures 13B-1 and 13B-2 is also removed. The sidewalls of dielectric layer 46 and semiconductor layer 44 are exposed. Semiconductor layer 44 may or may not be slightly recessed, and semiconductor layer 44 may not be removed due to its thin material and thickness.

[0061] Next, a displacement gate stack is formed, as shown in Figures 14A-1, 14A-2, 14B-1, and 14B-2. Individual processes may include process 236 in process flow 200 shown in Figure 25. As shown in Figures 14A-1 and 14A-2, a dielectric layer 60 containing an interface layer and a high-dielectric-constant dielectric layer (not shown) can be formed, extending into the recess formed by removing the dummy gate stack 30 and the sacrificial layer such as the first layer 22A. In some embodiments, the interface layer is composed of silicon oxide, which can be formed by an oxidation process or a deposition process. The high-dielectric-constant dielectric layer can be deposited compliantly, for example via compliant deposition processes such as atomic layer deposition, chemical vapor deposition, or similar processes. The dielectric layer with a high dielectric constant may be composed of or include a dielectric material with a high dielectric constant greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

[0062] Gate 62 is deposited on a dielectric layer with a high dielectric constant. Gate 62 may include metallic materials such as titanium nitride, tantalum nitride, titanium aluminum, titanium aluminum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. The material may be related to whether the final nanosheet transistor is a p-type or n-type transistor, and the work function layer of gate 62 may be selected to have the corresponding p-type or n-type work function. Thus, a nanosheet transistor 70-NS is formed, which has a sheet width W1' (Figure 14A-2). The width W1' is approximately the width W1 shown in Figures 4 and 5A-2 (e.g., the difference is less than 20%).

[0063] As shown in Figures 14B-1 and 14B, a displacement gate stack 64-NW is also formed. The displacement gate stacks 64-NW and 64-NW can share common fabrication processes, such as removing the dummy gate stack and depositing and planarizing the displacement gate dielectric layer and the displacement gate.

[0064] Unlike the substitution gate stack 64-NS in device region 100-NS, because the sacrificial layer such as the first layer 22A has been removed during the process and replaced with the dielectric layer 46 and the semiconductor layer 44, the recess does not extend significantly between the nanostructures such as the second layer 22B.

[0065] In some embodiments where the semiconductor layer 44 is composed of silicon or low germanium atomic percent silicon-germanium, the semiconductor layer 44 is not etched (together with nanostructures such as the second layer 22B). When the semiconductor layer 44 is composed of germanium or high germanium atomic percent silicon-germanium, the semiconductor layer 44 can be slightly laterally recessed due to its thin thickness.

[0066] As shown in Figures 14B-1 and 14B-2, the substitution gate stack 64-NW does not contain portions that separate the nanostructures such as the second layer 22B from each other. Instead, the nanostructures such as the second layer 22B, the dielectric layer 46, and the semiconductor layer 44 together form protruding fins, and the substitution gate stack 64-NW is formed on the sidewalls and top of the protruding fins. Thus, a nanowire transistor 70-NW is formed, whose sheet width W2' (Figure 14B-2) is approximately the same as the width W1 shown in Figures 4 and 5B-2 (e.g., the difference is less than 20%). The channel region of the nanowire transistor 70-NW includes the nanostructure 22B', which includes the nanostructures such as the second layer 22B and the semiconductor layer 44.

[0067] Figures 15-1, 15-2, 15B-1, and 15B-2 to Figures 17A-1, 17A-2, 17B-1, and 18B-2 represent other embodiments of methods for forming the sheet transistor 70-NS and the wire transistor 70-NW. The sheet transistor 70-NS and the wire transistor 70-NW in these embodiments are substantially the same as those in Figures 14A-1, 14B-1, 14A-2, and 14B-2, except that additional inner spacers 50-NW are formed in the wire transistor 70-NW in Figures 17B-1 and 17B-2, while no inner spacers are formed in the wire transistor 70-NW in Figures 14B-1 and 14B-2. Unless otherwise stated, the reference numerals in these embodiments denote similar units in the embodiments shown in Figures 1 to 14A-1, 14A-2, 14B-1, and 14B-2.

[0068] The initial steps of this embodiment are substantially the same as those shown in Figures 1 to 10A-1, 10A-2, 10B-1, and 10B-2. Next, the processes shown in Figures 15A-1, 15A-2, 15B-1, and 15B-2 are performed. A protective layer 51' is formed in device regions 100-NS and 100NW. Then, the protective layer 51' is removed from device region 100-NW, leaving it in device region 100-NS. Next, the dielectric layer 46 (Figures 15B-1 and 15B-2) is recessed, and the dielectric material is filled into the recess to form the inner spacer 50-NW, as shown in Figure 15B-1. Then, the protective layer 51' is removed.

[0069] Next, the processes shown in Figures 16A-1, 16A-2, 16B-1, and 16B-2 are performed to form the inner spacer 50-NS in the device region 100-NS. A protective layer 51" is formed in the device regions 100-NS and 100-NW, and then the protective layer 51" is removed from the device region 100-NS while retaining the protective layer 51" in the device region 100-NW. Next, the sacrificial layer is recessed as in the first layer 22A, and then the dielectric material is filled into the recess to form the inner spacer 50-NS, as shown in Figure 16A-1. Then, the protective layer 51" is removed. It should be understood that the process sequence for forming the inner spacers 50-NW and 50-NS can be interchanged.

[0070] Next, the processes shown in Figures 12B-1 and 12B-2 (optional) are performed up to Figures 14A-1, 14A-2, 14B-1, and 14B-2. Figures 17A-1, 17A-2, 17B-1, and 17B-2 are the final structures, which are essentially the same as those shown in Figures 14A-1, 14A-2, 14B-1, and 14B-2, except for the formation of the inner spacer 50-NW.

[0071] In Figures 14A-2 and 17A-2, the width W1' of the sheet can be greater than about 8 nm and less than about 80 nm, while the space between adjacent nanostructures, such as the second layer 22B, can be between about 8 nm and about 10 nm. The thickness H1 of the nanostructure, such as the second layer 22B, can be between about 4 nm and about 7 nm. The width W1' is greater than the thickness H1, and the ratio W1' / H1 can be between about 1.6 and about 16. If the ratio W1' / H1 is too high, it is difficult to form a gap between the structure and the filled nanosheet. If the ratio W1' / H1 is too small, the current is not large enough.

[0072] In Figures 14-B2 and 17-B2, the width W2' of the sheet can be between approximately 4 nm and approximately 6 nm, while the space between adjacent nanostructures, such as the second layer 22B, can be between approximately 3 nm and approximately 5 nm. The thickness H2 of the nanostructure 22B' can be between approximately 9 nm and approximately 11 nm. The width W2' is closer to and can be smaller than the thickness H2, while the ratio W2' / H2 can be between approximately 0.3 and approximately 0.7. If the ratio W2' / H2 is too high, the displacement gate stack may extend between the nanostructures, such as the second layer 22B. If the ratio W2' / H2 is too low, the current will not be large enough.

[0073] Figures 18 to 22 are top views of some nanosheets and nanowires that can be used to form the aforementioned nanosheet transistors and nanowire transistors. Figures 18 and 19 are top views of nanowires (such as second layer 22B or nanostructure 22B') and nanosheets such as second layer 22B, respectively. Using a hybrid of nanosheet transistors and nanowire transistors can reduce the wafer area used without sacrificing circuit performance. For example, the nanowires such as second layer 22B / nanostructure 22B' shown in Figure 20 are used to form three nanowire transistors (assuming two nanosheets such as second layer 22B / nanostructure 22B' form one nanowire transistor), occupying the same wafer area as two nanosheet transistors (assuming two nanosheets such as second layer 22B form one nanosheet transistor). When no drive current is required, nanowire transistors can be used to reduce the wafer area used. The nanosheet transistors and nanowire transistors shown in Figure 21 can be aligned in the same row.

[0074] Nanosheet transistors have higher drive current but occupy more wafer area. Nanowire transistors use less wafer area but have lower drive current. A hybrid of nanosheet and nanowire transistors can be used to meet customized needs. For example, the static random access memory (SRAM) cell 74 shown in Figure 22 includes pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and bypass transistors PG-1 and PG-2. In some embodiments, when a high-density circuit is required, all transistors in the SRAM cell 74 can be formed as nanowire transistors 70-NW because current requirements do not need to be considered. Compared to SRAM composed of nanosheet transistors, the transistor density in these examples of SRAM can be improved by more than 15%.

[0075] Nanoscale transistors in the same device die (and the same wafer) can have different channel widths, and therefore can have different drive currents to meet customized circuit requirements. For example, the nanoscale transistors 70'-NS in device region 100'-NS shown in FIG. 23 have a channel width W1", while the nanoscale transistors 70"-NS in device region 100"-NS have a channel width W1"'. In some embodiments, the channel width W1" is smaller than the channel width W1' (FIG. 17A-2), while the channel width W1"' is larger than the channel width W1'.

[0076] The nanowire transistors 70'-NW in the device region 100'-NW shown in Figure 24 have a channel width W2", while the nanowire transistors 70"-NW in the device region 100"-NW have a channel width W2"'. In some embodiments, the channel width W2" is smaller than the channel width W2' (Figure 17B-2), while the channel width W2"' is larger than the channel width W2'. Transistors with larger channel widths can have higher drive currents.

[0077] In other embodiments, when the circuit requires a high current, pull-down transistors PD-1 and PD-2 can be formed as nanosheet transistors to meet the high current requirements of the pull-down transistors. On the other hand, pull-up transistors PU-1 and PU-2 and bypass transistors PG-1 and PG-2 do not require high current, so pull-up transistors PU-1 and PU-2 and bypass transistors PG-1 and PG-2 are formed as nanowire transistors. In these examples, the transistor density in static random access memory can be improved by more than 5% compared to circuits formed by nanosheet transistors, while still meeting or exceeding the circuit performance requirements.

[0078] Furthermore, the gate stack of the nanowire transistor does not extend between the channels, reducing the parasitic capacitance between the source / drain regions and the gate stack, and improving the AC gain. Since epitaxy can thicken the nanowires, it also improves stress.

[0079] The embodiments of the present invention have several advantages. By forming a hybrid device containing both wafer transistors and wire transistors, the wafer area used can be reduced and the device density increased without sacrificing circuit performance. The wafer transistors and wire transistors can share a common fabrication process, thus reducing manufacturing costs.

[0080] In some embodiments of the present invention, a method for forming a semiconductor structure includes patterning and stacking a plurality of layers to form a first multilayer stack and a second multilayer stack, each of the first multilayer stack and the second multilayer stack including a plurality of interleaved sacrificial layers and a plurality of nanostructures, wherein the second multilayer stack is wider than the first multilayer stack; forming a nanosheet transistor based on the first multilayer stack, wherein the nanosheet transistor includes a plurality of first channel regions having a first width; and a first gate stack located on the first channel regions; forming a nanowire transistor based on the second multilayer stack, wherein the nanowire transistor includes a plurality of second channel regions, and the second channel regions are narrower than the first channel regions; and a second gate stack located on the second channel regions.

[0081] In one embodiment, the step of forming a nanowire crystal includes removing a sacrificial layer in a second multilayer stack to leave a gap; and epitaxially growing a plurality of semiconductor layers in the gap. In one embodiment, the step of forming a nanowire crystal further includes, after growing semiconductor layers in the gap, filling the gap with a plurality of dielectric layers, wherein one of the dielectric layers physically contacts one of the dielectric layers above it and one of the dielectric layers below it. In one embodiment, the step of epitaxially growing semiconductor layers includes growing a plurality of silicon layers.

[0082] In one embodiment, the step of epitaxially growing a semiconductor layer includes growing a plurality of germanium-containing layers. In one embodiment, the step of forming a nanosheet transistor includes removing a sacrificial layer in a first multilayer stack; and forming a first gate stack, wherein the first gate stack includes a plurality of portions located between nanostructures in the first multilayer stack. In one embodiment, the height of a first channel region of the nanosheet transistor is less than the height of a second channel region of the nanowire transistor. In one embodiment, the method further includes forming a plurality of first inner spacers for the nanosheet transistor, wherein the first gate stack includes a plurality of portions located in regions between the first inner spacers, and the nanowire transistor does not have any inner spacers.

[0083] In one embodiment, the method further includes forming a plurality of first inner spacers for forming a sheet transistor, wherein a first gate stack includes a plurality of regions partially located between the first inner spacers; and forming a plurality of second inner spacers for forming a wire transistor, wherein a dielectric layer is located between the second inner spacers. In one embodiment, the method further includes forming a static random access memory (SRAM) cell, wherein the sheet transistor is a pull-down transistor of the SRAM cell, and the wire transistor is a pull-up transistor of the SRAM cell.

[0084] In some embodiments of the present invention, the semiconductor structure includes a substrate semiconductor substrate; a nanoplate transistor located on the substrate semiconductor substrate, wherein the nanoplate transistor includes a plurality of first channel regions, wherein an upper first channel region overlaps with a lower first channel region; a first gate stack located on the first channel regions; and a nanowire transistor located on the substrate semiconductor substrate, wherein the nanowire transistor includes a plurality of second channel regions narrower than the first channel regions, wherein an upper second channel region overlaps with a lower second channel region; and a second gate stack located on the second channel regions.

[0085] In one embodiment, the first channel region has a first thickness, and the second channel region has a second thickness, wherein the second thickness is greater than the first thickness. In one embodiment, the first channel region includes a first semiconductor material; and one of the second channel regions includes a first layer including the first semiconductor material; and a second layer including a second semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In one embodiment, the first channel region and the second channel region include the same semiconductor material.

[0086] In one embodiment, the first gate stack includes a plurality of intermediate portions located between adjacent first channel regions; and the second gate stack includes a plurality of dielectric layers located between adjacent second channel regions. In one embodiment, the nanosheet transistor includes a plurality of first inner spacers, and the first inner spacers contact first opposing sidewalls of the intermediate portions of the first gate stack; and the nanowire transistor includes a plurality of second inner spacers, and the second inner spacers contact second opposing sidewalls of the dielectric layers. In one embodiment, the semiconductor structure further includes a static random access memory cell, which includes a nanosheet transistor as a pull-down transistor; and a nanowire transistor as a pull-up transistor.

[0087] In some embodiments of the present invention, the semiconductor structure includes a nanowire transistor, including a protrusion structure, including a plurality of channel regions; and a plurality of dielectric regions located between the channel regions; a first source / drain region and a second source / drain region located on both sides of the channel regions and the dielectric regions and bonded to the channel regions and the dielectric regions; and a gate stack located on the protrusion structure. In one embodiment, the dielectric region includes a dielectric layer; and a plurality of inner spacers located on both sides of the dielectric layer and contacting the dielectric layer. In one embodiment, the channel region includes a plurality of first semiconductor layers including a first semiconductor material; and a plurality of second semiconductor layers including a second semiconductor material, wherein the second semiconductor material is different from the first semiconductor material, and the second semiconductor layers are located on the first semiconductor layers.

[0088] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

[0089] CL-CL, GL-GL: Section H1, H2: Thickness L0, L1, L2: Sub-layers PD-1, PD-2: Pull-down transistors PG-1, PG-2: Through-gate transistors PU-1, PU-2: Pull-up transistors W1,W1',W1",W1"',W2,W2',W2",W2"': Width 10: Wafer 20:Substrate 20': Substrate strip 22,22': Multi-layer stacking 22A: First Floor 22B: Second Floor 22B': Nanostructure 23: Trench 24: Semiconductor Strip 26: Quarantine Zone 26T: Upper surface 28: Protruding fin-like structures 30: Virtual gate stacking 32: Virtual gate dielectric layer 34: Virtual gate 36, 39: Hard mask layer 38: Gate spacer 41: Gap 42: Depression 44: Semiconductor layer 46, 60: Dielectric layer 47: Dashed line 48-NS, 48-NW: Source / Drain Region 50-NS, 50-NW: Inner spacer 51,51',51": Protective layer 54: Area 62: Gate 64-NS, 64-NW: Replacement gate stack 66: Contact Etching Stop Layer 68: Interlayer dielectric layer 70-NS, 70'-NS, 70"-NS: Nanoparticle transistors 70-NW, 70'-NW, 70"-NW: Nanowire Transistor 74: Static Random Access Memory (SRAM) unit 100-NS,100'-NS,100"-NS,100-NW,100'-NW,100"-NW: Device area 200: Manufacturing Process 202,204,206,208,210,212,214,216,218,220,222,224, 226,228,230,232,234,236: Manufacturing Process

Claims

1. A method for forming a semiconductor structure, comprising: A patterned stack of multiple layers forms a first multilayer stack and a second multilayer stack, each including multiple interleaved sacrificial layers and multiple nanostructures, wherein the first multilayer stack is wider than the second multilayer stack; a nanosheet transistor is formed based on the first multilayer stack, wherein the nanosheet transistor includes: multiple first channel regions having a first width; and a first gate stack located on the first channel regions; and a nanowire transistor is formed based on the second multilayer stack, wherein the nanowire transistor includes: multiple second channel regions, and the second channel regions are narrower than the first channel regions; multiple dielectric layers located between the second channel regions; and a second gate stack located on the second channel regions, wherein in a cross-section perpendicular to the longitudinal direction of the second gate stack, the dielectric layers are spaced apart from the second gate stack.

2. The method for forming a semiconductor structure as described in claim 1, wherein the step of forming the nanowire transistor includes: Remove these sacrificial layers from the second multilayer stack, leaving multiple gaps; And epitaxial growth of multiple semiconductor layers in these gaps.

3. The method for forming a semiconductor structure as described in claim 2, wherein the step of forming the nanowire transistor further includes: After the semiconductor layers are grown in the gaps, the dielectric layers are filled into the gaps, wherein one of the dielectric layers is in physical contact with one of the semiconductor layers above it and one of the semiconductor layers below it.

4. The method for forming a semiconductor structure as described in claim 2, wherein the step of epitaxially growing the semiconductor layers includes growing a plurality of silicon layers.

5. A semiconductor structure, comprising: A substrate semiconductor substrate; A nanosheet transistor is located on the substrate semiconductor substrate, wherein the nanosheet transistor includes: a plurality of first channel regions, wherein upper first channel regions overlap with lower first channel regions; and a first gate stack located on the first channel regions; and a nanowire transistor is located on the substrate semiconductor substrate, wherein the nanowire transistor includes: a plurality of second channel regions narrower than the first channel regions, wherein upper second channel regions overlap with lower second channel regions; a plurality of dielectric regions located between the second channel regions; and a second gate stack located on the second channel regions, wherein in a cross-section perpendicular to the longitudinal direction of the second gate stack, the dielectric regions are separated from the second gate stack.

6. The semiconductor structure as claimed in claim 5, wherein the first channel regions have a first thickness, the second channel regions have a second thickness, and the second thickness is greater than the first thickness.

7. The semiconductor structure as described in claim 5 or 6, wherein: The first channel regions include a first semiconductor material; and one of the second channel regions includes: a first layer including the first semiconductor material; and a second layer including a second semiconductor material, wherein the second semiconductor material is different from the first semiconductor material.

8. A semiconductor structure, comprising: A nanowire transistor includes: a protrusion structure including: a plurality of channel regions; and a plurality of dielectric regions located between the channel regions; a first source / drain region and a second source / drain region located on both sides of the channel regions and the dielectric regions and bonded to the channel regions and the dielectric regions; and a gate stack located on the protrusion structure, wherein in a cross-section perpendicular to the longitudinal direction of the gate stack, the dielectric regions are spaced apart from the gate stack.

9. The semiconductor structure as described in claim 8, wherein the dielectric regions include: Multiple dielectric layers; And multiple inner spacers, located on both sides of the dielectric layers and in contact with the dielectric layers.

10. The semiconductor structure as described in claim 8 or 9, wherein the channel regions include: Multiple first semiconductor layers, including a first semiconductor material; And a plurality of second semiconductor layers, including a second semiconductor material, wherein the second semiconductor material is different from the first semiconductor material, wherein the second semiconductor layers are located on the first semiconductor layers.

Images