Storage device and method for operating the same

Abstract

A storage device includes an array of latching cells and a plurality of inter-cell transfer switches. Each pair of adjacent latching cells is coupled together via an inter-cell transfer switch. Each latching cell includes a first inverter and a first transfer switch connected in series between a first bit node and a second bit node, and a second inverter and a second transfer switch connected in series between a second bit node and a first bit node. The first inverter has an input for receiving voltage from the first bit node directly or through the first transfer switch. The second inverter has an input for receiving voltage from the second bit node directly or through the second transfer switch.

Description

Technical Field

[0001] none Prior Technology

[0002] Recent trends in integrated circuit (IC) miniaturization have resulted in smaller devices that consume less power but offer more functionality at higher speeds. This miniaturization process also leads to more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for ICs, while ensuring compliance with standard cell layout design and manufacturing specifications. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a circuit diagram of a storage device having an array of latching units according to some embodiments. Figures 2A to 2D are circuit diagrams of latching units implemented in various configurations according to some embodiments. Figures 3A to 3C are three circuit diagrams of a storage device operating in one of three operating modes according to some embodiments. Figure 4 is a circuit diagram of a storage device having an array of latching units according to some embodiments. Figures 5A to 5B are circuit diagrams of a storage device according to some embodiments, the storage device having a state change after a long pulse operation of forward shift. Figures 6A to 6B, 7A to 7B, 8A to 8B, and 9A to 9B are circuit diagrams of a storage device according to some embodiments, the storage device having a state change after a short pulse operation of backward shift. Figure 10 is a schematic diagram of the process of repeatedly applying short pulse operations to a storage device according to some embodiments. Figure 11 is a timing diagram illustrating the process of applying various backward shift short-pulse operations and forward shift long-pulse operations to a storage device according to some embodiments. Figures 12A to 12B, 13A to 13B, 14A to 14B, and 15A to 15B are circuit diagrams of a storage device according to some embodiments, the storage device having a state change after a forward shift short pulse operation. Figure 16 is a table of various encoding schemes for encoding the state of a storage device having latching units, according to some embodiments. Figure 17 is a table of various encoding schemes for encoding the state of a storage device having latching units, according to some embodiments. Figure 18 is a circuit diagram of a storage device having an array of latching units according to some embodiments. Figures 19A to 19C are circuit diagrams of an example implementation of a latching unit used in a storage device. Figure 20 is a schematic diagram of a row of storage cells according to some embodiments. Figure 21A is a schematic diagram of a row of three storage units according to some embodiments, each storage unit having a storage device. Figure 21B is a table that maps the combination of states of three storage units to coded numbers written in decimal values, according to some embodiments. Figure 22 is a schematic diagram of a multi-column storage unit and an instance column controller for the first column according to some embodiments. Figures 23A to 23B are tables of matrices to be added together according to some embodiments. Figure 24 is a flowchart of a method of operating a storage device according to some embodiments. Figure 25 is a flowchart of a method of operating a storage device according to some embodiments. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific instances of components, values, operations, materials, configurations, or the like are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, configurations, or the like are contemplated. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly.

[0007] In some embodiments, the storage device includes an array of latch cells and a plurality of inter-cell transfer gates. Each pair of adjacent latch cells is coupled together via an inter-cell transfer gate. Each latch cell includes a first inverter and a first transfer gate connected in series between a first bit node and a second bit node, the first inverter having an input for receiving voltage from the first bit node directly or through the first transfer gate; and a second inverter and a second transfer gate connected in series between a second bit node and a first bit node, the second inverter having an input for receiving voltage from the second bit node directly or through the second transfer gate. Arithmetic operations are performed using a storage device that operates as a finite state machine. State changes of the storage device are controlled based on the timing of various pulses. Parallel arithmetic operations in a multi-column storage device provide increased computational speed compared to column-by-column arithmetic operations.

[0008] Figure 1 is a circuit diagram of a storage device 100 having an array of latching cells 110-140 according to some embodiments. In Figure 1, the storage device 100 includes latching cells 110-140, a PMOS transistor 102, an NMOS transistor 108, and inter-cell transfer switches 112, 123, and 134. Latching cells 110-140 are connected in series between the drain of PMOS transistor 102 and the drain of NMOS transistor 108, and the source of PMOS transistor 102 and the source of NMOS transistor 108 are correspondingly connected to the upper supply voltage VDD and the lower supply voltage VSS. Latching cells 110 and 120 are a pair of adjacent latching cells and are coupled together through inter-cell transfer switch 112. Latching cells 120 and 130 are a pair of adjacent latching cells and are coupled together through inter-cell transfer switch 123. Latch unit 130 and latch unit 140 are a pair of adjacent latch units and are coupled together through inter-unit transfer switch 134.

[0009] Each of latch units 110-140 includes a first inverter INV1 and a first transmission switch S1 connected in series between the first bit node BN1 and the second bit node BN2. Each of latch units 110-140 also includes a second inverter INV2 and a second transmission switch S2 connected in series between the second bit node BN2 and the first bit node BN1. Inter-unit transmission switch 112 connects the second bit node BN2 of latch unit 110 to the first bit node BN1 of latch unit 120. Inter-unit transmission switch 123 connects the second bit node BN2 of latch unit 120 to the first bit node BN1 of latch unit 130. Inter-unit transmission switch 134 connects the second bit node BN2 of latch unit 130 to the first bit node BN1 of latch unit 140.

[0010] In each of the latching units 110-140 in Figure 1, the input of the first inverter INV1 is directly connected to the first bit node BN1, and the input of the second inverter INV2 is directly connected to the second bit node BN2. In some alternative embodiments, the input of the first inverter INV1 is electrically coupled to the first bit node BN1 through a first transmission switch S1, and the first transmission switch S1 is directly connected to the first bit node BN1. In some alternative embodiments, the input of the second inverter INV2 is electrically coupled to the second bit node BN2 through a second transmission switch S2, and the second transmission switch S2 is directly connected to the second bit node BN2.

[0011] In Figure 1, the storage device 100 includes various transfer switches, such as inter-unit transfer switches 112, 123, and 134, a first transfer switch S1, and a second transfer switch S2. Each of the transfer switches can operate in a connected state (i.e., closed state) or an open state (i.e., unopened state). When an inter-unit transfer switch operates in the connected state, its two terminals are electrically connected together (when the switch is closed), but when an inter-unit transfer switch operates in the open state, its two terminals are electrically isolated from each other (when the switch is open).

[0012] Figures 2A to 2D are circuit diagrams of latching units implemented in various configurations according to some embodiments. In the example circuits of Figures 2A to 2D, each of the transfer switches is implemented as a transfer gate, which is formed by a PMOS transistor and an NMOS transistor connected in parallel between the two terminals of the transfer switch. Other implementations of the transfer switches are also within the scope of this disclosure. In the example circuits of Figures 2A to 2C, each of the inverters (such as the first inverter INV1 and the second inverter INV2) is implemented using a PMOS transistor and an NMOS transistor. In each inverter, the gates of the transistors are connected together as the input of the inverter, the drains of the transistors are connected together as the output of the inverter, and the channels of the transistors are connected in series between the upper supply voltage VDD and the lower supply voltage VSS. Other implementations of the inverters are also within the scope of this disclosure.

[0013] In Figure 2A, the input of the first inverter INV1 is directly connected to the first bit node BN1, and the output of the first inverter INV1 is electrically coupled to the second bit node BN2 through the first transfer switch S1. The input of the second inverter INV2 is directly connected to the second bit node BN2, and the output of the second inverter INV2 is electrically coupled to the first bit node BN1 through the second transfer switch S2.

[0014] In Figure 2B, the input of the first inverter INV1 is electrically coupled to the first bit node BN1 through the first transfer switch S1, and the output of the first inverter INV1 is directly connected to the second bit node BN2. The input of the second inverter INV2 is electrically coupled to the second bit node BN2 through the second transfer switch S2, and the output of the second inverter INV2 is directly connected to the first bit node BN1.

[0015] In Figure 2C, the input of the first inverter INV1 is directly connected to the first bit node BN1, and the output of the first inverter INV1 is electrically coupled to the second bit node BN2 through the first transfer switch S1. The input of the second inverter INV2 is electrically coupled to the second bit node BN2 through the second transfer switch S2, and the output of the second inverter INV2 is directly connected to the first bit node BN1.

[0016] In Figure 2D, the input of the first inverter INV1 is electrically coupled to the first bit node BN1 through the first transfer switch S1, and the output of the first inverter INV1 is directly connected to the second bit node BN2. The input of the second inverter INV2 is directly connected to the second bit node BN2, and the output of the second inverter INV2 is electrically coupled to the first bit node BN1 through the second transfer switch S2.

[0017] In Figures 1 and 2A through 2D, each latch unit can operate in three modes: forward-connected mode, backward-connected mode, and latching mode. A storage device having series-coupled latch units can operate in three modes: forward-shift mode, backward-shift mode, and storage mode. Figures 3A through 3C are three circuit diagrams of the storage device 100 of Figure 1 operating in one of the three modes according to some embodiments. Each latch unit in the storage device 100 in Figures 3A through 3C operates correspondingly in forward-connected mode, backward-connected mode, and latching mode.

[0018] A storage device having multiple latch units generally includes a first latch unit, a last latch unit, and remaining latch units connected in series between the first latch unit and the last latch unit. In the example storage device of Figure 1, the first latch unit is latch unit 110, and the last latch unit is latch unit 140. Latch units 120 and 130 are remaining latch units, connected in series between latch unit 110 and latch unit 140.

[0019] In Figure 3A, each of the latching units 110-140 operates in forward connection mode, with the inter-unit transmission switches 112, 123, and 134 set to the connected state. During the operation of setting the latching units to forward connection mode, the first transmission switch S1 of latching units 110-140 is set to the connected state, and the second transmission switch S2 of latching units 110-140 is set to the disconnected state.

[0020] Additionally, the storage device 100 in Figure 3A operates in forward shift mode. During the operation of setting the storage device 100 to forward shift mode, in addition to setting each latch cell (e.g., 110-140) to forward connection mode and setting the inter-cell transfer switches (e.g., 112, 123, and 134) to a connected state, the first bit node BN1 of the first latch cell (e.g., 110) remains at a fixed logic level voltage, and the second bit node BN2 of the last latch cell (e.g., 140) remains floating. In the example implementation of Figure 3A, in response to a logic low voltage applied to the gate of the PMOS transistor 102, the first bit node BN1 of latch cell 110 (as the first latch cell) is conductively connected to the upper supply voltage VDD, while the PMOS transistor 102 is set to the on state. In addition, in response to a logic low voltage applied to the gate of the NMOS transistor 108, the second bit node BN2 of the latch unit 140 (as the last latch unit) remains floating, while the NMOS transistor 108 is set to a non-conducting state during this period.

[0021] In Figure 3B, each of the latching units 110-140 operates in backward connection mode, with the inter-unit transmission switches 112, 123, and 134 set to the connected state. During the operation of setting the latching units 110-140 to backward connection mode, the first transmission switch S1 of the latching units 110-140 is set to the open state, and the second transmission switch S2 of the latching units 110-140 is set to the connected state.

[0022] Furthermore, the storage device 100 in Figure 3B operates in backward shift mode. During the operation of setting the storage device 100 to backward shift mode, in addition to setting each latch cell (e.g., 110-140) to backward connection mode and setting the inter-cell transfer switches (e.g., 112, 123, and 134) to a connected state, the first bit node BN1 of the first latch cell (e.g., 110) remains floating, and the second bit node BN2 of the last latch cell (e.g., 140) remains at a fixed logic level voltage. In the example implementation of Figure 3B, in response to a logic high voltage applied to the gate of the PMOS transistor 102, the first bit node BN1 of latch cell 110 (as the first latch cell) remains floating, while the PMOS transistor 102 is set to a non-conducting state during this period. In addition, in response to a logic high voltage applied to the gate of the NMOS transistor 108, the second bit node BN2 of the latch unit 140 (as the last latch unit) is conductively connected to the lower supply voltage VSS, during which time the NMOS transistor 108 is set to the on state.

[0023] In Figure 3C, each of the latching units 110-140 operates in latching mode, and the inter-unit transmission switches 112, 123, and 134 are set to the off state. During the operation of setting the latching units 110-140 to latching mode, the first transmission switch S1 of the latching units 110-140 is set to the connected state, and the second transmission switch S2 of the latching units 110-140 is set to the connected state.

[0024] Additionally, the storage device 100 in Figure 3C operates in storage mode. During the operation of setting the storage device 100 to storage mode, in addition to setting each latch cell (e.g., 110-140) to latch mode and setting the inter-cell transfer switches (e.g., 112, 123, and 134) to the off state, the first bit node BN1 of the first latch cell (e.g., 110) remains floating, and the second bit node BN2 of the last latch cell (e.g., 140) remains floating. In the example implementation of Figure 3A, in response to a logic high voltage applied to the gate of the PMOS transistor 102, the first bit node BN1 of latch cell 110 (as the first latch cell) remains floating, while the PMOS transistor 102 is set to a non-conducting state during this period. In addition, in response to a logic low voltage applied to the gate of the NMOS transistor 108, the second bit node BN2 of the latch unit 140 (as the last latch unit) remains floating, while the NMOS transistor 108 is set to a non-conducting state during this period.

[0025] The storage device 100 in Figure 1 can operate as a finite state machine to store digital information. When the storage device 100 operates in storage mode, the state of the finite state machine is identified by the state of each latch unit 110-140 in the storage device 100. In each latch unit 110-140, the state of the latch unit 110-140 is identified by the voltage level at the first bit node BN1 or the voltage level at the second bit node BN2. In Figure 1, the state of the storage device 100 (as a finite state machine) is identified by the state of each of the latch units 110-140. In a specific implementation, as shown in Figure 4, the state b0 of latch unit 110 is identified by the voltage level at the first bit node BN1 of latch unit 110, the state b1 of latch unit 120 is identified by the voltage level at the second bit node BN2 of latch unit 120, the state b2 of latch unit 130 is identified by the voltage level at the second bit node BN2 of latch unit 130, and the state b3 of latch unit 140 is identified by the voltage level at the first bit node BN1 of latch unit 140.

[0026] Each element node (e.g., BN1 or BN2) has a voltage level that is either high or low. Each of the high and low voltage levels is interpreted as one of two binary logic voltage levels. The high and low voltage ranges typically depend on the specific implementation of the inverter used in the latch cell. For latch cells implemented as shown in Figures 2A through 2D, the high voltage is at VDD- The voltage is low from VSS to VSS+ within the range up to VDD. Within the range.

[0027] In Figure 4, the state of storage device 100 can be identified by the combination "b 0b 1b 2b 3", where each of the bit values ​​b0, b1, b2, and b3 corresponds to the state of one of the latch units 110, 120, 130, and 140. In one encoding scheme, a high voltage is associated with binary "1", and a low voltage is associated with binary "0". The five states of storage device 100 in Figure 4 are "1100", "1101", "1111", "1011", and "0011".

[0028] When the storage device 100 is in storage mode, the state of the storage device 100 is maintained. However, during the period when the storage device 100 is in forward shift mode or backward shift mode, the state of the storage device 100 changes. In some embodiments, with the operation of a long pulse for forward shift, the state of the storage device 100 is set to state "1100". Furthermore, with the operation of a short pulse for backward shift, one of the following occurs: state "1100" changes to state "1101", or state "1101" changes to "1111", state "1111" changes to state "1011", or state "1011" changes to "0011".

[0029] Figures 5A and 5B are circuit diagrams of a storage device 100 that undergoes a state change after a long pulse operation of forward shifting, according to some embodiments. During the long pulse operation, as shown in Figure 5A, the storage device 100 is set to forward shift mode. In response to the first bit node BN1 of latch unit 110 remaining at logic high (i.e., b0 = "1"), the first bit node BN1 of latch unit 120 is set to logic low, and the second bit node BN2 of latch unit 120 becomes logic high (i.e., b1 = "1"). In response to the second bit node BN2 of latch unit 120 remaining at logic high, the first bit node BN1 of latch unit 130 is set to logic low (i.e., b2 = "0"), and the first bit node BN1 of latch unit 140 is set to logic low (i.e., b3 = "0"). Therefore, the state of the storage device 100 changes to state "1100". The duration of the long pulse operation is designed to be long enough to ensure that the first element node BN1 of latch unit 140 goes low, because any voltage change at the first element node BN1 of the first latch unit (i.e., 110) has sufficient time to propagate to the first element node BN1 of the last latch unit (i.e., 140). In some embodiments, the backward shift short pulse operation immediately follows the forward shift long pulse operation without first setting the storage device 100 to storage mode before the short pulse operation begins. In some embodiments, as shown in Figure 5B, the storage device 100 is set to storage mode at the end of the long pulse operation, and the state of the storage device 100 is maintained at "1100". In some embodiments, the backward shift short pulse operation is applied to the storage device 100 after the storage device 100 is set to storage mode.

[0030] Figures 6A to 6B, 7A to 7B, 8A to 8B, and 9A to 9B are circuit diagrams of a storage device 100 according to some embodiments, which has a state change after a short pulse operation of backward shift.

[0031] In Figures 6A and 6B, the storage device 100 is in state "1100" before the short pulse operation of backward shift is applied to the storage device 100. During the short pulse operation, as shown in Figure 6A, the storage device 100 is set to backward shift mode, and the voltage of the second bit node BN2 of the latch unit 140 remains logic low. The duration of the short pulse operation is designed to be short enough to ensure that the second bit node BN2 of the latch unit 130 remains logic low (i.e., b2 = "0"). That is, due to the insufficient time of the short pulse operation, the voltage change at the second bit node BN2 of the latch unit 140 will not propagate to the second bit node BN2 of the latch unit 130.

[0032] At the end of the short pulse operation, as shown in Figure 6B, the storage device 100 is set to storage mode. After the inter-cell transfer switch 134 is set to the open state, the first bit node BN1 of the latch unit 140 is flipped to logic high (i.e., b3 = "1") by the second inverter INV2 of the latch unit 140. In some embodiments, during the process of flipping the first bit node BN1 of the latch unit 140 from logic low to logic high, the voltage of the second bit node BN2 of the latch unit 140 is kept at logic low by the capacitance at the input of the second inverter INV2. After the first bit node BN1 of the latch unit 140 is flipped, the first transfer switch S1 is closed, and the storage device 100 is stably in state "1101". In some embodiments, before the first transmission switch S1 is closed, the voltage of the second bit node BN2 of the latch unit 140 is kept at logic low by the NMOS transistor 108, and after the storage device 100 is stably in state "1101", the NMOS transistor 108 becomes non-conducting. In some alternative embodiments, the NMOS transistor 108 becomes non-conducting without waiting for the first transmission switch S1 to close.

[0033] In Figures 7A and 7B, storage device 100 is in state "1101" before the short pulse operation of backward shift is applied to storage device 100. During the short pulse operation, as shown in Figure 7A, storage device 100 is set to backward shift mode, and the voltage of the second bit node BN2 of latch unit 130 flips to logic high (i.e., b2 = "1"), because the voltage at the first bit node BN1 of latch unit 140 is logic high. The duration of the short pulse operation is designed to be short enough to ensure that the second bit node BN2 of latch unit 120 remains at logic high (i.e., b1 = "1"). That is, due to the insufficient time of the short pulse operation, the voltage change at the second bit node BN2 of latch unit 130 will not propagate to the second bit node BN2 of latch unit 120.

[0034] At the end of the short pulse operation, as shown in Figure 7B, the storage device 100 is set to storage mode. After the inter-cell transfer switch 123 is set to the open state, the first bit node BN1 of the latch cell 130 is flipped to logic low by the second inverter INV2 in the latch cell 130, because the voltage of the second bit node BN2 of the latch cell 130 is kept at logic high by the capacitor at the input of the second inverter INV2. Then, the first transfer switch S1 in each latch cell 110-140 is closed, and the storage device 100 is stably in state "1111". In some embodiments, the NMOS transistor 108 becomes non-conducting before the first transfer switch S1 in each latch cell 110-140 is closed. In some embodiments, the NMOS transistor 108 becomes non-conducting without waiting for the first transfer switch S1 in each latch cell 110-140 to close.

[0035] In Figures 8A and 8B, the storage device 100 is in state "1111" before the short pulse operation of backward shift is applied to the storage device 100. During the short pulse operation, as shown in Figure 8A, the storage device 100 is set to backward shift mode, and the voltage of the second bit node BN2 of latch unit 120 flips to logic low (i.e., b1 = "0"), because the voltage at the first bit node BN1 of latch unit 130 is logic low. The duration of the short pulse operation is designed to be short enough to ensure that the second bit node BN2 of latch unit 110 remains logic low (correspondingly, b0 = "1" at the first bit node BN1 of latch unit 110). That is, due to the insufficient time of the short pulse operation, the voltage change at the second bit node BN2 of latch unit 120 will not propagate to the second bit node BN2 of latch unit 110.

[0036] At the end of the short pulse operation, as shown in Figure 8B, the storage device 100 is set to storage mode. After the inter-cell transfer switch 112 is set to the open state, the first bit node BN1 of the latch unit 120 is flipped to logic high by the second inverter INV2 in the latch unit 120, because the voltage of the second bit node BN2 of the latch unit 120 is kept at logic low by the capacitor at the input of the second inverter INV2. Then, the first transfer switch S1 in each latch unit 110-140 is closed, and the storage device 100 is stably in state "1011".

[0037] In Figures 9A and 9B, before the short pulse operation of backward shift is applied to the storage device 100, the storage device 100 is in state "1011". During the short pulse operation, as shown in Figure 9A, the storage device 100 is set to backward shift mode, and the voltage of the second bit node BN2 of the latch unit 110 flips to logic high because the voltage at the first bit node BN1 of the latch unit 120 is logic high. In Figure 9A, the first bit node BN1 of the latch unit 110 remains logic high.

[0038] During or at the end of the short pulse operation, the first bit node BN1 of latch unit 120 is flipped low by the second inverter INV2 in latch unit 110, because the voltage at the second bit node BN2 of latch unit 110 is kept high by the capacitor at the input of the second inverter INV2. At the end of the short pulse operation, as shown in Figure 9B, storage device 100 is set to storage mode. The first transmission switch S1 in each latch unit 110-140 is closed, and storage device 100 is stably in state "0011".

[0039] Figure 10 is a schematic diagram illustrating the process of repeatedly applying short pulse operations to the storage device 100 according to some embodiments. With each forward-shifting long pulse operation, the storage device 100 is initially set to state "1100," and examples of the long pulse operation are described with reference to Figures 5A to 5B. The storage device 100 then sequentially undergoes four backward-shifting short pulse operations. After the first backward-shifting short pulse operation, the state "1100" of the storage device 100 changes to state "1101," and examples of the first short pulse operation are described with reference to Figures 6A to 6B. After the second backward-shifting short pulse operation, the state "1101" of the storage device 100 changes to state "1111," and examples of the second short pulse operation are described with reference to Figures 7A to 7B. After the third backward-shifting short pulse operation, the state "1111" of the storage device 100 changes to state "1011," and examples of the third short pulse operation are described with reference to Figures 8A to 8B. After the backward shifting fourth short pulse operation, the state of storage device 100 "1011" changes to state "0011". An example of the fourth short pulse operation will be described with reference to Figures 9A to 9B.

[0040] Figure 11 is a timing diagram illustrating the process of applying various short-pulse operations for backward shift and long-pulse operations for forward shift to storage device 100 according to some embodiments. In the example of Figure 11, storage device 100 is in the state of "0011" before time t0. As shown in the timing diagram of Figure 11, in response to the long-pulse operation for forward shift applied to storage device 100, the state of storage device 100 changes to "1100" at time t0. In response to the first short-pulse operation for backward shift applied to storage device 100, the state of storage device 100 changes to "1101" at time t1. In response to the second short-pulse operation for backward shift applied to storage device 100, the state of storage device 100 changes to "1111" at time t2. In response to the third short-pulse operation for backward shift applied to storage device 100, the state of storage device 100 changes to "1011" at time t3. In response to the fourth short pulse operation that applies a backward shift to the storage device, the state of the storage device changes to "0011" at time t4. The effects of each of the four short pulse operations between time t0 and time t4 on the storage device 100 are illustrated in the schematic diagram of Figure 10.

[0041] In addition to the long pulse operation for forward shift and the short pulse operation for reverse shift, the short pulse operation for forward shift is also performed on the storage device 100 having latching units 110-140. The short pulse operation for forward shift and the short pulse operation for backward shift are opposite operations to each other. For example, when the short pulse operation for backward shift changes the storage device from state "1100" to state "1101", the short pulse operation for forward shift changes the storage device 100 back from state "1101" to state "1100". When the short pulse operation for backward shift changes the storage device 100 from state "1101" to state "1111", the short pulse operation for forward shift changes the storage device 100 back from state "1111" to state "1101". When the backward shift short pulse operation changes the storage device 100 from state "1111" to state "1011", the forward shift short pulse operation changes the storage device 100 back from state "1011" to state "1111". When the backward shift short pulse operation changes the storage device 100 from state "1011" to state "0011", the forward shift short pulse operation changes the storage device 100 back from state "0011" to state "1011".

[0042] Figures 12A to 12B, 13A to 13B, 14A to 14B, and 15A to 15B are circuit diagrams of a storage device 100 according to some embodiments, which has a state change after a forward shift short pulse operation.

[0043] In Figures 12A and 12B, before the short pulse operation of forward shift is applied to storage device 100, storage device 100 is in state "0011". During the short pulse operation, as shown in Figure 12A, storage device 100 is set to forward shift mode, and the voltage of the first bit node BN1 of latch unit 110 remains at logic high. The duration of the short pulse operation is designed to be short enough to ensure that the first bit node BN1 of latch unit 120 remains at logic high. That is, due to the insufficient time of the short pulse operation, the voltage change at the second bit node BN2 of latch unit 110 will not propagate to the second bit node BN2 of latch unit 120. At the end of the short pulse operation, as shown in Figure 12B, storage device 100 is set to storage mode. After the inter-unit transfer switches 112, 123, and 134 are set to the open state and the second transfer switch S2 in each latching unit 110-140 is closed, the storage device 100 is stably in state "1011".

[0044] In Figures 13A and 13B, before the short pulse operation of forward shift is applied to the storage device 100, the storage device 100 is in state "1011". During the short pulse operation, as shown in Figure 13A, the storage device 100 is set to forward shift mode. When the inter-cell transfer switch 112 is set to the connected state, the voltage of the first element node BN1 of the latch unit 120 becomes logic low. The duration of the short pulse operation is designed to be short enough to ensure that the first element node BN1 of the latch unit 130 remains logic low. At the end of the short pulse operation, as shown in Figure 13B, the storage device 100 is set to storage mode. After the inter-cell transfer switches 112, 123, and 134 are set to the disconnected state and the second transfer switch S2 in each latch unit 110-140 is closed, the storage device is stably in state "1111".

[0045] In Figures 14A and 14B, before the short pulse operation of forward shift is applied to the storage device 100, the storage device 100 is in state "1111". During the short pulse operation, as shown in Figure 14A, the storage device 100 is set to forward shift mode. When the inter-cell transfer switch 123 is set to the connected state, the voltage of the first element node BN1 of the latch unit 130 becomes logic high. The duration of the short pulse operation is designed to be short enough to ensure that the first element node BN1 of the latch unit 140 remains at logic high. At the end of the short pulse operation, as shown in Figure 14B, the storage device 100 is set to storage mode. After the inter-cell transfer switches 112, 123, and 134 are set to the disconnected state and the second transfer switch S2 in each latch unit 110-140 is closed, the storage device 100 is stably in state "1101".

[0046] In Figures 15A and 15B, before the short pulse operation of forward shift is applied to the storage device 100, the storage device 100 is in state "1111". During the short pulse operation, as shown in Figure 15A, the storage device 100 is set to forward shift mode. When the inter-cell transfer switch 134 is set to the connected state, the voltage of the first bit node BN1 of the latch unit 140 becomes logic low. When the gate of the NMOS transistor 108 remains logic low, the second bit node BN2 of the latch unit 140 remains floating. At the end of the short pulse operation, as shown in Figure 14B, the storage device 100 is set to storage mode. After the inter-cell transfer switches 112, 123, and 134 are set to the disconnected state and the second transfer switch S2 in each latch unit 110-140 is closed, the storage device 100 is stably in state "1100".

[0047] Figure 16 is a table of various encoding schemes for encoding the states of a storage device 100 having latching units 110-140 according to some embodiments. Row 1630 of the table lists the encoding schemes based on the states b0, b1, b2, and b3 of the latching units in Figure 4. In row 1630, the five states encoded using a thermometer-like encoding scheme are states 1100, 1101, 1111, 1011, and 0011, each of which is depicted in Figure 10.

[0048] In Figure 16, using the standard coding scheme, the codes 00, 01, 10, 11, and 100 in row 1610 correspond to the states 1100, 1101, 1111, 1011, and 0011 in row 1630 of the thermometer coding scheme. Using the thermometer coding scheme, the codes 0000, 0001, 0011, 0111, and 1111 in row 1620 correspond to the states 1100, 1101, 1111, 1011, and 0011 in row 1630 of the thermometer coding scheme.

[0049] Using the -1 encoding scheme, codes 0, 1, 2, 3, and 4 in line 1640 correspond to states 1100, 1101, 1111, 1011, and 0011 in line 1630 of the thermometer encoding scheme. The backward shift short pulse operation performs an increment (+1), changing the code from 0 to 1, from 1 to 2, from 2 to 3, and from 3 to 4. The forward shift short pulse operation performs a decrement (-1), changing the code from 1 to 0, from 2 to 1, from 3 to 2, and from 4 to 3. The forward shift long pulse operation performs a decrement (-4), changing the code from 4 to 0.

[0050] Using the -2 encoding scheme, the codes 0, 4, 8, 12, and 16 in line 1650 correspond to the states 1100, 1101, 1111, 1011, and 0011 in line 1630 of the thermometer encoding scheme. The backward shift short pulse operation performs an addition of four (i.e., +4), changing the code from 0 to 4, from 4 to 8, from 8 to 12, and from 12 to 16. The forward shift short pulse operation performs a subtraction of four (i.e., -4), changing the code from 4 to 0, from 8 to 4, from 12 to 8, and from 16 to 8. The forward shift long pulse operation performs the arithmetic operation -16, changing the code from 16 to 0.

[0051] Using the Encoding-3 scheme, codes 1, 2, 4, 8, and 16 in line 1660 correspond to states 1100, 1101, 1111, 1011, and 0011 in line 1630 of the thermometer-like encoding scheme. A short pulse operation for backward shift performs a multiplication by 2, changing the code from 1 to 2, from 2 to 4, from 4 to 8, and from 8 to 16. A short pulse operation for forward shift performs a division by 2, changing the code from 2 to 1, from 4 to 2, from 8 to 4, and from 16 to 8. A long pulse operation for forward shift performs a division by 16, changing the code from 16 to 1.

[0052] In Figure 16, the encoding schemes coded-1 and coded-2 are based on arithmetic sequences in the form of A, A+b, A+2b, A+3b, and A+4b. In encoding-1, the first term A=0, and the common difference b=1. In encoding-2, the first term A=0, and the common difference b=4. Encoding-3 is based on a geometric sequence in the form of A, A*b, A*b2, A*b3, and A*b4. In encoding-3, the first term A=1, and the common ratio b=2.

[0053] The encoding scheme in Figure 16 is based on a storage device 100 with four latch units 110-140, which forms a finite state machine with five states. An example is provided of a storage device 100 implemented with four latch units 110-140 connected to inter-cell transfer switches 112, 123, and 134. In other implementations, a storage device having an array of N latch units connected to inter-cell transfer switches forms a finite state machine with N+1 states, where N is a positive integer. In some encoding schemes, the N+1 states are represented by N+1 codes based on an arithmetic sequence of N+1 elements, in the form of A, A+1*b, A+2*b, A+3*b, ..., and A+N*b. In some encoding schemes, the N+1 states are represented by N+1 codes based on a geometric sequence, in the form of A, A*b, A*b2, A*b3, ..., and A*bN. As a specific example, for a storage device with an array of eight latching units (i.e., N=8), the table in Figure 17 lists encoding schemes based on arithmetic and geometric sequences. The first row of the table also lists the N+1 states (N=8) represented by a thermometer-like encoding scheme.

[0054] In a specific embodiment of Figure 4, the state of storage device 100 is represented by the combination "b 0b 1b 2b 3", where bit values ​​b 0, b 1, b 2, and b 3 correspond to the voltage level at the first bit node BN1 of latch unit 110, the voltage level at the second bit node BN2 of latch unit 120, the voltage level at the second bit node BN2 of latch unit 130, and the voltage level at the first bit node BN1 of latch unit 140. In some alternative implementations, as shown in Figure 18, the state of storage device 100 is represented by the combination "b 0b 1b 2b 3", where bit values ​​b 0, b 1, b 2, and b 3 correspond to the voltage levels at the first bit node BN1 of latch unit 110, the first bit node BN1 of latch unit 120, the first bit node BN1 of latch unit 130, and the first bit node BN1 of latch unit 140. In the state representation of Figure 18, the five states of storage device 100 are "1010", "1011", "1001", "1101", and "0101".

[0055] In the specific embodiments shown in Figures 2A to 2C, each of the inverters (i.e., the first inverter INV1 and the second inverter INV2) is implemented using a PMOS transistor and an NMOS transistor. Other embodiments of the inverters in the latch cells 110 to 140 of the storage device 100 are within the scope of this disclosure. Figures 19A to 19C show three example implementations of latch cells available in the storage device of this disclosure.

[0056] In Figure 19A, each of the first inverter INV1 and the second inverter INV2 is implemented using 2n+1 series-connected single-stage inverters. In the examples in Figures 2A to 2C, each inverter is implemented using a PMOS transistor and an NMOS transistor, providing an example of a single-stage inverter. By changing the number of single-stage inverters used to form the first inverter INV1, the delay time of the first inverter INV1 is adjusted. By changing the number of single-stage inverters used to form the second inverter INV2, the delay time of the second inverter INV2 is adjusted.

[0057] In Figure 19B, the first inverter INV1 receives a first supply voltage VDD via a PMOS transistor, the PMOS transistor having a gate biased by a gate voltage Vbias-P, and receives a second supply voltage VSS via an NMOS transistor, the NMOS transistor having a gate biased by a gate voltage Vbias-N. The second inverter INV2 similarly receives both the first supply voltage VDD and the second supply voltage VSS. By changing the gate voltage Vbias-P and / or the gate voltage Vbias-N, the delay times of the first inverter INV1 and / or the second inverter INV2 are adjusted.

[0058] In Figure 19C, each of the first inverter INV1 and the second inverter INV2 is implemented using a D flip-flop. In Figures 19A to 19C, the inter-cell transfer switch S3 (which is connected to the second bit node BN2) is shown together with latching units 1910A, 1910B, or 1910C.

[0059] In some embodiments, as shown in Figure 20, multiple storage devices are linked together to form a storage cell column. In Figure 20, the storage cell column includes cell 0, cell 1, ..., and cell m. Each storage cell includes a storage device. The output of cell 0 is connected to the input of cell 1, the output of cell 1 is connected to the input of cell 2, ..., the output of cell m-1 is connected to the input of cell m. In some embodiments, in an example where the storage device 100 in Figure 1 is used to implement the storage cells (e.g., cells 0, 1, ..., cell m) in Figure 20, the second bit node BN2 of the last latching unit (i.e., 140) is implemented as the input of the storage cell, and the first bit node BN1 of the first latching unit (i.e., 110) is implemented to generate an output bit signal for the output of the storage cell.

[0060] Figure 21A is a schematic diagram of a three-cell array according to some embodiments, each cell having a storage device. In Figure 21A, each storage device in the cell is implemented using four latching cells, similar to the example implementation in Figure 1. The storage device of cell 0 is implemented by encoding the first digit q0 of a quaternary number and its corresponding carry bit; in the storage device, each of the five states 1100, 1101, 1111, 1011, and 0011 corresponds to one of the five numbers 0, 1, 2, 3, and 4. The storage device of cell 1 is implemented by encoding the second digit q1 of a quaternary number and its corresponding carry bit; in the storage device, each of the five states 1100, 1101, 1111, 1011, and 0011 corresponds to one of the five numbers 0*4, 1*4, 2*4, 3*4, and 4*4. The storage device of Unit 2 is implemented to encode the third digit q 2 of the quaternary number and the corresponding carry bit of the third digit; in the storage device, each of the five states 1100, 1101, 1111, 1011, and 0011 corresponds to one of the five numbers 0*4 2, 1*4 2, 2*4 2, 3*4 2, and 4*4 2.

[0061] Unit 0 is configured to detect the overflow indicator "0" in bit value b0 during states b0b1b2b3. The overflow indicator "0" in bit value b0 appears when the state changes to 0011. In response to the appearance of the overflow indicator "0", unit 0 sends a carry bit signal to unit 1, and unit 0 resets to state 1100 using a long pulse operation of forward shift. In response to receiving the carry bit signal from unit 0, a short pulse operation of backward shift is performed on the storage device of unit 1.

[0062] Similarly, unit 1 is implemented to detect the overflow indicator "0" in bit value b0 in state b0b1b2b3. The overflow indicator "0" in bit value b0 appears when the state changes to 0011. In response to the appearance of the overflow indicator "0", unit 1 sends a carry bit signal to unit 2, and unit 1 resets to state 1100 using a long pulse operation of forward shift. In response to receiving the carry bit signal from unit 1, a short pulse operation of backward shift is performed on the storage device of unit 2.

[0063] Similarly, unit 2 is implemented to detect the overflow indicator "0" in bit value b0 in state b 0b 1b 2b 3. The overflow indicator "0" in bit value b0 appears when the state changes to 0011. In response to the appearance of the overflow indicator "0", unit 2 resets to state 1100 using a forward shift long pulse operation, and unit 2 can optionally send a carry bit signal to another circuit.

[0064] In Figure 21A, the three-cell column is used to represent the coded number q0+q1*4+q2*4 2. Figure 21B is a table that maps the combination of states of the three cells (i.e., cell 0, cell 1, and cell 2) to coded numbers written in decimal values.

[0065] In the operational example of the three-cell column shown in Figure 21A, when the decimal value 3 is represented using a three-cell column, the states of cell 2, cell 1, and cell 0 are 1100, 1100, and 1011 respectively. In response to adding the decimal value 1 to the decimal value 3, a short pulse backward shift operation is performed on the storage device of cell 0, changing the state of cell 0 from 1011 to 0011. Because the overflow indicator "0" is in state 0011, cell 0 sends a carry bit signal to cell 1, and cell 0 resets to state 1100 using a long pulse forward shift operation. In response to receiving the carry bit signal from cell 0, a short pulse backward shift operation is performed on the storage device of cell 1, changing the state of cell 1 from 1100 to 1101. The state of cell 2 remains at 1100. At the end of the operation, after the decimal value 1 is added to the decimal value 3, the combination of the states of the three units (i.e., unit 0, unit 1, and unit 2) is 1100 1101 1100, which corresponds to the decimal value 4.

[0066] In some embodiments, the matrix of storage cells is formed by multiple columns of storage cells, and each column is controlled by a corresponding column controller. Figure 22 is a schematic diagram of a multi-column storage cell and an example column controller 2210 for column 0 according to some embodiments. The multi-column storage cells are configured in columns 0, 1, 2, ..., and 256. Each storage cell column includes a plurality of storage cells (such as cell 0, cell 1, ..., etc.). Each storage cell includes a storage device (such as storage device 100 in Figure 1), the storage device having a plurality of latching cells connected in series. That is, each storage cell includes a storage device having a first latching cell, a last latching cell, and remaining latching cells connected in series between the first latching cell and the last latching cell. In Figure 22, each of the bit latch circuits 2221 and 2222 is associated with one of the storage cells (i.e., cell 0 or cell 1), and each of the bit latch circuits 2221 or 2222 is coupled to the first bit node of the first latch cell in the storage device of the corresponding storage cell (i.e., cell 0 or cell 1) (such as the first bit node BN1 of latch cell 110 in Figure 1). Each of the bit latch circuits 2221 and 2222 is used to capture the voltage at the first bit node of the first latch cell in the storage device of the corresponding storage cell (i.e., cell 0 or cell 1). In the example column controller 2210, various pulses are generated by the pulse generator 2255 to control the short pulse operation of backward shift, the long pulse operation of forward shift, and the short pulse operation of forward shift.

[0067] In some embodiments, whether an individual storage cell undergoes either short-pulse or long-pulse operations is individually controlled by the column controller 2210, thus selectively performing short-pulse and / or long-pulse operations on each storage cell. As an example, in some embodiments, a stored number encoded in the quaternary system q0 + q1*4 + q2*42 is stored in three storage cells of Figure 21A. To add the decimal value 1 to the stored number, a backward-shift short-pulse operation is performed on the storage device of cell 0. To subtract the decimal value 1 from the stored number, a forward-shift short-pulse operation is performed on the storage device of cell 0. To add the decimal value 4 to the stored number, a backward-shift short-pulse operation is performed on the storage device of cell 1. To add the decimal value 16 to the stored number, a backward-shift short-pulse operation is performed on the storage device of cell 2.

[0068] In some implementations, systems based on matrices having storage cells formed by multiple columns of storage cells as shown in Figure 22 accelerate the addition of two matrices by performing multi-column addition in parallel. Because each storage cell in a column is individually controlled to receive either short-pulse or long-pulse operations, different decimal values ​​can be added to different elements in a column of the matrix. In one example, as shown in Figures 23A to 23B, a first matrix 2310 is stored in multiple columns of storage cells in Figure 22. To add a second matrix 2320A or 2320B from Figures 23A to 23B to the first matrix 2310, a backward-shifted short-pulse operation is selectively applied to the corresponding storage cells in Figure 22. The second matrix 2320A includes submatrices ((+1,+4,+1),(+4,+16,+4),(+1,+4,+1)). The second matrix 2320B includes submatrices ((AW / 4,AW / 2,AW / 4), (AW / 2,AW,AW / 2), AW / 4,AW / 2,AW / 4)). Each element in the submatrix of the second matrix 2320A or 2320B is added in parallel to the corresponding element in the first matrix 2310.

[0069] Figure 24 is a flowchart of a method of operating a storage device according to some embodiments. The order of operations of method 2400 depicted in Figure 24 is for illustrative purposes only; the operation of method 2400 can be performed in a different order than that depicted in Figure 24. It should be understood that additional operations may be performed before, during, and / or after method 2400 shown in Figure 24, and only some other processes are briefly described herein. Method 2400 includes operations 2410 and 2420.

[0070] In operation 2410, a forward shift long pulse operation is performed on the storage device. Operation 2410 includes operations 2412 and 2414. In operation 2412, each latch cell in the array of latch cells is set to forward-connected mode during the long pulse. Operation 2412 also includes stabilizing the voltage at the second bit node of the last latch cell at the end of the long pulse to a level determined by a first voltage applied to the first bit node of the first latch cell. The second bit node of the last latch cell is set to floating during the long pulse. In the example shown in Figure 5A, each of latch cells 110-140 is set to forward-connected mode, and the second bit node BN2 of latch cell 140 is set to floating by keeping the gate voltage of NMOS transistor 108 at logic low. In Figure 5A, the voltage at the second bit node BN2 of latch cell 140 is determined by the voltage applied to the first bit node BN1 of latch cell 110. In one example, the upper supply voltage VDD is applied to the first element node BN1 of the latch cell 110 through the PMOS transistor 102. After operation 2412, the process proceeds to operation 2414.

[0071] In operation 2414, each latch cell in the array of latch cells is set to latch mode, and the inter-cell transfer switch is set to open. In the example embodiment shown in Figure 5B, each of the latch cells 110-140 is set to latch mode, and each of the inter-cell transfer switches 112, 123, and 134 is set to open.

[0072] In operation 2420, a short-pulse backward shift operation is performed on the storage device. Operation 2420 includes operations 2422 and 2424. In operation 2422, each latch cell in the array of latch cells is set to a backward-connected mode during the short pulse. In the examples shown in Figures 6A, 7A, 8A, and 9A, each of latch cells 110-140 is set to a backward-connected mode. After operation 2422, the process proceeds to operation 2424.

[0073] In operation 2424, each latching unit in the array of latching units is set to latching mode, and the inter-unit transmission switch is set to the open state. In the example embodiments shown in Figures 6B, 7B, 8B, and 9B, each of latching units 110-140 is set to latching mode, and the inter-unit transmission switches 112, 123, and 134 are set to the open state.

[0074] Operation 2422 also includes stabilizing the voltage at the first bit node of the given latch cell at the end of the short pulse operation to the level determined by the initial voltage at the second bit node of the given latch cell at the start of the short pulse operation.

[0075] In one example, at the start of the short pulse operation, as shown in Figure 6A, the initial voltage at the second bit node BN2 of latch cells 110-140 is correspondingly logic low, logic high, logic low, logic low (at the drain of NMOS transistor 108). At the end of the short pulse operation, as shown in Figure 6B, the voltage at the first bit node BN1 of latch cells 110-140 is correspondingly logic high, logic low, logic high, and logic high.

[0076] In another example, at the start of the short pulse operation, as shown in Figure 7A, the initial voltage at the second bit node BN2 of latch units 110-140 is correspondingly logic low, logic high, logic high, and logic low. At the end of the short pulse operation, as shown in Figure 7B, the voltage at the first bit node BN1 of latch units 110-140 is correspondingly logic high, logic low, logic low, and logic high.

[0077] In some embodiments, operation 2424 is repeated until a change in the voltage level at the first element node of the first latch unit is detected, and then another long pulse operation is performed on the storage device. In some example embodiments, as shown in Figures 6A to 6B, 7A to 7B, 8A to 8B, and 9A to 9B, operation 2424 is repeated. In response to a change in the voltage level at the first element node BN1 of the latch unit 110 from logic high to logic low, as shown in Figure 9B, a forward shift long pulse operation (such as the operation shown in Figures 5A to 5B) is performed on the storage device.

[0078] Figure 25 is a flowchart of a method of operating a storage device according to some embodiments. The order of operations of method 2500 depicted in Figure 25 is for illustrative purposes only; the operation of method 2500 can be performed in a different order than that depicted in Figure 25. It should be understood that additional operations may be performed before, during, and / or after method 2500 shown in Figure 25, and only some other processes are briefly described herein. Method 2500 includes operations 2510, 2520, 2530, and 2540.

[0079] In operation 2510, each latch cell in the array of latch cells is set to forward-connected mode during the first time period. In the example shown in Figure 5A, each of latch cells 110-140 is set to forward-connected mode. Refer to Figure 3A to explain the example operation of the forward-connected mode.

[0080] In operation 2520, each latch cell in the array of latch cells is set to latch mode, and the inter-cell transfer switch is set to the open state. In the example embodiment shown in Figure 5B, each of latch cells 110-140 is set to latch mode, and each of the inter-cell transfer switches 112, 123, and 134 is set to the open state. Refer to Figure 3C to explain an example operation of the backward connection mode.

[0081] In operation 2530, each latch cell in the array of latch cells is set to backward-connected mode during the second time period. In the examples shown in Figures 6A, 7A, 8A, and 9A, each of latch cells 110-140 is set to backward-connected mode. Refer to Figure 3B for an example operation of the backward-connected mode.

[0082] In operation 2540, each latch cell in the array of latch cells is set to latch mode, and the inter-cell transfer switch is set to the open state. In the example embodiment shown in Figure 6B, each of latch cells 110-140 is set to latch mode, and each of the inter-cell transfer switches 112, 123, and 134 is set to the open state. Refer to Figure 3C to explain an example operation of the backward connection mode.

[0083] This disclosure relates to a storage device. The storage device includes an array of latch cells and a plurality of inter-cell transfer switches. Each pair of adjacent latch cells is coupled together via an inter-cell transfer switch. Each latch cell includes a first inverter and a first transfer switch connected in series between a first bit node and a second bit node, the first inverter having an input for receiving voltage directly or through the first transfer switch from the first bit node; and a second inverter and a second transfer switch connected in series between a second bit node and a first bit node, the second inverter having an input for receiving voltage directly or through the second transfer switch from the second bit node.

[0084] Another aspect of this disclosure relates to a method. The method includes setting each latch cell in an array of latch cells to a forward-connected mode during a first time period, during which each of a plurality of inter-cell transfer switches is in a connected state, wherein each latch cell has a first bit node and a second bit node, wherein each pair of adjacent latch cells is coupled together via an inter-cell transfer switch connecting the second bit node of the first of two adjacent latch cells to the first bit node of the second of two adjacent memory cells; after the first time period, setting each latch cell in the array of latch cells to a latched mode and setting each inter-cell transfer switch to an open state; setting each latch cell in the array of latch cells to a backward-connected mode during a second time period, during which each inter-cell transfer switch is in a connected state; and after the second time period, setting each latch cell in the array of latch cells to a latched mode and setting each inter-cell transfer switch to an open state.

[0085] Another aspect disclosed herein relates to a storage device. The storage device includes an array of at least four latch cells, wherein each latch cell may include: a first inverter and a first transfer switch connected in series between a first bit node and a second bit node, the first inverter having an input for receiving voltage directly or through the first transfer switch from the first bit node; and a second inverter and a second transfer switch connected in series between the second bit node and the first bit node, the second inverter having an input for receiving voltage directly or through the second transfer switch from the second bit node. The device also includes a plurality of at least three inter-cell transfer switches, wherein each inter-cell transfer switch engaging two adjacent latch cells is used to couple a second bit node of the first of the two adjacent latch cells to a first bit node of the second of the two adjacent latch cells.

[0086] Those skilled in the art will readily see that one or more of the disclosed embodiments satisfy one or more of the advantages set forth above. After reading the foregoing specification, those skilled in the art will be able to make various modifications and substitutions to equivalents and various other embodiments within the broad scope of this disclosure. Therefore, the protection granted herein is limited only to the definitions contained in the appended claims and their equivalents.

[0087] 100: Storage device 102: PMOS transistor 108: NMOS transistor 110~140: Latch Unit 112: Inter-unit transfer switch 123: Inter-unit transfer switch 134: Inter-unit transfer switch 1610~1660: lines 1910A~1910C: Latch Unit 2210: Column Controller 2221~2222: Bit latch circuit 2255: Pulse Generator 2310: First Matrix 2320A~2320B: Second Matrix 2400: Method 2410~2414: Operation 2420~2424: Operation 2500: Method 2510~2540: Operations INV1: First Inverter INV2: Second inverter S1: First transmission switch S2: Second transmission switch

[0088] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A storage device comprising: an array of at least four latch cells, wherein each latch cell comprises: a first inverter and a first transfer switch directly connected in series between a first bit node and a second bit node, the first inverter having an input for receiving a voltage directly or through the first transfer switch from the first bit node; and a second inverter and a second transfer switch directly connected in series between the second bit node and the first bit node, the second inverter having an input for receiving a voltage directly or through the second transfer switch from the second bit node; and a plurality of inter-cell transfer switches, wherein each pair of adjacent latch cells is directly coupled together through an inter-cell transfer switch, wherein each of the inter-cell transfer switches is configured to be in an off state for a period of time, wherein during the period of time, the first and second transfer switches of each latch cell are in an on state.

2. The storage device as claimed in claim 1, wherein the inter-cell transfer switch is between the second bit node of a first of two adjacent latching cells and the first bit node of a second of the two adjacent latching cells.

3. The storage device of claim 1, wherein the first bit node of a first latching unit is coupled to a bit latching circuit for capturing a voltage at the first bit node of the first latching unit.

4. The storage device as claimed in claim 1, wherein the first inverter is coupled between the first bit node and the first transmission switch, and the first transmission switch is coupled between an output of the first inverter and the second bit node.

5. The storage device as claimed in claim 1, wherein the second inverter is coupled between the second bit node and the second transmission switch, and the second transmission switch is coupled between an output of the second inverter and the first bit node.

6. A method of operating a storage device, comprising: setting each latch cell in an array of latch cells to a forward-connected mode during a first time period, during which each of a plurality of inter-cell transfer switches is in a connected state, wherein each latch cell has a first bit node and a second bit node, the array comprising at least four latch cells, wherein each pair of two adjacent latch cells is directly coupled together via an inter-cell transfer switch, the inter-cell transfer switch connecting the second bit node of a first of the two adjacent latch cells to the first bit node of a second of the two adjacent latch cells, wherein each latch cell includes a first inverter and a first transfer switch directly coupled in series between the first bit node and the second bit node, and includes a second inverter and a second transfer switch directly coupled in series between the second bit node and the first bit node; After the first time period, each latch unit in the array of latch units is set to a latch mode, and the inter-unit transmission switch is set to an open state. In the latch mode, the first and second transmission switches of each latch unit are in a connected state. Each latch unit in the array of latch units is set to a backward connection mode during a second time period, during which the inter-unit transmission switch is in a connected state. After the second time period, each latch unit in the array of latch units is set to the latch mode, and the inter-unit transmission switch is set to the open state.

7. The method of claim 6, wherein the first inverter has an input directly or through the first transmission switch coupled to the first bit node; and the second inverter has an input directly or through the second transmission switch coupled to the second bit node.

8. A storage device comprising: an array of at least four latch cells, wherein each latch cell comprises: a first inverter and a first transfer switch directly connected in series between a first bit node and a second bit node, the first inverter having an input for receiving a voltage directly or through the first transfer switch from the first bit node; and a second inverter and a second transfer switch directly connected in series between the second bit node and the first bit node, the second inverter having an input for receiving a voltage directly or through the second transfer switch from the second bit node; and a plurality of at least three inter-cell transfer switches, wherein each inter-cell transfer switch of two adjacent latch cells is coupled to couple the second bit node of a first of the two adjacent latch cells to the first bit node of a second of the two adjacent latch cells, wherein each of the inter-cell transfer switches is configured to be in an off state for a period of time, wherein during the period of time, the first and second transfer switches of each latch cell are in an on state.

9. The storage device as claimed in claim 8, wherein the first transmission switch is coupled between the first bit node and the input of the first inverter, and the first inverter is coupled between the first transmission switch and the second bit node.

10. The storage device of claim 9, wherein the second transmission switch is coupled between the second bit node and the input of the second inverter, and the second inverter is coupled between the second transmission switch and the first bit node.

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