Semiconductor device and method of forming the same

Abstract

The method includes forming a fin-like structure on a substrate; forming a plurality of first and second nanostructures on the fin-like structure, wherein the first nanostructures and individual second nanostructures are continuous structures; forming a plurality of first dielectric dummy regions between the first nanostructures and a plurality of second dielectric dummy regions between the second nanostructures; forming a plurality of first source / drain regions adjacent to the first nanostructures and forming a plurality of second source / drain regions adjacent to the second nanostructures; performing an etching process to remove the first and second dielectric dummy regions; depositing a plurality of gate structure layers on the first and second nanostructures; and forming an isolation region between the first and second nanostructures, wherein the isolation region physically separates the first and second nanostructures.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to fins formed by dividing a continuous fin structure. Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce minimum structural dimensions to improve the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, or the like, allowing more components to be integrated into a given area. However, as the minimum structural dimensions shrink, additional problems arise that need to be addressed. Summary of the Invention

[0004] In one embodiment, a method for forming a semiconductor device includes forming a fin structure on a substrate; forming a plurality of first nanostructures and a plurality of second nanostructures on the fin structure, wherein the first nanostructures and individual second nanostructures are continuous structures; forming a plurality of first dielectric dummy regions between the first nanostructures and a plurality of second dielectric dummy regions between the second nanostructures; forming a plurality of first source / drain regions adjacent to the first nanostructures and forming a plurality of second source / drain regions adjacent to the second nanostructures; performing an etching process to remove the first dielectric dummy regions and the second dielectric dummy regions; depositing a plurality of gate structure layers on the first nanostructures and the second nanostructures; and forming an isolation region between the first nanostructures and the second nanostructures, wherein the isolation region physically separates the first nanostructures and the second nanostructures.

[0005] In one embodiment, a method of forming a semiconductor device includes forming a first nanostructure stack adjacent to a second nanostructure stack, wherein the first nanostructure stack and the second nanostructure stack include a plurality of first nanostructures and a plurality of second nanostructures, wherein a first sidewall of the first nanostructure stack is adjacent to a second sidewall of the second nanostructure stack, wherein the first sidewall is perpendicularly offset from the second sidewall; replacing the first nanostructures of the first nanostructure stack and the first nanostructure stack with a plurality of dielectric regions; replacing the dielectric regions of the first nanostructure stack and the dielectric regions of the second nanostructures with a continuous gate structure; and replacing a portion of the continuous gate structure with an isolation region, wherein the isolation region extends between the first nanostructure stack and the second nanostructure stack.

[0006] In one embodiment, the semiconductor device includes a first fin and a second fin located on a semiconductor substrate, wherein a first width of the first fin is different from a second width of the second fin; a plurality of first nanostructures located on the first fin; a plurality of second nanostructures located on the second fin; a first gate structure located on the first fin, wherein the first gate structure separates individual adjacent first nanostructures; and a second gate structure located on the second fin, wherein the second gate structure separates individual adjacent second nanostructures; and an isolation structure extending from the first fin to the second fin, wherein the isolation structure protrudes into the semiconductor substrate. Simple Explanation of the Diagram

[0007] Figure 1 shows a three-dimensional view of a nanostructured field-effect transistor in some embodiments. Figure 2, 3A, 3B, 4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 8C, 8D, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 12C, 13A, 1 3B, 14A, 14B, 14C, 14D, 14E, 15A, 15B, 15C, 15D, 16A, 16B, 16C, 16D, 17A, 17B, 17C, 17D, 18A, 18B, 18C, 1 8D, 19A, 19B, 19C, 19D, 20, 21A, 21B, 22A, 22B, 22C, 22D, 23A, 23B, 23C, 23D, 24A, 24B, 24C, 24D, 25A, 25B, 25C, 25D, 26A, 26B, 26C, 26D, 27A, 27B, 27C, 27D, 28A, 28B, and 28C are various patterns representing intermediate stages in the fabrication of nanostructured field-effect transistors in some embodiments. Figures 29A, 29B, and 29C are plan views of the continuous fin structure in some embodiments. Figures 30A, 30B, 30C, and 30D are plan views of the isolation zone between fins in some embodiments. Figures 31A, 31B, 31C, 31D, 31E, 31F, and 31G are plan views of the continuous fin structure in some embodiments. Figures 32A, 32B, 33A, 33B, 33C, 33D, 34A, 34B, 34C, 34D, 35A, 35B, 35C, 35D, 36A, 36B, 36C, 36D, 37A, 37B, 37C, 37D, 38, and 39 are various diagrams of intermediate stages in the fabrication of nanostructured field-effect transistors in some embodiments. Implementation

[0008] The following detailed description, accompanied by accompanying drawings, will aid in understanding various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity of explanation.

[0009] It is understood that the different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The specific components and arrangements described are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or that the two are separated by other additional components rather than in direct contact. Furthermore, the same reference numerals may be used repeatedly in various embodiments of the present invention for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] In addition, spatial relative terms such as "below," "below," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90 degrees or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0011] The following embodiments are specifically illustrated using a grain containing a nanostructured field-effect transistor. However, various embodiments can be used with grains containing other types of transistors (such as finned field-effect transistors, planar transistors, stacked transistors, or the like) to replace or combine with nanostructured field-effect transistors.

[0012] In various embodiments, oxide dummy regions are used to fill the areas between the channel regions of the nanostructured field-effect transistor, i.e., the regions formed after the gate structure. Using oxide dummy regions allows for more selective etching during removal, reducing the risk of etching damage to the channel regions or source / drain regions. This reduced risk of etching damage allows for safer formation of the isolation region after the gate structure, improving device density and yield.

[0013] Figure 1 is a three-dimensional view of a nanostructured field-effect transistor (such as a nanowire field-effect transistor, a nanosheet field-effect transistor, a nanostructured field-effect transistor, a fully wound gate field-effect transistor, or the like) in some embodiments. Figure 1 simplifies and / or omits some structures of the nanostructured field-effect transistor for clarity. The nanostructured field-effect transistor includes a second nanostructure 66 (such as a nanosheet, nanowire, or the like) located on a fin 62 on a substrate 50 (such as a semiconductor substrate), and the second nanostructure 66, such as a semiconductor structure, may be a channel region used by the nanostructured field-effect transistor. The second nanostructure 66 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation region 70, such as a shallow trench isolation region, is located between adjacent fins 62, and the fins 62 may protrude above the isolation regions 70 from between adjacent isolation regions 70. The second nanostructure 66 is located between and above adjacent isolation regions 70. A protective layer or hard masking layer (not shown in FIG1) may cover a portion of the isolation region 70. Although the isolation region 70 is described separately from the substrate 50 in the illustrations and figures, the term "substrate" as used herein may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom of the fin 62 in the illustrations and the substrate 50 are a single continuous material, the bottom of the fin 62 and / or the substrate 50 may comprise a single material or multiple materials. In this description, fin 62 refers to the portion extending between adjacent isolation regions 70.

[0014] A gate dielectric layer 110 is located on the upper surface of the fin 62 and extends along the upper surface, sidewalls, and lower surface of the second nanostructure 66. A gate 112 is located on the gate dielectric layer 110. The gate dielectric layer 110 and the gate 112 can be considered together as a "gate structure" or "gate stack". Isolation regions (not shown in FIG1 but detailed below) may be formed between the fins 62 or at the ends of some fins 62. Source / drain regions 100 (such as epitaxial source / drain regions) are located on the fins 62 on both sides of the gate dielectric layer 110 and the gate 112. The source / drain regions 100 can be considered individually or together as sources or drains, depending on the content. A first interlayer dielectric layer 104 is formed on the source / drain regions 100. The contacts connected to the source / drain regions 100 (as described later) pass through the first interlayer dielectric layer 104. Multiple second nanostructures 66 may share the source / drain regions 100. For example, adjacent source / drain regions 100 may be electrically connected by merging epitaxially grown source / drain regions 100, or by being coupled to source / drain regions 100 using the same contacts.

[0015] Figure 1 also shows the reference cross-sections used in subsequent illustrations. Cross-section A-A' is along the longitudinal axis of the fin 62 of the nanostructured field-effect transistor and in the current direction between the source / drain regions 100 of the nanostructured field-effect transistor. Cross-section B-B' is perpendicular to cross-section A-A' and extends along the longitudinal axis of the gate 112. Cross-section C-C' is parallel to cross-section BB' (i.e., perpendicular to cross-section A-A') and extends through the source / drain regions 100 of the nanostructured field-effect transistor. Subsequent illustrations are based on these reference cross-sections for clarity.

[0016] Some embodiments described herein are illustrated using nanostructured field-effect transistors (FETs) formed using a post-gate fabrication process. In other embodiments, a gate-first fabrication process may be used. Furthermore, some embodiments may be used in planar devices (such as planar FETs) or finned FETs to replace or complement nanostructured FETs. For example, a finned FET may include semiconductor fins located on a substrate, and the semiconductor fins, such as semiconductor structures, may serve as channel regions for the finned FET. Similarly, a planar FET includes a substrate, and the flat portion of the substrate, such as a semiconductor structure, may serve as a channel region for the planar FET. Other FETs or FET configurations are also possible.

[0017] Figures 2 to 28C are diagrams of intermediate stages in the fabrication of nanostructured field-effect transistors in some embodiments. Figures 2, 3B, 5B, 6A, 7A, 8A, 8D, 9A, 10A, 11A, 11C, 12A, 12C, 13A, 13B, 14A, 14E, 15A, 15D, 16A, 16D, 17A, 17D, 18A, 18D, 19A, 19D, 20, 21A, 22A, 22D, 23A, 23D, 24A, 24D, 25A, 25D, 26A, 26D, 27A, 27D, and 28A are cross-sectional views along a section similar to section A-A' in Figure 1. Figures 3A, 4, 5A, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 14B, 15B, 16B, 17B, 18B, 19B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, and 28B are sectional views along a section similar to section B-B' in Figure 1. Figures 8C, 14C, 14D, 15C, 16C, 17C, 18C, 19C, 22C, 23C, 24C, 25C, 26C, 27C, and 28C are sectional views along a section similar to section C-C' in Figure 1.

[0018] In some embodiments of FIG. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a substrate semiconductor, a semiconductor-on-insulator (SIA) substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate may be a wafer such as a silicon wafer. Generally, a SIA substrate has a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. An insulating layer is provided on the substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), or combinations thereof.

[0019] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices such as n-type metal-oxide-semiconductors (e.g., n-type nanostructured field-effect transistors), while the p-type region 50P can be used to form p-type devices such as p-type metal-oxide-semiconductors (e.g., p-type nanostructured field-effect transistors). The n-type region 50N and the p-type region 50P are physically separated (not shown), and any number of device structures (e.g., other active regions, doped regions, isolation structures, or the like) can be located between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P can be provided. The subsequent process steps shown in the diagram can be performed in either the n-type region 50N or the p-type region 50P, unless otherwise stated.

[0020] In some embodiments of FIG. 2, a multilayer stack 52 is formed on a substrate 50. The multilayer stack 52 includes an interleaved first semiconductor layer 54 and a second semiconductor layer 56. The first semiconductor layer 54 is composed of a first semiconductor material, and the second semiconductor layer 56 is composed of a second semiconductor material. The semiconductor materials may each be selected from candidate semiconductor materials of the substrate 50. In the embodiments described, the first semiconductor layer 54 is removed and the second semiconductor layer 56 is patterned to form channel regions used by nanostructured field-effect transistors in the n-type region 50N and the p-type region 50P, as detailed below. In these embodiments, the channel regions in the n-type region 50N and the p-type region 50P may have the same material composition (such as silicon or another semiconductor material) and may be formed simultaneously. The first semiconductor layer 54 is a dummy layer that will be removed in a subsequent process to expose the upper and lower surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54, such as silicon-germanium, has high etch selectivity relative to the second semiconductor layer 56. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0021] In another embodiment (not shown), a first semiconductor layer 54 is patterned to form a channel region for a nanostructured field-effect transistor in one region (e.g., p-type region 50P), and a second semiconductor layer 56 is patterned to form a channel region for a nanostructured field-effect transistor in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium, pure germanium, group III-V semiconductor compounds, group II-VI semiconductor compounds, or the like. The second semiconductor material of the second semiconductor layer 56 may be a material suitable for n-type devices, such as silicon, silicon carbide, group III-V semiconductor compounds, group II-VI semiconductor compounds, or the like. The first and second semiconductor materials may have high etch selectivity relative to each other, so that the first semiconductor layer 54 can be removed in the n-type region 50N without significantly removing the second semiconductor layer 56, and the second semiconductor layer 56 can be removed in the p-type region 50P without significantly removing the first semiconductor layer 54.

[0022] The multilayer stack 52 in the diagram includes four first semiconductor layers 54 and four second semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 54 and second semiconductor layers 56. Each layer of the multilayer stack 52 may be formed using growth processes such as vapor phase epitaxy or molecular beam epitaxy, deposition processes such as chemical vapor deposition or atomic layer deposition, or similar processes. In some embodiments, the thickness of some layers of the multilayer stack 52 is less than the thickness of other layers of the multilayer stack 52. For example, the bottommost second semiconductor layer 56 (such as the second semiconductor layer 56 closest to the substrate 50) may be thinner than the upper second semiconductor layers 56 to improve short-channel control of the final nanostructure field-effect transistor. Other combinations or variations in layer thickness are also possible.

[0023] In some embodiments of Figures 3A and 3B, fins 62 are formed in substrate 50, while first nanostructures 64 and second nanostructures 66 are formed in a multilayer stack 52. First nanostructures 64 and second nanostructures 66 can be considered together here as nanostructures 64 / 66. Figure 3A is a cross-sectional view along a section similar to section B-B' in Figure 1, and Figure 3B is a cross-sectional view along a section similar to section A-A' in Figure 1. Figure 3B shows the distal portion of fin 62 and the overlying nanostructures 64 / 66, where nanostructures 64 / 66 and fin 62 are removed to longitudinally terminate fins 62 and nanostructures 64 / 66. The region located in or near fins 62 and nanostructures 64 / 66 is designated as fin distal region 51 in Figure 3B. Figures 3A and 3B may be n-type region 50N or p-type region 50P of substrate 50, unless otherwise stated.

[0024] In some embodiments, nanostructures 64 / 66 and fins 62 may be formed in the multilayer stack 52 and the substrate 50, respectively, and the formation method is to etch trenches in the multilayer stack 52 and the substrate 50. Etching may be any acceptable etching process such as reactive ion etching, neutral beam etching, similar processes, or combinations thereof. Etching may be anisotropic. Etching the multilayer stack 52 to form nanostructures 64 / 66 may further define a first nanostructure 64 from a first semiconductor layer 54 and a second nanostructure 66 from a second semiconductor layer 56.

[0025] The fins 62 and nanostructures 64 / 66 can be patterned by any suitable method. For example, the fins 62 and nanostructures 64 / 66 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, resulting in a pattern pitch that is smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers are subsequently used to pattern the fins 62 and nanostructures 64 / 66. Other patterning techniques are also possible. In some examples, the patternable fin 62 is formed into a continuous fin structure 61, and then the continuous fin structure 61 is separated into separate fins 62 by an isolation region 125, as detailed below in conjunction with Figures 29A to 31G.

[0026] The illustrated fin 62 may have substantially the same width in both the n-type region 50N and the p-type region 50P. In some embodiments, the width of the fin 62 in the n-type region 50N may be greater than the width of the fin 62 in the p-type region 50P. Furthermore, while the fin 62 and nanostructures 64 / 66 in the illustration have fixed widths, in other embodiments, the fins 62 and nanostructures 64 / 66 may have trapezoidal sidewalls, meaning that the width of each of the fins 62 and / or nanostructures 64 / 66 continuously increases in the direction toward the substrate 50. In these embodiments, the widths of the nanostructures 64 / 66 may be different and may be trapezoidal.

[0027] In Figure 4, an insulating material 68 is formed on the substrate 50 and between adjacent fins 62 and adjacent nanostructures 64 / 66. The insulating material 68 may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition, flowable chemical vapor deposition, similar methods, or a combination thereof. Other insulating materials formed by any acceptable process may also be used. In some embodiments, the insulating material 68 comprises silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material 68 is formed, an annealing process can be performed. Although the insulating material 68 in the figures is a single layer, in some embodiments the insulating material 68 may be multilayered. For example, in some embodiments, a pad (not shown) may first be formed along the surfaces of the substrate 50, fins 62, and nanostructures 64 / 66. A filler material (such as the aforementioned insulating material) may then be formed on the pad.

[0028] Insulating material 68 may be deposited on the fins 62 and the nanostructures 64 / 66, such that excess insulating material 68 covers the nanostructures 64 / 66. A removal process is then performed on the insulating material 68 to remove the excess insulating material 68 from the nanostructures 64 / 66. In some embodiments, a planarization process such as chemical mechanical polishing, etch-back, a combination thereof, or a similar process may be used. The planarization process exposes the nanostructures 64 / 66, so that the nanostructures 64 / 66 are flush with the upper surface of the insulating material 68 after the planarization process.

[0029] In some embodiments of Figures 5A and 5B, insulating material 68 is recessed to form shallow trench isolation regions 70. The shallow trench isolation regions 70 are adjacent to fins 62 and may be adjacent to the end portions of fins 62 (e.g., fin end regions 51). The insulating material 68 is recessed such that the upper portions of fins 62 and / or nanostructures 64 / 66 protrude from between adjacent shallow trench isolation regions 70. The upper portions of fins 62 and / or nanostructures 64 / 66 are higher than the shallow trench isolation regions 70. In some examples, portions of fins 62 and / or nanostructures 64 / 66 may be lower than the upper surface of the shallow trench isolation regions 70. Furthermore, the upper surface of the shallow trench isolation regions 70 may be a flat surface, a convex surface, a recessed surface (e.g., dished), or a combination thereof, as illustrated. The upper surface of the shallow trench isolation regions 70 may be flat, convex, and / or recessed by appropriate etching. The shallow trench isolation region 70 can be recessed using an acceptable etching process, such as an etching process selectively etching the insulating material 68 (where the etching rate of the insulating material 68 is greater than the etching rate of the fins 62 and the nanostructures 64 / 66). For example, an oxide removal method using diluted hydrofluoric acid can be used.

[0030] The above process is only one example of how the fins 62 and nanostructures 64 / 66 can be formed. In some embodiments, a masking and epitaxial growth process can be used to form the fins 62 and / or nanostructures 64 / 66. For example, a dielectric layer can be formed on the upper surface of the substrate 50, and trenches can be etched to penetrate the dielectric layer and expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, causing the dielectric layer to be recessed, thus the epitaxial structures protrude from the dielectric layer to form the fins 62 and / or nanostructures 64 / 66. The epitaxial structures may include the aforementioned interleaved semiconductor materials, such as a first semiconductor material and a second semiconductor material. In some embodiments, the method for forming the epitaxial structure is epitaxial growth, in which case the epitaxial growth material can be in-situ doped during growth to omit the preceding and / or subsequent implantation, but in-situ doping and implantation doping can be used in combination.

[0031] In Figures 5A and 5B, suitable wells (not shown) can be formed in the fins 62, nanostructures 64 / 66, and / or shallow trench isolation regions 70. In embodiments with different well morphologies, photoresist or other masks (not shown) can be used to achieve different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed on the fins 62, nanostructures 64 / 66, and shallow trench isolation regions 70 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating technology and patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurities can be implanted in the p-type region 50P, while the photoresist acts as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, or similar substances, and its concentration in the implanted region can be from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. The photoresist can be removed after implantation, and the removal method can be an acceptable ashing process.

[0032] Before or after implanting the p-type region 50P, photoresist or other masks (not shown) can be formed on the fins 62, nanostructures 64 / 66, and shallow trench isolation regions 70 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating technology and patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurities can be implanted in the n-type region 50N, while the photoresist acts as a mask to substantially prevent p-type impurities from implanting into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or the like, and the concentration implanted in the region can be from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. The photoresist can be removed after implantation, and the removal method can be an acceptable ashing process.

[0033] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped to omit implantation, but in-situ doping and implantation doping can be used in combination.

[0034] In other embodiments, a hard mask (not shown) may be formed on the upper surface of the shallow trench isolation region 70 to protect the shallow trench isolation region 70 in subsequent process steps. For example, the hard mask may be formed by first depositing a hard mask material on the nanostructures 64 / 66, the fins 62, and the shallow trench isolation region 70. In some examples, the hard mask material is compliantly deposited to form a continuous layer. The hard mask material is then removed from the upper surface and sidewalls of the nanostructures 64 / 66 and the fins 62 using an etching process, and the remaining portion of the hard mask material on the shallow trench isolation region 70 can form the hard mask. The method for removing the upper portion of the hard mask material may employ an acceptable etching process, such as dry etching, wet etching, or a combination thereof. The hard mask material may include one or more materials that have high etch selectivity relative to the material of the shallow trench isolation region 70 and / or the nanostructures 64 / 66. For example, hard masking materials may include nitrides such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, combinations thereof, or similar materials. In some examples, hard masking materials include oxides such as hafnium oxide, zirconium oxide, or similar materials. In some examples, other materials are also possible, and hard masking materials may include multiple layers of different materials. The deposition method for hard masking materials may employ suitable processes, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar methods.

[0035] In some embodiments of Figures 6A and 6B, a dummy dielectric layer 82, a dummy gate 84, and a mask 86 are formed along the sidewalls and top surface of the fins 62 and / or nanostructures 64 / 66. In some embodiments, the dummy dielectric layer is formed on the fins 62 and / or nanostructures 64 / 66. The dummy dielectric layer may be composed of silicon oxide, silicon nitride, combinations thereof, or the like, and may be formed by deposition or thermal growth according to acceptable techniques. A dummy gate layer is formed on the dummy dielectric layer, and a mask is formed on the dummy gate layer. The dummy gate layer may be deposited on the dummy dielectric layer, and then planarized by a chemical mechanical polishing process or a similar method. The dummy gate layer may be composed of a conductive or non-conductive material, selected from amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicates, metal oxides, or metals. The deposition method for the dummy gate layer can be chemical vapor deposition, physical vapor deposition, sputtering deposition, or another suitable technique. The composition of the dummy gate layer can be other materials, provided they exhibit high etch selectivity relative to insulating materials such as the shallow trench isolation region 70 and / or the dummy dielectric layer. A masking layer can be deposited on the dummy gate layer. The composition of the masking layer can be a dielectric material such as silicon nitride, silicon oxynitride, or the like.

[0036] The mask layer is then patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 can then be transferred to a dummy gate layer and a dummy dielectric layer to form dummy gate 84 and dummy dielectric layer 82, respectively. The dummy gate 84 covers individual channel regions of nanostructures 64 / 66. The pattern of mask 86 can be used to physically separate each adjacent dummy gate 84. The length direction of the dummy gate 84 can also be substantially perpendicular to the length direction of the individual fins 62 (e.g., longitudinal). Mask 86 can be removed after patterning, and the removal method can be any acceptable etching technique. In this example, a single dummy gate layer and a single mask layer are formed to cross the n-type region 50N and the p-type region 50P. In an exemplary embodiment, the dummy dielectric layer covers the shallow trench isolation region 70, such that the dummy dielectric layer 82 extends between the dummy gate 84 and the shallow trench isolation region 70. In another embodiment, the dummy dielectric layer 82 covers only the fins 62 and / or the nanostructures 64 / 66.

[0037] In some embodiments of Figures 7A and 7B, a spacer layer 90 is compliantly formed on the structure. The spacer layer 90 is formed on the nanostructures 64 / 66 and the shallow trench isolation region 70. The spacer layer 90 is also formed on the exposed sidewalls of the mask 86 (if present), the dummy gate 84, the dummy dielectric layer 82, the nanostructures 64 / 66, and / or the fins 62. The spacer layer 90 may be composed of one or more dielectric materials. The spacer layer 90 shown in Figures 7A and 7B is a single layer of dielectric material, but in other embodiments, the spacer layer 90 may be two or more layers of dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, and may be formed by deposition processes such as chemical vapor deposition, atomic layer deposition, or similar methods. Other dielectric materials formed by any acceptable process may also be used. The spacer layer 90 may then be etched to form the spacers.

[0038] In Figures 8A to 8D, the spacer layer 90 is patterned to form the gate spacer 92 and the fin spacer 94. The terminal portion of the fin 62 containing the fin terminal region shown in Figure 8D is similar to that shown in Figure 3B. Any acceptable etching process, such as dry etching, wet etching, similar processes, or combinations thereof, can be performed to pattern the spacer layer 90. The etching can be anisotropic. The etched spacer layer 90 has portions retained on the sidewalls of the dummy gate 84 (thus forming the gate spacer 92) and portions retained on the sidewalls of the fins 62 and / or nanostructures 64 / 66 (thus forming the fin spacer 94). The etched fin spacers 94 and / or gate spacers 92 can have flat or curved sidewalls. In some embodiments, shallow trench isolation regions 70 can also be etched when patterning the spacer layer 90. For example, etching can partially recess the shallow trench isolation area 70 between the fins 62 and / or between the gate spacers 92. The gate spacers 92 and / or the fin spacers 94 may have flat sidewalls (as shown) or curved sidewalls (not shown).

[0039] Furthermore, the implantation used for lightly doped source / drain regions (not shown) can be performed. In embodiments of different device types, similar to the implantation used for the aforementioned well, a mask, such as photoresist, can be formed on the n-type region 50N, exposing the p-type region 50P, and a suitable type of impurity (such as p-type) can be implanted into the exposed fins 62 and nanostructures 64 / 66 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The impurity concentration of the lightly doped source / drain regions can be from about 10¹⁵ atoms / cm³ to about 10¹⁹ atoms / cm³. Annealing can be used to repair damage and revitalize implanted impurities.

[0040] It is worth noting that the above describes a general process for forming spacers and lightly doped source / drain regions. Other processes and sequences can also be used. For example, fewer or additional steps can be used, different step sequences can be used, additional spacers can be formed and removed, and / or similar adjustments can be made. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0041] As shown in some embodiments of Figures 8A to 8D, source / drain recesses 96 are patterned in the fins 62, nanostructures 64 / 66, and substrate 50. Epitaxial source / drain regions are then formed in the source / drain recesses 96. The source / drain recesses 96 may extend through the nanostructures 64 / 66 into the substrate 50. In some embodiments of Figure 8C, the fins 62 may be etched such that the lower surface of the source / drain recesses 96 is lower than the upper surface of the shallow trench isolation region 70. In other embodiments, the lower surface of the source / drain recesses 96 is generally flush with or higher than the upper surface of the shallow trench isolation region 70. The source / drain recesses 96 may be formed using anisotropic etching processes such as reactive ion etching, neutral beam etching, or similar processes to etch the fins 62, nanostructures 64 / 66, and substrate 50. In some embodiments, during the etching process used to form the source / drain recess 96, portions of the gate spacer 92 and dummy gate 84 mask the fins 62, nanostructures 64 / 66, shallow trench isolation regions 70, and / or the substrate 50. A single etching process or multiple etching processes can be used to etch each layer of the nanostructures 64 / 66 and / or fins 62. A time-controlled etching process can be used to stop etching the source / drain recess 96 after it reaches the desired depth. Etching may etch the shallow trench isolation regions 70 to form the recess 96', which may extend into the shallow trench isolation regions 70 between the gate spacers 92. In other embodiments, the shallow trench isolation regions 70 are not etched. For embodiments forming a hard mask on the shallow trench isolation regions 70, etching may stop at the hard mask, thin the hard mask, or remove the hard mask, depending on the characteristics of the etching process.

[0042] In Figures 9A and 9B, the remainder of the first nanostructure 64 is then removed to form an opening 65 in the region between the second nanostructures 66. The remainder of the first nanostructure 64 can be removed via an etching process through a source / drain recess 96. The etching process can include any acceptable etching process that selectively etches the material of the first nanostructure 64 at a rate greater than the rate at which it etches the material of the second nanostructure 66 and the fin 62. The etching process can include a wet etching process and / or a dry etching process, and the etching can be isotropic. For example, when the first nanostructure 64 is composed of silicon germanium and the second nanostructure 66 is composed of silicon or silicon carbide, the etching process can be a wet etching using tetramethylammonium hydroxide, ammonium hydroxide, or the like. In other embodiments, the etching process can be a dry etching using fluorine gas, ammonia, hydrofluoric acid, chlorine trifluoride, xenon trifluoride, or the like. In some embodiments, a trimming process (not shown) is performed to reduce the thickness of the exposed portion of the second nanostructure 66 and enlarge the opening 65. The second nanostructure 66 can then be viewed as a nanostructure, and vertically adjacent second nanostructures 66 on each fin 62 can be viewed as a stack of second nanostructures 66.

[0043] In some embodiments of Figures 10A to 11C, the first nanostructure 64 is replaced with a dummy material 71 to form a dummy region 72. In some examples, the dummy material 71 can be considered a sacrificial material or a sacrificial oxide. In some examples, the dummy region 72 can be considered a sacrificial region, a dielectric dummy region, a dummy nanostructure, a dummy gate region, or a one-time oxide interlayer. Replacing the first nanostructure 64 with the dummy region 72 offers advantages. For example, subsequent source / drain formation steps may involve one or more high-temperature processes to activate the dopants in the source / drain regions. When the first nanostructure 64 (such as silicon-germanium or the like) is exposed to high temperatures, germanium may mix with each other, and the interface roughness between the first nanostructure 64 and the second nanostructure 66 may increase. These manufacturing defects can degrade the performance of the final transistor device. For example, when germanium diffuses into the second nanostructure 66, germanium residue may remain in the channel region of the final transistor device, which may negatively affect the performance of the channel region. Furthermore, mixing can reduce the etch selectivity of the first nanostructure 64 or the second nanostructure 66 and decrease the etch definition. For example, this could result in unwanted removal of portions of the second nanostructure 66, reducing yield and / or degrading performance. Replacing the first nanostructure 64 with an insulating material (such as a dummy material) before high-temperature processes (such as source / drain annealing) can reduce manufacturing defects and improve device performance (e.g., increase drive current, reduce capacitance, and improve short-channel effects). Additionally, the dummy material 71 and the second nanostructure 66 can have high etch selectivity to improve the etch definition and reduce unwanted etching of the second nanostructure 66.

[0044] In some embodiments of Figures 10A and 10B, dummy material 71 is deposited in the source / drain recess 96 and the opening 65. The deposition method for the dummy material 71 may be a compliant deposition process such as chemical vapor deposition, atomic layer deposition, or a similar process. The dummy material 71 may include an insulating material such as silicon oxide or the like, which has etch selectivity relative to the second nanostructure 66 and the fin 62. As shown in Figures 10A and 10B, the dummy material 71 may fill or overfill the opening 65 and may cover the sidewalls of the second nanostructure 66. The dummy material 71 may cover the upper surface of the fin 62. In some embodiments, the dummy material 71 does not completely fill the source / drain recess 96.

[0045] In some embodiments of Figures 11A to 11C, dummy material 71 may be etched to form dummy region 72. Etching may be isotropic or anisotropic. For example, a wet etching process such as dilute hydrofluoric acid or the like may be used to etch the dummy material 71. In some embodiments, etching is performed until the sidewall recesses of the dummy material 71 extend beyond the sidewalls of the second nanostructure 66 to form sidewall recesses 97. In summary, the width of the dummy region 72 is less than the width of the second nanostructure 66. In some examples, the sidewall recesses 97 may be considered as part of the source / drain recesses 96. Although the sidewalls of the dummy region 72 in the illustrated sidewall recesses 97 are flat, the sidewalls may be recessed or protruding. As shown in Figure 11C, the dummy material 71 may be completely removed from the sidewall recesses 97 in the fin end region 51 to expose the dummy gate 84 adjacent to the fin end region 51. In other embodiments, a portion of the etched dummy material 71 may be retained in the sidewall recess 97 in the fin end region 51.

[0046] In some embodiments of Figures 12A to 12C, an inner spacer 98 is formed in the sidewall recess 97. In other words, the inner spacer 98 is formed on the sidewall of the dummy region 72. As detailed below, source / drain regions are subsequently formed in the source / drain recesses, and the dummy region 72 can later be replaced with the corresponding gate structure. The inner spacer 98 serves as an isolation structure between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the inner spacer 98 can be used to prevent subsequent etching processes from damaging the subsequently formed source / drain regions.

[0047] In some embodiments, the inner spacer 98 is formed by conformally depositing an insulating material in the source / drain recess 96 and the sidewall recess 97, followed by etching the insulating material. The insulating material may be silicon nitride, silicon oxynitride, or the like. However, any suitable material, such as a material with a low dielectric constant (less than about 3.5), may be used. The insulating material may be formed by a deposition process such as atomic layer deposition, chemical vapor deposition, or a similar process. The etching method for the insulating material may be anisotropic. For example, the etching process may be dry etching such as reactive ion etching, neutral beam etching, or a similar process. After etching the insulating material, the remaining portion of the insulating material in the sidewall recess 97 forms the inner spacer 98. The thickness of the inner spacer 98 may be less than, approximately equal to, or greater than the thickness of the adjacent dummy region 72.

[0048] Although the outer sidewall of the inner spacer 98 shown in the figure is flush with (approximately coplanar with) the sidewall of the second nanostructure 66, the outer sidewall of the inner spacer 98 may extend beyond or be recessed from the sidewall of the second nanostructure 66. In other words, the inner spacer 98 may partially fill, completely fill, or overfill the sidewall recess 97. Furthermore, although the sidewall of the inner spacer 98 in Figures 12A to 12C is flat, the sidewall of the inner spacer 98 may be recessed or protruding. In one example, the sidewall of the dummy region 72 in the embodiment shown in Figure 13A is arc-shaped, the outer sidewall of the inner spacer 98 is recessed, and the inner spacer 98 is recessed from the sidewall of the second nanostructure 66. In another example, the dummy region 72 in the embodiment shown in FIG13B has an arc-shaped sidewall, the outer sidewall of the inner spacer 98 is flat, and the outer sidewall of the inner spacer 98 is flush with the sidewall of the second nanostructure 66. Other configurations of the sidewall profile are also possible.

[0049] In some embodiments of Figures 14A to 14E, epitaxial source / drain regions 100 are formed within the source / drain recesses 96 of the n-type region 50N and the p-type region 50P. The epitaxial source / drain region 100 can also be considered as a source / drain region. For example, the epitaxial source / drain region 100 in the n-type region 50N can be considered as an n-type epitaxial source / drain region, while the epitaxial source / drain region 100 in the p-type region 50P can be considered as a p-type epitaxial source / drain region. The n-type epitaxial source / drain region 100 can be formed before, after, or simultaneously with the formation of the p-type epitaxial source / drain region 100. The method for forming the epitaxial source / drain region 100 can be an epitaxial process such as vapor phase epitaxy, molecular beam epitaxy, or similar methods.

[0050] In some embodiments, a semiconductor layer 100' may be formed in the source / drain recess 96 before the epitaxial source / drain region 100 is formed in the source / drain recess 96. For example, the semiconductor layer 100' may include undoped silicon or the like. Although the upper surface of the illustrated semiconductor layer 100' is flat, the upper surface of the semiconductor layer 100' may be recessed or protruding. The upper surface of the semiconductor layer 100' may be higher than, nearly flush with, or lower than the upper surface of the fin 62. In some embodiments, the semiconductor layer 100' does not physically contact the inner spacers 98. In other embodiments, the semiconductor layer 100' may physically contact some of the sidewalls of the inner spacers 98. In some examples, the semiconductor layer 100' may be considered as a portion of the corresponding epitaxial source / drain region 100. In other embodiments, an insulating layer (not shown) may be deposited in the source / drain recess 96 before the semiconductor layer 100' and / or the epitaxial source / drain region 100 are formed in the source / drain recess 96. For example, the insulating layer may include a silicon nitride layer, a silicon oxide layer, or the like.

[0051] In some embodiments, the epitaxial source / drain regions 100 apply stress to the channel regions of the second nanostructure 66 in the n-type region 50N and / or the p-type region 50P to improve performance. The epitaxial source / drain regions 100 are formed in the source / drain recesses 96 such that the dummy gates 84 of the p-type region 50P are each located between individual adjacent pairs of epitaxial source / drain regions 100. In some embodiments, gate spacers 92 are used to separate the epitaxial source / drain regions 100 from the dummy gates 84, while inner spacers 98 are used to provide a suitable lateral distance between the epitaxial source / drain regions 100 and the second nanostructure 66, so that the epitaxial source / drain regions 100 are not shorted to the gate subsequently formed by the final nanostructure field-effect transistor.

[0052] The epitaxial source / drain region 100 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the n-type epitaxial source / drain region 100 is epitaxially grown within the source / drain recess 96 in the n-type region 50N. The n-type epitaxial source / drain region 100 can comprise any acceptable material suitable for an n-type nanostructure field-effect transistor. For example, if the second nanostructure 66 is silicon, the material comprising the n-type epitaxial source / drain region 100 can be subjected to tensile stress on the second nanostructure 66, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0053] The epitaxial source / drain region 100 in the p-type region 50P can be formed by masking the n-type region 50N. The p-type epitaxial source / drain region 100 is then epitaxially grown within the source / drain recess 96 in the p-type region 50P. The p-type epitaxial source / drain region 100 can comprise any acceptable material suitable for a p-type nanostructure field-effect transistor. For example, if the second nanostructure 66 is silicon, the material comprising the p-type epitaxial source / drain region 100 can be subjected to compressive stress on the second nanostructure 66, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like.

[0054] Dopants can be implanted into the epitaxial source / drain region 100, the second nanostructure 66, and / or the substrate 50 to form the source / drain region, which can be similar to the process described above for forming lightly doped source / drain regions. Annealing can then be performed. The impurity concentration of the source / drain region can be between about 1 x 10¹⁹ atoms / cm³ and about 1 x 10²¹ atoms / cm³. The n-type and / or p-type impurities used in the source / drain region can be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain region 100 can be in-situ doped during growth.

[0055] Epitaxial source / drain regions 100 are formed in the n-type region 50N and the p-type region 50P using an epitaxial process, resulting in crystal planes on the upper surface of the epitaxial source / drain regions 100 extending laterally beyond the sidewalls of the second nanostructure 66. In some embodiments, adjacent epitaxial source / drain regions 100 remain separated after the epitaxial process is completed, as shown in FIG14C. In other embodiments, these crystal planes cause adjacent epitaxial source / drain regions 100 of the same nanostructure field-effect transistor to merge, as shown in FIG14D. In the embodiments shown in FIG14C and 14D, fin spacers 94 may be formed on the upper surface of the shallow trench isolation region 70 to block epitaxial growth. In some other embodiments, the fin spacers 94 may cover a portion of the sidewalls of the second nanostructure 66 to further block epitaxial growth. In some other embodiments, the spacer etching step used to form the fin spacer 94 can be adjusted to remove the spacer material, allowing the epitaxial growth region to extend to the surface of the shallow trench isolation region 70.

[0056] The n-type epitaxial source / drain region 100 and / or the p-type epitaxial source / drain region 100 may include one or more semiconductor material layers. The epitaxial source / drain region 100 may employ any number of semiconductor material layers. Each semiconductor material layer may be composed of different semiconductor materials and may be doped to different dopant concentrations. In an embodiment where the epitaxial source / drain region 100 includes three semiconductor material layers, a first semiconductor material layer may be deposited, a second semiconductor material layer may be deposited on the first semiconductor material layer, and a third semiconductor material layer may be deposited on the second semiconductor material layer. In some embodiments, the dopant concentration of the first semiconductor material layer may be less than the dopant concentration of the second semiconductor material layer and greater than the dopant concentration of the third semiconductor material layer. Other semiconductor material layers, dopant concentrations, or arrangements are also possible.

[0057] In Figures 15A to 15D, a first interlayer dielectric layer 104 is deposited on the epitaxial source / drain region 100, fin spacer 94, gate spacer 92, mask 86 (if present), and / or dummy gate 84. The first interlayer dielectric layer 104 may be composed of a dielectric material, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. Suitable dielectric materials may include silica, phospholipid glass, borosilicate glass, borosilicate glass, undoped silicate glass, or the like. Other insulating materials formed by any acceptable process may also be used. In some examples, the first interlayer dielectric layer 104 may extend below the upper surface of the shallow trench isolation region 70 and / or below the lower surface of the epitaxial source / drain region 100. In some embodiments, a capping layer (not shown) is formed on the first interlayer dielectric layer 104. For example, the capping layer can be formed by using a dry or wet etching process to recess the first interlayer dielectric layer 104, followed by depositing dielectric material onto the structure. The dielectric material may include one or more materials such as silicon nitride, silicon oxynitride, or the like. A planarization process, such as chemical mechanical polishing or a polishing process, can then be performed to remove excess dielectric material from the structure, leaving the dielectric material remaining on the first interlayer dielectric layer 104 to form the capping layer.

[0058] In some embodiments, a contact etch stop layer 102 is formed between the first interlayer dielectric layer 104 and the epitaxial source / drain region 100, fin spacer 94, gate spacer 92, mask 86 (if present), and / or dummy gate 84. The contact etch stop layer 102 may be composed of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, a combination thereof, or the like, which has high etch selectivity relative to the first interlayer dielectric layer 104, and its formation method may employ any suitable deposition process such as chemical vapor deposition, atomic layer deposition, or similar processes.

[0059] In some embodiments of Figures 16A to 16D, a removal process is performed to make the upper surface of the first interlayer dielectric layer 104 flush with the upper surfaces of the gate spacer 92 and the dummy gate 84. In some embodiments, a planarization process removes a portion of the mask 86 and the gate spacer 92 along the sidewalls of the mask 86. The removal process may include planarization processes such as chemical mechanical polishing, polishing, etch-back, combinations thereof, or similar processes. After the planarization process, the upper surfaces of the first interlayer dielectric layer 104, the gate spacer 92, and the dummy gate 84 may be substantially flush or coplanar (in process variations). Furthermore, the upper surface of the dummy gate 84 may be exposed from the first interlayer dielectric layer 104. In other embodiments, the planarization process does not remove the mask 86. In these embodiments, the first interlayer dielectric layer 104, the gate spacer 92, and the upper surface of the mask 86 after the planarization process may be substantially flush or coplanar (in process variables).

[0060] In Figures 17A to 17D, the mask 86 (if present) and the dummy gate 84 are removed in one or more etching steps to form a recess 108 between the gate spacers 92. In some embodiments, the dummy gate 84 and the dummy dielectric layer 82 may be removed by an isotropic dry etching process. For example, the etching process may include a dry etching process in which the reactive gas selectively etches the material of the dummy gate 84 at a rate greater than the rate at which the material of the first interlayer dielectric layer 104 and the gate spacers 92 are etched. The dummy dielectric layer 82 may serve as an etch stop layer during the etching removal of the dummy gate 84. After the dummy gate 84 is removed, the dummy dielectric layer 82 may be removed.

[0061] In some embodiments of Figures 18A to 18D, the dummy region 72 is removed to extend the recess 108. Methods for removing the dummy region 72 may include performing an isotropic etching process such as wet etching or a similar process. The etchant used in the etching process may be selective for the material of the dummy region 72, while the second nanostructure 66 remains relatively unetched compared to the dummy region 72. In some embodiments, the shallow trench isolation region 70 may be at least partially etched when removing the dummy region 72, but etching parameters (such as time) for removing the dummy region 72 can be controlled to reduce the total loss of the shallow trench isolation region 70. In other embodiments, a hard mask may protect the shallow trench isolation region 70 from etching, and the hard mask may be the hard mask described above in conjunction with Figures 5A and 5B.

[0062] The dummy material 71 of the dummy region 72 can be completely removed, or a residue of the dummy material 71 can be retained on some sidewall portions of the inner spacer 98 in the recess 108 (see Figure 20). After removing the dummy region 72, each recess 108 exposes a portion of the second nanostructure 66, which can serve as a channel region for the subsequently completed nanostructure field-effect transistor. The portion of the second nanostructure 66 serving as the channel region can be located between adjacent pairs of epitaxial source / drain regions 100.

[0063] In some examples, replacing the first nanostructure 64 with a dummy region 72 can reduce the risk of unwanted etching of the epitaxial source / drain region 100 and / or the second nanostructure 66 near the fin end region 51. For example, the etching process used to remove the dummy region 72 is more selective than the etching process used to remove the first nanostructure 64. In this manner, using the dummy region 72 and more selective etching reduces the risk of unwanted etching of the second nanostructure 66. In some examples, unwanted etching of the second nanostructure 66 in the fin end region 51 may cause adjacent epitaxial source / drain regions 100 to be etched or damaged. In summary, using the dummy region 72 and more selective etching reduces the etching of the second nanostructure 66 in the fin end region 51, thus reducing or eliminating the risk of damage to the epitaxial source / drain region 100 near the fin end region 51. In some examples, the probability of damage to the epitaxial source / drain region 100 can be reduced or eliminated in some fin end regions 51 of a continuous fin structure formed by fins 62 with different offsets and / or widths (described in detail below).

[0064] In some embodiments of Figures 19A to 19D, a gate dielectric layer 110 and a gate 112 are formed for the replacement gate structure. The gate dielectric layer 110 is compliantly deposited in the recess 108. The gate dielectric layer 110 may be formed on the upper surface and sidewalls of the substrate 50, and on the exposed upper surface, sidewalls, and lower surface of the second nanostructure 66. The gate dielectric layer 110 may also be deposited on the upper surface of the first interlayer dielectric layer 104, the contact etch stop layer 102, the gate spacer 92, and the shallow trench isolation region 70.

[0065] In some embodiments, the gate dielectric layer 110 includes one or more dielectric layers such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric layer 110 may include a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 110 includes a dielectric material with a high dielectric constant (greater than about 7.0), such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or metal oxides or silicates of combinations thereof. The structures of the gate dielectric layer 110 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 110 may include molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0066] Gate 112 may be deposited on gate dielectric layer 110 and fill the remaining portion of recess 108. Gate 112 may comprise a metallic material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although Figures 19A, 19B, and 19D show a single-layer gate 112, gate 112 may comprise any number of pad layers, any number of work function adjustment layers, and conductive filler material. Gate 112 of any combination of layers may be deposited on the surface of second nanostructure 66.

[0067] Gate dielectric layers 110 in both the n-type region 50N and the p-type region 50P can be formed simultaneously, with the gate dielectric layers 110 in each region having the same material composition. Gates 112 in both the n-type region 50N and the p-type region 50P can also be formed simultaneously, with the gates 112 in each region having the same material composition. In some embodiments, the gate dielectric layers 110 in the n-type region 50N and the p-type region 50P can be formed by separate processes, allowing the gate dielectric layers 110 in each region to be made of different materials and / or have different numbers of layers; and / or the gates 112 in the n-type region 50N and the p-type region 50P can be formed by separate processes, allowing the gates 112 in each region to be made of different materials and / or have different numbers of layers. When using separate processes, suitable areas can be masked and exposed through multiple masking steps.

[0068] After filling the depression 108, a planarization process such as chemical mechanical polishing can be performed to remove excess material from the gate dielectric layer 110 and gate 112 above the upper surface of the first interlayer dielectric layer 104. Therefore, the remaining material of gate 112 and gate dielectric layer 110 can form the substitution gate structure of the final nanostructure field-effect transistor. Gate 112 and gate dielectric layer 110 can be considered together as a gate structure or gate stack.

[0069] Figure 20 is a detailed view of various units in Figure 19A, including epitaxial source / drain regions 100, gate dielectric layer 110, gate 112, second nanostructure 66, and inner spacer 98. Figure 20 may be a partially enlarged view of a nanostructured field-effect transistor in an n-type region 50N or a p-type region 50P. In some embodiments shown in Figure 20, residues of dummy material 71 may be retained on the inner spacer 98, for example, between the inner spacer 98 and the gate dielectric layer 110. For example, the dummy region 72 may not be completely removed, and the gate dielectric layer 110 may be formed on the retained dummy material 71 in the dummy region 72. Since the dummy material 71 is an insulating material (such as silicon oxide or the like), the retained residue does not significantly affect the electrical performance of the final device.

[0070] In some embodiments of Figures 21A and 21B, a gate isolation region 120 is formed in the gate structure. The gate isolation region 120 separates (e.g., cuts) the gate structure into independent gate structures, which may be physically and / or electrically isolated from each other. In some embodiments, the gate isolation region 120 may be formed by first forming a trench (not shown) extending through the gate structure (e.g., through the gate 112 and the gate dielectric layer 110). The trench may be formed using suitable photolithography and etching techniques. The etching may be performed using a wet etching process and / or a dry etching process, which may be anisotropic. An insulating material may then be filled into the trench. The insulating material may include one or more dielectric materials such as silicon nitride, silicon oxide, the like, or combinations thereof. In some examples, a pad or the like may be deposited in the trench before the insulating material is deposited. A planarization process such as chemical mechanical polishing, polishing, or similar processes may then be performed to remove excess insulating material. The retained portion of the insulating material forms the gate isolation region 120. After the planarization process, the gate structure, the gate isolation region 120, the first interlayer dielectric layer 104, and the upper surface of the gate spacer 92 can be flush or coplanar.

[0071] The gate isolation region 120 can extend longitudinally (parallel to the fin 62) and can extend between adjacent fins 62. As shown in FIG21B, the gate isolation region 120 extends completely through the gate structure and into the shallow trench isolation region 70. The gate isolation region 120 can extend below the upper surface of the shallow trench isolation region 70. Since the gate isolation region 120 is formed after the gate structure is formed, the gate dielectric layer 110 does not cover the sidewall of the gate isolation region 120, but the position where the gate dielectric layer 110 physically contacts the lower portion of the gate isolation region 120 can be the position where the gate isolation region 120 passes through the gate dielectric layer 110. In summary, the gate 112 covers the upper sidewall of the gate isolation region 120. In embodiments where the gate 112 comprises multiple layers (such as a padding layer, a work function adjustment layer, a conductive filler material, or the like), the location where each layer of the gate 112 physically contacts the gate isolation region 120 may be the location where the gate isolation region 120 passes through the layers of the gate 112. In some examples, the conductive filler material of the gate 112 may cover the upper sidewall of the gate isolation region 120. The gate isolation region 120 shown in Figure 21B is an example, but the gate isolation region 120 may have other heights, widths, or sidewall profiles than those shown in the figure. The gate isolation region 120 may be formed as appropriate, and other embodiments do not form a gate isolation region 120.

[0072] Figures 22A to 27D are diagrams illustrating the formation of isolation regions 125 between fins 62 in some embodiments. Isolation regions 125 can physically separate adjacent fins 62. In some examples, isolation regions 125 can separate (cut) continuous fin structures (detailed below) into independent fins 62, which can be physically and electrically isolated from each other. Isolation regions 125 can also separate gate structures into independent gate structures, which can be physically and / or electrically isolated from each other. In some examples, isolation regions 125 can be considered as isolation structures, dielectric plugs, dummy fins, or the like. In some examples, isolation regions 125 can be considered as isolation regions of continuous metal on-diffusion edge (CMODE), cut metal on-diffusion edge (CMODE), or continuous polysilicon on-diffusion edge (CPODE).

[0073] In Figures 22A to 22D, a hard masking layer 122 is formed on the gate structure, the first interlayer dielectric layer 104, the gate spacer 92, and the gate isolation region 120. In some embodiments, the hard masking layer 122 may be a single layer of a suitable dielectric material such as silicon nitride, silicon oxynitride, or the like. In some embodiments, the hard masking layer 122 is a multilayer structure containing layers of different materials. For example, the hard masking layer 122 may include a silicon layer sandwiched between two silicon nitride layers. The material of the hard masking layer 122 may be formed using suitable techniques, such as chemical vapor deposition or similar techniques. Other materials or formation techniques are also possible.

[0074] In some embodiments of Figures 23A to 23D, the opening 123 is patterned in the hard mask layer 122. The opening 123 defines a region in the structure that is subsequently replaced by the isolation region 125. As shown in Figures 23A to 23D, the opening 123 exposes a portion of the gate 112. As shown in Figure 23B, the opening 123 may expose the gate structure on one side of the gate isolation region 120, while the hard mask layer 122 still covers the gate structure on the opposite side of the gate isolation region 120. As shown in Figure 23D, the opening 123 may expose the gate structure adjacent to the fin end region 51. The opening 123 may be formed using suitable photolithography and etching techniques. For example, an etched mask, such as photoresist, a multilayer mask structure, or the like, may be formed on the hard mask layer 122, and the etched mask may be patterned. The pattern of the etched mask corresponds to the opening 123. The pattern may then be transferred to the hard mask layer 122 using an etching process to form the opening 123. The etching process may include one or more wet etching processes or dry etching processes, which may be anisotropic. The etch mask may then be removed using appropriate techniques such as etching, ashing, polishing, or similar techniques.

[0075] In some embodiments of Figures 24A to 24D, a portion of the gate structure exposed by opening 123 is removed. In some embodiments, the method for removing a portion of the gate structure may employ one or more selective etching processes that etch the gate 112 and the gate dielectric layer 110 without significantly etching the second nanostructure 66, fins 62, gate spacers 92, inner spacers 98, shallow trench isolation region 70, and / or gate isolation region 120. The etching process may include a wet etching process or a dry etching process, which may be isotropic or anisotropic. For example, some embodiments employ a wet etching process to remove the gate structure. After the etching process, the gate 112 and the gate dielectric layer 110 in the exposed portion of the gate structure are removed (e.g., completely removed), and opening 123 may extend downward through the gate structure to expose the upper surface of the shallow trench isolation region 70. Opening 123 may expose the second nanostructure 66 surrounding the exposed portion of the gate structure. In other words, the etching process exposes the upper surface, lower surface, and / or sidewall surfaces of the second nanostructure 66. Furthermore, the upper portion of the fin 62 and the upper surface of the shallow trench isolation region 70 are exposed. Removing the gate structure from the opening 123 exposes the sidewall surfaces of the fin end region 51. For example, the gate isolation region 120, gate spacer 92, inner spacer 98, and the sidewalls of the second nanostructure 66 are exposed. In embodiments where the gate isolation region 120 is not formed, the selective etching process can be anisotropic, which can reduce damage (or unintended etching) to the sidewalls of the gate 112 exposed by the opening 123.

[0076] In some embodiments of Figures 25A to 25D, an anisotropic etching process is performed to extend the opening 123 through the second nanostructure 66 and the fin 62. In some embodiments, the portion of the second nanostructure 66 and the fin 62 exposed by the opening 123 may be completely removed. In some embodiments, the opening 123 may extend through a portion of the shallow trench isolation region 70 into the substrate 50. For example, the anisotropic etching process may include a dry plasma etching process or a similar process. In some embodiments, the anisotropic etching process may include multiple cycles of passivation layer deposition steps and anisotropic etching steps. The anisotropic etching process may be performed until the opening 123 reaches a target depth, such as below the depth of the upper surface of the substrate 50.

[0077] In Figures 26A to 26D, one or more insulating materials are deposited over the rigid mask layer 122 and within the opening 123 to form the isolation region 125. In some embodiments, a pad layer 124 is compliantly deposited over the rigid mask layer 122 and within the opening 123. The pad layer 124 may comprise a single layer or multiple layers of insulating material. A filler material 126 is then deposited on the pad layer 124 to fill the opening 123. For example, the insulating material may comprise dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low dielectric constant materials, the like, combinations thereof, or multiple layers thereof. Any suitable formation technique may be employed, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar techniques. For example, in some embodiments, the pad layer 124 comprises an oxide material, while the filler material 126 comprises a nitride material. Other materials, layers, or formation techniques are also possible.

[0078] In some embodiments of Figures 27A to 27D, a planarization process is performed to remove excess insulating material and hard masking layer 122. Retained portions of the insulating material (such as padding layer 124 and filler material 126) form isolation region 125. For example, the planarization process may include a chemical mechanical polishing process, a polishing process, or a similar process. After the planarization process, the isolation region 125, the gate structure, the gate spacer 92, and the upper surface of the first interlayer dielectric layer 104 may be flush with or coplanar with each other. In some embodiments, the isolation region 125 may extend along a portion of the fin end region 51 and may separate adjacent fin end regions 51. As shown in Figures 27B and 27D, the layers of the gate structure (such as gate dielectric layer 110 and gate 112) may have a gate isolation region 120 with the isolation region 125, so that the layers of the gate structure do not physically contact the sidewalls of the isolation region 125. Furthermore, since the isolation region 125 is formed after the gate structure is formed, the gate dielectric layer 110 does not extend along the sidewall of the isolation region 125.

[0079] In some embodiments of Figures 28A to 28C, a second interlayer dielectric layer 130 is deposited on the gate spacer 92, the contact etch stop layer 102, the first interlayer dielectric layer 104, the gate structure, the gate isolation region 120, and the isolation region 125. In some embodiments, the second interlayer dielectric layer 130 is a flowable chemical vapor deposition (CVD) layer. In some embodiments, the second interlayer dielectric layer 130 is composed of a dielectric material such as phospholipid glass, borosilicate glass, borosilicate glass, undoped silicate glass, or the like, and its formation method can be any suitable deposition process such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar processes.

[0080] In some embodiments, an etch stop layer 128 may be formed prior to the deposition of the second interlayer dielectric layer 130. The etch stop layer 128 may be composed of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by any suitable deposition process such as chemical vapor deposition, atomic layer deposition, or similar processes, and has high etch selectivity relative to the second interlayer dielectric layer 130.

[0081] In other embodiments, the gate structure (containing the gate dielectric layer 110 and the corresponding upper gate 112) is recessed, so that the recess (not shown) is formed directly on the gate structure between portions of the gate spacers 92 on both sides. A gate mask (not shown) containing one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like can be filled into the recess, followed by a planarization process to remove excess dielectric material. The gate contact (as described below, gate contact 132) then forms through the gate mask to contact the upper surface of the recessed gate 112.

[0082] In Figures 28A to 28C, a gate contact 132 and a source / drain contact 134 are formed to contact the gate 112 and the epitaxial source / drain region 100, respectively. The gate contact 132 is physically and electrically coupled to the gate 112. The source / drain contact 134 is physically and electrically coupled to the epitaxial source / drain region 100.

[0083] In the example of forming the gate contact 132 and the source / drain contact 134, the opening used to form the gate contact 132 passes through the second interlayer dielectric layer 130 and the etch stop layer 128, and the opening used to form the source / drain contact 134 passes through the second interlayer dielectric layer 130, the etch stop layer 128, the first interlayer dielectric layer 104, and the contact etch stop layer 102. The openings can be formed using acceptable photolithography and etching techniques. A pad (not shown, such as a diffusion barrier layer, adhesive layer, or the like) and conductive material are formed in the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the surface of the second interlayer dielectric layer 130. The retained gasket and conductive material can form the gate contact 132 and the source / drain contact 134 within the opening. The gate contact 132 and the source / drain contact 134 can be formed by separate processes or by the same process. Although the gate contact 132 and the source / drain contact 134 are shown in the same cross-section, it should be understood that the gate contact 132 and the source / drain contact 134 can each be formed in different cross-sections to avoid short circuits.

[0084] A metal-semiconductor alloy region 133 may be formed at the interface between the epitaxial source / drain region 100 and the source / drain junction 134, depending on the situation. The metal-semiconductor alloy region 133 may be a silicate region composed of metal silicates (such as titanium silicates, cobalt silicates, nickel silicates, or the like), a germanium region composed of metal germanides (such as titanium germanides, cobalt germanides, nickel germanides, or the like), a silica-germanium region composed of metal silicates and metal germanides, or the like. Metal may be deposited in the opening used for the source / drain junction 134 before the material forming the source / drain junction 134, followed by a thermal annealing process to form the metal-semiconductor alloy region 133. The metal can be any metal-semiconductor alloy capable of reacting with the semiconductor material (such as silicon, silicon carbide, silicon germanium, germanium, or the like) of the epitaxial source / drain region 100 to form a drop resistance, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be formed by deposition processes such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar processes. After the thermal annealing process, a cleaning process such as wet cleaning can be performed to remove any residual metal from the openings used for the source / drain contacts 134, for example, from the surface of the metal-semiconductor alloy region 133. The material for forming the source / drain contacts 134 can then be applied to the metal-semiconductor alloy region 133.

[0085] In some embodiments, the isolation region 125 may be used to separate (e.g., cut) the continuous fin structure 61 into a plurality of isolated fins 62. In summary, Figures 29A to 29C are plan views of the continuous fin structure 61 before separation in some embodiments. Figures 30A to 30D are plan views of the continuous fin structure 61 after separation by the isolation region 125 in some embodiments. The continuous fin structure 61 and fins 62 are illustrative examples, and the continuous fin structure 61 and fins 62 in other embodiments may have other sizes, shapes, or configurations. Figures 31A to 31G also show non-limiting examples of the continuous fin structure 61, as detailed below. Although Figures 29A to 31G illustrate continuous fin structures 61 and fins 62, stacks of second nanostructures 66 are typically present on top of the continuous fin structure 61 and fins 62. For example, the isolation region 125 may also separate a continuous stack of second nanostructures 66 into a plurality of isolated stacks of second nanostructures 66. In summary, the following information regarding the continuous fin structure 61 and fin 62 can also be applied to the stacking of the second nanostructure 66 on the continuous fin structure 61 and fin 62.

[0086] Figures 29A to 29C are plan views of a continuous fin structure 61 in some embodiments. The continuous fin structure 61 may be a continuous structure formed by fin portions 62' (such as fin portions 62A', fin portions 62B', and the like), which may then be separated into corresponding individual fins 62 (such as fins 62A, fins 62B, and the like) by one or more isolation regions 125. The continuous fin structure 61 may be formed by appropriately patterning a multilayer stack 52, similar to the description above in conjunction with Figures 3A and 3B. In summary, the continuous fin structure 61 can be considered as a continuous structure formed from a multilayer stack 52. The fin portions 62' of the continuous fin structure 61 may include fin portions 62' offset from each other and / or different fin portions 62' with different widths. As shown in Figure 1, the longitudinal axis of the fin portion 62' extends parallel to section A-A', while the isolation region 125 may extend in a vertical direction, such as section B-B' or C-C'. In summary, in some embodiments, two fin portions 62' (e.g., fin portion 62A' and fin portion 62B') may be offset (e.g., vertically offset) in a direction perpendicular to the longitudinal direction of the fin portion 62'. For example, the offset direction may be parallel to the direction of section B-B' or C-C'. In a plan view, the sides of the continuous fin structure 61 may be stepped, as the sidewall of one fin portion 62' is vertically offset from the sidewall of the adjacent fin portion 62'. Forming the isolation region 125 to divide the continuous fin structure 61 into independent fins 62 allows the fins 62 of the device to be closer together, reducing device size and increasing device density. Figures 29A to 29C also show the fin end region 51 and the offset end region 51' of the continuous fin structure 61. The offset end region 51' is similar to the fin end region 51, except that the offset end region 51' is the end region of the continuous fin structure 61 formed by the offset of the fin portion 62' and / or different widths. In summary, the offset end region 51' may include the end region located at the corner where different fin portions 62' of the continuous fin structure 61 meet. In some embodiments, an isolation region 125 is subsequently formed in or near the offset end region 51'. In some examples, the aforementioned dummy region 72 can reduce damage to the second nanostructure 66 located in the offset end region 51' and / or the epitaxial source / drain region 100, similar to the description above in conjunction with Figures 18A to 18D.

[0087] The continuous fin structure 61 shown in Figure 29A includes a continuous, wider fin portion 62A' and a narrower fin portion 62B'. An isolation region 125 is then formed between the fin portions 62A' and 62B' to form isolated and separate fins 62A and 62B (see Figure 30A). As shown in Figure 29A, each of the fin portions 62A' and 62B' has a fin tip region 51. Because the fin portion 62B' is narrower than the fin portion 62A', the offset tip region 51' of the fin portion 62A' is adjacent to the fin portion 62B'.

[0088] The continuous fin structure 61 in Figure 29B is similar to the continuous fin structure 61 in Figure 29A, except that the continuous fin structure 61 in Figure 29B includes a wide fin portion 62A' and two narrow fin portions 62B' and 62C'. An isolation region 125 is then formed between the fin portions 62A' and 62B' and 62C' to form isolated and separated fins 62A to 62C (see Figure 30B). As shown in Figure 29B, each of the fin portions 62A', 62B', and 62C' has a fin tip region 51. Because the fin portions 62B' and 62C' are narrower than the fin portion 62A', the off-tip region 51' of the fin portion 62A' is located between the fin portions 62B' and 62C'. In other embodiments, the continuous fin structure 61 may include a wide fin portion and more than two narrow fin portions.

[0089] The continuous fin structure 61 in Figure 29C is similar to the continuous fin structure 61 in Figure 29A, except that the continuous fin structure 61 in Figure 29C includes two offset fin portions 62A' and 62B'. Fin portions 62A' and 62B' may have the same width or different widths. An isolation region 125 is then formed between fin portions 62A' and 62B' to form separate and isolated fins 62A and 62B (see Figure 30C). As shown in Figure 29C, each fin portion 62A' and 62B' has a fin tip region 51. Because fin portions 62A' and 62B' are offset from each other, each fin portion 62A' and 62B' also has an offset tip region 51'.

[0090] Figures 30A to 30C are diagrams showing the division of the continuous fin structure 61 of Figures 29A to 29C into individual fins 62 after the isolation region 125 is formed. For example, the isolation region 125 of Figure 30A forms two separate fins 62A, the isolation region 125 of Figure 30B forms three separate fins 62A, 62B, and 62C, and the isolation region 125 of Figure 30C forms two separate fins 62A and 62B. The materials and techniques for forming the isolation region 125 are similar to those described above in conjunction with Figures 22A to 27D. As shown in Figures 30A to 30C, the isolation region 125 can be formed in the off-end region 51', such that the fin off-end region 51 of the isolated fins 62 is formed on one or both sides of the isolation region 125. In some examples, the isolation region 125 can be used to make the separation distance S1 (e.g., end-to-end distance) of the fin 62 about 20 nm to about 80 nm, but other separation distances are also possible. In some examples, the isolation region 125 may be located at or near the end region 51 of the fin (as shown in Figure 30D), and the three isolation regions 125 divide the continuous fin structure 61 of Figure 29A into fins 62A and 62B.

[0091] Figures 31A to 31G are diagrams of various continuous fin structures 61 in some embodiments. The examples in Figures 31A to 31G are not limiting examples, and other shapes, arrangements, or configurations of the continuous fin structures 61 are also possible. For example, the fin portions 62' of the continuous fin structure 61 (such as fin portion 62A', fin portion 62B, or the like) may have a width or offset different from those shown in the figures, or the fin portions 62' of a single continuous fin structure 61 may have a number or configuration different from those shown in the figures.

[0092] The continuous fin structure 61 shown in Figure 31A is composed of fin portions 62A' and fin portions 62B'. For example, the continuous fin structure 61 shown in Figure 31A can be further divided into fins 62A and fins 62B by an isolation region 125. The width WA of fin 62A is about 5 nm to about 120 nm, and the width WB of fin 62B is about 5 nm to about 120 nm, and the width WB is less than the width WA. The deviation D1 between fins 62A and fin 62B can be about 0 nm to about 115 nm, and the deviation D2 can be about 0 nm to about 115 nm, therefore D1 + D2 = WA - WB. The continuous fin structure 61 shown in Figure 31B is formed by fin-shaped portions 62A' and 62B'. The width WA of fin-shaped portion 62A' is approximately 5 nm to approximately 120 nm, and the width WB of fin-shaped portion 62B' is approximately 5 nm to approximately 120 nm, with WB being less than the width WA. The deviation D1 between fin-shaped portions 62A' and 62B' can be approximately 0 nm to approximately 115 nm, therefore D1 = WA - WB. The continuous fin structure 61 shown in Figure 31C is formed by fin-shaped portions 62A' and 62B'. The width WA of fin-shaped portion 62A' is approximately 5 nm to approximately 120 nm, and the width WB of fin-shaped portion 62B' is approximately 5 nm to approximately 120 nm, with WB being less than the width WA. The deviation D2 between fin-shaped portions 62A' and 62B' can be approximately 0 nm to approximately 115 nm, therefore D2 = WA - WB.

[0093] The continuous fin structure 61 shown in Figure 31D is formed by fin-shaped portions 62A' and 62B'. The width WA of fin-shaped portion 62A' is about 5 nm to about 120 nm, while the width WB of fin-shaped portion 62B' is about 5 nm to about 120 nm. Fin-shaped portion 62A' is offset from fin-shaped portion 62B'. The deviation D1 between fin-shaped portion 62A' and fin-shaped portion 62B' can be between about 0 nm and about 115 nm, while the deviation D2 can be between about 0 nm and about 115 nm.

[0094] The continuous fin structure 61 shown in Figure 31E is formed by fin-shaped portions 62A', 62B', and 62C'. The width WA of fin-shaped portion 62A' is approximately 20 nm to approximately 120 nm, the width WB of fin-shaped portion 62B' is approximately 5 nm to approximately 120 nm, and the width WC of fin-shaped portion 62C' is approximately 5 nm to approximately 120 nm, such that the widths WB and WC are each smaller than the width WA. The deviation D3 between fins 62B and 62C is approximately 5 nm to approximately 110 nm, therefore WB + WC + D3 = WA. The continuous fin structure 61 shown in Figure 31F is formed by fin-shaped portions 62A', 62B', and 62C'. The width WA of fin-shaped portion 62A' is about 20 nm to about 120 nm, the width WB of fin-shaped portion 62B' is about 5 nm to about 120 nm, and the width WC of fin-shaped portion 62C' is about 5 nm to about 120 nm, such that widths WB and WC are each smaller than width WA. The deviation D1 between fin 62B and fin 62A can be about 0 nm to about 105 nm, the deviation D2 between fin 62C and fin 62A can be about 0 nm to about 105 nm, and the deviation D3 between fin 62B and fin 62C can be about 5 nm to about 110 nm. Therefore, WB + WC + D1 + D2 + D3 = WA. The continuous fin structure 61 shown in Figure 31 is formed by fin-shaped portions 62A', 62B', and 62C'. The width WA of fin-shaped portion 62A' is about 15 nm to about 120 nm, the width WB of fin-shaped portion 62B' is about 5 nm to about 120 nm, and the width WC of fin-shaped portion 62C' is about 5 nm to about 120 nm. Fin-shaped portion 62B' is offset from fin-shaped portions 62B' and fin-shaped portion 62C'. The deviation D1 between fin-shaped portion 62B and fin-shaped portion 62A can be about 0 nm to about 105 nm, the deviation D2 between fin-shaped portion 62C and fin-shaped portion 62A can be about 0 nm to about 105 nm, and the deviation D3 between fin-shaped portion 62B and fin-shaped portion 62C can be about 5 nm to about 110 nm. Other widths or deviations are also possible.

[0095] Figures 32A to 39 show intermediate steps in the formation of a nanostructured field-effect transistor from the continuous fin structure 61 in some embodiments. As detailed below, the isolation region 125 divides the continuous fin structure 61 into individual fins 62A to 62E. Many materials, techniques, and structures in Figures 32A to 39 are similar to those illustrated above with reference to Figures 2 to 27D, and some details are not repeated below. Figures 32A and 32B are plan views of the continuous fin structure 61 in some embodiments. Similar to the above, the continuous fin structure 61 includes fins 62 and an upper second nanostructure 66. As shown in Figures 32A and 32B, the continuous fin structure 61 includes fin portions 62A', 62B', 62C', 62D', and 62E', and some fin portions have different widths and / or offsets. The subsequently formed isolation region 125 divides the continuous fin structure 61 into a nanostructured field-effect transistor device containing fins 62A, a nanostructured field-effect transistor device containing fins 62B and 62C, and a nanostructured field-effect transistor device containing fins 62D and 62E. Each nanostructured field-effect transistor device may include one or more nanostructured field-effect transistors, which share the same gate structure.

[0096] The cross section A1-A1' shown in Figure 32A passes through fin portions 62B' and 62D', and the cross section A2-A2' passes through fin portion 62A'. Cross sections A1-A1' and A2-A2' are similar to cross section A-A' in Figure 1. Cross sections B1-B1' and B2-B2' shown in Figure 32 are similar to cross section B-B' in Figure 1. The cross sections shown in Figures 33A, 34A, 35A, 36A, and 37A follow a cross section similar to cross section A1-A1' in Figure 32A. The cross sections shown in Figures 33B, 34B, 35B, 36B, and 37B follow a cross section similar to cross section A2-A2' in Figure 32A. The cross sections shown in Figures 33C, 34C, 35C, 36C, and 37C follow a cross section similar to cross section B1-B1' in Figure 32A. The sectional views shown in Figures 33D, 34D, 35D, 36D, and 37D follow a section similar to section B2-B2' in Figure 32A.

[0097] The continuous fin structure 61 shown in Figure 32A corresponds to the process steps shown in Figures 3A and 3B. Figure 32B is a plan view of the continuous fin structure 61 after the gate structure and gate isolation region 120 are formed in some embodiments. The continuous fin structure 61 shown in Figure 32B corresponds to the process steps shown in Figures 21A and 21B. As shown in Figure 32B, the gate structure extends through the fin portions 62A' to 62E' and through a portion of the continuous fin structure 61 between the fin portions 62' and 62B' to 62E' (which includes the off-end region 51'). An example of the off-end region 51' is shown in Figure 32A.

[0098] Some embodiments of Figures 33A to 33D show the structure after the hard mask layer 122 has been formed. The materials and techniques used to form the structures shown in Figures 33A to 33D are similar to those described in conjunction with Figures 2 to 22D. In summary, the hard mask layer 122 can be similar to the hard mask layer 122 of Figures 22A to 22D and can be formed by similar techniques.

[0099] In some embodiments of Figures 34A to 34D, patterned openings 123 are formed in the hard mask layer 122. Openings 123 may be similar to those shown in Figures 23A to 23D and may be formed using similar techniques. For example, openings 123 expose gate structures, and in some examples, the gate structures may be adjacent to the fin tip region 51 and / or the gate isolation region 120.

[0100] In some embodiments of Figures 35A to 35D, one or more etching processes are performed to extend the opening 123 through the gate structure, the second nanostructure 66, and the fin 62. In some embodiments, portions of the gate structure, the second nanostructure 66, and the fin 62 exposed by the opening 123 may be completely removed. The opening 123 may extend through a portion of the shallow trench isolation region 70 into the substrate 50. The etching technique used to extend the opening 123 may be similar to that described above in conjunction with Figures 24A to 25D. For example, in some embodiments, the method for removing the gate structure may employ a wet etching process, while the method for removing the second nanostructure 66 and the fin 62 may employ an isotropic dry etching process.

[0101] After one or more etching processes, the lower surface of the opening 123 may be flat, recessed, convex, irregular, or have other shapes. For example, in some examples, the lower surface of the opening 123 may have a serrated or fan-shaped shape, as shown in Figures 35C and 35D. For example, the selectivity of one or more etching processes can be controlled to control the shape or profile of the lower surface of the opening 123. For example, if the etching process etches oxide at a rate greater than that of silicon, the serration in the lower surface of the opening 123 may correspond to the location where the opening 123 extends through the shallow trench isolation region 70, the first interlayer dielectric layer 104, or the like. In another example, if the etching process etches silicon at a rate greater than that of oxide, the serration in the lower surface of the opening 123 may correspond to the location where the opening 123 extends through the fin 62. In some examples, etching processes with approximately the same selectivity between silicon and oxide can result in a flatter lower surface of the opening 123. For example, using more boron trichloride in the etching process can increase the etching rate of oxides relative to silicon, although other etchants or process gases may also be possible. These are for illustrative purposes only, and other conditions, etching parameters, etchants, structural setups, or structural features may affect the shape of the lower surface of opening 123.

[0102] In some embodiments of Figures 36A to 36D, insulating material for the deposition isolation region 125 is deposited over the rigid mask layer 122 and within the opening 123. The insulating material may be similar to that described above with reference to Figures 26A to 26D and may be formed using similar techniques. For example, in some embodiments, a padding layer 124 is compliantly deposited, followed by the deposition of a filler material 126 on the padding layer 124 to fill the opening 123. In some embodiments, the padding layer 124 comprises an oxide material, while the filler material 126 comprises a nitride material. Other materials, layers, or formation techniques are also possible.

[0103] In some embodiments of Figures 37A to 37D, a planarization process is performed to remove excess insulating material and the hard mask layer 122 to form an isolation region 125. After the planarization process, the remaining portions of the padding layer 124 and the filler material form the isolation region 125. The planarization process may be similar to that described above with reference to Figures 27A to 27D. For example, the planarization process may include a chemical mechanical polishing process, a polishing process, or a similar process. In some embodiments, the isolation region 125 may extend along a portion of the fin end region 51 and may separate adjacent fin end regions 51. Subsequent processes may be performed, such as similar process steps described above with reference to Figures 28A to 28C.

[0104] Figure 38 is a plan view of fins 62A to 62E after the formation of isolation region 125 in some embodiments. The plan view of Figure 38 corresponds to the cross-sectional views of Figures 37A to 37D. As shown in Figure 38, isolation region 125 can separate the continuous fin structure 61 into separate fins 62A, 62B, 62C, 62D, and 62E. The cross-section A3-A3' shown in Figure 38 passes through fins 62A and 62E, corresponding to the cross-sectional view of Figure 39. Cross-section A3-A3' is similar to cross-section A-A' in Figure 1. Figure 39 is a cross-sectional view of fins 62A and 62E of Figure 38 in some embodiments. As shown in Figure 39, isolation region 125 can separate fins 62 and thus extends between the fin end regions 51.

[0105] The embodiments offer several advantages. The techniques described herein allow for the formation of isolation regions after the gate structure is formed, without increasing the risk of etch damage to the nanostructure or source / drain regions. Forming isolation regions after the gate structure allows for smaller separation between fins. Furthermore, forming isolation regions after, rather than before, the gate structure avoids process challenges such as polysilicon deformation or structural bending. Using dummy regions described herein improves the etch selectivity of exposed nanostructures before the gate structure is formed, reducing the risk of etch damage to the nanostructure or source / drain regions. Specifically, using dummy regions reduces the risk of etch damage to offset regions between fins and / or fins of varying widths. Therefore, the techniques described herein can improve yield, increase device density, and improve layout flexibility.

[0106] In one embodiment, a method for forming a semiconductor device includes forming a fin-like structure on a substrate; forming a plurality of first nanostructures and a plurality of second nanostructures on the fin-like structure, wherein the first nanostructures and individual second nanostructures are continuous structures; forming a plurality of first dielectric dummy regions between the first nanostructures and a plurality of second dielectric dummy regions between the second nanostructures; forming a plurality of first source / drain regions adjacent to the first nanostructures and forming a plurality of second source / drain regions adjacent to the second nanostructures; performing an etching process to remove the first dielectric dummy regions and the second dielectric dummy regions; depositing a plurality of gate structure layers on the first nanostructures and the second nanostructures; and forming an isolation region between the first nanostructures and the second nanostructures, wherein the isolation region physically separates the first nanostructures and the second nanostructures. In one embodiment, the first dielectric dummy region comprises an oxide material. In one embodiment, the first nanostructure is wider than the second nanostructure. In one embodiment, the step of forming the first dielectric dummy region includes depositing a dielectric material on the first nanostructure and the second nanostructure; and etching the dielectric material to expose the sidewalls of the first nanostructure and the second nanostructure. In one embodiment, the isolation region extends below the upper surface of the substrate. In one embodiment, the step of forming the isolation region includes forming an opening in the gate structure layer and depositing an insulating material in the opening. In one embodiment, the sidewalls of the first nanostructure are offset from the sidewalls of the second nanostructure. In one embodiment, the method further includes forming a gate isolation region extending through the gate structure layer.

[0107] In one embodiment, a method of forming a semiconductor device includes forming a first nanostructure stack adjacent to a second nanostructure stack, wherein the first and second nanostructure stacks include a plurality of first nanostructures and a plurality of second nanostructures, wherein a first sidewall of the first nanostructure stack is adjacent to a second sidewall of the second nanostructure stack, and wherein the first sidewall is perpendicularly offset from the second sidewall; replacing the first nanostructures of the first and second nanostructure stacks with a plurality of dielectric regions; replacing the dielectric regions of the first and second nanostructure stacks with a continuous gate structure; and replacing a portion of the continuous gate structure with an isolation region, wherein the isolation region extends between the first and second nanostructure stacks. In one embodiment, prior to the step of replacing a portion of the continuous gate structure with an isolation region, the first and second nanostructure stacks are a continuous structure. In one embodiment, the first semiconductor material of the first nanostructure is different from the second semiconductor material of the second nanostructure. In one embodiment, the step of replacing a portion of the continuous gate structure with an isolation region includes performing a first etching process that removes a portion of the continuous gate structure to form an opening; performing a second etching process that removes a second nanostructure from the portion of the continuous gate structure to expand the opening; and filling the opening with an insulating material. In one embodiment, the step of replacing the dielectric region includes etching the dielectric region with an etchant, wherein the etchant selectively etches the dielectric region at a rate greater than the rate at which the second nanostructure is etched. In one embodiment, a portion of the dielectric region remains on the sidewall of the continuous gate structure.

[0108] In one embodiment, the semiconductor device includes a first fin and a second fin located on a semiconductor substrate, wherein a first width of the first fin is different from a second width of the second fin; a plurality of first nanostructures are located on the first fin; a plurality of second nanostructures are located on the second fin; a first gate structure is located on the first fin, wherein the first gate structure separates individual adjacent first nanostructures; and a second gate structure is located on the second fin, wherein the second gate structure separates individual adjacent second nanostructures; and an isolation structure extending from the first fin to the second fin, wherein the isolation structure protrudes into the semiconductor substrate. In one embodiment, the distance between the first fin and the second fin is 20 nm to 80 nm. In one embodiment, the semiconductor device further includes a shallow trench isolation region surrounding the first fin, wherein the isolation structure extends between the first fin and the shallow trench isolation region. In one embodiment, the difference between the first width and the second width is 5 nm to 115 nm. In one embodiment, the semiconductor device further includes a third fin located on the semiconductor substrate, wherein an isolation structure extends from the first fin to the third fin. In one embodiment, the isolation structure completely covers the sidewall of the first fin.

[0109] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

[0110] A-A',A1-A1',A2-A2',A3-A3',B-B',B1-B1',B2-B2',C-C': Section D1, D2, D3: Deviation S1: Separation distance WA, WB, WC: Width 50:Substrate 50N: n-type region 50P: p-type area 51: Fin terminal area 51': Deviation from the end region 52: Multi-layer stacking 54: First semiconductor layer 56: Second semiconductor layer 61: Continuous fin structure 62, 62A, 62B, 62C, 62D, 62E: Fins 62', 62A', 62B', 62C', 62D', 62E': Fin-like portions 64: First nanostructure 64 / 66: Nanostructure 65,123: Opening 66: Second nanostructure 68: Insulating materials 70, 125: Quarantine Zone 71: Dummy Materials 72: Virtual Area 82: Virtual Dielectric Layer 84: Dummy gate 86: Mask 90: Spacer layer 92: Gate spacer 94: Fin-shaped spacers 96: Source / Drain Depression 96', 108: Depression 97: Side wall depression 98: Inner spacer 100: Source / Drain Region 100': Semiconductor layer 102: Contact Etching Stop Layer 104: First interlayer dielectric layer 110: Gate dielectric layer 112: Gate 120: Gate isolation region 122: Hard mask layer 124: Lining layer 126: Filling material 128: Etching Stop Layer 130: Second interlayer dielectric layer 132: Gate contact 133: Metal-Semiconductor Alloy Region 134: Source / drain contact

Claims

1. A method for forming a semiconductor device, comprising: A fin-like structure is formed on a substrate; alternating plurality of first nanostructures and plurality of first sacrificial structures and alternating plurality of second nanostructures and plurality of second sacrificial structures are formed on the fin-like structure, wherein the first nanostructures and individual second nanostructures are continuous structures; a plurality of first dielectric dummy regions are formed to replace the first sacrificial structures between the first nanostructures, such that the first dielectric dummy regions are respectively located between the first nanostructures; and a plurality of second dielectric dummy regions are formed to replace the second sacrificial structures between the second nanostructures, such that the second dielectric dummy regions are respectively located between the second nanostructures; a plurality of first source / drain regions are formed adjacent to the first nanostructures, and a plurality of second source / drain regions are formed adjacent to the second nanostructures; and an etching process is performed to remove the first dielectric dummy regions and the second dielectric dummy regions; Multiple gate structure layers are deposited on the first nanostructures and the second nanostructures; and an isolation region is formed between the first nanostructures and the second nanostructures, wherein the isolation region physically separates the first nanostructures and the second nanostructures.

2. A method for forming a semiconductor device as claimed in claim 1, wherein the first dielectric dummy region comprises an oxide material.

3. A method of forming a semiconductor device as described in claim 1 or 2, wherein the first nanostructures are wider than the second nanostructures.

4. A method for forming a semiconductor device as described in claim 1 or 2, wherein the step of forming the first dielectric dummy regions includes: Remove these first sacrifice structures; A dielectric material is deposited on these first nanostructures; And etching the dielectric material to expose the sidewalls of the first nanostructures.

5. A method for forming a semiconductor device, comprising: A first nanostructure stack is formed adjacent to a second nanostructure stack, wherein the first nanostructure stack and the second nanostructure stack include a plurality of first nanostructures and a plurality of second nanostructures, wherein a first sidewall of the first nanostructure stack is adjacent to a second sidewall of the second nanostructure stack, wherein the first sidewall is perpendicularly offset from the second sidewall; the first nanostructures of the first nanostructure stack and the first nanostructures of the second nanostructure stack are replaced with a plurality of dielectric regions, wherein the dielectric regions are respectively located between the second nanostructures of the first nanostructure stack and between the second nanostructures of the second nanostructure stack; the dielectric regions of the first nanostructure stack and the dielectric regions of the second nanostructures are replaced with a continuous gate structure; and a portion of the continuous gate structure is replaced with an isolation region, wherein the isolation region extends between the first nanostructure stack and the second nanostructure stack.

6. A method of forming a semiconductor device as claimed in claim 5, wherein prior to the step of replacing the portion of the continuous gate structure with the isolation region, the first nanostructure stack and the second nanostructure stack are a continuous structure.

7. A method for forming a semiconductor device as described in claim 5 or 6, wherein the first semiconductor material of the first nanostructure is different from the second semiconductor material of the second nanostructure.

8. A semiconductor device, comprising: A first fin and a second fin are located on a semiconductor substrate, wherein a first width of the first fin is different from a second width of the second fin; a plurality of first nanostructures are located on the first fin; a plurality of second nanostructures are located on the second fin; a first gate structure is located on the first fin, wherein the first gate structure separates individual adjacent first nanostructures; and a second gate structure is located on the second fin, wherein the second gate structure separates individual adjacent second nanostructures; and an isolation structure extends from the first fin to the second fin, wherein the isolation structure protrudes into the semiconductor substrate.

9. The semiconductor device as claimed in claim 8, wherein the distance between the first fin and the second fin is 20 nm to 80 nm.

10. The semiconductor device as claimed in claim 8 or 9 further includes a shallow trench isolation region surrounding the first fin, wherein the isolation structure extends between the first fin and the shallow trench isolation region.

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