Semiconductor devices and electronic devices including the semiconductor devices

Abstract

A novel semiconductor device is provided. The semiconductor device includes: a first element layer including a first memory cell; a second element layer including a second memory cell; and a silicon substrate including a driving circuit. The first element layer is disposed between the silicon substrate and the second element layer. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of the source and drain terminals of the first transistor and one of the source and drain terminals of the second transistor are respectively electrically connected to wiring for electrical connection to the driving circuit. The wiring contacts the first semiconductor layer including the first transistor and the second semiconductor layer including the second transistor, and is disposed in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

Description

Technical Field

[0001] This manual describes semiconductor devices, etc.

[0002] In this specification, a semiconductor device refers to a device that utilizes the properties of semiconductors, and includes circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) and devices having such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that house chips in packages. Additionally, memory devices, display devices, light-emitting devices, lighting equipment, and electronic devices are themselves semiconductor devices, or sometimes include semiconductor devices. Prior Technology

[0003] Metal oxides have attracted attention as semiconductors that can be used in transistors. In-Ga-Zn oxides, such as "IGZO", are typical examples of multi-component metal oxides. Through the study of IGZO, CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single crystals nor amorphous, have been discovered (e.g., Non-Patent Literature 1).

[0004] Reports indicate that transistors comprising metal oxide semiconductors (hereinafter sometimes referred to as "oxide semiconductor transistors" or "OS transistors") in the channel formation region exhibit extremely small off-state currents (e.g., Non-Patent Documents 1, 2). Various semiconductor devices using OS transistors (e.g., Non-Patent Documents 3, 4) have been manufactured.

[0005] The fabrication process of OS transistors can be incorporated into the conventional CMOS fabrication process of Si transistors, and OS transistors can be stacked on top of Si transistors. For example, Patent Document 1 discloses a structure in which multiple memory cell arrays including OS transistors are stacked on a substrate provided with Si transistors.

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2012 / 0063208

[0007] [Non-patent document 1] S.Yamazaki et al., "Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics," Jpn.J.Appl.Phys., vol.53,04ED18(2014). [Non-patent document 2] K.Kato et al., "Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide," Jpn.J.Appl.Phys., vol.51,021201(2012). [Non-patent document 3] S.Amano et al., "Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency," SID Symp. Dig. Papers, vol.41, pp.626-629 (2010). [Non-Patent Literature 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol. 79, pp. 149-156 (2017). Summary of the Invention

[0008] One objective of one embodiment of the present invention is to provide a semiconductor device, etc., with a novel structure. Another objective of one embodiment of the present invention is to provide a semiconductor device, etc., with a novel structure that can reduce manufacturing costs in a semiconductor device used as a memory device utilizing extremely small off-state currents. Another objective of one embodiment of the present invention is to provide a semiconductor device, etc., with a novel structure that achieves low power consumption in a semiconductor device used as a memory device utilizing extremely small off-state currents. Another objective of one embodiment of the present invention is to provide a semiconductor device, etc., with a novel structure that can achieve device miniaturization in a semiconductor device used as a memory device utilizing extremely small off-state currents. Another objective of one embodiment of the present invention is to provide a semiconductor device, etc., with a novel structure that exhibits small variations in the electrical characteristics of transistors and excellent reliability in a semiconductor device used as a memory device utilizing extremely small off-state currents.

[0009] The description of multiple objectives does not preclude the existence of mutually exclusive objectives. One embodiment of the present invention does not need to achieve all of the exemplified objectives. Furthermore, objectives other than those listed above are naturally apparent from the description in this specification, etc., and such objectives may become the objectives of one embodiment of the present invention.

[0010] One embodiment of the present invention is a semiconductor device comprising: a first element layer including a first memory cell; a second element layer including a second memory cell; a third element layer including a switching circuit; and a silicon substrate including a driving circuit. The first element layer is disposed between the silicon substrate and the second element layer, and the third element layer is disposed between the silicon substrate and the first element layer. The first memory cell includes a first transistor and a first capacitor, the second memory cell includes a second transistor and a second capacitor, and the switching circuit includes a third transistor. The third transistor has the function of controlling the conduction state between the first memory cell or the second memory cell and the driving circuit. One of the source and drain electrodes of the first transistor and one of the source and drain electrodes of the second transistor are respectively electrically connected to wiring for electrically connecting to one of the source and drain electrodes of the third transistor. The other of the source and drain electrodes of the third transistor is electrically connected to the driving circuit. The wiring contacts the first semiconductor layer included in the first transistor and the second semiconductor layer included in the second transistor and is disposed in a vertical or substantially vertical direction relative to the surface of the silicon substrate.

[0011] In one embodiment of the present invention, a semiconductor device is preferred, wherein the first semiconductor layer and the second semiconductor layer respectively include metal oxides in the channel forming region.

[0012] In one embodiment of the present invention, a semiconductor device is preferred, wherein a first capacitor is disposed in a layer below a first semiconductor layer, and a second capacitor is disposed in a layer below a second semiconductor layer.

[0013] In one embodiment of the invention, a semiconductor device is preferred, wherein a first capacitor is disposed in a layer above a first semiconductor layer, and a second capacitor is disposed in a layer above a second semiconductor layer.

[0014] In one embodiment of the present invention, a semiconductor device is preferred, wherein one electrode of the first capacitor is disposed on the same layer as the first semiconductor layer, and one electrode of the second capacitor is disposed on the same layer as the second semiconductor layer.

[0015] One embodiment of the present invention is a semiconductor device comprising: a first element layer including a first memory cell; a second element layer including a second memory cell; a third element layer including a first control circuit; and a silicon substrate including a driving circuit, wherein the first element layer is disposed between the silicon substrate and the second element layer, the third element layer is disposed between the silicon substrate and the first element layer, the first memory cell includes a first transistor and a first capacitor, the second memory cell includes a second transistor and a second capacitor, the first control circuit includes a third transistor for amplifying a signal read from the first memory cell, one of the source and drain of the first transistor and one of the source and drain of the second transistor are respectively electrically connected to a first wiring for electrically connecting to the gate of the third transistor, one of the source and drain of the third transistor is electrically connected to a second wiring for electrically connecting to the driving circuit, the first wiring contacts the first semiconductor layer included in the first transistor and the second semiconductor layer included in the second transistor and is disposed in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate, and the second wiring is disposed in a direction parallel or substantially parallel to the first wiring.

[0016] In one embodiment of the present invention, a semiconductor device is preferred, wherein the first control circuit includes a fourth transistor, one of the source and drain of the fourth transistor is electrically connected to one of the source and drain of the third transistor, and the other of the source and drain of the fourth transistor is electrically connected to the second wiring.

[0017] In one embodiment of the present invention, a semiconductor device is preferred, wherein the first control circuit includes a fifth transistor and a sixth transistor, one of the source and drain of the fifth transistor is electrically connected to the gate of the third transistor, the other of the source and drain of the fifth transistor is electrically connected to the second wiring, one of the source and drain of the sixth transistor is electrically connected to the other of the source and drain of the third transistor, and the other of the source and drain of the sixth transistor is electrically connected to a ground wire.

[0018] In one embodiment of the present invention, a semiconductor device is preferred, wherein the first semiconductor layer and the second semiconductor layer respectively include metal oxides in the channel forming region.

[0019] In one embodiment of the present invention, a semiconductor device is preferred, wherein the metal oxide comprises In, Ga and Zn.

[0020] In one embodiment of the present invention, a semiconductor device is preferred, wherein the first capacitor is disposed in a layer below the first semiconductor layer, and the second capacitor is disposed in a layer below the second semiconductor layer.

[0021] In one embodiment of the present invention, a semiconductor device is preferred, wherein the first capacitor is disposed in a layer above the first semiconductor layer, and the second capacitor is disposed in a layer above the second semiconductor layer.

[0022] In one embodiment of the present invention, a semiconductor device is preferred, wherein one electrode of the first capacitor is disposed in the same layer as the first semiconductor layer, and one electrode of the second capacitor is disposed in the same layer as the second semiconductor layer.

[0023] One embodiment of the present invention is a semiconductor device, comprising: a first element layer including a first memory cell; and a second element layer including a second memory cell, wherein the first element layer and the second element layer are stacked thereon, the first memory cell including a first transistor and a first capacitor, the second memory cell including a second transistor, a third transistor and a second capacitor, one of the source and drain of the first transistor being electrically connected to an electrode of the first capacitor, and one of the source and drain of the second transistor being electrically connected to the gate of the third transistor and an electrode of the second capacitor.

[0024] In one embodiment of the present invention, a semiconductor device is preferred, comprising a substrate, wherein the second element layer is disposed between the substrate and the first element layer.

[0025] In one embodiment of the present invention, a semiconductor device is preferred, wherein the first transistor includes a first semiconductor layer, the second transistor includes a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer respectively include metal oxide in the channel forming region.

[0026] In one embodiment of the present invention, a semiconductor device is preferred, wherein the metal oxide comprises In, Ga and Zn.

[0027] Note that other embodiments of the present invention are described in the following description and figures.

[0028] One embodiment of the present invention can provide a semiconductor device with a novel structure. Another embodiment of the present invention can provide a semiconductor device with a novel structure that reduces manufacturing costs in a semiconductor device used as a memory device utilizing extremely small off-state currents. Another embodiment of the present invention can provide a semiconductor device with a novel structure that achieves low power consumption in a semiconductor device used as a memory device utilizing extremely small off-state currents. Another embodiment of the present invention can provide a semiconductor device with a novel structure that enables miniaturization of the device in a semiconductor device used as a memory device utilizing extremely small off-state currents. Finally, one embodiment of the present invention can provide a semiconductor device with a novel structure in a semiconductor device used as a memory device utilizing extremely small off-state currents where the electrical characteristics of the transistors exhibit minimal variation and excellent reliability.

[0029] The description of multiple effects does not preclude the existence of each other's effects. Furthermore, one embodiment of the present invention does not necessarily require all of the aforementioned effects. In one embodiment of the present invention, objectives, effects, and novel features beyond the above descriptions can be readily understood from the description and drawings herein. Simple Explanation of the Diagram

[0030] In the diagram: [Figure 1A] is a block diagram showing an example of the structure of a semiconductor device, and [Figure 1B] is a schematic diagram showing it; [Figure 2] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 3A] is a schematic diagram showing an example of the structure of a semiconductor device, and [Figure 3B] is a schematic diagram thereof; [Figure 4] is a circuit diagram showing an example of the structure of a semiconductor device; [Figure 5] is a timing diagram showing an example of the structure of a semiconductor device; [Figure 6A] is a block diagram showing an example of the structure of a semiconductor device, and [Figure 6B] is a schematic diagram thereof; [Figure 7] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 8] is a circuit diagram showing an example of the structure of a semiconductor device; [Figure 9] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 10A] is a schematic diagram showing an example of the structure of a semiconductor device, and [Figure 10B] is a schematic diagram thereof; [Figure 11A] is a block diagram showing an example of the structure of a semiconductor device, and [Figure 11B] is a schematic diagram thereof; [Figure 12A] is a block diagram showing an example of the structure of a semiconductor device, and [Figure 12B] is its circuit diagram; [Figure 13] is a block diagram showing an example of the structure of a semiconductor device; [Figure 14] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 15] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 16] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 17] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 18A] is a circuit diagram showing an example of the structure of a semiconductor device, and [Figure 18B] is its circuit diagram; [Figure 19A] is a circuit diagram showing an example of the structure of a semiconductor device, and [Figure 19B] is its circuit diagram; [Figure 20] is a circuit diagram showing an example of the structure of a semiconductor device; [Figure 21] is a circuit diagram showing an example of the structure of a semiconductor device; [Figure 22] is a circuit diagram showing an example of the structure of a semiconductor device; [Figure 23] is a timing diagram showing an example of the structure of a semiconductor device; [Figure 24] is a circuit diagram showing an example of the structure of a semiconductor device; [Figure 25A] is a block diagram showing an example of the structure of a semiconductor device, and [Figure 25B] is a schematic diagram thereof; [Figure 26] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 27A] is a schematic diagram showing an example of the structure of a semiconductor device, and [Figure 27B] is a schematic diagram thereof; [Figure 28] is a circuit diagram showing an example of the structure of a semiconductor device; [Figure 29] is a timing diagram showing an example of the structure of a semiconductor device; [Figure 30] is a schematic diagram illustrating an example of the structure of a semiconductor device; [Figure 31] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 32] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 33] is a schematic diagram illustrating an example of the structure of a semiconductor device; [Figure 34] is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device; [Figure 35A] is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device, and [Figure 35B] is a cross-sectional schematic diagram thereon; [Figure 36A] is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device, [Figure 36B] is a cross-sectional schematic diagram thereof, and [Figure 36C] is a cross-sectional schematic diagram thereof; [Figure 37] is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device; [Figure 38] is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device; [Figure 39A] is a top view showing an example of the structure of a semiconductor device, [Figure 39B] is a schematic cross-sectional view of it, and [Figure 39C] is a schematic cross-sectional view of it; Figures 40A to 40D are top views illustrating structural examples of semiconductor devices; [Figure 41A] is a diagram illustrating the classification of the crystal structure of IGZO, [Figure 41B] is a diagram illustrating the XRD spectrum of the CAAC-IGZO film, and [Figure 41C] is a diagram illustrating the nano-beam electron diffraction pattern of the CAAC-IGZO film; [Figure 42] is a block diagram illustrating an example of the structure of a semiconductor device; [Figure 43] is a schematic diagram showing an example of the structure of a semiconductor device; [Figure 44A] is a diagram illustrating an example of the structure of a semiconductor device, and [Figure 44B] is a diagram thereof; [Figure 45A] is a schematic diagram illustrating an example of an electronic component, and [Figure 45B] is a schematic diagram thereof; [Figure 46] is a diagram showing an example of an electronic device. Implementation

[0031] The embodiments will now be described with reference to the drawings. Note that one embodiment of the present invention is not limited to the following description. Those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0032] Note that in this specification, ordinal numbers such as "first," "second," and "third" are added to avoid confusion regarding the components. Therefore, these ordinal numbers do not limit the number of components. Furthermore, these ordinal numbers do not limit the order of the components. Additionally, for example, in this specification, a component referred to as "first" in one embodiment may be designated as a component referred to as "second" in other embodiments or claims. Furthermore, for example, in this specification, a component referred to as "first" in one embodiment may be omitted in other embodiments or claims.

[0033] In diagrams, the same symbol is sometimes used to represent the same element or elements with the same function, elements of the same material, or elements formed at the same time, and sometimes repeated descriptions are omitted.

[0034] In this specification, the power supply potential VDD is sometimes simply referred to as potential VDD, VDD, etc. The same applies to other components (e.g., signals, voltages, circuits, elements, electrodes, and wiring).

[0035] In addition, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as “_1”, “_2”, “[n]”, “[m,n]” are sometimes added to the symbol for identification. For example, the second wiring GL is represented as wiring GL[2].

[0036] Implementation Method 1 A structural example of a semiconductor device and its operation method according to an embodiment of the present invention will be described with reference to Figures 1 to 5.

[0037] Note that a semiconductor device refers to a device that utilizes the characteristics of a semiconductor, a circuit that includes semiconductor elements (transistors, diodes, photodiodes, etc.), and a device that includes such a circuit. In this embodiment, the semiconductor device described may be a semiconductor device used as a memory device utilizing a transistor with extremely small off-state current.

[0038] Figure 1A is a block diagram illustrating the semiconductor device described in this embodiment. The semiconductor device 10 shown in Figure 1A includes peripheral circuitry 20 and a memory cell array 30.

[0039] Peripheral circuitry 20 includes row driver 21 and column driver 22. Sometimes row driver 21 and column driver 22 are simply referred to as drive circuitry or drivers.

[0040] The row driver 21 is a circuit that outputs signals to word lines WL to drive the memory cell array 30. Specifically, the row driver 21 transmits word signals to word lines WL (WL_1 and WL_N are shown in Figure 1A; N is a natural number greater than 2). The row driver 21 is sometimes referred to as a word line-side driver circuit. Additionally, the row driver 21 includes decoder circuitry and buffer circuitry for selecting word lines WL according to a specified address. Note that word lines WL are sometimes simply referred to as wiring.

[0041] The column driver 22 is a circuit that outputs signals to the bit lines BL to drive the memory cell array 30. Specifically, the column driver 22 transmits data signals to the bit lines BL (BL_1 and BL_2 in FIG. 1A). The column driver 22 is sometimes referred to as a bit line-side drive circuit. Furthermore, the column driver 22 includes a sense amplifier, a pre-charge circuit, and a decoder circuit for selecting bit lines according to a specified address. Note that the bit lines BL are sometimes simply referred to as wiring. Additionally, in the diagrams, the bit lines BL are shown using thick lines or thick dashed lines for improved visibility.

[0042] The data signal supplied to the bit line BL is equivalent to a signal written to or read from a memory cell. The data signal is explained as a binary signal with a high or low level potential corresponding to data 1 or data 0. Alternatively, the data signal can be multi-valued with three or more values. The high level potential is VDD, and the low level potential is VSS or ground potential (GND). In addition to the data signal, the signals supplied to the bit line BL also include a pre-charge potential for reading data. The pre-charge potential can be set to VDD / 2.

[0043] The memory cell array 30 includes multiple element layers, such as N (N is a natural number greater than 2) element layers 34_1 to 34_N. Element layer 34_1 includes one or more memory cells 31_1. Memory cell 31_1 includes a transistor 32_1 and a capacitor 33_1. Element layer 34_N includes one or more memory cells 31_N. Memory cell 31_N includes a transistor 32_N and a capacitor 33_N. Note that capacitors are sometimes referred to as capacitor elements. Note that an element layer is a layer in which elements such as capacitors or transistors are disposed, and is formed of components such as conductors, semiconductors, and insulators.

[0044] Transistors 32_1 to 32_N are used as switches to control the on or off state according to the word signals supplied to word lines WL_1 to WL_N. One of the respective source and drain terminals of transistors 32_1 to 32_N is connected to any one of the bit lines BL (BL_1 in the diagram).

[0045] The transistors 32_1 to 32_N are preferably composed of an oxide semiconductor transistor (hereinafter referred to as an OS transistor) in the channel forming region. By employing a memory cell structure including an OS transistor in one embodiment of the present invention, the leakage current (hereinafter referred to as off-state current) flowing between the source and drain is minimal when the circuit is off. Therefore, utilizing this characteristic, the charge corresponding to the desired voltage can be retained in a capacitor 33_1 to 33_N connected to the other of the source and drain. In other words, the written data can be retained in the memory cells 31_1 to 31_N for a long time. Therefore, the frequency of data update can be reduced, thereby achieving low power consumption.

[0046] Furthermore, in the memory cells 31_1 to 31_N using OS transistors, data can be rewritten and read out through charging or discharging of electrical charges, thus enabling virtually unlimited write and read operations. Because the memory cells 31_1 to 31_N using OS transistors do not involve atomic-level structural changes as seen in magnetic or resistive memory, they exhibit excellent write resistance. Additionally, even with repeated rewriting operations like flash memory, the memory cells 31_1 to 31_N using OS transistors do not exhibit instability due to the increase in electron trapping centers.

[0047] Furthermore, the memory cells 31_1 to 31_N using OS transistors can be freely arranged on a silicon substrate containing a silicon transistor (hereinafter referred to as a Si transistor) with a channel forming region, thus facilitating integration. Additionally, OS transistors can be manufactured using the same manufacturing apparatus as Si transistors, thus enabling low-cost manufacturing.

[0048] Furthermore, OS transistors, when equipped with a back gate electrode in addition to the gate, source, and drain electrodes, can become four-terminal semiconductor devices. An OS transistor is constructed by a circuit network that allows independent control of the input and output signals flowing between the source and drain electrodes based on the voltage applied to the gate or back gate electrode. Therefore, circuit design can be performed in the same manner as LSI transistors. Moreover, OS transistors exhibit superior electrical characteristics compared to Si transistors at high temperatures. Specifically, even at temperatures above 125°C and below 150°C, the ratio of on-state current to off-state current is high, resulting in excellent switching performance.

[0049] Furthermore, the memory cell shown in Figure 1A can be referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) using OS transistors for memory. Because it can be constructed from a single transistor and a capacitor, high-density memory can be achieved. Additionally, by using OS transistors, the data retention period can be extended. Capacitors 33_1 to 33_N have a structure in which an insulator is sandwiched between conductive materials used as electrodes. Note that, in addition to metals, conductive materials such as semiconductor layers that impart conductivity can also be used as the conductive materials constituting the electrodes. Further details will be explained later; however, capacitors 33_1 to 33_N can be positioned above or below transistors 32_1 to 32_N, or a portion of the semiconductor layer or electrodes constituting transistors 32_1 to 32_N can be used as an electrode of capacitors 33_1 to 33_N.

[0050] In the structures illustrated in FIG1A, to illustrate element layers 34_1 to 34_N in one embodiment of the present invention, a schematic diagram with reference to FIG1B will be used for explanation. To illustrate the configuration of the structures illustrated in FIG1A, the schematic diagram shown in FIG1B corresponds to a perspective view with the x-axis, y-axis, and z-axis directions defined. Note that, for clarity, in this specification, the x-axis direction is sometimes referred to as the depth direction, the y-axis direction as the horizontal direction, and the z-axis direction as the vertical direction.

[0051] As shown in Figure 1B, there are N stacked element layers 34_1 to 34_N. Each of the element layers 34_1 to 34_N, including memory cells 31_1 to 31_N, has a region that overlaps with the column driver 22 disposed on the silicon substrate 11. As shown in Figure 1B, element layer 34_1 can be said to be disposed between the silicon substrate 11 and element layer 34_N.

[0052] Furthermore, the transistors of memory cells 31_1 included in element layer 34_1 and the transistors of memory cells 31_N included in element layer 34_N are connected via bit lines BL disposed in the vertical direction. Additionally, bit lines BL are connected to column drivers 22 disposed on silicon substrate 11.

[0053] Bit line BL_1 is configured to contact the semiconductor layer of the transistor included in memory cell 31_1 and the semiconductor layer of the transistor included in memory cell 31_N. Alternatively, bit line BL_1 is configured to contact the region of the semiconductor layer of the transistor included in memory cell 31_1 that is used as a source or drain and the region of the semiconductor layer of the transistor included in memory cell 31_N that is used as a source or drain. Alternatively, bit line BL_1 is configured to contact a conductor that contacts the region of the semiconductor layer of the transistor included in memory cell 31_1 that is used as a source or drain and the region of the semiconductor layer of the transistor included in memory cell 31_N that is used as a source or drain. In other words, bit line BL can be said to be a wiring used to electrically connect one of the source and drain terminals of the transistor included in memory cell 31_1, one of the source and drain terminals of the transistor included in memory cell 31_N, and column driver 22 in the vertical direction.

[0054] Note that the bit line BL can be said to extend in a direction perpendicular to or substantially perpendicular to the surface of the silicon substrate 11 on which the column driver 22 is located. In other words, as shown in FIG1B, the bit line BL is connected to the transistors included in memory cell 31_1 and memory cell 31_N, and is provided in a direction perpendicular to or substantially perpendicular to the surface (xy plane) of the silicon substrate (z direction). In addition, "substantially perpendicular" means a state in which it is provided at an angle of 85 degrees or more and 95 degrees or less.

[0055] Furthermore, the row driver 21 disposed on the silicon substrate 11 and the word lines WL extending in the depth direction of the component layers 34_1 to 34_N can have a structure that connects through regions where memory cells 31_1 to 31_N in the component layers 34_1 to 34_N are not disposed, such as the openings on the outer periphery of the component layers 34_1 to 34_N. The row driver 21 disposed on the silicon substrate 11 and the word lines WL disposed on each component layer can be connected through wiring in the layer above the component layers 34_1 to 34_N.

[0056] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors disposed in each element layer. Therefore, the update frequency of data stored in the memory cells can be reduced, enabling a low-power semiconductor device. OS transistors can be stacked and manufactured using the same process repeatedly in the vertical direction, thus reducing manufacturing costs. Furthermore, in one embodiment of the present invention, the transistors constituting the memory cells can be arranged vertically rather than planarly to increase storage density, thereby enabling device miniaturization. Additionally, OS transistors exhibit less variation in electrical characteristics even at high temperatures than Si transistors, thus enabling a semiconductor device with minimal variation in electrical characteristics when stacked and integrated, and suitable for use as a reliable memory device. Furthermore, in one embodiment of the present invention, the bit lines extending from the memory cell array are arranged vertically, thus shortening the length of the bit lines of the memory cell array and column drivers. This significantly reduces the parasitic capacitance of the bit lines, allowing multiple levels of data signals stored in the memory cells to be read out.

[0057] Figure 2 shows a schematic cross-section of a plane parallel to the vertical direction (z-axis direction) of the semiconductor device 10 described with reference to Figures 1A and 1B.

[0058] As shown in Figure 2, the semiconductor device 10 can also be structured such that the memory cells 31_1 to 31_N disposed in each element layer and the column driver 22 disposed in the silicon substrate 11 are connected via bit lines BL disposed in the vertical direction as the shortest distance. Compared with a structure in which the bit lines BL are arranged in a planar direction, although the number of bit lines BL is increased, the number of memory cells 31_1 to 31_N connected to a single bit line can be reduced, thus reducing the parasitic capacitance of the bit lines BL. Therefore, even if the capacitance of the capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N is reduced, the potential change of the bit lines BL that occurs when charge moves can still be controlled.

[0059] Furthermore, because the capacitance of capacitors 33_1 to 33_N included in memory cells 31_1 to 31_N can be reduced, capacitors 33_1 to 33_N can be disposed on the same layer as transistors 32_1 to 32_N. By disposing capacitors 33_1 to 33_N on the same layer as transistors 32_1 to 32_N, the element layers 34_1 to 34_N of each layer can be thinned. Therefore, miniaturization of the semiconductor device 10 is possible.

[0060] Furthermore, the capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N can be arranged in the same layer as the transistors 32_1 to 32_N, or other structures can be used. For example, the schematic diagram shown in FIG3A illustrates a structure in which the capacitor 33A of the memory cell 31 included in the element layers 34_1 to 34_N is arranged above the transistor 32 in the vertical direction. By adopting this structure, the capacitance can be increased, thereby improving the reliability of the read data and extending the data retention time. In addition, in the structure of FIG3A, a capacitor 33A with one electrode connected to a fixed potential can be arranged above the transistor 32, thereby suppressing the influence of external noise.

[0061] Furthermore, the schematic diagram shown in Figure 3B illustrates a structure in which the capacitor 33B of the memory cell 31 included in element layers 34_1 to 34_N is disposed below the transistor 32 in the vertical direction. By employing this structure, the capacitance can be increased, thereby improving the reliability of the read data and extending the data retention time. Additionally, in the structure of Figure 3B, a capacitor 33B with one electrode connected to a fixed potential can be positioned between the transistor 32 and the column driver 22, thus suppressing the influence of noise from the column driver 22 on the memory cell 31.

[0062] Figure 4 shows a circuit diagram illustrating an example of the circuit structure of the memory cell array 30, which includes element layers 34_1 to 34_N as illustrated in Figure 1A, and a specific example of the circuit structure of the column driver 22 connected to the memory cell.

[0063] In Figure 4, element layers 34_1 to 34_N are shown as memory cell array 30. In Figure 4, memory cell 31_N_A is shown as a memory cell connected to bit line BL_A. Memory cell 31_N_A includes a transistor 32A whose gate is connected to word line WL_A and a capacitor 33. Additionally, in Figure 4, memory cell 31_N_B is shown as a memory cell connected to bit line BL_B. Memory cell 31_N_B includes a transistor 32B whose gate is connected to word line WL_B and a capacitor 33. The capacitor 33 of each element layer is connected to a wiring VL supplied with a fixed potential, such as ground potential.

[0064] Additionally, Figure 4 shows the circuitry included in the column driver 22, comprising a pre-charge circuit 22_1, a sense amplifier 22_2, a selection switch 22_3, and a write / read circuit 29 located on the silicon substrate side. The transistors constituting the pre-charge circuit 22_1 and the sense amplifier 22_2 are Si transistors. The selection switch 22_3 may also be a Si transistor.

[0065] The pre-charge circuit 22_1 is composed of n-channel transistors 24_1 to 24_3. The pre-charge circuit 22_1 refers to the circuit that pre-charges bit lines BL_A and BL_B to the intermediate potential VPC, which is equivalent to the potential VDD / 2 between VDD and VSS, according to the pre-charge signal supplied to the pre-charge line PCL.

[0066] The sensing amplifier 22_2 is composed of p-channel transistors 25_1 and 25_2 and n-channel transistors 25_3 and 25_4 connected to wiring VHH or wiring VLL. Wiring VHH or wiring VLL is wiring that supplies VDD or VSS. Transistors 25_1 to 25_4 are transistors that form an inverter loop. The sensing amplifier 22_2 sets the potentials of bit lines BL_A and BL_B to a high supply potential VDD or a low supply potential VSS. The potentials of bit lines BL_A and BL_B are varied by setting word lines WL_A and WL_B to a high level and selecting memory cells 31_N_A and 31_N_B. The potentials of bit lines BL_A and BL_B are output to the outside through the write-read circuit 29. Bit lines BL_A and BL_B are equivalent to a bit line pair.

[0067] Additionally, Figure 5 shows a timing diagram illustrating the operation of the circuit diagram shown in Figure 4. In the timing diagram shown in Figure 5, period T1 corresponds to the initialization period, period T2 corresponds to the write period, period T3 corresponds to the non-access period, and period T4 corresponds to the read period. Note that the descriptions of switches 23_A and 23_B, which are included in the selection switch 22_3, are omitted in Figure 5; however, they are appropriately selected in a conducting manner during write and read operations.

[0068] The arrows between the waveforms in Figure 5 are for ease of understanding. The high level (H level) of the PCL wiring in the signal line is VDD. The high level of WL can be either VHM (>VDD) or VDD.

[0069] During period T1, the wiring VPC, wiring VHH, and wiring VLL are VDD / 2. Bit line BL_A is pre-charged to VDD / 2. Pre-charge circuit 22_1 pre-charges bit line BL_A. By setting wiring PCL to a high level (H level), pre-charging and potential smoothing of bit line BL_A (or bit line BL_B) are performed.

[0070] During period T2, when a write access occurs, bit line BL_A (or bit line BL_B) is changed from a precharge state to a floating state. This is done by changing the routing PCL from H level to L level. Word line WL_A is set to H level. After WL_A is selected, VHH becomes VDD and VLL becomes GND. Data DA1 is written to bit line BL_A by turning on transistor 32A. After word line WL_A is set to L level, the precharge process of bit line BL_A (or bit line BL_B) begins to precharge bit line BL_A (or bit line BL_B) to VDD / 2.

[0071] During period T3, the wiring PCL is at level H, and the word line WL_A is at level L. VPC, VHH, and VLL are VDD / 2. Bit line pairs and local bit line pairs are precharged to VDD / 2. By setting VHH and VLL to VDD / 2, the leakage current of the sense amplifier 22_2 can be reduced.

[0072] During period T4, when a read access occurs, bit line BL_A (or bit line BL_B) is changed from a pre-charge state to a floating state. Then, word line WL_A is set to level H to turn on transistor 32A. Data DA1 is written to bit line BL_A. After word line WL_A is set to level H, VHH becomes VDD and VLL becomes GND, and sense amplifier 22_2 is used as a differential amplifier circuit to amplify the data DA1 on bit line BL_A. The data DA1 on bit line BL_A is read out by write-read circuit 29.

[0073] In a semiconductor device according to one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors disposed in each element layer. OS transistors can be stacked on a silicon substrate on which Si transistors are disposed. Therefore, the same process can be repeatedly used in the vertical direction, thereby reducing manufacturing costs. In addition, in one embodiment of the present invention, the transistors constituting the memory cells can be arranged in the vertical direction instead of the planar direction to increase memory density, thereby enabling device miniaturization.

[0074] Implementation Method 2 A structural example of a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 6 to 10. The description of Embodiment 1 is used in connection with structures using the same reference numerals as in Embodiment 1, and sometimes the description is omitted.

[0075] Figure 6A shows a block diagram of semiconductor device 10A.

[0076] Peripheral circuitry 20 includes row drivers 21, column drivers 22, and a component layer 26 with switching circuitry. The switching circuitry is sometimes simply referred to as the drive circuitry. The switching circuitry includes transistors that control the conduction state between the memory cells and the column drivers.

[0077] The component layer 26, equipped with a switching circuit, has the function of selectively connecting the column driver 22 to the bit line BL. The switching circuit functions as a multiplexer, connecting the specified bit line and the drive circuitry such as the sense amplifier of the column driver 22 according to a selection signal output from the column driver 22. The switching circuit is a circuit that outputs a signal to the bit line BL selected by the switching circuit to drive the memory cell array 30.

[0078] In the semiconductor device of FIG6A, the component layer 26 with switching circuitry can reduce the number of bit lines BL connected to the column driver 22 in the vertical direction, shorten the data writing time, and improve read accuracy.

[0079] Furthermore, the transistor constituting the switching circuit is preferably an OS transistor. The component layer 26, including the switching circuit using an OS transistor, can be freely arranged on the circuit using a Si transistor, thus facilitating integration. Additionally, OS transistors can be manufactured using the same manufacturing equipment as Si transistors, allowing for low-cost manufacturing.

[0080] In the structures illustrated in FIG6A, to illustrate the component layers 34_1 to 34_N and the component layer 26 including the switching circuit in one embodiment of the present invention, a schematic diagram with reference to FIG6B will be used for explanation. To illustrate the configuration of the structures illustrated in FIG6A, the schematic diagram shown in FIG6B corresponds to a perspective view with the x-axis, y-axis, and z-axis directions set.

[0081] As shown in FIG6B, in the semiconductor device 10A, V (V being a natural number greater than or equal to 1) element layers 26, each containing transistors constituting a switching circuit, and N element layers 34_1 to 34_N are stacked on a silicon substrate 11, totaling (N+V) layers including OS transistors. The memory cells 31_1 to 31_N included in element layers 34_1 to 34_N, and the element layers 26 containing transistors constituting the switching circuit, each have regions overlapping with the column driver 22 disposed on the silicon substrate 11. As shown in FIG6B, element layer 26 can be said to be disposed between the silicon substrate 11 and element layer 34_1. Similarly, as shown in FIG6B, element layer 34_1 can be said to be disposed between the silicon substrate 11 and element layer 34_N.

[0082] Furthermore, the transistors of memory cells 31_1 included in element layer 34_1 and the transistors of memory cells 31_N included in element layer 34_N are connected via bit lines BL disposed in the vertical direction. Additionally, bit lines BL are connected to element layer 26, which is provided with transistors constituting a switching circuit. Element layer 26 is connected to column drivers 22 disposed on silicon substrate 11.

[0083] Bit line BL_1 is configured to contact the semiconductor layer of the transistor included in memory cell 31_1. Alternatively, bit line BL_1 is configured to contact a region of the semiconductor layer of the transistor included in memory cell 31_1 that is used as a source or drain. Alternatively, bit line BL_1 is configured to contact a conductor in a region of the semiconductor layer of the transistor included in memory cell 31_1 that is used as a source or drain. In other words, bit line BL can be described as wiring used to electrically connect one of the source and drain of the transistor included in memory cell 31_1, one of the source and drain of the transistor included in memory cell 31_N, and element layer 26 in the vertical direction.

[0084] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors disposed in each element layer. Therefore, the update frequency of data stored in the memory cell can be reduced, and a low-power semiconductor device can be realized. OS transistors can be stacked and manufactured by repeatedly using the same process in the vertical direction, thus reducing manufacturing costs. Furthermore, in one embodiment of the present invention, the transistors constituting the memory cell can be arranged vertically rather than planarly to increase storage density, thereby enabling device miniaturization. In addition, OS transistors exhibit less variation in electrical characteristics even at high temperatures than Si transistors, thus enabling a semiconductor device with minimal variation in electrical characteristics when stacked and integrated, and suitable for use as a reliable memory device.

[0085] Furthermore, one embodiment of the present invention includes a component layer comprising a switching circuit. The switching circuit reduces the number of bit lines BL connected to the sense amplifier included in the column driver. Therefore, the load on the bit lines BL can be reduced. The switching circuit reduces the number of bit lines BL connected to the column driver in the vertical direction, shortening the data write time and improving read accuracy. Additionally, unnecessary charging and discharging of bit lines can be avoided, enabling a low-power semiconductor device. Since memory cells can be arranged directly above the circuitry of the sense amplifier, miniaturization of the semiconductor device is possible. Furthermore, operation is possible even with reduced capacitance of the capacitors included in the memory cells. In another embodiment of the present invention, the bit lines extending from the memory cell array are arranged in the vertical direction, thus shortening the length of the bit lines in the memory cell array and the column driver. This significantly reduces the parasitic capacitance of the bit lines, thereby enabling the read potential of multiple levels of the data signal stored in the memory cells.

[0086] Figure 7 shows a schematic cross-section of a plane parallel to the vertical direction (z-axis direction) of the semiconductor device 10A described with reference to Figures 6A and 6B.

[0087] As shown in Figure 7, the semiconductor device 10A can also be structured such that the memory cells 31_1 to 31_N of the element layers, the element layer 26, and the column driver 22 of the silicon substrate 11 are connected via bit lines BL arranged in the vertical direction as the shortest distance. Although the number of element layers 26 including the switching circuit 27 is increased, the number of bit lines BL connected to the sense amplifier included in the column driver 22 can be reduced. Therefore, the load on the bit lines BL can be reduced.

[0088] Furthermore, as shown in Figure 7, the transistors 28_1 to 28_n (n being a natural number greater than 2) included in the switching circuit 27 can output the potential of the bit line BL selected according to the selection signal MUX output from the column driver 22 as the signal BL_OUT to the column driver 22. Note that the semiconductor device 10A shown in Figure 7 can be represented by unit 30_1.

[0089] Figure 8 shows a circuit diagram of a memory cell array 30, in which a component layer 26 including transistors 28_a and 28_b is added in addition to component layers 34_1 to 34_N. Component layers 34_1 to 34_N are disposed on component layer 26 including transistors 28_a and 28_b as shown in Figure 8, and bit lines BL_A and BL_B are arranged in the vertical direction. In other words, a component layer including switching circuitry that forms part of the peripheral circuitry can be stacked in the same manner as component layers 34_1 to 34_N. Bit lines BL_A and BL_B are connected to one of the source and drain terminals of transistors 28_a and 28_b.

[0090] Additionally, in Figure 8, the circuitry included in the column driver 22 includes a pre-charge circuit 22_1, a sense amplifier 22_2, a switching circuit 22_3, and a write / read circuit 29 located on the silicon substrate side. The transistors constituting the pre-charge circuit 22_1 and the sense amplifier 22_2 are Si transistors. The selection switch 22_3 may also use a Si transistor. The other of the source and drain terminals of transistors 28_a and 28_b is connected to the transistor constituting the pre-charge circuit 22_1 and the sense amplifier 22_2. Furthermore, Figure 8 shows blocks representing component layers 34_1 to 34_N and component layer 26 connected to the wiring of the switching circuit 23_A included in the switching circuit 22_3, and blocks representing component layers 34_1 to 34_N and component layer 26 connected to the wiring of the switching circuit 23_B included in the switching circuit 22_3.

[0091] Component layer 26, including switching circuitry, selects either bit line BL_A or BL_B and connects it to one of a pair of wirings connected to precharge circuit 22_1 and sense amplifier 22_2, as well as switch 23_A. Furthermore, in component layer 26, which includes another pair of switching circuits, bit line BL is selected and connected to the other of a pair of wirings connected to precharge circuit 22_1 and sense amplifier 22_2, as well as switch 23_B. By setting the word line of the memory cell connected to the selected bit line to a high level, the potential of the precharged bit line changes, and therefore, according to this change, the potential of the pair of wirings connected to precharge circuit 22_1 and sense amplifier 22_2 becomes a high power supply potential VDD or a low power supply potential VSS. This potential can be output to the outside via switching circuit 22_3 and write / read circuit 29.

[0092] As shown in Figure 8, although the number of component layers 26 including switching circuits is increased in the semiconductor device 10A, any one of the multiple bit lines BL can be selected and connected to the column driver 22. Therefore, a smaller number of bit lines BL can be connected to the sense amplifier 22_2, reducing the load on the bit lines BL.

[0093] Furthermore, the cells 30_1 in the semiconductor device 10A shown in FIG. 7 can be arranged in a structure stacked in the vertical direction. FIG. 9 shows a semiconductor device 10A with M cells 30_1 (cells 30_1 to 30_M, where M is 2 or more) stacked as described in FIG. 7. FIG. 9 is a schematic diagram of the semiconductor device parallel to the vertical direction (z-axis direction). In other words, the semiconductor device 10A shown in FIG. 9 has a structure with a total of M×(N+V) layers of the element layers shown in FIG. 7.

[0094] As shown in Figure 9, in the semiconductor device 10A, units 30_1 to 30_M each include switching circuits 27_1 to 27_M. Switching circuits 27_1 to 27_M output a signal BL_OUT via an input selection signal MUX. A switching circuit 98, which can be switched by a selection signal SEL, selects any one of the wirings of the output signal BL_OUT, and connects it to the column driver 22 via a wiring GBL, which is different from the bit line BL. Switching circuit 98 can use OS transistors constituting switching circuits 27_1 to 27_M.

[0095] By adopting this structure, the stack-up number of the respective component layers 34_1 to 34_N for cells 30_1 to 30_M can be reduced. Therefore, the length of the respective bit lines BL for cells 30_1 to 30_M can be shortened, thereby reducing the load on the bit lines BL. Note that in the diagrams, for improved visibility, thick lines or thick dashed lines are sometimes used to indicate the routing GBL. The routing GBL is sometimes referred to as the global bit line.

[0096] Furthermore, the wiring GBL shown in FIG9 can be provided after the component layer including the OS transistor is manufactured. For example, as shown in the cross-sectional view of FIG10A, a component layer including the OS transistor can be manufactured and an opening can be formed on the outer periphery of the sealing layer 70A surrounding each component layer, and the wiring GBL can be provided in this opening. Alternatively, as shown in the cross-sectional view of FIG10A, a component layer including the OS transistor can be manufactured and an opening can be formed on the outer periphery of the sealing layer 70B surrounding each component layer, and the wiring GBL can be provided in this opening. Furthermore, the details of each component layer equipped with the wiring GBL will be described in Embodiment 3.

[0097] In a semiconductor device according to one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors disposed in each element layer. OS transistors can be stacked on a silicon substrate on which Si transistors are disposed. Therefore, the same process can be repeatedly used in the vertical direction, thereby reducing manufacturing costs. In addition, in one embodiment of the present invention, the transistors constituting the memory cells can be arranged in the vertical direction instead of the planar direction to increase memory density, thereby enabling device miniaturization.

[0098] Furthermore, one embodiment of the present invention includes a component layer comprising a switching circuit. The switching circuit can reduce the number of bit lines (BLs) connected to the column driver in the vertical direction, shorten data write time, and improve read accuracy. Additionally, it can avoid the charging and discharging of unnecessary bit lines, thus enabling a low-power semiconductor device.

[0099] Implementation Method 3 A structural example of a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 11 to 24. The description of Embodiment 1 is used in connection with structures using the same reference numerals as in Embodiment 1, and sometimes the description is omitted.

[0100] Figure 11A shows a block diagram of semiconductor device 10B.

[0101] The peripheral circuitry 20 includes a row driver 21, a column driver 22, and a component layer 40 with control circuitry. The control circuitry includes circuitry composed of OS transistors that serves as a sense amplifier.

[0102] The component layer 40, which includes control circuitry, comprises a circuitry used as a sense amplifier, constructed from an OS transistor. This sense amplifier, constructed from an OS transistor, is used as a switching circuit for selecting whether data signals are written to or read from each memory cell, and for switching between cells 50_1 to 50_M, including memory cells 31_1 to 31_N. Control signals WE, RE, and MUX, which drive the sense amplifier constructed from the OS transistor, are supplied to the component layer 40 from the column driver 22. The circuitry used as the sense amplifier is sometimes referred to as control circuitry because it includes a transistor used to control the reading or writing of data signals to the memory cells.

[0103] In the semiconductor device of Figure 11A, the control circuit can be used as an amplifier. By employing this structure, the small potential difference of bit line BL can be amplified during readout to drive a sense amplifier using Si transistors.

[0104] Furthermore, the transistor constituting the control circuit is preferably an OS transistor. The component layer 40, including the control circuit using an OS transistor, can be freely arranged on the circuit using a Si transistor, thus facilitating integration. Additionally, OS transistors can be manufactured using the same manufacturing equipment as Si transistors, allowing for low-cost manufacturing.

[0105] In the structures illustrated in FIG11A, to illustrate the component layers 34_1 to 34_N and the component layer 40 including the control circuit in one embodiment of the present invention, a schematic diagram with reference to FIG11B will be used for explanation. To illustrate the configuration of the structures illustrated in FIG11A, the schematic diagram shown in FIG11B corresponds to a perspective view with the x-axis direction, y-axis direction, and z-axis direction set.

[0106] As shown in FIG11B, in the semiconductor device 10B, V (V being a natural number greater than or equal to 1) element layers 40 containing transistors constituting control circuits and N element layers 34_1 to 34_N are stacked on a silicon substrate 11, totaling (N+V) layers including OS transistors. The memory cells 31_1 to 31_N included in element layers 34_1 to 34_N and the element layers 40 containing transistors constituting control circuits each have regions overlapping with the column driver 22 disposed on the silicon substrate 11. As shown in FIG11B, element layer 40 can be said to be disposed between the silicon substrate 11 and element layer 34_1. Furthermore, as shown in FIG11B, element layer 34_1 can be said to be disposed between the silicon substrate 11 and element layer 34_N.

[0107] Furthermore, the transistors of memory cells 31_1 included in component layer 34_1 and the transistors of memory cells 31_N included in component layer 34_N are connected via bit lines BL provided in the vertical direction. Additionally, bit lines BL are connected to component layer 40, which is provided with transistors constituting control circuitry. Component layer 40 is connected to column drivers 22 provided on silicon substrate 11 via wiring GBL (not shown) separately provided with bit lines BL. Note that in the figures, wiring GBL is sometimes shown using thick lines or thick dashed lines to improve visibility.

[0108] Bit line BL_1 is configured to contact the semiconductor layer of the transistor included in memory cell 31_1. Alternatively, bit line BL_1 is configured to contact a region of the semiconductor layer of the transistor included in memory cell 31_1 that is used as a source or drain. Alternatively, bit line BL_1 is configured to contact a conductor in the region of the semiconductor layer of the transistor included in memory cell 31_1 that is used as a source or drain. In other words, bit line BL can be described as wiring used to electrically connect one of the source and drain of the transistor included in memory cell 31_1, one of the source and drain of the transistor included in memory cell 31_N, and element layer 40 in the vertical direction.

[0109] Semiconductor device 10B may include one type of memory cell or two or more types of memory cells. Figure 12A is a block diagram showing a structural example of semiconductor device 10C, which is a variation of semiconductor device 10B. Semiconductor device 10C differs from semiconductor device 10B in that, in addition to memory cells 31, it also includes memory cells 51 with a different structure than memory cells 31 in the memory cell array 30. Semiconductor device 10C includes a component layer 54 composed of one or more memory cells 51.

[0110] In the semiconductor device 10C, the element layer 54 can be disposed between the element layer 34_i (where i is an integer greater than or equal to 1 and less than or equal to N-1) and the element layer 34_i+1. Alternatively, two or more element layers 54 can be disposed. In cases where the semiconductor device 10C includes two or more element layers 54, for example, the element layer 34 can be disposed between the first element layer 54 and the second element layer, or it can be omitted.

[0111] In the semiconductor device 10C, the row driver 21 is electrically connected to the memory cell 51 via word line WL2. The row driver 21 included in the semiconductor device 10C has the function of outputting signals to drive the memory cell array 30 to word line WL2, in addition to to word line WL. Specifically, the row driver 21 has the function of transmitting word signals not only to word line WL but also to word line WL2. Alternatively, a separate row driver capable of transmitting word signals to word line WL2 may be provided alongside the row driver capable of transmitting word signals to word line WL. Furthermore, word line WL2 is sometimes simply referred to as wiring.

[0112] Figure 12B is a circuit diagram showing an example of the structure of memory cell 51. Memory cell 51 includes transistor 55, transistor 56, and capacitor element 57.

[0113] One of the source and drain terminals of transistor 55 is electrically connected to the gate of transistor 56. The gate of transistor 56 is electrically connected to one electrode of capacitor element 57. The other of the source and drain terminals of transistor 55 and one of the source and drain terminals of transistor 56 are electrically connected to wiring BL. The other of the source and drain terminals of transistor 56 is electrically connected to wiring SL. The other electrode of capacitor element 57 is electrically connected to wiring CAL. Here, the node where one of the source and drain terminals of transistor 55, the gate of transistor 56, and one electrode of capacitor element 57 are electrically connected is called node N.

[0114] The wiring CAL functions as a wiring to apply a specified potential to the other electrode of the capacitor element 57. The potential of the wiring CAL when reading data from the memory cell 51 is different from the potential of the wiring CAL when writing data to the memory cell 51 and when storing data in the memory cell 51. Therefore, the critical voltage on the appearance of the transistor 56 when reading data from the memory cell 51 is different from the critical voltage on the appearance of the transistor 56 when writing data to the memory cell 51 and when storing data in the memory cell 51.

[0115] When the memory cell 51 adopts the structure shown in FIG12B, when writing data to the memory cell 51 and storing data in the memory cell 51, regardless of the data written to the memory cell 51, current does not flow between the wiring SL and the wiring BL. On the other hand, when reading data from the memory cell 51, the current corresponding to the data stored in the memory cell 51 flows between the wiring SL and the wiring BL.

[0116] Transistor 55 is preferably an OS transistor. As described above, the off-state current of an OS transistor is extremely small. Therefore, the charge corresponding to the data written to memory cell 51 can be maintained in node N for a long time. In other words, the written data can be maintained in memory cell 51 for a long time. Therefore, the frequency of data update can be reduced, thereby reducing the power consumption of the semiconductor device according to one embodiment of the present invention.

[0117] Furthermore, the memory cell 51 using an OS transistor can be freely configured on a silicon substrate, thus facilitating integration. Also, from the viewpoint of integrating the memory cell 51, the transistor 56 is preferably an OS transistor.

[0118] Transistor 55 preferably includes a back gate electrode. By controlling the potential applied to the back gate electrode, the threshold voltage of transistor 55 can be controlled. Therefore, for example, the on-state current of transistor 55 can be increased, and the off-state current can be reduced. Note that when transistor 56 is an OS transistor, it is preferable to also provide a back gate electrode in transistor 56.

[0119] The memory cell 51 shown in Figure 12B can be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM) using an OS transistor for memory. NOSRAM has the characteristic of being able to be read non-destructively. On the other hand, when reading the stored data from the DOSRAM that can be used in memory cell 31, a destructive read is performed.

[0120] The operation of the semiconductor device 10C will be described. Data written from the column driver 22 to the memory cell array 30 is stored in memory cells 31. Among the data stored in memory cells 31, data with high read frequencies is written from memory cells 31 to memory cells 51. As described above, memory cells 51 using NOSRAM can be read non-destructively, thus reducing the frequency of data updates. Therefore, the power consumption of the semiconductor device according to one embodiment of the present invention can be reduced.

[0121] Furthermore, the potential of node N varies not only according to the data written to memory cell 51, but also according to the potential of the wiring CAL. Therefore, after data is written to memory cell 51, the data stored in memory cell 51 can be corrected by adjusting the potential of the wiring CAL. For example, when correcting the data stored in memory cell 51, the potential of the wiring CAL when reading data from memory cell 51 can be different from the potential of the wiring CAL when reading data from memory cell 51 without correcting the data stored in memory cell 51. Therefore, for example, if the data written to memory cell is image data, semiconductor device 10C can perform image processing. Thus, semiconductor device 10C can, for example, be an image engine.

[0122] Note that in the semiconductor device 10C, i is preferably N / 2 or a value close to that. This allows, for example, the wiring distance from memory cell 51 to memory cell 31_1 or from memory cell 51 to memory cell 31_N to be shortened. Therefore, for example, when writing data from memory cell 51 to memory cell 31_1 or memory cell 31_N, the drop in data potential caused by wiring resistance such as wiring BL can be suppressed.

[0123] Figure 13 is a block diagram showing a structural example of semiconductor device 10D, which is a variation of semiconductor device 10C. Semiconductor device 10D differs from semiconductor device 10C in that it has a component layer 54 disposed above component layer 34_1, that is, between component layer 34_1 and component layer 40.

[0124] The semiconductor device 10D features a short wiring distance between the component layer 40 and component layer 54, which are equipped with a sense amplifier and the like. Therefore, the problem of difficulty in operation caused by the increased wiring resistance of the memory cell 51 can be solved, making it easier to control the operation of the memory cell 51. Alternatively, the component layer 54 can be disposed below the component layer 34_N, that is, for example, above the component layer 34_N.

[0125] Figure 14 is a perspective view showing the configuration of the various structures of the semiconductor device 10C shown in Figure 12A, with the x-axis, y-axis, and z-axis directions defined. Similarly, Figure 15 is a perspective view showing the configuration of the various structures of the semiconductor device 10D shown in Figure 13, with the x-axis, y-axis, and z-axis directions defined.

[0126] In the semiconductor device 10C having the structure shown in FIG. 14 and the semiconductor device 10D having the structure shown in FIG. 15, V element layers 40, N element layers 34_1 to 34_N, and one element layer 54 are stacked on a silicon substrate 11, totaling (N+V+1) layers including OS transistors. The memory cells 51 included in the element layer 54 have a region overlapping with the column driver 22 provided on the silicon substrate 11. In addition, more than two element layers 54 may be provided. For example, H element layers 54 (H is an integer greater than or equal to 1) may be provided. When H element layers 54 are provided in the semiconductor device 10C, a total of (N+V+H) layers including OS transistors are provided in the semiconductor device 10C.

[0127] Figure 16 is a perspective view illustrating the structure of a semiconductor device 10E with the x-axis, y-axis, and z-axis directions set. In the semiconductor device 10E, a component layer 40 including a sense amplifier can be disposed between component layers 34_i and 34_i+1, which may include DOSRAM. Furthermore, component layers 541, which may include DOSRAM, are disposed between component layers 34_i and 40, and between component layers 40 and 34_i+1, respectively. In other words, component layers 40 and 54 can be disposed between two component layers 34. Additionally, in the semiconductor device 10E, either a single component layer 54 or three or more component layers 54 can be disposed.

[0128] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors disposed in each element layer. Therefore, the update frequency of data stored in the memory cell can be reduced, and a low-power semiconductor device can be realized. OS transistors can be stacked and manufactured by repeatedly using the same process in the vertical direction, thus reducing manufacturing costs. Furthermore, in one embodiment of the present invention, the transistors constituting the memory cell can be arranged vertically rather than planarly to increase storage density, thereby enabling device miniaturization. In addition, OS transistors exhibit less variation in electrical characteristics even at high temperatures than Si transistors, thus enabling a semiconductor device with minimal variation in electrical characteristics when stacked and integrated, and suitable for use as a reliable memory device.

[0129] Furthermore, one embodiment of the present invention includes a component layer comprising a control circuit. The control circuit can be used as an amplifier. By employing this structure, a small potential difference in bit line BL can be amplified during readout to drive a sense amplifier using Si transistors. This allows for miniaturization of circuits such as sense amplifiers using Si transistors, thereby enabling miniaturization of semiconductor devices. Additionally, operation is possible even with reduced capacitance of the capacitors included in the memory cells. Furthermore, in one embodiment of the present invention, the bit lines extending from the memory cell array are configured in a vertical direction, thus shortening the length of the bit lines of the memory cell array and column drivers. This significantly reduces parasitic capacitance of the bit lines, enabling the readout potential of multi-level data signals stored in the memory cells. Furthermore, in one embodiment of the present invention, the data stored in the memory cells can be read out as current, thus facilitating easy readout of potentials even with multi-level operation.

[0130] Figure 17 shows a schematic cross-section of a plane parallel to the vertical direction (z-axis direction) of the semiconductor device 10B described with reference to Figures 11A and 11B.

[0131] As shown in Figure 17, the semiconductor device 10B can also be structured such that the memory cells 31_1 to 31_N of the element layers, the element layers 40, and the column driver 22 of the silicon substrate 11 are connected via bit lines BL and wiring GBL arranged in the vertical direction as the shortest distance. Although the number of element layers 40, including transistors constituting the control circuit, is increased, the number of vertical wirings connected to the column driver 22 can be reduced. By reducing the load on the bit lines BL, the write time can be shortened and data can be read more easily.

[0132] Furthermore, as shown in Figure 17, the transistors 41 to 44 included in the element layer 40 can be controlled according to the control signals WE, RE and the selection signal MUX output from the column driver 22. Each transistor can output the potential of the bit line BL to the column driver 22 through the wiring GBL according to the control signal and the selection signal. In addition, the semiconductor device 10B shown in Figure 17 can be represented by unit 50_1.

[0133] Next, referring to Figures 18A and 18B and Figures 19A and 19B, a specific structural example of a circuit used as a sense amplifier, which is composed of OS transistors included in element layer 40, will be described.

[0134] Figure 18A shows unit 50, which corresponds to unit 50_1 shown in Figure 17. In unit 50 shown in Figure 19A, element layer 40A includes transistors 41 to 44. Transistors 41 to 44 are each composed of an OS transistor and an n-channel transistor.

[0135] Transistor 41 is a source-follower transistor that amplifies the wiring GBL to a potential corresponding to the bit line BL during the data read signal from the memory cell. Transistor 42 is a switch that controls the conduction between its source and drain according to the selection signal MUX input to the gate. Transistor 43 is a switch that controls the conduction between its source and drain according to the write control signal WE input to the gate. Transistor 44 is a switch that controls the conduction between its source and drain according to the read control signal RE input to the gate. Additionally, a ground potential GND, which is a fixed potential, is applied to the source side of transistor 44.

[0136] Furthermore, the structure of component layer 40A shown in FIG18A can be adapted to the modified examples shown in FIG18B, FIG19A, and FIG19B. In the structure of component layer 40B in FIG18B, the wiring GBL connected to one of the source and drain terminals of transistor 43 is switched to one of the source and drain terminals of transistor 41. The structure of component layer 40C in FIG19A is equivalent to performing the function of transistor 42 in the column driver 22 while omitting the structure of transistor 42. The structure of component layer 40D in FIG19B is equivalent to omitting the structure of transistor 44.

[0137] Figure 20 shows a schematic diagram of the structure of cell 50_1 illustrated in stack-up diagram 17. As shown in Figure 17, the semiconductor device 10B shown in Figure 20 includes memory cells 31_1 to 31_N disposed in each element layer. In the semiconductor device 10B shown in Figure 20, memory cells 31_1 to 31_N and element layers 40_1 to 40_M are connected by bit lines BL disposed in the vertical direction as the shortest distance, and element layer 40 is connected to column driver 22 by wiring GBL.

[0138] Furthermore, the M units 50_1 to 50_M in the semiconductor device 10B shown in FIG. 18 can be stacked in the vertical direction. The semiconductor device 10B shown in FIG. 18 includes element layers 40_1 to 40_M in units 50_1 to 50_M, each comprising a circuit used as a sense amplifier made of OS transistors. In other words, the structure of the semiconductor device 10B shown in FIG. 20 is a structure with a total of M×(N+V) stacked element layers as shown in FIG. 17.

[0139] Figure 21 shows a schematic diagram of the structure of the semiconductor device 10D shown in Figure 14 used as unit 50. In each of units 50_1 to 50_M, element layers 40, 54, and 34_1 to 34_N are stacked in the vertical direction. Alternatively, semiconductor devices 10C and 10E can be used as unit 50.

[0140] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors disposed in each element layer. Therefore, the update frequency of data stored in the memory cell can be reduced, and a low-power semiconductor device can be realized. OS transistors can be stacked and manufactured by repeatedly using the same process in the vertical direction, thus reducing manufacturing costs. Furthermore, in one embodiment of the present invention, the transistors constituting the memory cell can be arranged vertically rather than planarly to increase storage density, thereby enabling device miniaturization. In addition, OS transistors exhibit less variation in electrical characteristics even at high temperatures than Si transistors, thus enabling a semiconductor device with minimal variation in electrical characteristics when stacked and integrated, and suitable for use as a reliable memory device.

[0141] Furthermore, one embodiment of the present invention includes an element layer comprising a control circuit. In the control circuit, the bit line BL is connected to the gate of the transistor 41, thus the transistor 41 is used as an amplifier. By employing this structure, the small potential difference of the bit line BL can be amplified during readout, thereby driving a sense amplifier using a Si transistor. This allows for the miniaturization of circuits such as sense amplifiers using Si transistors, thereby enabling the miniaturization of semiconductor devices. Additionally, operation is possible even with reduced capacitance of the capacitors included in the memory cells.

[0142] In Figure 22, in addition to the element layers 34_1 to 34_N illustrated in Figure 17, which are used as memory cell array 30, element layer 40 including transistors 41_a, 41_b, 42_a, 42_b, 43_a, 43_b, 44_a, and 44_b is shown. Element layers 34_1 to 34_N are disposed on element layer 40 including transistors 41_a, 41_b, 42_a, 42_b, 43_a, 43_b, 44_a, and 44_b, and bit lines BL_A and BL_B are disposed in the vertical direction. In other words, element layers including switching circuits that form part of peripheral circuitry can be stacked in the same manner as element layers 34_1 to 34_N. Bit lines BL_A and BL_B are connected to the gates of transistors 41_a and 41_b.

[0143] Additionally, as shown in Figure 22, the transistors 42_a, 42_b, 43_a, and 43_b included in component layer 40 are connected to wirings GBL_A and GBL_B. Similar to bit lines BL_A and BL_B, wirings GBL_A and GBL_B are arranged vertically and connected to the transistors included in column driver 22. Furthermore, control signals WE, RE, and MUX are supplied to the gates of the transistors 42_a, 42_b, 43_a, 43_b, 44_a, and 44_b included in component layer 40.

[0144] Additionally, in Figure 22, the circuitry included in the column driver 22 includes a pre-charge circuit 22_A, a pre-charge circuit 22_B, a sense amplifier 22_C, a switch circuit 22_D, a switch circuit 22_E, and a write / read circuit 29 located on the silicon substrate side. The transistors constituting the pre-charge circuits 22_A, 22_B, and the sense amplifier 22_C are Si transistors. The switches 23_A to 23_D constituting the switch circuits 22_D and 22_E can also be Si transistors. One of the source and drain terminals of transistors 42_a, 42_b, 43_a, and 43_b is connected to the transistor constituting the pre-charge circuits 22_A, 22_B, the sense amplifier 22_C, and the switch circuit 22_D.

[0145] The pre-charge circuit 22_A is composed of n-channel transistors 24_1 to 24_3. The pre-charge circuit 22_A is a circuit that pre-charges bit lines BL_A and BL_B to an intermediate potential VPC, which is equivalent to the potential VDD / 2 between VDD and VSS, according to the pre-charge signal supplied to the pre-charge line PCL1.

[0146] The pre-charge circuit 22_B is composed of n-channel transistors 24_4 to 24_6. The pre-charge circuit 22_B is a circuit that pre-charges wiring GBL_A and wiring GBL_B to an intermediate potential VPC, which is equivalent to the potential VDD / 2 between VDD and VSS, according to the pre-charge signal supplied to the pre-charge line PCL2.

[0147] The sensing amplifier 22_C is composed of p-channel transistors 25_1 and 25_2 and n-channel transistors 25_3 and 25_4 connected to wiring VHH or wiring VLL. Wiring VHH or wiring VLL is a wiring that supplies VDD or VSS. Transistors 25_1 to 25_4 are transistors that form an inverter loop. The sensing amplifier 22_C changes the potentials of bit lines BL_A and BL_B to either a high power supply potential VDD or a low power supply potential VSS based on the potential changes of bit lines BL_A and BL_B. The potentials of bit lines BL_A and BL_B are changed by setting word lines WL_A and WL_B to a high level and selecting memory cells 31_N_A and 31_N_B. The potentials of wirings GBL_A and GBL_B are output to the outside through switching circuits 22_D and 22_E and write / read circuit 25. Bit lines BL_A and BL_B, and wiring GBL_A and GBL_B are equivalent to bit line pairs. The write / read circuit 25 writes data based on the EN_data signal controlled by the data signal.

[0148] Switching circuit 22_D controls the conduction state between sense amplifier 22_C and wiring GBL_A and wiring GBL_B. Switching circuit 22_D can be switched on or off by the control switching signal CSEL1. When switches 23_A and 23_B are n-channel transistors, when the switching signal CSEL1 is active, switches 23_A and 23_B are on, and when the switching signal CSEL1 is active, switches 23_A and 23_B are off. Switching circuit 22_E controls the conduction state between write / read circuit 29 and the bit line pairs connected to sense amplifier 22_C. Switching circuit 22_D can be switched on or off by the control switching signal CSEL1. Similar to switches 23_A and 23_B, switches 23_C and 23_D can be switched on or off by the control switching signal CSEL2.

[0149] Additionally, Figure 23 shows a timing diagram illustrating the operation of the circuit diagram shown in Figure 22. In the timing diagram shown in Figure 23, period T11 corresponds to the write operation period, period T12 corresponds to the pre-charge operation period of bit line BL, period T13 corresponds to the pre-charge operation period of wiring GBL, period T14 corresponds to the charge sharing operation period, period T15 corresponds to the read standby operation period, and period T16 corresponds to the read operation period.

[0150] During period T11, the word line connecting the gate of the transistor included in the memory cell to which the data signal is to be written is set to a high level. At this time, the control signal WE and the signal EN_data are set to a high level, and the data signal is written to the memory cell through the wiring GBL and the bit line BL.

[0151] During period T12, in order to precharge bit line BL, with control signal WE at a high level, precharge line PCL1 is made high level. Bit line BL is precharged to the precharge potential. During period T12, it is preferable to make the wiring VHH or wiring VLL supplying the power supply voltage to the sensing amplifier 22_C VDD / 2 to suppress power consumption caused by the through current.

[0152] During period T13, in order to precharge the wiring GBL, the precharge line PCL2 is made to a high level. The wiring GBL is precharged to the precharge potential. During period T13, by making both wiring VHH and wiring VLL VDD, the heavily loaded wiring GBL can be precharged for a short time.

[0153] During period T14, in order to perform charge sharing to balance the pre-charged charges of bit lines BL and GBL, control signals WL and MUX are set to high levels. Bit lines BL and GBL are made to be at the same potential. During period T14, it is preferable to make the power supply voltage supplied to the sensing amplifier 22_C, either the wiring VHH or the wiring VLL, VDD / 2 to suppress power consumption caused by the through current.

[0154] During period T15, the control signal RE is set to a high level. Current flows through transistor 41 according to the potential of bit line BL, and the potential of wiring GBL changes according to the amount of current. The potential changes of wiring GBL are prevented from being affected by the sense amplifier 22_C by setting the switching signal CSEL1 to a low level. Wiring VHH or wiring VLL is the same as wiring VHH or wiring VLL in period T14.

[0155] During period T16, by making the switching signal CSEL1 a high level, the potential change of the wiring GBL is amplified by the bit line pair connected to the sensing amplifier 22_C, so as to read out the data signal written to the memory cell.

[0156] Furthermore, when using the circuit structure of element layer 40B in FIG18B, the semiconductor device 10B shown in FIG17 can be rewritten as the circuit diagram shown in FIG24. In FIG24, the transistors 42 of element layers 40_1 to 40_M included in each unit are extracted, and the switching circuit 49 composed of the transistors 42 is shown. In other words, by selecting any one of the memory cells 31_1 to 31_M selected by element layers 40_1 to 40_M selected by the switching circuit 49, data signals can be written or read.

[0157] In a semiconductor device according to one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors disposed on each element layer. OS transistors can be stacked on a silicon substrate on which Si transistors are disposed. Therefore, the same process can be repeatedly used in the vertical direction, thereby reducing manufacturing costs. In addition, in one embodiment of the present invention, the transistors constituting the memory cells can also be arranged in the vertical direction instead of the planar direction to increase memory density, thereby enabling device miniaturization.

[0158] Furthermore, one embodiment of the present invention includes an element layer comprising a control circuit. In the control circuit, the bit line BL is connected to the gate of the transistor 41, thus the transistor 41 is used as an amplifier. By employing this structure, the small potential difference of the bit line BL can be amplified during readout, thereby driving a sense amplifier using a Si transistor. This allows for the miniaturization of circuits such as sense amplifiers using Si transistors, thereby enabling the miniaturization of semiconductor devices. Additionally, operation is possible even with reduced capacitance of the capacitors included in the memory cells.

[0159] Implementation Method 4 A structural example of a semiconductor device and its operation method according to one embodiment of the present invention will be described with reference to Figures 25 to 29. The description of embodiments 1, using the same reference numerals as in Embodiment 1, is cited, and sometimes omits the description.

[0160] Figure 25A is a block diagram illustrating the semiconductor device described in this embodiment. The semiconductor device 10F shown in Figure 1A includes peripheral circuitry 20 and a memory cell array 30.

[0161] The memory cell array 30 includes multiple or single-layer element layers 34. Element layer 34 includes one or more memory cells 31_1 to 31_N (N is a natural number greater than 2). Memory cell 31_1 includes a transistor 32_1 and a capacitor 33_1. Memory cell 31_N includes a transistor 32_N and a capacitor 33_N. Note that capacitors are sometimes referred to as capacitor elements. Note that an element layer is a layer in which elements such as capacitors or transistors are disposed, and is formed of components such as conductors, semiconductors, and insulators.

[0162] In the structures illustrated in FIG25A, the element layer 34 in one embodiment of the present invention will be described with reference to the schematic diagram in FIG25B. To illustrate the configuration of the structures illustrated in FIG25A, the schematic diagram in FIG25B corresponds to a perspective view with the x-axis, y-axis, and z-axis directions defined.

[0163] As shown in FIG25B, the element layer 34 including memory cells 31_1 to 31_N has a region that overlaps with the column driver 22 disposed on the silicon substrate 11.

[0164] The transistors of memory cells 31_1 included in component layer 34 are connected to column drivers 22 via bit lines BL_1 arranged in the vertical direction. The transistors of memory cells 31_N included in component layer 34 are connected to column drivers 22 via bit lines BL_N arranged in the vertical direction. Bit lines BL_1 and BL_N, as well as other bit lines BL, are connected to column drivers 22 disposed on silicon substrate 11.

[0165] In one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors disposed in each element layer. Therefore, the update frequency of data stored in the memory cells can be reduced, enabling a low-power semiconductor device. OS transistors can be stacked and manufactured using the same process repeatedly in the vertical direction, thus reducing manufacturing costs. Furthermore, in one embodiment of the present invention, the transistors constituting the memory cells can be arranged vertically rather than planarly to increase storage density, thereby enabling device miniaturization. Additionally, OS transistors exhibit less variation in electrical characteristics even at high temperatures than Si transistors, thus enabling a semiconductor device with minimal variation in electrical characteristics when stacked and integrated, and suitable for use as a reliable memory device. Furthermore, in one embodiment of the present invention, the bit lines extending from the memory cell array are arranged vertically, thus shortening the length of the bit lines of the memory cell array and column drivers. This significantly reduces the parasitic capacitance of the bit lines, allowing multiple levels of data signals stored in the memory cells to be read out.

[0166] Figure 26 shows a schematic cross-section of a plane parallel to the vertical direction (z-axis direction) of the semiconductor device 10F described with reference to Figures 25A and 25B.

[0167] As shown in Figure 26, the semiconductor device 10F can also be structured such that the memory cells 31_1 to 31_N disposed on the element layer 34 and the column driver 22 disposed on the silicon substrate 11 are connected via bit lines BL disposed in the vertical direction as the shortest distance. Compared with a structure in which the bit lines are arranged in a planar direction, although the number of bit lines increases, the number of memory cells connected to a single bit line can be reduced, thus reducing the parasitic capacitance of the bit lines. Therefore, even if the capacitance of the capacitors included in the memory cells is reduced, the potential changes of the bit lines that occur when charge moves can be minimized.

[0168] Furthermore, because the capacitance of capacitors 33_1 to 33_N included in memory cells 31_1 to 31_N can be reduced, capacitors 33_1 to 33_N can be disposed on the same layer as transistors 32_1 to 32_N. By disposing capacitors 33_1 to 33_N on the same layer as transistors 32_1 to 32_N, the element layers 34_1 to 34_N of each layer can be thinned. Therefore, miniaturization of the semiconductor device 10F is possible.

[0169] Furthermore, the capacitors 33_1 to 33_N included in the memory cells 31_1 to 31_N can be arranged in the same layer as the transistors 32_1 to 32_N, or other structures can be used. For example, the schematic diagram shown in FIG27A illustrates a structure in which the capacitor 33A of the memory cell 31 included in the element layers 34_1 to 34_N is arranged above the transistor 32 in the vertical direction. By adopting this structure, the capacitance can be increased, thereby improving the reliability of the read data and extending the data retention time. In addition, in the structure of FIG27A, one electrode of the capacitor 33A connected to a fixed potential can be arranged above the transistor 32, thereby suppressing the influence of external noise.

[0170] Furthermore, the schematic diagram shown in Figure 27B illustrates a structure in which the capacitor 33B of the memory cell 31 included in the element layers 34_1 to 34_N is disposed below the transistor 32 in the vertical direction. By employing this structure, the capacitance can be increased, thereby improving the reliability of the read data and extending the data retention time. Additionally, in the structure of Figure 27B, a capacitor 33B with one electrode connected to a fixed potential can be positioned between the transistor 32 and the column driver 22, thus suppressing the influence of noise from the column driver 22 on the memory cell 31.

[0171] Figure 28 shows a circuit diagram illustrating an example of the circuit structure of the memory cell array 30 including the element layer 34 illustrated in Figure 25A, and a specific example of the circuit structure of the column driver 22 connected to the memory cell.

[0172] In Figure 28, element layer 34 is shown as memory cell array 30. In Figure 28, memory cell 31_N_A is shown as a memory cell connected to bit line BL_A. Memory cell 31_N_A includes a transistor 32A whose gate is connected to word line WL_A and a capacitor 33. Additionally, in Figure 28, memory cell 31_N_B is shown as a memory cell connected to bit line BL_B. Memory cell 31_N_B includes a transistor 32B whose gate is connected to word line WL_B and a capacitor 33. The capacitor 33 of each element layer is connected to wiring VL, which is supplied with a fixed potential such as ground potential.

[0173] Additionally, in Figure 28, the circuitry included in the column driver 22 includes a pre-charge circuit 22_1, a sense amplifier 22_2, a switch circuit 22_3, and a write / read circuit 29 located on the silicon substrate side. The transistors constituting the pre-charge circuit 22_1 and the sense amplifier 22_2 are Si transistors. The selection switch 22_3 may also be a Si transistor.

[0174] Additionally, Figure 29 shows a timing diagram illustrating the operation of the circuit diagram shown in Figure 28. In the timing diagram shown in Figure 29, period T1 corresponds to the initialization period, period T2 corresponds to the write period, period T3 corresponds to the non-access period, and period T4 corresponds to the read period.

[0175] In a semiconductor device according to one embodiment of the present invention, OS transistors with extremely low off-state current are used as transistors disposed in each element layer. OS transistors can be stacked on a silicon substrate on which Si transistors are disposed. Therefore, the same process can be repeatedly used in the vertical direction, thereby reducing manufacturing costs. In addition, in one embodiment of the present invention, the transistors constituting the memory cells can be arranged in the vertical direction instead of the planar direction to increase memory density, thereby enabling device miniaturization.

[0176] Implementation Method 5 In this embodiment, a modified example of the circuit applicable to the semiconductor device 10 described in Embodiment 1 will be described with reference to FIG30.

[0177] In the memory cells included in the element layers 34_1 to 34_N described above, the transistors shown in the diagram do not have a top-gate structure or a bottom-gate structure with a back gate electrode; however, the structure of transistor 32 is not limited to this. For example, as shown in FIG30, the transistor included in memory cell 31 can be a transistor 32 having a back gate electrode connected to the back gate electrode line BGL. By adopting the structure shown in FIG30, the electrical characteristics of transistor 32, such as the threshold voltage, can be easily controlled externally.

[0178] Implementation Method 6 In this embodiment, a modified example of the circuit applicable to the semiconductor device 10A described in Embodiment 2 will be illustrated with reference to FIG31.

[0179] The transistor illustration of the switching circuit constituting element layer 26 described above does not include a top-gate structure or a bottom-gate structure with a back-gate electrode; however, the transistor structure is not limited to these. For example, as shown in FIG31, the transistor constituting the switching circuit 27 can be a transistor 28 having a back-gate electrode connected to the back-gate electrode line BGL. By adopting the structure shown in FIG31, the electrical characteristics of the transistor 28, such as the threshold voltage, can be easily controlled externally.

[0180] Implementation Method 7 In this embodiment, a modified example of the circuit applicable to the semiconductor device 10B described in Embodiment 3 will be illustrated with reference to FIG32.

[0181] In the memory cells included in the element layers 34_1 to 34_N described above, the transistors shown in the diagram do not have a top-gate structure or a bottom-gate structure with a back gate electrode; however, the structure of transistor 32 is not limited to this. For example, as shown in FIG32, the transistor included in memory cell 31 can be a transistor 32 having a back gate electrode connected to the back gate electrode line BGL. By adopting the structure shown in FIG32, the electrical characteristics of transistor 32, such as the threshold voltage, can be easily controlled externally.

[0182] Implementation Method 8 In this embodiment, a modified example of a circuit applicable to the semiconductor device described in Embodiment 4 will be illustrated with reference to FIG33.

[0183] In the memory cells included in the element layer 34 described above, the transistors shown in the diagram do not have a top-gate structure or a bottom-gate structure with a back gate electrode; however, the structure of transistor 32 is not limited to this. For example, as shown in FIG33, the transistor included in the memory cell 31 can be a transistor 32 having a back gate electrode connected to the back gate electrode line BGL. By adopting the structure shown in FIG33, the electrical characteristics of transistor 32, such as the threshold voltage, can be easily controlled externally.

[0184] Implementation Method 9 The following describes an example of a semiconductor device used as a memory device according to an embodiment of the present invention.

[0185] Figure 34 is a diagram illustrating an example of a semiconductor device in which memory cells 470 (memory cells 470_1 to 470_m: m is a natural number of 2 or more) are stacked on a component layer 411 including a circuit disposed on a semiconductor substrate 311. In Figure 34, a component layer 411 and a plurality of memory cells 470 on the component layer 411 are stacked. In each of the plurality of memory cells 470, a transistor layer 413 (transistor layer 413_1 to transistor layer 413_m) and a plurality of memory device layers 415 (memory device layers 415_1 to 415_n: n is a natural number of 2 or more) are respectively disposed. In addition, an example is shown where a memory device layer 415 is disposed on a transistor layer 413 for each memory cell 470; however, this embodiment is not limited to this. The transistor layer 413 can be disposed on multiple memory device layers 415, and the memory device layer 415 can be disposed above and below the transistor layer 413.

[0186] The component layer 411 may include transistors 300 disposed on the semiconductor substrate 311 and circuits (sometimes referred to as peripheral circuits) used as semiconductor devices. Examples of such circuits include column drivers, row drivers, column decoders, row decoders, sense amplifiers, precharge circuits, amplifier circuits, word line drive circuits, output circuits, and control logic circuits.

[0187] Transistor layer 413 may include transistor 200T and is used as circuitry to control each memory cell 470. Memory device layer 415 includes memory device 420. The memory device 420 shown in this embodiment includes transistor 200M and capacitor element 292.

[0188] Furthermore, there are no particular restrictions on the value of m, but it is preferably 2 or higher and 100 or lower, more preferably 2 or higher and 50 or lower, and even more preferably 2 or higher and 10 or lower. Similarly, there are no particular restrictions on the value of n, but it is preferably 2 or higher and 100 or lower, more preferably 2 or higher and 50 or lower, and even more preferably 2 or higher and 10 or lower. Additionally, the product of m and n is preferably 4 or higher and 256 or lower, more preferably 4 or higher and 128 or lower, and even more preferably 4 or higher and 64 or lower.

[0189] In addition, Figure 34 shows a cross-sectional view along the channel length of the transistors 200T and 200M included in the memory cell.

[0190] As shown in Figure 34, a transistor 300 is disposed on a semiconductor substrate 311. A transistor layer 413 and a memory device layer 415, comprising a memory cell 470, are disposed on the transistor 300. In one memory cell 470, the transistor 200T included in the transistor layer 413 and the memory device 420 included in the memory device layer 415 are electrically connected by a plurality of conductors 424. The transistor 300 and the transistor 200T included in the transistor layer 413 of each memory cell 470 are electrically connected by conductors 426. Furthermore, the conductor 426 is preferably electrically connected to the transistor 200T via a conductor 428 electrically connected to any one of the source, drain, and gate of the transistor 200T. The conductors 424 are preferably disposed in each layer of the memory device layer 415. Additionally, the conductors 426 are preferably disposed in each layer of the transistor layer 413 and the memory device layer 415.

[0191] Furthermore, it is preferable to provide an insulator on the side of conductor 424 and the side of conductor 426 to suppress the permeation of impurities such as water or hydrogen, or oxygen. Details will be explained later. As such an insulator, silicon nitride, aluminum oxide, or silicon oxynitride are preferably used.

[0192] The memory device 420 includes a transistor 200M and a capacitor element 292. The transistor 200M has the same structure as the transistor 200T included in the transistor layer 413. In addition, the transistors 200T and 200M are collectively referred to as transistor 200.

[0193] Here, it is preferred that the metal oxide (hereinafter sometimes referred to as oxide semiconductor) used as an oxide semiconductor in the transistor 200 is used in the semiconductor that includes the region in which the channel is formed (hereinafter sometimes referred to as the channel forming region).

[0194] For example, In-M-Zn oxides (where element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) are preferred as oxide semiconductors. Indium oxide, In-Ga oxide, and In-Zn oxide are also preferred as oxide semiconductors. Note that by using oxide semiconductors with a high indium ratio, the on-state current or field-effect mobility of the transistor can be improved.

[0195] Because the leakage current of the transistor 200, which uses oxide semiconductors in the channel formation region, is extremely small in the non-conducting state, a low-power semiconductor device can be provided. Furthermore, since oxide semiconductors can be formed using methods such as sputtering, they can be used to construct transistors 200 for highly integrated semiconductor devices.

[0196] On the other hand, in transistors using oxide semiconductors, their electrical characteristics vary due to impurities and oxygen vacancies (also known as VO:oxygen vacancy) in the oxide semiconductor. Therefore, such transistors tend to have always-on characteristics (meaning that the channel exists and current flows through the transistor even when no voltage is applied to the gate electrode).

[0197] Therefore, it is preferable to use an oxide semiconductor in which the impurity concentration and defect state density are reduced. Note that in this specification, the case of low impurity concentration and low defect state density is referred to as high purity or substantially high purity.

[0198] Therefore, it is preferable to minimize the impurity concentration in oxide semiconductors. Other examples of impurities in oxide semiconductors include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0199] In particular, hydrogen, as an impurity contained in oxide semiconductors, sometimes forms oxygen vacancies in the oxide semiconductor. Furthermore, defects in oxygen vacancies (hereinafter sometimes referred to as VOHs) may generate electrons that can become carriers. Moreover, a portion of the hydrogen may react with oxygen atoms bonded to metal atoms to generate electrons that can become carriers.

[0200] Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have always-on characteristics. Furthermore, because hydrogen in oxide semiconductors is easily mobile due to heat, electric fields, etc., a large amount of hydrogen in the oxide semiconductor may lead to a decrease in transistor reliability.

[0201] Therefore, as an oxide semiconductor used in transistor 200, it is preferable to use an oxide semiconductor with high purity, which reduces impurities such as hydrogen and oxygen vacancies.

[0202] <Sealing Structure> Therefore, in order to suppress impurities introduced from the outside, it is preferable to use a material that suppresses the diffusion of impurities (hereinafter also referred to as a material that blocks impurities) to seal the transistor 200.

[0203] Note that in this specification, barrier properties refer to the ability to inhibit the diffusion of the corresponding substance (also known as low permeability). Alternatively, it refers to the ability to capture and fix the corresponding substance (also known as gettering).

[0204] For example, materials that can inhibit the diffusion of hydrogen and oxygen include aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride. In particular, silicon nitride or silicon oxynitride has high hydrogen barrier properties, so it is preferred as a sealing material.

[0205] For example, metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide are materials that can capture and fix hydrogen.

[0206] As a barrier layer, insulators 211, 212, and 214 are preferably disposed between transistors 300 and 200. By using a material that inhibits the diffusion or permeation of impurities such as hydrogen in at least one of insulators 211, 212, and 214, the diffusion of impurities such as hydrogen or water contained in the semiconductor substrate 311 and transistor 300 into transistor 200 can be suppressed. Furthermore, by using a material that inhibits oxygen permeation in at least one of insulators 211, 212, and 214, the diffusion of oxygen contained in the channels of transistor 200 or transistor layer 413 into element layer 411 can be suppressed. For example, materials that inhibit the permeation of impurities such as hydrogen or water are used as insulators 211 and 212, and materials that inhibit oxygen permeation are preferably used as insulator 214. Additionally, materials with hydrogen absorption and storage properties are preferably used as insulator 214. For example, silicon nitride and silicon oxynitride can be used as insulators 211 and 212. For example, metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide can be used as insulator 214. It is particularly preferred that aluminum oxide is used as insulator 214.

[0207] Furthermore, an insulator 287 is preferably disposed on the side surface of the transistor layer 413 and the memory device layer 415, that is, on the side surface of the memory cell 470, and an insulator 282 is preferably disposed on the top surface of the memory cell 470. In this case, the insulator 282 is preferably in contact with the insulator 287, and the insulator 287 is preferably in contact with at least one of the insulators 211, 212, and 214. The insulators 287 and 282 are preferably made of a material suitable for the insulator 214.

[0208] Furthermore, it is preferable that insulators 283 and 284 are provided in a manner that covers insulators 282 and 287, and insulator 283 preferably contacts at least one of insulators 211, 212, and 214. In FIG. 34, an example is shown where insulator 287 contacts the side surface of insulator 214, the side surface of insulator 212, and the top and side surfaces of insulator 211, and insulator 283 contacts the top and side surfaces of insulator 287 and the top surface of insulator 211; however, this embodiment is not limited to this. Insulator 287 may also contact the side surface of insulator 214 and the top and side surfaces of insulator 212, and insulator 283 may also contact the top and side surfaces of insulator 287 and the top surface of insulator 212. Preferably, materials suitable for insulators 211 and 212 are used for insulators 282 and 287.

[0209] In the above structure, insulators 287 and 282 are preferably made of materials that suppress oxygen permeation. Furthermore, insulators 287 and 282 are more preferably made of materials that trap and fix hydrogen. By using a material with hydrogen trapping and fixing function on the side adjacent to the transistor 200, hydrogen in the transistor 200 or memory cell 470 is trapped and fixed by insulators 214, 287, and 282, thereby reducing the hydrogen concentration in the transistor 200. Additionally, insulators 283 and 284 are preferably made of materials that suppress the permeation of impurities such as hydrogen or water.

[0210] By employing the above structure, the memory cell 470 is surrounded by insulators 211, 212, 214, 287, 282, 283, and 284. Specifically, the memory cell 470 is surrounded by insulators 214, 287, and 282 (sometimes referred to as a first structure), and the memory cell 470 and the first structure are surrounded by insulators 211, 212, 283, and 284 (sometimes referred to as a second structure). Furthermore, such a structure, where multiple structures surround the memory cell 470 in two or more layers, is sometimes referred to as a nested structure. Here, the case where the memory cell 470 is surrounded by multiple structures is described as the case where the memory cell 470 is sealed by multiple insulators.

[0211] Furthermore, the second structure seals the transistor 200 through the first structure. Therefore, the second structure can suppress the diffusion of hydrogen present outside the second structure into the interior of the second structure (on the transistor 200 side). In other words, the first structure can efficiently capture and immobilize hydrogen present in the internal structure of the second structure.

[0212] Specifically, the first structure can be a metal oxide such as aluminum oxide, while the second structure can be a nitride such as silicon nitride. More specifically, it is preferable to place an aluminum oxide film between the transistor 200 and the silicon nitride film.

[0213] Furthermore, as a material used in structures, the hydrogen concentration in the membrane can be reduced by appropriately setting the film formation conditions.

[0214] Generally, membranes formed by CVD have higher coverage than those formed by sputtering. On the other hand, the compound gases used in CVD often contain hydrogen, therefore membranes formed by CVD have a higher hydrogen content than those formed by sputtering.

[0215] Therefore, for example, the film adjacent to the transistor 200 is preferably a film with a reduced hydrogen concentration (specifically, a film formed by sputtering). On the other hand, when a film with high coverage and a high hydrogen concentration (specifically, a film formed by CVD) is used as a film to suppress the diffusion of impurities, it is preferable to place a film with the function of trapping and fixing hydrogen and with a reduced hydrogen concentration between the transistor 200 and the film with a high hydrogen concentration and high coverage.

[0216] In other words, it is preferable to use a membrane with a lower hydrogen concentration as the membrane disposed adjacent to the transistor 200. On the other hand, it is preferable to dispose of the membrane with a higher hydrogen concentration separately from the transistor 200.

[0217] Specifically, when sealing the transistor 200 with a silicon nitride film formed by CVD, it is preferable to place an alumina film formed by sputtering between the transistor 200 and the silicon nitride film formed by CVD. More preferably, it is preferable to place a silicon nitride film formed by sputtering between the silicon nitride film formed by CVD and the alumina film formed by sputtering.

[0218] In addition, when using CVD to form films, the concentration of hydrogen contained in the formed film can be reduced by using a compound gas that does not contain hydrogen atoms or has a low hydrogen atom content.

[0219] Furthermore, it is preferable to provide insulators 282 and 214 between each transistor layer 413 and memory device layer 415, or between each memory device layer 415. It is also preferable to provide insulator 296 between insulator 282 and insulator 214. The same material as insulator 283 and insulator 284 can be used as insulator 296. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, known insulating materials can be used. Here, insulators 282, 296, and 214 can also be elements constituting transistor 200. Insulators 282, 296, and 214 serving as components of transistor 200 reduces the number of processes required to manufacture the semiconductor device, which is therefore preferable.

[0220] Furthermore, it is preferable that the sides of the insulators 282, 296, and 214 disposed between each transistor layer 413 and memory device layer 415, or between each memory device layer 415, are in contact with the insulator 287. With this structure, the transistor layer 413 and memory device layer 415 are surrounded and sealed by the insulators 282, 296, 214, 287, 283, and 284, respectively.

[0221] Alternatively, an insulator 274 may be disposed around an insulator 284. Alternatively, a conductor 430 may be formed by embedding it into insulators 274, 284, 283, and 211. The conductor 430 is electrically connected to the transistor 300, i.e., the circuitry included in the element layer 411.

[0222] Furthermore, in the memory device layer 415, the capacitor element 292 is disposed on the same layer as the transistor 200M. Therefore, the height of the memory device 420 and the height of the transistor 200M can be made to be similar, thus preventing the height of each memory device layer 415 from becoming too large. As a result, it is relatively easy to increase the number of memory device layers 415. For example, the layers consisting of the transistor layer 413 and the memory device layer 415 can be stacked to about 100 layers.

[0223] <Telecon 200> Referring to FIG35A, a transistor 200 that can be used in transistor 200T included in transistor layer 413 and transistor 200M included in memory device 420 is described.

[0224] As shown in Figure 35A, transistor 200 includes insulator 216, conductor 205 (conductor 205a and conductor 205b), insulator 222, insulator 224, oxide 230 (oxide 230a, oxide 230b and oxide 230c), conductor 242 (conductor 242a and conductor 242b), oxide 243 (oxide 243a and oxide 243b), insulator 272, insulator 273, insulator 250, and conductor 260 (conductor 260a and conductor 260b).

[0225] Furthermore, an insulator 216 and a conductor 205 are provided on insulator 214, and an insulator 280 and an insulator 282 are provided on insulator 273. Insulators 214, 280, and 282 can be considered as part of transistor 200.

[0226] Additionally, one embodiment of the semiconductor device of the present invention includes a conductor 240 (conductor 240a and conductor 240b) electrically connected to a transistor 200 and used as a plug. Alternatively, an insulator 241 (insulator 241a and insulator 241b) may be provided in contact with the side of the conductor 240. Furthermore, conductors 246 (conductor 246a and conductor 246b) electrically connected to the conductor 240 and used as wiring are provided on the insulator 282 and the conductor 240.

[0227] Furthermore, conductors 240a and 240b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. Additionally, conductors 240a and 240b may have a laminated structure.

[0228] When the conductor 240 adopts a multilayer structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen and oxygen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are preferred. Furthermore, the conductive material with the function of suppressing the permeation of impurities such as water or hydrogen and oxygen can be used as a single layer or in multilayers. By using this conductive material, impurities such as water or hydrogen diffusing from the insulator 280 can be further reduced from entering the oxide 230 through conductors 240a and 240b. In addition, oxygen added to the insulator 280 can be prevented from being absorbed into conductors 240a and 240b.

[0229] Furthermore, the insulator 241, which is provided in contact with the side of the conductor 240, can be, for example, silicon nitride, aluminum oxide, or silicon oxynitride. Because the insulator 241 is provided in contact with insulators 272, 273, 280, and 282, impurities such as water or hydrogen from insulators 280 can be suppressed from entering the oxide 230 through conductors 240a and 240b. In particular, silicon nitride is preferred due to its high hydrogen barrier properties. Furthermore, it can prevent the absorption of oxygen contained in the insulator 280 by conductors 240a and 240b.

[0230] The conductor 246 is preferably made of a conductive material with tungsten, copper, or aluminum as the main component. Additionally, the conductor may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride with the aforementioned conductive material. Furthermore, the conductor may be formed by being embedded in an opening in an insulator.

[0231] In transistor 200, conductor 260 is used as the first gate of the transistor, while conductor 205 is used as the second gate of the transistor. In addition, conductors 242a and 242b are used as source electrodes or drain electrodes.

[0232] Oxide 230 is used as a semiconductor including the channel formation region.

[0233] Insulator 250 is used as the first gate insulator. Insulators 222 and 224 are used as the second gate insulators.

[0234] Here, in the transistor 200 shown in FIG35A, a conductor 260 is formed in a self-aligned manner in the openings provided in the insulator 280, insulator 273, insulator 272 and conductor 242, with oxide 230c and insulator 250 in between.

[0235] In other words, the conductor 260 is formed by being embedded in an opening including the insulator 280, with the oxide 230c and the insulator 250 in between. Therefore, the alignment of the conductor 260 is not required in the region between the conductor 242a and the conductor 242b.

[0236] Here, it is preferable to place oxide 230c within the opening formed in insulator 280, etc. Therefore, insulator 250 and conductor 260 include regions overlapping with the stacked structures of oxide 230c, oxide 230b, and oxide 230a. By employing this structure, oxide 230c and insulator 250 can be formed continuously, thereby maintaining the cleanliness of the interface between oxide 230 and insulator 250. Therefore, the influence of interface scattering on carrier conduction is reduced, thereby enabling transistor 200 to achieve high on-state current and high frequency characteristics.

[0237] In the transistor 200 shown in Figure 35A, the bottom and side surfaces of the conductor 260 are in contact with the insulator 250. Furthermore, the bottom and side surfaces of the insulator 250 are in contact with the oxide 230c.

[0238] Furthermore, as shown in Figure 35A, the transistor 200 has a structure in which the insulator 282 and the oxide 230c are in direct contact. By employing this structure, the diffusion of oxygen contained in the insulator 280 into the conductor 260 can be suppressed.

[0239] Therefore, the oxygen contained in the insulator 280 can be efficiently supplied to oxides 230a and 230b by oxide 230c, thereby reducing oxygen vacancies in oxides 230a and 230b and improving the electrical characteristics and reliability of transistor 200.

[0240] The detailed structure of a semiconductor device including a transistor 200 according to one embodiment of the present invention will now be described.

[0241] Alternatively, it is preferable that the metal oxide (hereinafter, sometimes referred to as oxide semiconductor) used as an oxide semiconductor is used in the transistor 200 for the oxide 230 (oxide 230a, oxide 230b and oxide 230c) including the channel forming region.

[0242] For example, the bandgap of the metal oxide used as an oxide semiconductor is 2 eV or higher, preferably 2.5 eV or higher. By using a metal oxide with a wider bandgap, the leakage current (off-state current) of the transistor 200 in the non-conducting state can be minimized. By employing such a transistor, low-power semiconductor devices can be provided.

[0243] Specifically, the oxide 230 is preferably an In-M-Zn oxide (where element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). In particular, aluminum, gallium, yttrium, or tin can be used as element M. Furthermore, In-M oxide, In-Zn oxide, or M-Zn oxide can also be used as oxide 230.

[0244] As shown in Figure 35A, oxide 230 preferably includes oxide 230a on insulator 224, oxide 230b on oxide 230a, and oxide 230c disposed on oxide 230b, at least a portion of which is in contact with the top surface of oxide 230b. Preferably, oxide 230c is disposed such that its side surface is in contact with oxide 243a, oxide 243b, conductor 242a, conductor 242b, insulator 272, insulator 273, and insulator 280.

[0245] In other words, oxide 230 includes oxide 230a, oxide 230b on oxide 230a, and oxide 230c on oxide 230b. When oxide 230a is disposed under oxide 230b, the diffusion of impurities from the structure formed under oxide 230a to oxide 230b can be suppressed. When oxide 230c is disposed on oxide 230b, the diffusion of impurities from the structure formed above oxide 230c to oxide 230b can be suppressed.

[0246] Note that in transistor 200, three layers of oxide 230a, oxide 230b, and oxide 230c are stacked in and around the channel forming region, but the present invention is not limited thereto. For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or a stacked structure of four or more layers can be provided. For example, oxide 230c can also have a two-layer structure to form a four-layer stacked structure.

[0247] Furthermore, oxide 230 preferably has a layered structure composed of oxides in which the atomic ratios of each metal atom are different. Specifically, the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 230a is preferably greater than that of element M in the constituent elements of the metal oxide used for oxide 230b. Additionally, the atomic ratio of element M relative to In in the metal oxide used for oxide 230a is preferably greater than that of element M relative to In in the metal oxide used for oxide 230b. Furthermore, the atomic ratio of In relative to element M in the metal oxide used for oxide 230b is preferably greater than that of In relative to element M in the metal oxide used for oxide 230a. Additionally, oxide 230c can use a metal oxide that can be used for either oxide 230a or oxide 230b.

[0248] Specifically, as oxide 230a, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or similar, or an In:Ga:Zn ratio of 1:1:0.5 or similar, can be used.

[0249] Alternatively, as oxide 230b, a metal oxide with an In:Ga:Zn ratio of 4:2:3 or similar, or an In:Ga:Zn ratio of 1:1:1 or similar, can be used. Alternatively, as oxide 230b, a metal oxide with an In:Ga:Zn ratio of 5:1:3 or similar, or an In:Ga:Zn ratio of 10:1:3 or similar, can also be used. Furthermore, In-Zn oxides (e.g., In:Zn = 2:1 or similar, In:Zn = 5:1 or similar, or In:Zn = 10:1 or similar) can also be used. Additionally, In oxides can also be used as oxide 230b.

[0250] Alternatively, as oxide 230c, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or similar, a Ga:Zn ratio of 2:1 or similar, or a Ga:Zn ratio of 2:5 or similar can be used. Furthermore, as oxide 230c, a material suitable for oxide 230b can be used, and it can be arranged in a single layer or in a stack. For example, as specific examples of oxide 230c having a layered structure, we can cite layered structures with In:Ga:Zn = 4:2:3 [atomic ratio] or near and In:Ga:Zn = 1:3:4 [atomic ratio] or near, Ga:Zn = 2:1 [atomic ratio] or near and In:Ga:Zn = 4:2:3 [atomic ratio] or near, Ga:Zn = 2:5 [atomic ratio] or near and In:Ga:Zn = 4:2:3 [atomic ratio] or near, and gallium oxide and In:Ga:Zn = 4:2:3 [atomic ratio] or near, etc.

[0251] Note that the structure of the OS transistor included in the memory cell array 30 shown in Embodiment 1 can also be different from the structure of the OS transistor included in the element layer 40. For example, the oxide 230c included in the OS transistor provided in the memory cell array 30 can be a metal oxide with an In:Ga:Zn ratio of 4:2:3 or similar, and the oxide 230c included in the OS transistor provided in the element layer 40 can be a metal oxide with an In:Ga:Zn ratio of 5:1:3 or similar, an In:Ga:Zn ratio of 10:1:3 or similar, an In:Zn ratio of 10:1 or similar, an In:Zn ratio of 5:1 or similar, or an In:Zn ratio of 2:1 or similar.

[0252] Furthermore, in oxides 230b and 230c, increasing the indium ratio in the film can improve the on-state current or field-effect mobility of the transistor, which is therefore preferable. Additionally, the aforementioned near-surface composition includes a range of ±30% of the desired atomic number ratio.

[0253] Furthermore, oxide 230b can also be crystalline. For example, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferred. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, oxygen extraction from oxide 230b at the source or drain electrode can be suppressed. In addition, even with heat treatment, oxygen extraction from oxide 230b can be reduced, so transistor 200 is also stable at high temperatures (so-called thermal budget) during the process.

[0254] Conductor 205 is arranged to overlap with oxide 230 and conductor 260. Alternatively, conductor 205 is preferably disposed in an insulator 216.

[0255] When conductor 205 is used as a gate, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential supplied to conductor 205 without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, the Vth of transistor 200 can be increased and the off-state current can be reduced. Therefore, compared with not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential applied to conductor 260 is 0V.

[0256] Additionally, as shown in FIG35A, the conductor 205 is preferably larger than the region in oxide 230 that does not overlap with conductors 242a and 242b. Although not shown here, the conductor 205 preferably extends beyond the region outside oxides 230a and 230b in the channel width direction of oxide 230. That is, preferably, conductors 205 and 260 overlap with an insulator on the outer side of the side in the channel width direction of oxide 230. By making the conductor 205 large, localized charging (also known as charge up) can sometimes be mitigated in plasma processing after the conductor 205 is formed. However, one embodiment of the invention is not limited to this. It is sufficient that the conductor 205 overlaps at least with the oxide 230 located between conductors 242a and 242b.

[0257] Furthermore, taking the bottom surface of insulator 224 as a standard, the bottom surface of conductor 260 in the region where oxides 230a and 230b do not overlap with conductor 260 is preferably located at a position lower than the bottom surface of oxide 230b.

[0258] Although not illustrated, by having the conductor 260, used as a gate, have a structure in the channel width direction such that the sides and top surfaces of the oxide 230b, which covers the channel-forming region, separated by the oxide 230c and the insulator 250, it is easy for the electric field generated from the conductor 260 to act on the entire channel-forming region formed in the oxide 230b. Therefore, the on-state current of the transistor 200 can be increased to improve the frequency characteristics. In this specification, the structure of the transistor in which the electric fields of the conductor 260 and the conductor 205 surround the channel-forming region is referred to as a surrounded channel (S-channel) structure.

[0259] Conductor 205a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen, as well as oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Furthermore, conductor 205b is preferably a conductive material with tungsten, copper, or aluminum as its main components. Although a two-layer structure of conductor 205 is shown, conductor 205 can also have a multi-layer structure with three or more layers.

[0260] Here, by continuously forming different types of films in a manner that does not expose them to the atmosphere, an oxide semiconductor film with substantially high purity and reduced impurity (especially hydrogen and water) concentration can be formed, which is preferable.

[0261] At least one of insulators 222, 272, and 273 is preferably used as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into the transistor 200 from one side or above the substrate. Therefore, at least one of insulators 222, 272, and 273 is preferably an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate). Furthermore, it is preferable to use an insulating material that has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate).

[0262] For example, silicon nitride or silicon oxynitride is preferably used as insulator 273, while aluminum oxide or hafnium oxide is preferably used as insulator 222 and insulator 272.

[0263] Therefore, the diffusion of impurities such as water or hydrogen to the transistor 200 side through the insulator 222 can be suppressed. Alternatively, the diffusion of oxygen contained in the insulator 224 to the substrate side through the insulator 222 can be suppressed.

[0264] Furthermore, it can also suppress the diffusion of impurities such as water or hydrogen from the insulator 280, which is disposed between insulator 272 and insulator 273, to the transistor 200 side. Thus, it is preferable to adopt a structure in which the transistor 200 is surrounded by insulator 272 and insulator 273, which have the function of suppressing the diffusion of impurities such as water or hydrogen and oxygen.

[0265] Here, the insulator 224 in contact with the oxide 230 is preferably heated to remove oxygen. In this specification, the oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulator 224. By providing an insulator containing excess oxygen in a manner that allows it to contact the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0266] Specifically, as the insulator 224, it is preferable to use an oxide material that allows partial oxygen removal by heating. The oxide that allows oxygen removal by heating refers to an oxide film in which the amount of oxygen molecules removed in thermal desorption spectroscopy (TDS) analysis is 1.0 × 10¹⁸ molecules / cm³ or more, preferably 1.0 × 10¹⁹ molecules / cm³ or more, further preferably 2.0 × 10¹⁹ molecules / cm³ or more, or 3.0 × 10²⁰ molecules / cm³ or more. Furthermore, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0267] Insulator 222 is preferably used as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into the transistor 200 from the substrate side. For example, the hydrogen permeability of insulator 222 is preferably lower than that of insulator 224. By surrounding insulator 224 and oxide 230 with insulator 222 and insulator 283, impurities such as water or hydrogen from the outside can be prevented from entering the transistor 200.

[0268] Furthermore, insulator 222 preferably has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate). For example, the oxygen permeability of insulator 222 is preferably lower than that of insulator 224. By enabling insulator 222 to inhibit the diffusion of oxygen or impurities, the diffusion of oxygen present in oxide 230 to the underside of insulator 220 can be reduced, which is therefore preferable. In addition, the reaction between conductor 205 and oxygen present in insulator 224 and oxide 230 can be suppressed.

[0269] The insulator 222 is preferably an insulator containing one or both of aluminum and hafnium as insulating materials. As an insulator containing one or both of aluminum and hafnium oxide, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) are preferred. When this material is used to form the insulator 222, the insulator 222 serves as a layer to inhibit the release of oxygen from the oxide 230 or the entry of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230.

[0270] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the above-mentioned insulator. Alternatively, the above-mentioned insulator can be nitrided. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride can be laminated on the above-mentioned insulator.

[0271] Furthermore, as the insulator 222, high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used as a single layer or in a stack. For example, when the insulator 222 is a stack, a three-layer stack of zirconium oxide, alumina, and zirconium oxide formed sequentially, or a four-layer stack of zirconium oxide, alumina, zirconium oxide, and alumina formed sequentially, can be used. Additionally, compounds containing hafnium and zirconium can be used as the insulator 222. During the miniaturization and high-integration of semiconductor devices, the thin-film nature of the dielectric used for gate insulators and capacitor elements sometimes causes problems such as leakage current in transistors or capacitor elements. By using high-k materials as the insulator used as the dielectric for gate insulators and capacitor elements, the gate potential during transistor operation can be reduced while maintaining the physical thickness, and the capacitance of the capacitor element can be ensured.

[0272] In addition, insulators 222 and 224 may also have a multilayer structure with two or more layers. In this case, it is not limited to a multilayer structure made of the same material, but may also be a multilayer structure made of different materials.

[0273] Alternatively, oxide 243 (oxide 243a and oxide 243b) can be disposed between oxide 230b and conductor 242 (conductor 242a and conductor 242b) used as source or drain electrodes. Since conductor 242 does not contact oxide 230b, the absorption of oxygen from oxide 230b by conductor 242 can be suppressed. In other words, by preventing oxidation of conductor 242, the decrease in conductivity of conductor 242 can be suppressed. Therefore, oxide 243 preferably has the function of suppressing oxidation of conductor 242.

[0274] When an oxide 243, which has the function of inhibiting oxygen permeation, is disposed between the conductor 242, which is used as a source electrode or a drain electrode, and the oxide 230b, the resistance between the conductor 242 and the oxide 230b decreases, which is preferable. By adopting this structure, the electrical characteristics and reliability of the transistor 200 can be improved.

[0275] As oxide 243, a metal oxide having one or more elements M selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium can also be used. In particular, aluminum, gallium, yttrium, or tin is preferred as element M. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. Additionally, gallium oxide can also be used as oxide 243. Furthermore, metal oxides such as In-M-Zn oxide can also be used as oxide 243. Specifically, the number of atoms of element M relative to In in the metal oxide used for oxide 243 is preferably greater than the ratio of the number of atoms of element M relative to In in the metal oxide used for oxide 230b. Furthermore, the thickness of oxide 243 is preferably 0.5 nm or more and 5 nm or less, and preferably 1 nm or more and 3 nm or less. Additionally, oxide 243 is preferably crystalline. When oxide 243 is crystalline, it can better suppress the release of oxygen from oxide 230. For example, when oxide 243 has a hexagonal or other crystalline structure, it can sometimes suppress the release of oxygen from oxide 230.

[0276] Furthermore, oxide 243 is not necessarily required. In this case, because conductor 242 (conductors 242a and 242b) is in contact with oxide 230, oxygen in oxide 230 diffuses into conductor 242, thereby sometimes oxidizing conductor 242. The possibility of the conductivity of conductor 242 decreasing due to oxidation increases. Note that the diffusion of oxygen from oxide 230 into conductor 242 can also be referred to as conductor 242 absorbing oxygen from oxide 230.

[0277] Furthermore, when oxygen in oxide 230 diffuses into conductor 242 (conductors 242a and 242b), unwanted layers may form between conductor 242a and oxide 230b, and between conductor 242b and oxide 230b. Since these unwanted layers contain more oxygen than conductor 242, it is presumed that they possess insulating properties. In this case, the three-layer structure of conductor 242, the unwanted layer, and oxide 230b can be considered a metal-insulator-semiconductor three-layer structure, sometimes referred to as a MIS (Metal-Insulator-Semiconductor) structure or a diode structure dominated by MIS.

[0278] Note that the aforementioned unnecessary layer is not limited to being formed between conductor 242 and oxide 230b. For example, the unnecessary layer may be formed between conductor 242 and oxide 230c, or between conductor 242 and oxide 230b, and between conductor 242 and oxide 230c.

[0279] Conductors 242 (conductors 242a and conductors 242b) used as source and drain electrodes are disposed on oxide 243. The thickness of conductor 242 can be, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0280] As the conductor 242, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, so they are preferred.

[0281] An insulator 272 is disposed in contact with the top surface of the conductor 242, and the insulator 272 is preferably used as a barrier layer. By adopting this structure, the absorption of excess oxygen contained in the insulator 280 by the conductor 242 can be suppressed. In addition, by suppressing the oxidation of the conductor 242, the increase in contact resistance between the transistor 200 and the wiring can be suppressed. Thus, the transistor 200 can be endowed with good electrical characteristics and reliability.

[0282] Therefore, insulator 272 preferably has the function of suppressing oxygen diffusion. For example, insulator 272 preferably has the function of suppressing oxygen diffusion from insulator 280. As insulator 272, for example, it is preferably an insulator that forms an oxide containing one or both of aluminum and hafnium. In addition, as insulator 272, for example, an insulator containing aluminum nitride can be used.

[0283] As shown in Figure 35A, insulator 272 is in contact with a portion of the top surface and the side surface of conductor 242b. Although not shown, insulator 272 is in contact with a portion of the top surface and the side surface of conductor 242a. Additionally, insulator 273 is disposed on insulator 272. By employing this structure, for example, it is possible to suppress the absorption of oxygen added to insulator 280 by conductor 242.

[0284] Insulator 250 is used as a gate insulator. Insulator 250 is preferably configured to contact the top surface of oxide 230c with ground. Insulator 250 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0285] Similar to insulator 224, insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating in contact with the top surface of oxide 230c as insulator 250, oxygen can be efficiently supplied to the channel-forming region of oxide 230b. Similar to insulator 224, it is preferable to reduce the concentration of impurities such as water or hydrogen in insulator 250. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less.

[0286] Alternatively, a metal oxide can be disposed between the insulator 250 and the conductor 260. This metal oxide is preferably configured to suppress the diffusion of oxygen from the insulator 250 to the conductor 260. By disposing of a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0287] Furthermore, this metal oxide is sometimes used as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a high-k metal oxide, which is a material with a high relative permittivity, as the metal oxide. By making the gate insulator have a stacked structure of insulator 250 and the metal oxide, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0288] Specifically, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, it is preferred to use aluminum oxide, hafnium oxide, or oxides containing aluminum and hafnium (hafnium aluminate) as insulators containing one or both of aluminum and hafnium.

[0289] Alternatively, the metal oxide is sometimes used as part of the gate. In this case, it is preferable to place an oxygen-containing conductive material on one side of the channel forming region. By placing an oxygen-containing conductive material on one side of the channel forming region, oxygen detached from the conductive material can be easily supplied to the channel forming region.

[0290] In particular, it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide forming the channel as the conductor used as the gate. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0291] Although the conductor 260 in Figure 35A has a two-layer structure, it can also have a single-layer structure or a stacked structure of three or more layers.

[0292] The conductor 260a is preferably a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Furthermore, it is preferable to use a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0293] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. As a conductive material with the function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, or ruthenium oxide are preferably used, for example.

[0294] Furthermore, it is preferable to use a conductive material with tungsten, copper, or aluminum as the main component as the conductor 260b. Additionally, since the conductor 260 is also used for wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material with tungsten, copper, or aluminum as the main component can be used. Furthermore, the conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride with the aforementioned conductive material.

[0295] <<Metal Oxides>> As oxide 230, a metal oxide that is used as an oxide semiconductor is preferred. Hereinafter, a metal oxide that can be used for oxide 230 according to the present invention will be described.

[0296] The metal oxide preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. Additionally, it is preferred to also contain gallium, yttrium, tin, etc. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0297] Here, it is estimated that the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc (element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). In particular, aluminum, gallium, yttrium, or tin can be used as element M.

[0298] Note that in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Furthermore, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0299] <Transistor 300> The transistor 300 is illustrated using Figure 35B. The transistor 300 is disposed on a semiconductor substrate 311 and includes: a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 formed by a portion of the semiconductor substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. The transistor 300 can be a p-channel or n-channel type.

[0300] In the transistor 300 shown in FIG. 35B, the semiconductor region 313 (a portion of the semiconductor substrate 311) forming the channel has a convex shape. Furthermore, a conductor 316 is provided such that it covers the side and top surfaces of the semiconductor region 313 with an insulator 315 in between. The conductor 316 can be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate 311, this transistor 300 is also referred to as a FIN-type transistor. Furthermore, an insulator used to form a shield for the convex portion may be provided in contact with the upper surface of the convex portion. Although the case shown here is that a portion of the semiconductor substrate 311 is processed to form the convex portion, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0301] Note that the structure of transistor 300 shown in Figure 35B is only an example and is not limited to the above structure. Appropriate transistors can be used according to the circuit structure or driving method.

[0302] <Memory Device 420> Next, the memory device 420 shown in FIG34 will be described with reference to FIG36A. Furthermore, regarding the transistor 200M included in the memory device 420, descriptions that are redundant with those of the transistor 200 will be omitted.

[0303] In the memory device 420, the conductor 242a of the transistor 200M is used as one of the electrodes of the capacitor element 292, and the insulators 272 and 273 are used as dielectrics. A conductor 290 is disposed in a manner overlapping the conductor 242a with the insulators 272 and 273 in between, and is used as another electrode of the capacitor element 292. The conductor 290 can also be used as another electrode of the capacitor element 292 included in an adjacent memory device 420. Furthermore, the conductor 290 can also be electrically connected to another conductor 290 included in an adjacent memory device 420.

[0304] Conductor 290 is disposed on the top surface and side surface of conductor 242a, separated by insulators 272 and 273. In this case, capacitor element 292 can achieve a larger capacitance than the capacitance obtained by utilizing the overlapping area of ​​conductors 242a and 290, which is therefore preferable.

[0305] Conductor 424 is electrically connected to conductor 242b, and is electrically connected to conductor 424 in the layer below through conductor 205.

[0306] The dielectric material used as capacitor element 292 can be silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide, etc. Alternatively, a stack of these materials can be used. When the dielectric material of capacitor element 292 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide, can be used. Here, the top and bottom layers of the stack are not limited. For example, silicon nitride can be stacked on aluminum oxide, or aluminum oxide can be stacked on silicon nitride.

[0307] Furthermore, zirconium oxide, which has a higher dielectric constant than the materials described above, can be used as the dielectric of capacitor element 292. Zirconia can be used as a single layer or as part of a stack as the dielectric of capacitor element 292. For example, a stack of zirconium oxide and alumina can be used. Alternatively, a three-layer stack can be used as the dielectric of capacitor element 292, with zirconium oxide used as the first and third layers and alumina used as the second layer between the first and third layers.

[0308] Using zirconium oxide, which has a high dielectric constant, as the dielectric of capacitor element 292 can reduce the area occupied by capacitor element 292 in memory device 420. Therefore, the area required for memory device 420 can be reduced, thereby improving bit cost, which is preferable.

[0309] In addition, materials that can be used for conductors 205, 242, 260 and 424 can be used as conductors 290.

[0310] This embodiment shows an example where transistors 200M and capacitors 292 are symmetrically arranged with conductors 424 between them. By arranging a pair of transistors 200M and capacitors 292, the number of conductors 424 electrically connected to the transistors 200M can be reduced. Therefore, the area required for the memory device 420 can be reduced, thereby improving bit cost, which is preferable.

[0311] When the insulator 241 is provided on the side of the conductor 424, the conductor 424 is connected to at least a portion of the top surface of the conductor 242b.

[0312] By using conductors 424 and 205, the transistor 200T in memory cell 470 can be electrically connected to memory device 420.

[0313] <Example 1 of the variation of memory device 420> Next, the memory device 420A will be described with reference to FIG36B as a modified example of the memory device 420. The memory device 420A includes a transistor 200M and a capacitor element 292A electrically connected to the transistor 200M. The capacitor element 292A is disposed below the transistor 200M.

[0314] In memory device 420A, conductor 242a is disposed in an opening formed in oxides 243a, 230b, 230a, insulator 224, and 222, and is electrically connected to conductor 205 at the bottom of the opening. Conductor 205 is electrically connected to capacitor element 292A.

[0315] Capacitor element 292A includes a conductor 294 used as one of the electrodes, an insulator 295 used as a dielectric, and a conductor 297 used as the other electrode. Conductor 297 overlaps conductor 294 across insulator 295. Additionally, conductor 297 is electrically connected to conductor 205.

[0316] Conductors 294 are disposed at the bottom and sides of the opening formed in the insulator 298 on the insulator 296, and the insulator 295 is disposed such that it covers the insulator 298 and the conductors 294. In addition, conductors 297 are formed in a way that they are embedded in the recesses of the insulator 295.

[0317] Additionally, a conductor 299 is formed by embedding it into an insulator 296, and the conductor 299 is electrically connected to the conductor 294. The conductor 299 can also be electrically connected to the conductor 294 of the adjacent memory device 420A.

[0318] Conductor 297 is disposed on the top surface and side surface of conductor 294, separated by insulator 295. In this case, capacitor element 292A can obtain a larger capacitance than the capacitance obtained by utilizing the overlapping area of ​​conductor 294 and conductor 297, so it is better.

[0319] The insulator 295, which serves as the dielectric for capacitor element 292A, can be made of silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide. Alternatively, a stack of these materials can be used. When the insulator 295 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide, can be used. The top and bottom layers of the stack are not limited. For example, silicon nitride can be stacked on aluminum oxide, or aluminum oxide can be stacked on silicon nitride.

[0320] Furthermore, zirconium oxide, which has a higher dielectric constant than the materials described above, can be used as insulator 295. Zirconia 295 can be used as a single layer or as part of a stack. For example, a stack of zirconium oxide and alumina can be used. Additionally, a three-layer stack can be used as insulator 295, with zirconium oxide as the first and third layers and alumina as the second layer between the first and third layers.

[0321] Using zirconium oxide, which has a high dielectric constant, as the insulator 295 reduces the area occupied by the capacitor element 292A in the memory device 420A. Therefore, the area required for the memory device 420A can be reduced, thus improving bit cost, which is preferable.

[0322] In addition, materials that can be used in conductors 205, 242, 260, and 424 can be used as conductors 297, 294, and 299.

[0323] In addition, materials that can be used for insulators 214, 216, 224 and 280 can be used as insulator 298.

[0324] <Example 2 of the variation of memory device 420> Next, the memory device 420B will be described with reference to FIG36C as a modified example of the memory device 420. The memory device 420B includes a transistor 200M and a capacitor element 292B electrically connected to the transistor 200M. The capacitor element 292B is disposed above the transistor 200M.

[0325] Capacitor element 292B includes a conductor 276 used as one of the electrodes, an insulator 277 used as a dielectric, and a conductor 278 used as the other of the electrodes. Conductor 278 overlaps conductor 276 through insulator 277.

[0326] An insulator 275 is provided on an insulator 282, and a conductor 276 is provided at the bottom and sides of the openings formed in the insulators 275, 282, 280, 273, and 272. An insulator 277 is provided to cover the insulator 282 and the conductor 276. Furthermore, a conductor 278 is provided to overlap the conductor 276 in a recess of the insulator 277, with at least a portion of it disposed on the insulator 275 across the insulator 277. The conductor 278 can also be used as another electrode of the capacitor element 292B included in the adjacent memory device 420B. Additionally, the conductor 278 can be electrically connected to the conductor 278 included in the adjacent memory device 420B.

[0327] Conductor 278 is disposed on the top surface and side surface of conductor 276, separated by insulator 277. In this case, capacitor element 292B can obtain a larger capacitance than the capacitance obtained by utilizing the overlapping area of ​​conductor 276 and conductor 278, so it is preferable.

[0328] Alternatively, the insulator 279 can be formed by embedding it into the recess provided in the conductor 278.

[0329] The insulator 277, which serves as the dielectric of capacitor element 292B, can be made of silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide. Alternatively, a stack of these materials can be used. When the insulator 277 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide, can be used. The top and bottom layers of the stack are not limited. For example, silicon nitride can be stacked on aluminum oxide, or aluminum oxide can be stacked on silicon nitride.

[0330] Furthermore, zirconium oxide, which has a higher dielectric constant than the materials described above, can be used as insulator 277. Zirconia 277 can be used as a single layer or as part of a stack. For example, a stack of zirconium oxide and alumina can be used. Additionally, a three-layer stack can be used as insulator 277, with zirconium oxide as the first and third layers and alumina as the second layer between the first and third layers.

[0331] Using zirconium oxide, which has a high dielectric constant, as the insulator 277 reduces the area occupied by the capacitor element 292B in the memory device 420B. Therefore, the area required for the memory device 420B can be reduced, thereby improving bit cost.

[0332] In addition, materials that can be used for conductors 205, 242, 260 and 424 can be used as conductors 276 and 278.

[0333] In addition, materials that can be used in insulators 214, 216, 224 and 280 can be used as insulators 275 and 279.

[0334] <Connection between memory device 420 and transistor 200T> In the area 422 surrounded by the dotted line in Figure 34, although the memory device 420 is electrically connected to the gate of the transistor 200T via conductors 424 and 205, this embodiment is not limited to this.

[0335] Figure 37 shows an example of memory device 420 being electrically connected to conductor 242b, which is used as one of the source and drain electrodes of transistor 200T, via conductors 424, 205, 246b, and 240b.

[0336] Thus, the connection method between the memory device 420 and the transistor 200T can be determined based on the function of the circuit included in the transistor layer 413.

[0337] Figure 38 shows an example of a memory cell 470 including a transistor layer 413 with a transistor 200T and four memory device layers 415 (memory device layers 415_1 to memory device layers 415_4).

[0338] The memory device layers 415_1 to 415_4 each include a plurality of memory devices 420.

[0339] The memory device 420 is electrically connected to the memory device 420 and the transistor 200T of the transistor layer 413 included in the different memory device layers 415 via conductors 424 and 205.

[0340] Memory cell 470 is sealed by insulators 211, 212, 214, 287, 282, 283, and 284. Insulator 274 is disposed around insulator 284. Furthermore, conductors 430 are provided on insulators 274, 284, 283, and 211 and are electrically connected to component layer 411.

[0341] In addition, an insulator 280 is provided inside the sealed structure. The insulator 280 has the function of releasing oxygen upon heating. In addition, the insulator 280 has an excess oxygen region.

[0342] Furthermore, insulators 211, 283, and 284 are preferably materials with high hydrogen barrier properties. Additionally, insulators 214, 282, and 287 are preferably materials that trap or fix hydrogen.

[0343] For example, silicon nitride or silicon oxynitride are examples of materials that have high hydrogen barrier properties. In addition, aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are examples of materials that can capture or fix hydrogen.

[0344] Note that in this specification, barrier properties refer to the ability to inhibit the diffusion of the corresponding substance (also known as low permeability). Alternatively, it refers to the ability to capture and fix the corresponding substance (also known as gettering).

[0345] Furthermore, there are no particular restrictions on the crystal structure of the materials used for insulators 211, 212, 214, 287, 282, 283, and 284; however, structures with either amorphous or crystalline properties are acceptable. For example, amorphous alumina films are preferred as materials for capturing or fixing hydrogen. Compared to highly crystalline alumina, amorphous alumina sometimes captures and fixes a larger amount of hydrogen.

[0346] Here, the excess oxygen in the insulator 280 can be estimated as the diffusion of hydrogen in the oxide semiconductor of the insulator 280, with the following model.

[0347] Hydrogen present in the oxide semiconductor diffuses to other structures through an insulator 280 in contact with the oxide semiconductor. Excess oxygen in the insulator 280 reacts with oxygen in the oxide semiconductor to form OH bonds, and this hydrogen diffuses into the insulator 280. When hydrogen atoms with OH bonds reach a material that traps or fixes hydrogen (typically insulator 282), the hydrogen atoms react with oxygen atoms bonded to atoms (e.g., metal atoms) in the insulator 282 and are trapped or fixed in the insulator 282. On the other hand, the oxygen atoms of the excess oxygen with OH bonds are estimated to remain in the insulator 280 as excess oxygen. In other words, the excess oxygen in the insulator 280 is highly likely to play a bridging role during the diffusion of this hydrogen.

[0348] To meet the requirements of the above model, one of the key elements is the manufacturing process of the semiconductor device.

[0349] As an example, after forming an insulator 280 containing excess oxygen in an oxide semiconductor, an insulator 282 is formed. Then, preferably, a heat treatment is performed. Specifically, the heat treatment is performed at a temperature of 350°C or higher, preferably 400°C or higher, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen. The heat treatment time is 1 hour or more, preferably 4 hours or more, and more preferably 8 hours or more.

[0350] Through the aforementioned heat treatment, hydrogen in the oxide semiconductor can diffuse to the outside through insulators 280, 282, and 287. In other words, the absolute amount of hydrogen present in and around the oxide semiconductor can be reduced.

[0351] Insulators 283 and 284 are formed after the above heat treatment. Because insulators 283 and 284 are materials with high hydrogen barrier properties, hydrogen that diffuses to the outside or hydrogen present in the outside can be suppressed from entering the interior, specifically, the oxide semiconductor or the insulator 280 side.

[0352] Note that while the above-described heat treatment is shown as being performed after the formation of insulator 282, it is not limited to this. For example, the heat treatment can be performed after the formation of transistor layer 413 or after the formation of memory device layers 415_1 to 415_3. Furthermore, when hydrogen is diffused to the outside by the above-described heat treatment, the hydrogen diffuses to the top or lateral direction of transistor layer 413. Similarly, when the heat treatment is performed after the formation of memory device layers 415_1 to 415_3, the hydrogen diffuses to the top or lateral direction.

[0353] In addition, in the above process, the sealing structure is formed by contact between insulator 211 and insulator 283.

[0354] As described above, by employing the above structure and process, a semiconductor device using an oxide semiconductor with reduced hydrogen concentration can be provided. Therefore, a semiconductor device with high reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided.

[0355] Figures 39A to 39C show examples where the arrangement of conductor 424 differs from that in Figure 38. Figure 39A shows a layout view of the memory device 420 from the top, Figure 39B shows a cross-sectional view of the portion indicated by dashed lines A1-A2 in Figure 39A, and Figure 39C shows a cross-sectional view of the portion indicated by dashed lines B1-B2 in Figure 39A. Additionally, conductor 205 is omitted in Figure 39A for clarity. When conductor 205 is provided, conductor 205 includes an area overlapping with conductor 260 and conductor 424.

[0356] As shown in Figure 39A, an opening is provided for the conductor 424, meaning that the conductor 424 is provided not only in the areas overlapping oxides 230a and 230b, but also on the outer side of oxides 230a and 230b. Figure 39A shows an example in which the conductor 424 protrudes to the B2 side of oxides 230a and 230b; however, this embodiment is not limited to this. The conductor 424 can be provided in a manner that protrudes to the B1 side of oxides 230a and 230b, or in a manner that protrudes to both the B1 and B2 sides.

[0357] Figures 39B and 39C show an example of a memory device layer 415_p stacked on top of a memory device layer 415_p-1 (p is a natural number greater than 2 and less than n). The memory device 420 included in the memory device layer 415_p-1 is electrically connected to the memory device 420 included in the memory device layer 415_p via conductors 424 and 205.

[0358] Figure 39B shows an example of conductor 424 in memory device layer 415_p-1 being connected to conductor 242 in memory device layer 415_p-1 and conductor 205 in memory device layer 415_p. Here, conductor 424 is connected to conductor 205 in memory device layer 415_p-1 on the outer side of conductor 242, oxide 243, oxide 230b, and oxide 230a on the B2 side.

[0359] In Figure 39C, conductor 424 is formed along the side surface of conductors 242, oxide 243, oxide 230b, and oxide 230a on the B2 side, and is electrically connected to conductor 205 through openings formed in insulators 280, 273, 272, 224, and 222. Here, in Figure 39B, an example is shown in dashed lines where conductor 424 is formed along the side surface of conductors 242, oxide 243, oxide 230b, and oxide 230a on the B2 side. Additionally, sometimes insulator 241 is formed between the side surface of conductors 242, oxide 243, oxide 230b, oxide 230a, insulator 224, and insulator 222 on the B2 side and conductor 424.

[0360] By placing the conductor 424 in a region that does not overlap with the conductor 242, the memory device 420 can be electrically connected to memory devices 420 disposed in different memory device layers 415. Additionally, the memory device 420 can also be electrically connected to the transistor 200T disposed in the transistor layer 413.

[0361] Furthermore, when conductor 424 is used as a bit line, by also providing conductor 424 in areas that do not overlap with conductor 242, the distance between bit lines of adjacent memory devices 420 in the B1-B2 direction can be increased. As shown in FIG39A, the distance between conductors 424 on conductor 242 is d1, but the distance between conductors 424 in the layer below oxide 230a, i.e., in the opening formed by insulator 224 and insulator 222, is d2, therefore d2 is larger than d1. Compared with the case where the distance between adjacent conductors 424 in the B1-B2 direction is d1, by setting a portion of the distance to d2, the parasitic capacitance of conductor 424 can be reduced. By reducing the parasitic capacitance of conductor 424, the capacitance required for capacitor element 292 can be reduced, which is preferable.

[0362] A conductor 424 is provided in the memory device 420 to serve as a common bit line for two memory cells. By appropriately adjusting the dielectric constant of the dielectric used as a dielectric or the parasitic capacitance between the bit lines, the cell size of each memory cell can be reduced. Here, the estimation of the cell size, bit density, and bit cost of the memory cell with a channel length of 30 nm (also known as the 30 nm node) will be explained. In addition, for clarity, the conductor 205 is omitted in Figures 40A to 40D described below. When the conductor 205 is provided, the conductor 205 includes a region that overlaps with the conductor 260 and the conductor 424.

[0363] Figure 40A shows an example of a dielectric material used as a capacitor element, consisting of a 10 nm thick layer of hafnium oxide and a 1 nm thick layer of silicon oxide stacked sequentially. A slit is formed between the conductors 242, oxide 243, oxide 230a, and oxide 230b of each memory cell included in the memory device 420, and a conductor 424, used as a bit line, is arranged in a manner overlapping the conductor 242 and the slit. The memory cell 432 obtained by this method is referred to as cell A.

[0364] The element size in element A is 45.25F2.

[0365] Figure 40B shows an example of a dielectric material serving as a capacitor element, consisting of a first zirconium oxide, an aluminum oxide layer thereon, and a second zirconium oxide layer thereon, stacked sequentially. A slit is formed between the conductors 242, oxide 243, oxide 230a, and oxide 230b of each memory cell included in the memory device 420, and a conductor 424, used as a bit line, is arranged in a manner overlapping the conductor 242 and the slit. The memory cell 433 obtained by this method is referred to as cell B.

[0366] Because the dielectric constant of the capacitor element in cell B is higher than that in cell A, the area of ​​the capacitor element can be reduced. Therefore, the cell size in cell B can be reduced compared to cell A. The cell size in cell B is 25.53F².

[0367] Unit A and Unit B correspond to the memory units included in memory device 420, memory device 420A or memory device 420B shown in Figures 34, 36A to 36C and 37.

[0368] Figure 40C shows a dielectric material serving as a capacitor element, consisting of a first zirconium oxide, an aluminum oxide layer thereon, and a second zirconium oxide layer thereon, stacked sequentially. Each memory cell collectively includes the conductor 242, oxide 243, oxide 230a, and oxide 230b included in the memory device 420. An example is shown where the conductor 424, used as a bit line, is arranged such that a portion overlaps with the conductor 242 and a portion overlaps the outer side of the conductor 242. The memory cell 434 obtained by this method is referred to as cell C.

[0369] Compared to the layer above conductor 242, the distance between conductors 424 in cell C, below oxide 230a, is greater. Therefore, the parasitic capacitance of conductor 424 can be reduced, and the area of ​​the capacitor element can be decreased. Furthermore, no slits are formed between conductors 242, oxide 243, oxide 230a, and oxide 230b. Thus, cell C can have a smaller cell size compared to cells A and B. The cell size in cell C is 17.20F².

[0370] Figure 40D shows an example where the conductor 205 and the insulator 216 are not provided in cell C. This memory cell 435 is referred to as cell D.

[0371] By omitting the conductor 205 and insulator 216 in cell D, the thickness of the memory device 420 can be reduced. Therefore, the memory device layer 415, including the memory device 420, can be thinned, and the height of the memory cell 470, which consists of multiple stacked memory device layers 415, can be reduced. When the conductor 424 and conductor 205 are considered as bit lines, the bit lines can be shortened in the memory cell 470. Because the bit lines can be shortened, the parasitic load on the bit lines is reduced, thereby further reducing the parasitic capacitance of the conductor 424, and thus reducing the area of ​​the capacitor element. Furthermore, no slits are formed in the conductor 242, oxide 243, oxide 230a, and oxide 230b. Therefore, compared to cells A, B, and C, cell D can have a smaller cell size. The cell size in cell D is 15.12F2.

[0372] Units C and D correspond to the memory units included in the memory device 420 shown in Figures 39A to 39C.

[0373] Here, the bit density and bit cost Cb of cells A to D, and cell E in cell D (which operates at multiple levels), are estimated. Furthermore, the obtained estimates are compared with estimates of bit density and bit cost in currently commercially available DRAMs.

[0374] The bit cost Cb in a semiconductor device according to one embodiment of the present invention is estimated using Formula 1.

[0375] [Formula 1]

[0376] Here, n represents the number of memory device layers stacked together, Pc, as a common part, mainly represents the number of patterning operations for element layer 411, Ps represents the number of patterning operations for each of memory device layer 415 and transistor layer 413, Dd represents the bit density of DRAM, D3d represents the bit density of a memory device layer 415, and Pd represents the number of patterning operations for DRAM. Note that Pd includes the increase due to shrinkage.

[0377] Table 1 shows estimated bit densities of commercially available DRAM and estimated bit densities of a semiconductor device according to one embodiment of the present invention. Furthermore, commercially available DRAMs have two process nodes: 18nm and 1Xnm. Additionally, taking the semiconductor device according to one embodiment of the present invention as having a process node of 30nm, the estimated bit densities are 5, 10, and 20 layers of memory device layers in cells A to E, respectively.

[0378] [Table 1] DRAM A memory device according to one embodiment of the present invention Manufacturing plant Company A Company B - process node 18 nm 1X nm 30nm Number of layers - - 5 10 20 Bit density [Gb / mm2] (*) represents the estimated value. 0.19 (*) 0.14 (*) Unit A 0.05 0.10 0.20 Unit B 0.09 0.17 0.35 Unit C 0.13 0.26 0.52 Unit D 0.15 0.29 0.59 Unit E 0.30 0.59 1.18

[0379] Table 2 shows the estimated bit cost of commercially available DRAM and the relative bit cost of a semiconductor device according to one embodiment of the present invention. Note that DRAM with a process node of 1Xnm is used in the bit cost comparison. In addition, with a process node of 30nm for the semiconductor device according to one embodiment of the present invention, the estimated bit densities of 5, 10, and 20 layers of memory device layers in cells A to D are estimated, respectively.

[0380] [Table 2] DRAM A memory device according to one embodiment of the present invention Manufacturing plant Company A Company B - process node 18 nm 1X nm 30nm Number of layers - - 5 10 20 Relative bit cost when Company B's bit density is 1 - 1 Unit A 1.7 1.3 1.2 Unit B 0.9 0.7 0.7 Unit C 0.6 0.5 0.4 Unit D 0.5 0.4 0.3

[0381] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0382] Implementation Method 10 In this embodiment, a metal oxide (hereinafter referred to as an oxide semiconductor) that can be used in the OS transistor described in the above embodiments is explained.

[0383] The metal oxide preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. Additionally, it preferably also contains aluminum, gallium, yttrium, or tin. Furthermore, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0384] <Classification of Crystal Structures> First, the classification of crystal structures in oxide semiconductors will be explained with reference to Figure 41A. Figure 41A is a diagram illustrating the classification of crystal structures in oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0385] As shown in Figure 41A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). The "Crystalline" classification does not include single crystal, poly crystal, or completely amorphous. The "Crystal" classification includes both single crystal and poly crystal.

[0386] Furthermore, the structure in the thickened portion of Figure 41A represents an intermediate state between "amorphous" and "crystal," belonging to a novel boundary region (New crystalline phase). In other words, this structure can be considered completely different from the energetically unstable "amorphous" or "crystal" structures.

[0387] Additionally, X-ray diffraction (XRD) spectroscopy can be used to evaluate the crystal structure of the film or substrate. Here, Figure 41B shows the XRD spectrum of a CAAC-IGZO film classified as "Crystalline" obtained by GIXD (Grazing-Incidence XRD) measurement (the vertical axis represents intensity expressed in arbitrary units (au)). The GIXD method is also known as the thin film method or the Seemann-Bohlin method. The XRD spectrum obtained by the GIXD measurement shown in Figure 41B will be simply referred to as the XRD spectrum. Furthermore, the composition of the CAAC-IGZO film shown in Figure 41B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Additionally, the thickness of the CAAC-IGZO film shown in Figure 41B is 500 nm.

[0388] As shown in Figure 41B, peaks indicating clear crystallinity were detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis alignment was detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Furthermore, as shown in Figure 41B, the peak near 2θ=31° is asymmetrical about the angle at which the peak intensity was detected.

[0389] Furthermore, the crystal structure of the film or substrate can be evaluated using diffraction patterns observed by Nano Beam Electron Diffraction (NBED). Figure 41C shows the diffraction pattern of the CAAC-IGZO film. Figure 41C is the diffraction pattern observed by NBED with an electron beam incident in a direction parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 41C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Additionally, in the nanobeam electron diffraction method, an electron diffraction pattern with a beam diameter of 1 nm was performed.

[0390] As shown in Figure 41C, multiple spots representing c-axis alignment were observed in the diffraction pattern of the CAAC-IGZO film.

[0391] <<Structure of Oxide Semiconductors>> Furthermore, when focusing on the crystal structure of oxide semiconductors, the classification of oxide semiconductors sometimes differs from that shown in Figure 41A. For example, oxide semiconductors can be classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include, for example, the aforementioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors, etc.

[0392] Here, we will explain the details of CAAC-OS, nc-OS, and a-like OS.

[0393] [CAAC-OS] CAAC-OS is an oxide semiconductor comprising multiple crystalline regions, whose c-axis is aligned in a specific direction. This specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. Furthermore, a crystalline region is a region exhibiting a periodic atomic arrangement. Note that when atomic arrangement is considered as lattice arrangement, a crystalline region is also a region with a consistent lattice arrangement. Moreover, CAAC-OS has regions where multiple crystalline regions are connected along the ab-plane direction, and sometimes these regions exhibit distortion. Distortion refers to the portion of the lattice arrangement direction that changes between regions with consistent lattice arrangement and other regions with consistent lattice arrangement within the region where multiple crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor with c-axis alignment but no obvious alignment along the ab-plane direction.

[0394] Furthermore, each of the aforementioned multiple crystalline regions is composed of one or more microcrystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single microcrystal, the maximum diameter of that region is less than 10 nm. Conversely, when a crystalline region is composed of multiple microcrystals, the size of that region can sometimes be around tens of nm.

[0395] Furthermore, in In-M-Zn oxides (where element M is selected from one or more of aluminum, gallium, yttrium, tin, and titanium), CAAC-OS tends to have a layered crystal structure (also called a layered structure) comprising layers containing stacked indium (In) and oxygen (hereinafter, In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer). In addition, indium and element M can substitute for each other. Therefore, sometimes the (M,Zn) layer contains indium. Also, sometimes the In layer contains element M. Note that sometimes the In layer contains Zn. This layered structure is observed, for example, as a lattice image in high-resolution TEM images.

[0396] For example, when performing structural analysis on CAAC-OS films using an XRD apparatus, the peak value of the c-axis alignment is detected at or near 2θ = 31° in out-of-plane XRD measurements using θ / 2θ scanning. Note that the position (2θ value) representing the peak value of the c-axis alignment sometimes varies depending on the type and composition of the metallic elements constituting CAAC-OS.

[0397] Additionally, for example, multiple bright spots (spots) were observed in the electron diffraction pattern of the CAAC-OS film. Furthermore, when the spot of the incident electron beam passing through the sample (also known as the direct spot) is taken as the center of symmetry, one spot and other spots are observed at point-symmetrical positions.

[0398] When observing the crystalline region from the aforementioned specific directions, although the lattice arrangement in this region is primarily hexagonal, the unit lattice is not limited to a regular hexagon; there are also cases where it is non-regular hexagonal. Furthermore, in the aforementioned distortions, pentagonal, heptagonal, and other lattice arrangements are sometimes observed. Additionally, no clear grain boundary is observed near the distortion of CAAC-OS. That is, the distortion of the lattice arrangement inhibits the formation of grain boundaries. This may be because CAAC-OS can tolerate distortions caused by reasons such as a low density of oxygen atoms in the ab-plane direction or changes in the bonding distance between atoms due to the substitution of metal atoms.

[0399] Furthermore, a crystalline structure with clearly defined grain boundaries is called a polycrystalline structure. Grain boundaries act as recombination centers, trapping carriers and potentially leading to a decrease in the transistor's on-state current and field-effect mobility. Therefore, CAAC-OS, which lacks clearly defined grain boundaries, is one of the crystalline oxides that provides an excellent crystalline structure for the semiconductor layer of the transistor. Note that a Zn-containing structure is preferred for constructing CAAC-OS. For example, In-Zn oxides and In-Ga-Zn oxides are preferred because they can further suppress grain boundary formation compared to In oxides.

[0400] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, it can be said that in CAAC-OS, the reduction in electron mobility due to grain boundaries is less likely to occur. Furthermore, the crystallinity of oxide semiconductors can sometimes decrease due to the incorporation of impurities or the formation of defects; therefore, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS exhibit stable physical properties. Thus, oxide semiconductors containing CAAC-OS possess high heat resistance and high reliability. In addition, CAAC-OS is also stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, by using CAAC-OS in OS transistors, process flexibility can be increased.

[0401] [nc-OS] In nc-OS, the atomic arrangement in tiny regions (e.g., regions larger than 1 nm and smaller than 10 nm, particularly regions larger than 1 nm and smaller than 3 nm) exhibits periodicity. In other words, nc-OS possesses tiny crystallinity. Furthermore, for example, these tiny crystallinity sizes are between 1 nm and 10 nm, particularly between 1 nm and 3 nm; these tiny crystallinity sizes are referred to as nanocrystals. Additionally, no regularity in crystallization orientation is observed between different nanocrystals in nc-OS. Therefore, no alignment is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods. For example, when performing structural analysis on nc-OS films using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when performing electron diffraction (also known as selected area electron diffraction) on nc-OS films using electron beams with a beam diameter larger than that of nanocrystals (e.g., larger than 50 nm), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also known as nano-beam electron ray) is performed on nc-OS films using electron beams whose beam diameter is close to or smaller than the size of nanocrystals (e.g., above 1 nm and below 30 nm), electron diffraction patterns of multiple spots are sometimes observed in an annular region centered on a direct spot.

[0402] [a-like OS] a-like OS is an oxide semiconductor with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Furthermore, the hydrogen concentration in a-like OS films is higher than that in nc-OS and CAAC-OS films.

[0403] <<Structure of Oxide Semiconductors>> Next, the detailed description of CAC-OS will be explained. Additionally, it will be explained that CAC-OS is related to material composition.

[0404] [CAC-OS] CAC-OS, for example, refers to a composition in which elements are non-uniformly distributed within a metal oxide, wherein the size of the material containing the non-uniformly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or approximately. Note that, below, the state in which one or more metal elements are non-uniformly distributed within a metal oxide and the regions containing those metal elements are mixed is also referred to as mosaic or patch-like, wherein the size of the region is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or approximately.

[0405] Furthermore, CAC-OS refers to a structure in which the material is divided into a first region and a second region, forming a mosaic-like structure, with the first region distributed throughout the film (hereinafter also referred to as cloud-like). In other words, CAC-OS refers to a composite metal oxide having a structure that combines the first and second regions.

[0406] Here, each of the atomic ratios of In, Ga, and Zn, the metal elements constituting the CAC-OS in In-Ga-Zn oxide, is denoted as [In], [Ga], and [Zn]. For example, in the CAC-OS of In-Ga-Zn oxide, a first region is a region where [In] is greater than [In] in the composition of the CAC-OS film. A second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. Alternatively, for example, a first region is a region where [In] is greater than [In] in the second region and [Ga] is less than [Ga] in the second region. A second region is a region where [Ga] is greater than [Ga] in the first region and [In] is less than [In] in the first region.

[0407] Specifically, the first region mentioned above is a region whose main component is indium oxide or indium zinc oxide. Furthermore, the second region mentioned above is a region whose main component is gallium oxide or gallium zinc oxide. In other words, the first region can be referred to as a region whose main component is In. The second region can be referred to as a region whose main component is Ga.

[0408] Note that sometimes the clear boundaries between the first region and the second region mentioned above are not observable.

[0409] For example, in CAC-OS of In-Ga-Zn oxide, based on the EDX surface analysis image (EDX-mapping) obtained by Energy Dispersive X-ray spectroscopy (EDX), a structure with an unevenly distributed and mixed structure of regions with In as the main component (first region) and regions with Ga as the main component (second region) can be identified.

[0410] When CAC-OS is used in transistors, the complementary effect of conductivity arising from the first region and insulation arising from the second region enables CAC-OS to possess switching functionality (the function of controlling conduction / turn-off). In other words, a part of the CAC-OS material has conductive functionality and another part has insulating functionality, while the entire material functions as a semiconductor. By separating the conductive and insulating functions, each function can be maximized. Therefore, by using CAC-OS in transistors, high on-state current (Ion), high field-effect mobility (μ), and good switching operation can be achieved.

[0411] Oxide semiconductors possess various structures and properties. In one embodiment of the present invention, the oxide semiconductor may also include two or more of the following: amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0412] <Transistors with oxide semiconductor properties> Here, we will explain the case where the above-mentioned oxide semiconductor is used as a transistor.

[0413] By using the aforementioned oxide semiconductors in transistors, transistors with high field-effect mobility can be realized. Furthermore, transistors with high reliability can be achieved.

[0414] It is preferable to use oxide semiconductors with low carrier concentrations in transistors. For example, the carrier concentration in the oxide semiconductor can be 1×10¹⁷ cm⁻³ or less, preferably 1×10¹⁵ cm⁻³ or less, more preferably 1×10¹³ cm⁻³ or less, further preferably 1×10¹¹ cm⁻³ or less, and even more preferably less than 1×10¹⁰ cm⁻³ and more than 1×10⁻⁹ cm⁻³. When the purpose is to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, the state of low impurity concentration and low defect state density is referred to as "high purity nature" or "substantially high purity nature". In addition, oxide semiconductors with low carrier concentrations are sometimes referred to as "high purity nature" or "substantially high purity nature oxide semiconductors".

[0415] Because high-purity or essentially high-purity oxide semiconductor films have a low defect state density, they may also have a low trap state density.

[0416] Furthermore, the charge trapped in the trap state level of an oxide semiconductor takes a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical properties of transistors forming channel formation regions in oxide semiconductors with high trap state density are sometimes unstable.

[0417] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical properties of the transistor. To further reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0418] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0419] When an oxide semiconductor contains silicon or carbon, one of the elements in Group 14, defect energy levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor or near the interface of the oxide semiconductor (the concentration measured by secondary ion mass spectrometry) is set to 2 × 10¹⁸ atoms / cm³ or less, preferably 2 × 10¹⁷ atoms / cm³ or less.

[0420] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect energy levels can sometimes be formed, thus creating carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to have always-on characteristics. Therefore, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor, as measured by SIMS, should be 1 × 10¹⁸ atoms / cm³ or less, preferably 2 × 10¹⁶ atoms / cm³ or less.

[0421] When oxide semiconductors contain nitrogen, electrons are readily generated as carriers, increasing the carrier concentration and resulting in n-type polarization. Consequently, transistors using nitrogen-containing oxide semiconductors tend to exhibit always-on characteristics. Alternatively, when nitrogen is included in the oxide semiconductor, trap levels sometimes form. As a result, the electrical properties of the transistor may sometimes be unstable. Therefore, the nitrogen concentration in the oxide semiconductor, measured using SIMS, is set to be below 5 × 10¹⁹ atoms / cm³, preferably below 5 × 10¹⁸ atoms / cm³, more preferably below 1 × 10¹⁸ atoms / cm³, and even more preferably below 5 × 10¹⁷ atoms / cm³.

[0422] Hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as carriers. Therefore, transistors using oxide semiconductors containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the oxide semiconductor. Specifically, in the oxide semiconductor, the hydrogen concentration measured using SIMS is set to be less than 1 × 10²⁰ atoms / cm³, preferably less than 1 × 10¹⁹ atoms / cm³, more preferably less than 5 × 10¹⁸ atoms / cm³, and even more preferably less than 1 × 10¹⁸ atoms / cm³.

[0423] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can be made to have stable electrical characteristics.

[0424] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0425] Implementation Method 11 In this embodiment, the details of the peripheral circuits 20 in the semiconductor devices 10, 10A, 10B and 10F described in Embodiments 1 to 4 will be explained.

[0426] Figure 42 is a block diagram showing an example of the structure of a semiconductor device used as a memory device. The semiconductor device 10E includes peripheral circuitry 20 and a memory cell array 30. Peripheral circuitry 20 includes a row decoder 71, a word line driver circuit 72, a column driver 22, an output circuit 73, and a control logic circuit 74. Note that the row decoder 71 and word line driver circuit 72 can be used in the row driver described in Embodiment 1, etc.

[0427] The column driver 22 includes a column decoder 81, a precharge circuit 82, an amplifier circuit 83, and a write circuit 84. The precharge circuit 82 precharges the wiring BL, etc. The amplifier circuit 83 amplifies the data signal read from the wiring BL. The amplified data signal is output as a digital data signal RDATA to the outside of the semiconductor device 10E via the output circuit 73.

[0428] The semiconductor device 10E is supplied with a low power supply voltage (VSS) as the power supply voltage from the outside, the peripheral circuit 20 is supplied with a high power supply voltage (VDD) and the memory cell array 30 is supplied with a high power supply voltage (VIL).

[0429] The semiconductor device 10E receives external control signals (CE, WE, RE), address signals ADDR, and data signals WDATA. The address signals ADDR are input to the row decoder 71 and the column decoder 81, and the WDATA is input to the write circuit 84.

[0430] The control logic circuit 74 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 71 and column decoder 81. CE is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 74 are not limited to these; other control signals can be input as needed. For example, a control signal used to determine bad bits can be used to identify data signals read from the address of a specific memory cell as bad bits.

[0431] The circuits or signals mentioned above can be used appropriately as needed.

[0432] Generally speaking, various memory devices can be used as semiconductor devices in computers and other applications, depending on their purpose. Figure 43 shows the hierarchy of various memory devices. The higher the level of the memory device, the faster the access speed is required; the lower the level of the memory device, the larger the storage capacity and the higher the recording density are required. In Figure 43, from the top layer, the memory installed as temporary storage in arithmetic processing devices such as CPUs, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory are shown in sequence.

[0433] Because memory installed as temporary storage in arithmetic processing devices such as CPUs is used for the temporary storage of calculation results, it is accessed frequently by the arithmetic processing device. Therefore, it is required to operate at a speed faster than storage capacitors. In addition, the temporary storage also has the function of holding setting information of the arithmetic processing device.

[0434] SRAM is used, for example, in cache memory. Cache memory has the function of copying and storing a portion of the information held in main memory. By copying frequently used data into cache memory, the speed of data access can be improved.

[0435] DRAM is used, for example, in main memory. Main memory has the function of holding programs or data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm².

[0436] 3D NAND memory is used, for example, for storage. Storage has the function of holding data that needs to be preserved for a long time and various programs used by computing devices. Therefore, compared with faster operating speeds, storage requires larger storage capacitors and higher recording densities. The recording density of memory devices used for storage is approximately 0.6 to 6.0 Gbit / mm².

[0437] A memory device according to one embodiment of the present invention operates at high speed and can retain data for a long period of time. A memory device according to one embodiment of the present invention can be used as a memory device located in the boundary region 901 between the hierarchy including cache memory and the hierarchy including main memory. Furthermore, a memory device according to one embodiment of the present invention can be used as a memory device located in the boundary region 902 between the hierarchy including main memory and the hierarchy including storage.

[0438] Implementation Method 12 In this embodiment, the power consumption of electronic components assembled with the semiconductor device shown in the above embodiment and the electronic device will be described.

[0439] Figures 44A and 44B illustrate the power consumption of DRAM and DOSRAM. Figure 44A shows the power consumption of DRAM, DOSRAM1, and DOSRAM2, and Figure 44B shows the power consumption of DRAM and DOSRAM2.

[0440] Furthermore, Figures 44A and 44B show the estimated results under various hypothetical usage scenarios. Note that Figure 44A shows the estimated results for a typical DRAM with a hypothetical activity level of 10% (assuming 10% activity per day when using electronic devices, etc.) and a standby mode of 90%, and for an electronic device (DOSRAM1 and DOSRAM2) according to one embodiment of the present invention. Figure 44B shows the estimated results for a typical DRAM with a hypothetical activity level of 1% (assuming 1% activity per day when using electronic devices, etc.) and a standby mode of 99%, and for an electronic device (DOSRAM2) according to one embodiment of the present invention.

[0441] Additionally, in Figures 44A and 44B, the vertical axis represents power consumption in arbitrary units (AU). Furthermore, in Figure 44A, the horizontal axis represents DRAM, DOSRAM1, and DOSRAM2, and in Figure 44B, the horizontal axis represents DRAM and DOSRAM2.

[0442] Additionally, in Figures 44A and 44B, the bottom of the graph represents the power consumption during Active mode, the middle represents the power consumption during Stanby mode, and the top represents the power consumption during Refresh mode.

[0443] In addition, DOSRAM2 is designed to perform power-on control on DOSRAM1 during standby.

[0444] As shown in Figure 44A, it can be seen that the electronic device (DOSRAM1 and DOSRAM2) of one embodiment of the present invention consumes less power than conventional DRAM. In particular, it can be estimated that DOSRAM2 has a power consumption reduction effect of 75% compared with conventional DRAM.

[0445] Furthermore, as shown in Figure 44B, when the activity mode is 1%, the electronic device (DOSRAM2) of one embodiment of the present invention can be estimated to have a 95% power consumption reduction effect compared to general DRAM.

[0446] As described above, one embodiment of the present invention can provide a semiconductor device or electronic device with reduced power consumption.

[0447] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0448] Implementation Method 13 This embodiment shows an example of an electronic component and electronic device equipped with the semiconductor device, etc., described in the above embodiment.

[0449] <Electronic Components> First, an example of an electronic component assembled with a semiconductor device 10 will be described with reference to Figures 45A and 45B.

[0450] Figure 45A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Figure 45A includes a semiconductor device 10 with a layer 34 of components stacked on a silicon substrate 11 within a mold 711. In Figure 45A, a portion of the interior of the electronic component 700 is omitted to show its internal structure. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, which is electrically connected to the semiconductor device 10 via a line 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. The mounting substrate 704 is completed by assembling multiple such electronic components and electrically connecting them respectively on the printed circuit board 702.

[0451] Figure 45B shows a perspective view of electronic component 730. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 100 are provided on the interposer 731.

[0452] The electronic component 730 shows an example of using the semiconductor device 10 as a high-bandwidth memory (HBM). Alternatively, the semiconductor device 735 can use integrated circuits (semiconductor devices) such as CPUs, GPUs, and FPGAs.

[0453] The packaging substrate 732 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The through-hole board 731 can be a silicon through-hole board, a resin through-hole board, etc.

[0454] The through-hole board 731 includes multiple wirings and functions to provide multiple integrated circuits with different spacing between electrically connected terminals. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 functions to electrically connect the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the packaging substrate 732. Therefore, the through-hole board is sometimes referred to as a "rewiring substrate" or "intermediate substrate." Additionally, sometimes a through electrode is provided in the through-hole board 731 to electrically connect the integrated circuits to the packaging substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV (Through Silicon Via) can also be used as the through electrode.

[0455] Silicon interposers are preferred for the 731. Since silicon interposers do not require active components, they can be manufactured at a lower cost than integrated circuits. Furthermore, the wiring of silicon interposers can be formed during semiconductor manufacturing processes, making it easy to create fine wiring that is difficult to form when using resin interposers.

[0456] In HBM, achieving wide memory bandwidth requires connecting numerous traces. Therefore, the board on which HBM is mounted needs to be able to form fine traces at high density. Thus, silicon boards are preferred for mounting HBM.

[0457] Furthermore, in SiP or MCM applications using silicon through-hole boards, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuits and the through-hole board is less likely to occur. Additionally, due to the high surface flatness of the silicon through-hole board, poor connections between the integrated circuits mounted on the board and the board itself are less likely to occur. Particularly preferred is the use of the silicon through-hole board in a 2.5D package (2.5D mounting) where multiple integrated circuits are arranged side-by-side on the through-hole board.

[0458] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the heights of the integrated circuits provided on the insert 731 are the same. For example, in the electronic component 730 shown in this embodiment, it is preferable that the heights of the semiconductor device 10 and the semiconductor device 735 are the same.

[0459] To mount the electronic component 730 onto other substrates, electrodes 733 can be disposed on the bottom of the package substrate 732. Figure 45B shows an example of forming the electrodes 733 using solder balls. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0460] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, it can be mounted using SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package).

[0461] <Electronic Devices> Next, an example of an electronic device equipped with the above-mentioned electronic components will be described with reference to FIG46.

[0462] Robot 7100 includes an illuminance sensor, microphone, camera, speaker, display, various sensors (infrared sensor, ultrasonic sensor, accelerometer, piezoelectric sensor, light sensor, gyroscope sensor, etc.) and a motion mechanism. Electronic component 730 includes a processor and has the function of controlling these peripheral devices. For example, electronic component 700 has the function of storing data measured by the sensors.

[0463] The microphone detects audio signals such as the user's voice and ambient sounds. The speaker emits audio signals such as sounds and warning tones. Robot 7100 analyzes the audio signals input through the microphone and emits the necessary audio signals from the speaker. Robot 7100 can communicate with the user using both the microphone and speaker.

[0464] The camera has the function of capturing images of the surroundings of the robot 7100. Additionally, the robot 7100 has the function of moving using a locomotion mechanism. The robot 7100 can analyze the images captured by the camera to determine the presence or absence of obstacles during movement.

[0465] The flying object 7120 includes a propeller, camera, and battery, and has autonomous flight capabilities. The electronic component 730 has the function of controlling these peripheral devices.

[0466] For example, image data captured by a camera is stored in electronic component 700. Electronic component 730 can analyze the image data to determine the presence or absence of obstacles during movement. In addition, electronic component 730 can use changes in battery capacity to estimate the remaining battery power.

[0467] The 7140 robotic vacuum cleaner includes a display on the top surface, multiple cameras on the sides, brushes, control buttons, and various sensors. Although not shown, the 7300 robotic vacuum cleaner is equipped with tires and a suction inlet. The 7300 can move automatically, detect debris, and suck up debris from the suction inlet on the bottom.

[0468] For example, the electronic component 730 can determine the presence or absence of obstacles such as walls, furniture, or steps by analyzing images captured by the camera. Furthermore, if image analysis detects objects such as wiring that may become entangled in the brush, the brush's rotation can be stopped.

[0469] The vehicle 7160 includes an engine, tires, brakes, steering system, camera, etc. For example, the electronic component 730 performs optimal control of the vehicle 7160's driving state based on data such as navigation information, speed, engine status, gear selection status, and brake usage frequency. For example, image data captured by the camera is stored in the electronic component 700.

[0470] Electronic component 700 and / or electronic component 730 can be installed in television receiver (TV) device 7200, smartphone 7210, PC 7220 (personal computer), 7230, game console 7240, game console 7260, etc.

[0471] For example, the electronic component 730 installed in the TV device 7200 can be used as an image engine. For example, the electronic component 730 can perform image processing such as noise removal and resolution up-conversion.

[0472] The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, camera, speaker, various sensors, and display. Electronic components 730 control these peripheral devices.

[0473] PC7220 and PC7230 are examples of a notebook PC and a desktop PC, respectively. A keyboard 7232 and a display device 7233 can be connected to PC7230 wirelessly or wiredly. Game console 7240 is an example of a portable game console. Game console 7260 is an example of a stationary game console. Game console 7260 connects to controller 7262 wirelessly or wiredly. Electronic components 700 and / or 730 can be installed on controller 7262.

[0474] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0475] (Notes regarding the contents of this instruction manual, etc.) Below, additional notes are added to the descriptions of the above embodiments and the structures in the embodiments.

[0476] The structures shown in each embodiment can be appropriately combined with structures shown in other embodiments to constitute an embodiment of the present invention. Furthermore, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0477] In addition, the content (or a part thereof) described in one embodiment may be applied / combined / replaced with other content (or a part thereof) described in that embodiment and / or content (or a part thereof) described in one or more other embodiments.

[0478] Note that the content described in the embodiments refers to the content illustrated using various diagrams or the content described using the text in the instruction manual.

[0479] Furthermore, more figures can be formed by combining a figure (or a portion thereof) shown in one embodiment with other parts of that figure, other figures (or a portion thereof) shown in that embodiment, and / or figures (or a portion thereof) shown in one or more other embodiments.

[0480] In this specification, components are categorized according to function and represented by independent blocks in the block diagram. However, in actual circuits, it is difficult to categorize components according to function; sometimes a circuit involves multiple functions or multiple circuits involve a single function. Therefore, the division of blocks in the block diagram is not limited to the components described in the specification and can vary appropriately depending on the situation.

[0481] For ease of illustration, dimensions, layer thicknesses, or regions are arbitrarily shown in the drawings. Therefore, the invention is not limited to the dimensions shown in the drawings. The drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include non-uniformity of signals, voltages, or currents caused by noise or timing deviations.

[0482] Furthermore, the positional relationships of components illustrated in diagrams are relative. Therefore, when describing components with reference to diagrams, terms such as "upper" and "lower" indicating positional relationships are sometimes used for convenience. The positional relationships of components are not limited to those described in this specification, and the terminology may be appropriately modified as needed.

[0483] In this specification, when describing the connection relationships of transistors, the terms "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. This is because the source and drain of the transistor may vary depending on the transistor's structure or operating conditions. Note that, depending on the circumstances, the source and drain of the transistor may be appropriately referred to as source (drain) terminals or source (drain) electrodes, etc.

[0484] Furthermore, in this specification and other documents, the terms "electrode" or "wiring" do not functionally limit the components. For example, sometimes an "electrode" is used as part of a "wiring," and vice versa. Moreover, "electrode" or "wiring" also includes cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0485] Furthermore, in this instruction manual and other documents, the terms voltage and potential may be appropriately interchanged. Voltage refers to the potential difference from a reference potential. For example, when the reference potential is ground voltage (grounding voltage), voltage can be replaced with potential. Grounding potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc., sometimes varies depending on the reference potential.

[0486] In this specification, nodes may be referred to as terminals, wiring, electrodes, conductive layers, conductors, or impurity regions, depending on the circuit or device structure. Additionally, terminals and wiring may also be referred to as nodes.

[0487] In this specification, A and B connection refers to A and B being electrically connected. Here, A and B electrical connection means a connection that allows the transmission of electrical signals between A and B when there is an object (such as a switch, transistor, or diode, or a circuit containing such an object and wiring) between A and B. Note that A and B electrical connection includes the case of A and B being directly connected. Here, A and B direct connection means a connection that transmits electrical signals between A and B through wiring (or electrodes) between A and B without passing through the aforementioned object. In other words, direct connection means a connection that can be considered as the same circuit diagram when using equivalent circuit representation.

[0488] In this specification and the like, a switch refers to a component that controls whether current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to a component that selects and switches the current path.

[0489] In this specification, for example, channel length refers to the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the conducting state) and the gate overlap or in the region forming the channel, as shown in a top view of the transistor.

[0490] In this specification, for example, channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap, or the length of the portion of the region in which the source and drain electrodes of the channel are opposite each other.

[0491] In this specification and other materials, the terms "film" and "layer" may be interchanged depending on the situation or condition. For example, "conductive layer" may sometimes be replaced with "conductive film." Furthermore, "insulating film" may sometimes be replaced with "insulating layer."

[0492] BL_1: Bitline DA1: Data PCL1: Precharge cable PCL2: Precharged cable T1: Period T2: Period T3: Period T4: Period T11: Period T12: Period T13: Period T14: Period T15: Period T16: Period WL_N: Word line WL_1: Wordline WL2: Wordline 10: Semiconductor devices 10A: Semiconductor Device 10B: Semiconductor Devices 10C: Semiconductor device 10D: Semiconductor Device 10E: Semiconductor Devices 10F: Semiconductor Device 11: Silicon substrate 20: Peripheral Circuits 21: Line drive 22: Column Driver 22_A: Pre-charge circuit 22_B: Pre-charge circuit 22_C: Sensing Amplifier 22_D: Switching circuit 22_E: Switching circuit 22_1: Pre-charge circuit 22_2: Sensing Amplifier 22_3: Switching Circuit 23_A: Switch 23_B: Switch 23_C: Switch 23_D: Switch 24_1: Transistor 24_3: Transistor 24_4: Transistor 24_6: Transistor 25: Circuit 25_1: Transistor 25_2: Transistor 25_3: Transistor 25_4: Transistor 26: Component Layer 27: Circuit 27_M: Circuit 27_1: Circuit 28: Transistor 28_a: Transistor 28_b: Transistor 28_n: Transistor 28_1: Transistor 29: Circuit 30: Memory cell array 30_M: Unit 30_1: Unit 31: Memory Unit 31_M: Memory unit 31_N: Memory unit 31_N_A: Memory unit 31_N_B: Memory unit 31_1: Memory Unit 31_1_A: Memory Unit 31_1_B: Memory Unit 32: Transistor 32_N: Transistor 32_1: Transistor 32A: Transistor 32B: Transistor 33: Capacitor 33_N: Capacitor 33_1: Capacitor 33A: Capacitor 33B: Capacitor 34: Component Layer 34_i: component layer 34_N: Component layer 34_1: Component Layer 40: Component Layer 40_M: Component Layer 40_1: Component Layer 40A: Component Layer 40B: Component Layer 40C: Component Layer 40D: Component Layer 41: Transistor 41_a: Transistor 41_b: Transistor 42: Transistor 42_a: Transistor 42_b: Transistor 43: Transistor 43_a: Transistor 43_b: Transistor 44: Transistor 44_a: Transistor 44_b: Transistor 49: Circuit 50: Unit 50_M: Unit 50_1: Unit 51: Memory Unit 54: Component Layer 55: Transistor 56: Transistor 57: Capacitor Components 70A: Sealing layer 70B: Sealing layer 71: Line Decoder 72: Word line drive circuit 73: Output Circuit 74: Control Logic Circuit 81: Column Decoder 82: Pre-charge circuit 83: Amplifier Circuit 84: Circuit 98: Switching Circuit 100: Memory Device 200: Transistor 200M: Transistor 200T: Transistor 205: Conductor 205a: Conductor 205b: Conductor 211: Insulator 212: Insulator 214: Insulator 216: Insulator 222: Insulator 224: Insulator 230: Oxides 230a: Oxide 230b: Oxide 230c: Oxide 240: Conductor 240a: Conductor 240b: Conductor 241: Insulator 241a: Insulator 241b: Insulator 242: Conductor 242a: Conductor 242b: Conductor 243: Oxides 243a: Oxide 243b: Oxide 246: Conductor 246a: Conductor 246b: Conductor 250: Insulator 260: Conductor 260a: Conductor 260b: Conductor 272: Insulator 273: Insulator 274: Insulator 275: Insulator 276: Conductor 277: Insulator 278: Conductor 279: Insulator 280: Insulator 282: Insulator 283: Insulator 284: Insulator 287: Insulator 290: Conductor 292: Capacitor Components 292A: Capacitor Component 292B: Capacitor Component 294: Conductor 295: Insulator 296: Insulator 297: Conductor 298: Insulator 299: Conductor 300: Transistor 311: Semiconductor substrate 313: Semiconductor Region 314a: Low resistance region 314b: Low resistance region 315: Insulator 316: Conductor 411: Component Layer 413: Transistor layer 413_m: Transistor layer 413_1: Transistor layer 415: Memory Device Layer 415_n: Memory device layer 415_p: Memory device layer 415_p-1: Memory Device Layer 415_1: Memory Device Layer 415_3: Memory Device Layer 415_4: Memory Device Layer 420: Memory device 420A: Memory device 420B: Memory device 422: Area 424: Conductor 426: Conductor 428: Conductor 430: Conductor 432: Memory Unit 433: Memory Unit 434: Memory Unit 435: Memory Unit 470: Memory Unit 470_m: Memory unit 470_1: Memory unit 700: Electronic Components 702: Printed Circuit Board 704: Mounting substrate 711: Mold 712: Connector 713: Electrode pads 714: Line 730: Electronic Components 731: Insert Board 732: Packaging substrate 733: Electrode 735: Semiconductor Device 901: Boundary Area 902: Boundary Area 7100: Robot 7120: Flying Object 7140: Robotic Vacuum Cleaner 7160: Cars 7200: TV device 7210: Smartphone 7220:PC 7230:PC 7232: Keyboard 7233: Display device 7240: Game console 7260: Game console 7262: Controller 7300: Robotic Vacuum Cleaner

Claims

1. A semiconductor device comprising: a memory cell array, including: a first memory cell including a first transistor; and a second memory cell including a second transistor; a control circuit including a third transistor and electrically connected to the memory cell array; and a drive circuit including a fourth transistor and electrically connected to the control circuit, wherein the gate of the third transistor is located on the gate of the fourth transistor, wherein the semiconductor layer of the first transistor is located on the semiconductor layer of the third transistor, wherein the semiconductor layer of the second transistor is located on the semiconductor layer of the first transistor, wherein the control circuit is configured as a sense amplifier and a switching circuit, and wherein the first transistor, the second transistor, and the third transistor each include a metal oxide in a channel forming region.

2. A semiconductor device comprising: a memory cell array, including: a first memory cell including a first transistor; and a second memory cell including a second transistor; a sense amplifier including a third transistor and electrically connected to the memory cell array; and a drive circuit including a fourth transistor and electrically connected to the sense amplifier, wherein the gate of the third transistor is located on the gate of the fourth transistor, wherein a semiconductor layer of the first transistor is located on the semiconductor layer of the third transistor, wherein a semiconductor layer of the second transistor is located on the semiconductor layer of the first transistor, wherein one of the source and drain of the third transistor is electrically connected to one of the source and drain of the first transistor through wiring, wherein the one of the source and drain of the third transistor is electrically connected to one of the source and drain of the second transistor through the wiring, and wherein the first transistor, the second transistor, and the third transistor each include a metal oxide in a channel forming region.

3. The semiconductor device according to claim 1 or 2, wherein the first memory cell further includes a capacitor, and wherein the capacitor is located under the semiconductor layer of the first memory cell.

4. The semiconductor device according to claim 1 or 2, wherein the first memory cell further includes a capacitor, and wherein the capacitor is located on the semiconductor layer of the first memory cell.

5. The semiconductor device according to claim 1 or 2, wherein the first memory cell further includes a capacitor, and wherein the electrodes of the capacitor are located on the same layer as the semiconductor layer of the first memory cell.

6. A semiconductor device comprising: a memory cell array; a sense amplifier electrically connected to the memory cell array; and a drive circuit electrically connected to the sense amplifier, wherein the memory cell array includes a first memory cell and a second memory cell, wherein the first memory cell includes a first transistor, a second transistor, and a first capacitor, wherein the second memory cell includes a third transistor and a second capacitor, wherein the sense amplifier includes a fourth transistor, wherein one of the source and drain of the first transistor is electrically connected to the first capacitor, wherein the source and drain of the first transistor are electrically connected to the gate of the second transistor, wherein one of the source and drain of the third transistor is electrically connected to the second capacitor, wherein the source and drain of the third transistor are not electrically connected to any transistor, wherein a semiconductor layer of the first transistor is located on a semiconductor layer of the fourth transistor, wherein a semiconductor layer of the third transistor is located on the semiconductor layer of the first transistor, and wherein the first transistor, the second transistor, the third transistor, and the fourth transistor each include a metal oxide in a channel forming region.

7. A semiconductor device comprising: a memory cell array; a sense amplifier electrically connected to the memory cell array; and a drive circuit electrically connected to the sense amplifier, wherein the memory cell array includes a first memory cell and a second memory cell, wherein the number of transistors included in the first memory cell is different from the number of transistors included in the second memory cell, wherein the first memory cell includes a first transistor, wherein the second memory cell includes a second transistor, wherein the sense amplifier includes a third transistor, wherein a semiconductor layer of the first transistor is located on a semiconductor layer of the third transistor, wherein a semiconductor layer of the second transistor is located on a semiconductor layer of the first transistor, and wherein the first transistor, the second transistor, and the third transistor each include a metal oxide in a channel forming region.

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