Semiconductor device and method of manufacturing thereof

Abstract

This disclosure provides a semiconductor device with insulating features and a method for manufacturing it. One method includes: forming a first source / drain feature and a second source / drain feature over a substrate, wherein the first source / drain feature and the second source / drain feature are separated by a gate structure; removing the gate structure to form a trench; forming an insulating feature in the trench; and forming a functional circuit over the substrate, wherein a shunt path connected in parallel with the functional circuit is defined below the insulating feature and between the first source / drain feature and the second source / drain feature.

Description

Technical Field

[0001] none. Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and using lithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] none. Simple Explanation of the Diagram

[0005] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the features may be increased or decreased arbitrarily. Figure 1 illustrates a simplified top-to-bottom layout of a semiconductor device according to one or more of the embodiments disclosed herein; Figure 2 is a flowchart of a method for manufacturing a semiconductor device according to one or more of the embodiments disclosed herein; Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A provide cross-sectional views of embodiments of the semiconductor device 300 according to various stages of the method of Figure 2, along a plane substantially parallel to the plane defined by cross-section X-X' of Figure 1; Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B provide cross-sectional views of embodiments of the semiconductor device 300 according to various stages of the method of Figure 2, along a plane substantially parallel to the plane defined by cross-section Y-Y' of Figure 1; Figure 11A is a schematic cross-sectional view of an embodiment of the semiconductor device 300 according to the method of Figure 2 at each stage, along a plane substantially parallel to the plane defined by cross-section X-X' of Figure 1; Figure 11B is a schematic cross-sectional view of the embodiment of Figure 11A taken along the plane B-B' defined in Figure 11C; Figure 11C is a top view of an embodiment of Figure 11A; Figure 12 is a circuit diagram showing the path of the TVS device from Figure 11A to Figure 11C; Figure 13 is a schematic cross-sectional view of an embodiment of the semiconductor device 300 according to the method of Figure 2 at each stage, along a plane substantially parallel to the plane defined by cross-section X-X' of Figure 1; Figures 14 and 15 are schematic cross-sectional views of an embodiment of semiconductor device 300 along a plane substantially parallel to the plane defined by cross-section X-X' in Figure 1, illustrating the breakdown voltage behavior; Figure 16 is a current-voltage diagram illustrating the behavior of a CPODE-based TVS device according to an embodiment of this document; Figure 17A is a schematic cross-sectional view of an embodiment of the semiconductor device 300 according to the method of Figure 2 at each stage, along a plane substantially parallel to the plane defined by cross-section X-X' of Figure 1; Figure 17B is a schematic cross-sectional view of the embodiment of Figure 17A taken along the plane B-B' defined in Figure 17C; Figure 17C is a top view of an embodiment of Figure 17A; Figure 17D is a schematic cross-sectional view of an embodiment of the semiconductor device 300 according to the method of Figure 2 at each stage, along a plane substantially parallel to the plane defined by cross-section X-X' of Figure 1; Figure 18A is a schematic cross-sectional view of an embodiment of the semiconductor device 300 according to the method of Figure 2 at each stage, along a plane substantially parallel to the plane defined by cross-section X-X' of Figure 1; Figure 18B is a schematic cross-sectional view of the embodiment of Figure 18A taken along the plane B-B' defined in Figure 17C; Figure 18C is a top view of an embodiment of Figure 18A; Figure 19A is a schematic cross-sectional view of an embodiment of the semiconductor device 300 according to the method of Figure 2 at each stage, along a plane substantially parallel to the plane defined by cross-section X-X' of Figure 1; Figure 19B is a schematic cross-sectional view of the embodiment of Figure 19A taken along the plane B-B' defined in Figure 17C; Figure 19C is a top view of an embodiment of Figure 19A; Figure 20A is a schematic cross-sectional view of an embodiment of the semiconductor device 300 according to the method of Figure 2 at each stage, along a plane substantially parallel to the plane defined by cross-section X-X' of Figure 1; Figure 20B is a top view of an embodiment of Figure 20A; Figure 21A is a schematic cross-sectional view of an embodiment of the semiconductor device 300 according to the method of Figure 2 at each stage, along a plane substantially parallel to the plane defined by cross-section X-X' of Figure 1; Figure 21B is a top view of an embodiment of Figure 21A; Figure 22A is a schematic cross-sectional view of an embodiment of the semiconductor device 300 according to the method of Figure 2 at each stage, along a plane substantially parallel to the plane defined by cross-section X-X' of Figure 1; Figure 22B is a top view of an embodiment of Figure 22A; Figures 23 and 24 are top views of two embodiments of the semiconductor device 300 according to the embodiments herein; Figure 25 is a current-voltage diagram illustrating the behavior of the devices in Figures 23 and 24; Figures 26 and 27 are top views of two embodiments of the semiconductor device 300 according to the embodiments herein; Figure 28 is a current-voltage diagram illustrating the behavior of the devices in Figures 26 and 27; Figures 29 and 30 are top views of two embodiments of the semiconductor device 300 according to the embodiments herein; Figure 31 is a current-voltage diagram illustrating the behavior of the devices in Figures 29 and 30; Figures 32 and 33 are top views of two embodiments of the semiconductor device 300 according to the embodiments herein. Figure 34 is a current-voltage diagram illustrating the behavior of the devices in Figures 32 and 33; Figures 35 and 36 are top views of two embodiments of the semiconductor device 300 according to the embodiments herein; and Figure 37 is a flowchart of a method according to one or more of the present disclosure. Implementation

[0006] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature is formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, this document uses spatial relative terms such as "below," "under," "lower part," "above," and "upper part" to describe the relationship between an element or feature and another element or feature shown in the figure. In addition to the orientation depicted in the figure, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0008] Some embodiments herein relate to semiconductor devices in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of a channel region. These multi-gate devices can include P-type metal-oxide-semiconductor devices or N-type metal-oxide-semiconductor multi-gate devices. Due to their fin-like structure, specific examples of which may be presented herein and referred to as FinFETs are shown. An embodiment of a multi-gate transistor referred to as a gate-all-around (GAA) device is also presented herein. A GAA device includes any device whose gate structure or a portion thereof is formed on four sides of a channel region (e.g., surrounding a portion of the channel region). Devices presented herein also include embodiments having channel regions disposed in nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. Embodiments of devices that may have one or more channel regions (e.g., nanowires / nanosheets) associated with a single continuous gate structure are presented herein. However, those skilled in the art will recognize that this teaching can be applied to a single channel (e.g., a single nanowire / nanosheet) or any number of channels. While some illustrations depict FinFET or GAA devices, this disclosure is not limited to such devices. For example, some embodiments relate to planar semiconductor devices. Those skilled in the art will recognize other examples of semiconductor devices from which the embodiments of this disclosure may benefit.

[0009] Some embodiments described herein include a continuous poly on diffusion edge (CPODE) process to form insulating features. A "diffusion edge" can be equivalently referred to as an active edge, for example, an active edge adjacent to an adjacent active region. Furthermore, the active region includes regions forming transistor structures (e.g., including source, drain, and gate / channel structures). In some instances, the active regions may be positioned between insulating features. The CPODE process can provide insulating features between adjacent active regions by performing a dry etching process along the active edge (e.g., at the boundary of adjacent active regions) to form diced regions and filling the diced regions with a dielectric such as silicon nitride (SiN), thereby providing insulating features between adjacent transistors. More specifically, the CPODE process can provide insulating features between adjacent source / drain features by performing a dry etching process along the active edge (e.g., at the boundary of adjacent active regions) to form cut regions and filling the cut regions with a dielectric such as silicon nitride (SiN).

[0010] Prior to the CPODE process, the active edge may include a virtual GAA structure with gate stacks and multiple channels (e.g., nanowire / nanosheet channels). Furthermore, internal spacers may be disposed between adjacent channels at the lateral ends of the multiple channels. In various instances, source / drain epitaxial layers of adjacent active regions are disposed on either side of the virtual GAA structure (formed at the active edge), such that adjacent source / drain epitaxial layers are in contact with the internal spacers and the multiple channels of the virtual GAA structure. A gate etching process can be performed just before the CPODE etching process to remove the gate layer from the virtual GAA structure.

[0011] In some embodiments, the source / drain features adjacent to the insulation feature are terminals electrically connected to the functional circuitry. Specifically, a shunt path in parallel with the functional circuitry is defined between the terminals. Below the CPODE feature, the shunt path extends from the source / drain feature to the source / drain feature. Therefore, the breakdown voltage can be selected and defined by the structure of the CPODE feature. In other words, the CPODE feature can be formed with the required depth, the required lateral width (in the lateral direction from the source / drain region to the source / drain region), and the required longitudinal length (in the direction perpendicular to the lateral direction) to define the required breakdown voltage.

[0012] In other words, the source / drain characteristics and insulation characteristics form a transient voltage suppressor (TVS) device, such as a diode. Within the normal operating voltage range of the functional circuit, the TVS exhibits high impedance. Only when the surge exceeds a preset limit will the TVS conduct, thereby suddenly limiting the voltage rise above the limit.

[0013] A transient voltage suppressor is connected in parallel with the functional circuit to protect the functional circuit from high voltage. When the applied voltage exceeds the maximum permissible transient voltage (i.e., breakdown voltage), current is conducted to ground via the source / drain characteristics.

[0014] In some embodiments, the transient voltage suppressor junction breakdown mechanism is formed by the CPODE feature covering the semiconductor material.

[0015] Unlike conventional transient voltage suppressors, the embodiments described herein do not rely on additional placement processes to define the N / P junction in order to define and set the breakdown voltage. By using CPODE-based features to define the breakdown voltage instead of the placement region, processing is simplified and costs are reduced. Furthermore, using insulating features to provide transient voltage suppressor isolation, rather than large doping distances, eliminates processing limitations.

[0016] Furthermore, using CPODE-based features to define the breakdown voltage allows for tuning the maximum transient voltage on a tens-nanometer scale without additional placement processing. The maximum permissible transient voltage can be tuned by changing the dimensions of the CPODE features (such as depth, width, and length). Therefore, the permissible transient current and maximum permissible transient voltage of a tunable transient voltage suppressor can be achieved solely through placement, without any additional placement processes.

[0017] In some embodiments, the scale of the CPODE-based transient voltage suppressor can be on the order of tens of nanometers, and the wafer area required to form the CPODE-based transient voltage suppressor may be much smaller than the area required for a fabric-based TVS structure. For example, the CPODE-based transient voltage suppressor can have an area of ​​10 to 20 nanometers.

[0018] Therefore, the embodiments in this paper provide designs for various small transient voltage suppressor structures that have selectable maximum transient voltages compatible with the small size of functional circuits.

[0019] In some embodiments, the two terminals formed by the source / drain features may be adjacent to the natural ends of the active region or oxide definition (OD) region; adjacent to a polysilicon on OD edge (PODE) structure; adjacent to a floating virtual gate; or adjacent to other structures. The source / drain features may be formed in planar transistors, FinFETs, gate-around devices including nanostructures (such as nanosheets or nanorods), or other devices.

[0020] The embodiments disclosed herein provide advantages over the prior art, but it should be understood that other embodiments may provide different advantages, and not all advantages must be discussed herein, nor are any specific advantages required for any embodiment.

[0021] For the purposes of the following discussion, Figure 1 provides a simplified top-down layout of the semiconductor device 100. In various embodiments, the semiconductor device 100 is a multi-gate device and may include a FinFET device, a GAA transistor, or other types of multi-gate devices. The multi-gate device 100 may include a plurality of fin elements 104 extending from a substrate, a gate structure 313 disposed above and around the fin elements 104, and source / drain features 105, 107, wherein the source / drain features 105, 107 are formed in, above, and / or around the fins 104. The channel regions of the multi-gate device 100, which may include a plurality of semiconductor channel layers (e.g., when the multi-gate device 100 includes a GAA transistor), are disposed within the fins 104 along a plane substantially parallel to the plane defined by cross section X-X' of Figure 1, and overlying the gate structure 313. In some embodiments, sidewall spacers may also be formed on the sidewalls of the gate structure 313. The various other features of the multi-gate device 100 are discussed in more detail below with reference to the method in Figure 2.

[0022] Referring to Figure 2, a method 200 for manufacturing a semiconductor device 300 (e.g., which may include a multi-gate device) using a CPODE process according to various embodiments is illustrated. Method 200 is discussed below with reference to a GAA device having a channel region, which may be referred to as a nanosheet and may include various geometries (e.g., cylindrical, rod-shaped) and sizes. However, it should be understood that the forms of method 200 (including the disclosed CPODE process) can be equally applied to other types of devices without departing from the scope of this disclosure. In some embodiments, method 200 can be used to manufacture the device 100 described above with reference to Figure 1. Therefore, one or more forms discussed above with reference to device 100 can also be applied to method 200. It should be understood that method 200 includes steps characteristic of a complementary metal-oxide-semiconductor (CMOS) technology process flow, and is therefore only briefly described herein. Furthermore, additional steps may be performed before, after, and / or during method 200.

[0023] Method 200 is described below with reference to Figures 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, and 10A and 10B, which illustrate a semiconductor device 300 at various manufacturing stages according to method 200. Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A provide cross-sectional views of an embodiment of the semiconductor device 300 along a plane substantially parallel to the plane defined by section X-X' of Figure 1. In addition, Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B and 10B provide cross-sectional views of an embodiment of the semiconductor device 300 along a plane substantially parallel to the plane defined by cross-section Y-Y' of Figure 1.

[0024] Furthermore, the semiconductor device 300 may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random-access memory (SRAM), and / or other logic circuits, but simplifications have been made for a better understanding of the inventive concept disclosed herein. In some embodiments, the semiconductor device 300 includes a plurality of semiconductor devices (e.g., transistors), including interconnectable PFETs, NFETs, etc. It should also be noted that the process steps of method 200 (including any descriptions given with reference to the accompanying drawings) are merely illustrative and are not intended to limit the specific references in the following claims.

[0025] Method 200 begins at block 202, where a partially manufactured apparatus is provided. Referring to the examples in Figures 3A and 3B, in the embodiment of block 202, apparatus 300 includes a first active region 303, a second active region 305, and an active edge 307 defined at the boundary between the first active region 302 and the second active region 305. In some embodiments, the first active region 303 includes a first GAA device 309, the second active region 305 includes a second GAA device 311, and the active edge 307 includes a virtual GAA structure 313, as described below. According to the embodiments disclosed herein, by performing a dry etching process along the active edge 307 to form a cut area and filling the cut area with a dielectric, the CPODE process can provide an insulating feature between the first active region 303 and the second active region 305, and thus between the first GAA device 309 and the second GAA device 311, as described in more detail below. Each of the first GAA device 309, the second GAA device 311, and the virtual GAA structure 313 is formed on a substrate 302 having fins 304.

[0026] Block 202 includes providing a substrate 302. In some embodiments, substrate 302 may be a semiconductor substrate, such as a silicon substrate. Substrate 302 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Depending on design requirements known in the art, substrate 302 may include various doping configurations. Substrate 302 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 302 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 302 may, where appropriate, include an epitaxial layer, may be strained to improve performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement features.

[0027] In some embodiments, block 202 includes a stack of epitaxial layers formed over a substrate. The stack includes a first epitaxial layer of a first composition interposed by a second epitaxial layer of a second composition. The first and second compositions may be different. Embodiments may include providing first and second compositions with different oxidation rates and / or etch selectivity. In one embodiment, the first epitaxial layer is silicon germanium (SiGe), and the second epitaxial layer is silicon.

[0028] In some embodiments, block 202 includes a patterned substrate and an overlay epitaxial layer stacked to form fin elements 104. Furthermore, block 202 may include shallow trench isolation (STI) features (also referred to as STI features) formed in trenches adjacent to the sides and ends of each fin element 104 having a dielectric layer. STI features can be formed by first filling the trenches around each fin element 104 with a dielectric material layer to cover the top surface and sidewalls of the fin element 104. The dielectric material layer may include one or more dielectric materials. Suitable dielectric materials for the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited using any suitable technique, including thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD, and / or spin coating. Subsequently, the dielectric material layer is planarized using, for example, chemical mechanical planarization (CMP), followed by a recess process to form a shallow trench isolation (STI) feature. Any suitable etching technique can be used to recess the STI feature, including dry etching, wet etching, RIE, and / or other etching methods. In one exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation feature without etching the fin element 104.

[0029] Block 202 further includes forming a sacrificial (virtual) gate structure 313, which can be formed in any suitable number. Each sacrificial gate structure 313 protrudes upward from the substrate in the Z direction and extends longitudinally in the Y direction. In Figure 1, additional sacrificial gate structures will be spaced apart along the X direction.

[0030] A sacrificial gate structure 313 is formed on a portion of the fin element 104 that will become a channel region. The sacrificial gate structure 313 may extend over several adjacent fin elements 104. The sacrificial gate structure 313 is located directly above and defines the channel regions of the semiconductor device to be formed. Each of the sacrificial gate structures 313 may include a sacrificial gate dielectric and a sacrificial gate electrode above the sacrificial gate dielectric.

[0031] The sacrificial gate structure 313 is formed by first depositing a sacrificial gate dielectric layer over the fin element 104. Subsequently, a sacrificial gate electrode layer is deposited over both the sacrificial gate dielectric layer and the fin element 104. The sacrificial gate dielectric layer includes silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100 nanometers to about 200 nanometers. The sacrificial gate electrode layer includes silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD (including LPCVD, PECVD, PVD, ALD, or other suitable processes). A mask layer is formed over the sacrificial gate electrode layer. The mask layer may include a silicon oxide layer and a silicon nitride layer. Subsequently, a patterning operation is performed on the mask layer, and the sacrificial gate electrode layer and the sacrificial gate dielectric layer are patterned into the sacrificial gate structure 313.

[0032] After the sacrificial gate structure 313 is formed, each fin element 104 is partially exposed on the opposite side of the sacrificial gate structure 312, thereby defining the source / drain (S / D) region. In this disclosure, depending on the context, "source / drain region" or "source / drain feature" may refer to the source or drain individually or collectively.

[0033] Block 202 may further include forming sidewall spacers 315 on the sidewalls of the sacrificial gate structure 313 and the fin element 104 by depositing spacer material followed by etching. The sidewall spacers 315 may include spacer materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film and / or combinations thereof.

[0034] Block 202 may further include back etch (e.g., anisotropic) to expose and remove portions of the fin element 104 that are adjacent to but not covered by the sacrificial gate structure 313 (e.g., source / drain regions). After removing portions of the fin element 104, a pad material layer and a dielectric material layer remain on the sidewalls of the sacrificial gate structure 313 as gate sidewall spacers and on the sidewalls of the fins as fin sidewall spacers.

[0035] Block 202 may further include the formation of internal spacers. For example, the second epitaxial layer in the fin element 104 may be etched. In an exemplary embodiment, the SiGe etch-back process is removed to laterally recess the second layer. Thus, a cavity is laterally formed near the second layer. Subsequently, material for forming the internal spacers 319 is deposited. For example, the internal spacers 319 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxide, silicon carbonitride, and / or other suitable dielectric materials. The internal spacers 319 may be formed by ALD or any other suitable method. After depositing the material forming the internal spacers 319, the material may be trimmed from the sidewalls of the first epitaxial layer.

[0036] Block 202 may also include the formation of source / drain features 321. In an exemplary embodiment, the source / drain features 321 are formed by epitaxial growth. In an exemplary embodiment, the source / drain features 321 are strained source / drain features. In an exemplary embodiment, the source / drain features 321 may include n-type epitaxial material source / drain features and p-type epitaxial material drain features. The epitaxial material may include one or more layers of Si, SiP, SiC, and SiCP (for n-channel FETs) or Si, SiGe, and Ge (for p-channel FETs). For p-channel FETs, the source / drain may also contain boron (B). The source / drain epitaxial layers may be formed by epitaxial growth methods using CVD, ALD, or molecular beam epitaxy (MBE).

[0037] Block 202 may include a dielectric covering of source / drain feature 321. Specifically, a dielectric pad 327, such as a contact etch stop layer (CESL), may be formed over the source / drain feature 321 and along the side of spacer 315. Furthermore, a dielectric 323 may be formed over the pad 327 above the source / drain feature 321. In an exemplary embodiment, dielectric 323 is a first interlayer dielectric layer (ILD). Dielectric 323 may be silicon oxide or other suitable dielectric material. In some embodiments, the ILD dielectric 323 is the same material as the sidewall spacer 315. In some embodiments, dielectric pad 327 is a dielectric, such as silicon nitride or another suitable material.

[0038] Block 202 may further include opening and removing the selected sacrificial gate structure, including removing the sacrificial gate dielectric and the sacrificial gate electrode. Specifically, a chemical mechanical planarization (CMP) process may be performed to expose the selected sacrificial gate structure. The selected sacrificial gate structure is then removed to form a gate cavity defined by sidewall spacers 315.

[0039] Block 202 further includes removing the first epitaxial layer beneath the removed selected sacrificial gate structure. This creates gaps between the second epitaxial layers. In this manner, the second epitaxial layers are formed as vertically spaced semiconductor nanosheet channel layers 306.

[0040] Block 202 also includes completing the replacement metal gate process. In an exemplary embodiment, the replacement metal gate process includes forming a gate dielectric layer 310 in the gate cavity and in the gap below the nanosheet channel layer 306, and forming a gate electrode material 312 above the gate dielectric layer 310 to fill the gate cavity and the gap.

[0041] An exemplary gate dielectric layer 310 is conformally deposited. The gate dielectric 310 can be formed on the semiconductor nanosheet channel layer 306, and the gate electrode material 312 can be formed on the gate dielectric layer 310. Therefore, each semiconductor nanosheet channel layer 306 is encapsulated in the gate dielectric 310 and surrounded by the gate electrode material 312.

[0042] According to some embodiments, the gate dielectric layer 310 may include silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 310 is a high-k dielectric material, in which case the gate dielectric layer 310 may have a k value greater than about 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming the gate dielectric layer 310 may include molecular-beam deposition (MBD), ALD, PECVD, etc.

[0043] Gate electrode material 312 is deposited on gate dielectric layer 310 and fills the remaining portion of the gate cavity. Gate electrode material 312 can be a metallic material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiple layers thereof. For example, although a single gate electrode material is shown, any number of work function tuning layers can be deposited.

[0044] The replacement metal gate process may further include removing excess portions of the gate dielectric layer 310 and gate electrode material 312 located above the top surface of the ILD 323. For example, a planarization process (such as a CMP process) may be performed to remove excess portions of the gate dielectric layer 310 and gate electrode material 312.

[0045] The remaining portion of the material of the gate dielectric layer 310 and the gate electrode material 312 thus forms the replacement metal gate structure of the resulting devices 309 and 311. The gate dielectric layer 310 and the gate electrode material 312 may be collectively referred to as a "gate", a "gate stack", or a "gate structure". Each gate structure may extend along the sidewall of the channel region of the fin structure.

[0046] Block 202 also includes forming a gate cap layer 325 above the gate structure. For example, the gate cap layer 325 may be a hard mask layer 325. The gate cap layer 325 may be formed by initially depositing a dielectric material above the gate. In some embodiments, the gate cap 325 is formed using a dielectric material such as silicon nitride (SiN), oxide (OX), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), etc. According to some embodiments, the gate cap 325 is formed using metal oxides such as zirconium (Zr), hafnium (Hf), aluminum (Al), etc. Furthermore, the gate cap 325 can be formed using a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. However, any suitable material and deposition process can be used. After deposition, a planarization process, such as chemical mechanical polishing, can be used to planarize the gate cap 325.

[0047] Block 202 may further include an additional material layer 331 deposited above device 300 (including above cover 325).

[0048] Furthermore, block 202 may include forming a dielectric layer 333 that can be formed over material layer 331. In some embodiments, dielectric layer 333 includes SiN. Dielectric layer 333 may also be used as a hard masking layer.

[0049] Referring to an end view of the nanosheet channel layer 306 (e.g., Figure 3B), the X and Y dimensions of the nanosheet channel layer 306 may be approximately five to fourteen nanometers, and the Y dimension may be approximately five to eight nanometers. In some cases, the X dimension and Y dimension of the nanosheet channel layer 306 are substantially the same. In some cases, the spacing between adjacent nanosheet channel layers 306 (e.g., along the Y direction) is approximately four to eight nanometers.

[0050] As shown in Figures 3A and 3B, each of the fins 304 may include a substrate portion 302A formed from a substrate 302 and nanosheet channel layers 306. It should be noted that although the fins 304 are illustrated as including three nanosheet channel layers 306, this is for illustrative purposes only and is not intended to limit the specific references in the claims. It will be understood that any number of nanosheet channel layers 306 can be formed, wherein, for example, the number of nanosheet channel layers 306 depends on the number of channel regions required by the GAA device (e.g., device 300). In some embodiments, the number of nanosheet channel layers 306 is between three and ten.

[0051] In some embodiments, the source / drain feature 321 is formed in a source / drain region adjacent to and located on either side of the gate structure of each of the first GAA device 309 and the second GAA device 311, and is formed above the substrate portion 302A. Therefore, the virtual GAA structure 313 is disposed between the first source / drain feature 321 of the first GAA device 309 (in the first active region 303) and the second source / drain feature 321 of the second GAA device 311 (in the second active region 305). As shown, the source / drain feature 321 of the first GAA device 309 contacts the internal spacer 319 and the nanoplate channel layer 306 of the first GAA device 309, and the source / drain feature 321 of the second GAA device 311 contacts the internal spacer 319 and the nanoplate channel layer 306 of the second GAA device 311. Furthermore, the source / drain features 321 (of the first GAA device 309 and the second GAA device 311) located on either side of the virtual GAA structure 313 are in contact with the internal spacers 319 and the nanosheet channel layer 306 of the virtual GAA structure 313.

[0052] In various instances, the source / drain feature 321 comprises a semiconductor epitaxial layer, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials, which can be formed by one or more epitaxial processes. In some embodiments, the source / drain feature 321 may be doped in situ during the epitaxial process. For example, in some embodiments, the epitaxially grown SiGe source / drain feature may be doped with boron. In some cases, the epitaxially grown Si source / drain feature may be doped with carbon to form a Si:C source / drain feature, doped with phosphorus to form a Si:P source / drain feature, or doped with both carbon and phosphorus to form a SiCP source / drain feature. In some embodiments, the source / drain feature 321 is not doped in situ, and instead a placement process is performed to dope the source / drain feature 321. In some embodiments, the formation of the source / drain feature 321 may be performed in separate processing sequences for each of the N-type and P-type source / drain features.

[0053] In some embodiments, method 200 then proceeds to block 204, whichever is selected, where a cut-gate or cut-metal-gate (CMG) process is performed. Referring to Figure 3B, in an embodiment of block 204 and after the formation of dielectric layer 333, a cut-metal-gate process is performed to isolate the metal layer 312 of the adjacent structure. For example, lithography and etching processes may be performed to etch portions of dielectric layer 333, material layer 331, metal layer 329, metal layer 312, and high-k gate dielectric layer 310 to form a trench 350 in the cut-metal-gate region 355. In some embodiments, the formation of trench 350 exposes portions of the underlying STI feature 317. In various instances, dry etching (e.g., reactive ion etching), wet etching, or a combination thereof may be used to etch trench 350.

[0054] Method 200 then proceeds to block 206, where a refill process is performed. Referring to Figures 3A, 3B, 4A, and 4B, in an embodiment of block 206, a dielectric layer 402 is formed over device 300 (including over dielectric layer 333) using a refill process. Dielectric layer 402 also fills the previously formed trench 350 and electrically isolates the metal layer 312 of adjacent structures. In some embodiments, dielectric layer 402 comprises SiN. Alternatively, in some cases, dielectric layer 402 may comprise SiO2, silicon oxynitride, FSG, low-k dielectrics, combinations thereof, and / or other suitable materials known in this art. In various instances, dielectric layer 402 may be deposited by CVD processes, SACVD processes, flowable CVD processes, ALD processes, PVD processes, and / or other suitable processes. In some cases, after depositing the dielectric layer 402, a chemical mechanical polishing (CMP) process can be performed to remove excess material and planarize the top surface of the apparatus 300.

[0055] Method 200 then proceeds to block 208, where a photolithography (photolithography) process is performed. Referring to Figures 4A, 4B, 5A, and 5B, in an embodiment of block 208, a photoresist layer is deposited over device 300 (e.g., using a spin coating process) and patterned to form a patterned photoresist layer 502 that exposes a portion of dielectric layer 402. In various embodiments, the photolithography process for forming the patterned photoresist layer 502 may also include other steps such as soft baking, mask alignment, exposure, post-exposure baking, development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography processes, and / or combinations thereof. In some embodiments, the photolithography process of block 208 may include a CPODE photolithography process, wherein the patterned photoresist layer 502 provides an opening 504 in a CPODE region 506 that exposes a portion of dielectric layer 402. In addition, CPODE region 506 may include the active edge 307 and virtual GAA structure 313 discussed above with reference to Figure 3A.

[0056] Method 200 then proceeds to block 210, where an etching and resist removal process is performed. Referring to Figures 5A, 5B, 6A, and 6B, in an embodiment of block 210, an etching process is performed to remove portions of dielectric layer 402 and dielectric layer 333 (e.g., in areas exposed by openings 504 in the patterned resist layer 502) to form opening 604. Thus, in some instances, the etching process of block 210 may be referred to as a SiN etching process, a hard mask etching process, or a SiN hard mask etching process. In various embodiments, the opening 604 formed by the etching process may expose a portion of the material layer 331 within the CPODE region 506. In some instances, the etching process may include a dry etching process, a wet etching process, and / or a combination thereof. After the etching process and in another embodiment of block 210, the patterned resist layer 502 can be removed, for example, by means of solvents, resist strippers, ashing or other suitable techniques.

[0057] Method 200 then proceeds to block 212, where an etching process is performed. Referring to Figures 6A, 6B, 7A, and 7B, in an embodiment of block 212, an etching process is performed to remove a portion of material layer 331 (e.g., in the area exposed by opening 604) to form opening 704. In various embodiments, such as when material layer 331 comprises silicon (Si), the etching process of block 212 may include a Si etching process or a Si dry etching process. In some instances, the opening 704 formed by the etching process of block 212 may expose the virtual gate GAA structure 313 within CPODE region 506. Specifically, opening 704 may expose a portion of metal layer 329, spacer layer 315, and in some cases, a portion of CESL 327 within CPODE region 506. In some instances, the etching process of block 212 may include a dry etching process, a wet etching process, and / or a combination thereof.

[0058] Method 200 then proceeds to block 214, where a gate etching process is performed. Referring to Figures 7A, 7B, 8A, and 8B, in the embodiment of block 214, the gate etching process includes removing layers 312 and 329 without removing the gate dielectric layer 310 of the virtual GAA structure 313. In other words, the wet etching process selectively removes layers 312 and 329 without removing the gate dielectric layer 310. Therefore, the wet etching process of block 214 can be referred to as a selective etching process or a selective wet etching process. It should be noted that the wet etching process can remove layer 312 from the top of the virtual GAA structure 313 and between adjacent channels of the nanosheet channel layer 306.

[0059] Method 200 then proceeds to block 216, where a CPODE etching process is performed. Referring to Figures 8A, 8B, 9A, and 9B, in the embodiment of block 216, the CPODE etching process removes a gate structure 313 (marked in Figure 7A) selected for removal via an etching apparatus 300 with an opening 804 within the CPODE region 506, thereby forming a trench 904 with an extension 906 that can extend into the underlay substrate 302. In some cases, the CPODE etching process includes a dry etching process. In some embodiments, the CPODE etching process removes the nanosheet channel layer 306, internal spacers 319, high-k gate dielectric layer 310, interface layer (if present), and portions of the underlay substrate 302 not protected by the spacer layer 315 (directly disposed thereunder) within the CPODE region 506.

[0060] Method 200 then proceeds to block 218, where a refill process is performed. Referring to Figures 9A, 9B, 10A, and 10B, in the embodiment of block 218, an insulating layer 1002 is formed over device 300 and within trench 904 formed by the CPODE etching process using the refill process. Thus, by performing a CPODE etching process along active edge 307 to form a cut area (trench 904) and filling the cut area with insulating layer 1002, insulating layer 1002 and, more generally, the CPODE process described herein, provide an isolation region between the first active region 303 and the second active region 305 (including between the first GAA device 309 and the second GAA device 311). In some embodiments, insulating layer 1002 comprises SiN. Alternatively, in some cases, insulating layer 1002 may comprise SiO2, silicon oxynitride, FSG, low-k dielectrics, combinations thereof, and / or other suitable materials known in the art. In various instances, the insulating layer 1002 can be deposited using CVD, SACVD, flowable CVD, ALD, PVD, and / or other suitable processes. In some cases, after depositing the insulating layer 1002, a CMP process can be performed to remove excess material and planarize the top surface of the apparatus 300.

[0061] Figures 3A through 10B indicate that the gate structure 313 selected for removal can be located between two other adjacent gate structures 309 and 311. However, it is conceivable that the gate structure 313 is alternatively located between the two ends 103 of the fin element 104, such that each source / drain feature 321, including the first source / drain feature 3211 and the second source / drain feature 3212, is laterally adjacent to the STI feature 317. Such an embodiment is shown in Figure 11A.

[0062] Method 200 can continue at block 220 to form a circuit in a semiconductor device. For example, block 220 may include an overlying dielectric layer, contact openings, contact metals, and various contact / via / wire and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) formed on substrate 302 to connect various features to form a functional circuit that may include one or more multi-gate devices. To further illustrate this example, the multilayer interconnects may include: vertical interconnects, such as vias or contacts; and horizontal interconnects, such as metal lines. Various interconnect features may be made of various conductive materials, including copper, tungsten, and / or silicates. In one example, damascene and / or dual damascene processes are used to form a copper-associated multilayer interconnect structure. Furthermore, additional process steps may be performed before, during, and after method 200, and some of the aforementioned process steps may be replaced or eliminated according to various embodiments of method 200. Moreover, although method 200 is shown and described as including device 300 with a GAA device, it should be understood that other device configurations are also possible. In some embodiments, method 200 can be used to manufacture FinFET devices or other multi-gate devices.

[0063] Figures 11A, 11B, and 11C illustrate the structure of the device 300 of Figures 10A and 10B during further processing. Figure 11A is a cross-sectional view similar to that of Figure 10A. Figure 11B is a cross-sectional view along the Y-axis indicated by line B-B' (i.e., through contact 1011, rather than through insulating feature 1002 as in the previous Y-section view). Figure 11C is a top view.

[0064] As shown in Figures 11A, 11B, and 11C, forming a circuit at block 220 includes: forming a first source / drain contact 1011 electrically connected to a first source / drain feature 3211; and forming a second source / drain contact 1012 electrically connected to a second source / drain feature 3212. As further shown, the first source / drain contact 1011 is electrically connected to a first node 911, and the second source / drain contact 1012 is electrically connected to a second node 912.

[0065] A transient voltage suppressor (TVS) device in the form of a shunt path 1100 is formed between the first source / drain feature 3211 and the second source / drain feature 3212. The shunt path 1100 extends through the fin element 104 and / or the substrate 302 and is below the CPODE insulating feature 1002.

[0066] Referring to Figure 12, forming a circuit at block 220 may include: forming a functional circuit 1200 above the substrate; and forming a TVS device 1100 as a shunt path in parallel with the functional circuit 1200 defined below an insulating feature and between a first source / drain feature 3211 and a second source / drain feature 3212. In Figure 12, nodes 911 and 912 are shown as connections to the functional circuit 1200 formed above the substrate 302. As shown, the TVS device 1100 is connected in parallel with the functional circuit 1200. Node 912 may be connected to a voltage source (Vin) 1400, and node 911 may be connected to ground 1300.

[0067] TVS device 1100 exhibits high impedance within the normal range of the signal operating voltage transmitted to functional circuit 1200. When the voltage exceeds a preset limit, TVS device 1100 becomes conductive, and when current flows through TVS device 1100 to ground 1300, the voltage is suddenly limited to rise above the preset limit.

[0068] The preset limit depends on the structural characteristics of the CPODE insulation feature 1002 relative to the source / drain features 3211 and 3212. For example, the depth of the CPODE insulation feature 1002 will affect the preset limit.

[0069] As shown in Figure 11A, the CPODE insulation feature 1002 has a lowermost point or surface defining a horizontal bottom plane 1003. Furthermore, the fin element 104 has a uppermost point or surface defining a horizontal upper plane 1004. The CPODE insulation feature 1002 is formed with a depth D1 from the upper surface plane 1004 to the horizontal bottom plane 1003. Although the depth of the CPODE insulation feature 1002 is defined relative to the uppermost surface of the fin element 104, this depth can be measured with reference to any component of the device 300. For example, the depth can be measured starting from the bottom surface of the source / drain region 321. Generally, increasing the depth of the CPODE insulation feature 1002 can increase the breakdown voltage of the TVS device 1100 to become active.

[0070] In some embodiments, the depth D1 is at least 1 nanometer (nm), such as at least 2 nm, at least 3 nm, at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 12 nm, at least 14 nm, at least 16 nm, at least 18 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 35 nm, at least 40 nm, at least 45 nm, at least 50 nm, at least 55 nm, at least 60 nm, at least 65 nm, at least 70 nm, at least 75 nm, at least 80 nm, or at least 85 nm. In some embodiments, the depth D1 is at most 1 nm, such as at most 2 nm, at most 3 nm, at most 4 nm, at most 5 nm, at most 6 nm, at most 7 nm, at most 8 nm, at most 9 nm, at most 10 nm, at most 12 nm, at most 14 nm, at most 16 nm, at most 18 nm, at most 20 nm, at most 22 nm, at most 25 nm, at most 30 nm, at most 35 nm, at most 40 nm, at most 45 nm, at most 50 nm, at most 55 nm, at most 60 nm, at most 65 nm, at most 70 nm, at most 75 nm, at most 80 nm, at most 85 nm, or at most 90 nm.

[0071] As shown in Figure 11A, each source / drain feature 321 has a lowermost point or surface defining a horizontal bottom plane 3218 and an uppermost point or surface defining a horizontal top plane 3219. Each source / drain feature 321 is formed with a height H1 from the horizontal bottom plane 3218 to the horizontal top plane 3219.

[0072] In some embodiments, the height H1 is at least 1 nm, such as at least 2 nm, at least 3 nm, at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 12 nm, at least 14 nm, at least 16 nm, at least 18 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 35 nm, at least 40 nm, at least 45 nm, at least 50 nm, at least 55 nm, at least 60 nm, at least 65 nm, at least 70 nm, at least 75 nm, at least 80 nm, or at least 85 nm. In some embodiments, the height H1 is at most 1 nm, such as at most 2 nm, at most 3 nm, at most 4 nm, at most 5 nm, at most 6 nm, at most 7 nm, at most 8 nm, at most 9 nm, at most 10 nm, at most 12 nm, at most 14 nm, at most 16 nm, at most 18 nm, at most 20 nm, at most 22 nm, at most 25 nm, at most 30 nm, at most 35 nm, at most 40 nm, at most 45 nm, at most 50 nm, at most 55 nm, at most 60 nm, at most 65 nm, at most 70 nm, at most 75 nm, at most 80 nm, at most 85 nm, or at most 90 nm.

[0073] In some embodiments, the device may have a depth D1:height H1 ratio of at least 0.1:1, at least 0.2:1, at least 0.3:1, at least 0.4:1, at least 0.5:1, at least 0.6:1, at least 0.7:1, at least 0.8:1, at least 0.9:1, at least 1.0:1, at least 1.1:1, at least 1.2:1, at least 1.3:1, at least 1.4:1, at least 1.5:1, at least 1.6:1, at least 1.7:1, at least 1.8:1, at least 1.9:1, or at least 2.0:1.

[0074] In some embodiments, the device may have a depth D1:height H1 ratio of up to 0.1:1, up to 0.2:1, up to 0.3:1, up to 0.4:1, up to 0.5:1, up to 0.6:1, up to 0.7:1, up to 0.8:1, up to 0.9:1, up to 1.0:1, up to 1.1:1, up to 1.2:1, up to 1.3:1, up to 1.4:1, up to 1.5:1, up to 1.6:1, up to 1.7:1, up to 1.8:1, up to 1.9:1, or up to 2.0:1.

[0075] In some embodiments, the device may have a height H1:depth D1 ratio of at least 0.1:1, at least 0.2:1, at least 0.3:1, at least 0.4:1, at least 0.5:1, at least 0.6:1, at least 0.7:1, at least 0.8:1, at least 0.9:1, at least 1.0:1, at least 1.1:1, at least 1.2:1, at least 1.3:1, at least 1.4:1, at least 1.5:1, at least 1.6:1, at least 1.7:1, at least 1.8:1, at least 1.9:1, or at least 2.0:1.

[0076] In some embodiments, the device may have a height H1:depth D1 ratio of up to 0.1:1, up to 0.2:1, up to 0.3:1, up to 0.4:1, up to 0.5:1, up to 0.6:1, up to 0.7:1, up to 0.8:1, up to 0.9:1, up to 1.0:1, up to 1.1:1, up to 1.2:1, up to 1.3:1, up to 1.4:1, up to 1.5:1, up to 1.6:1, up to 1.7:1, up to 1.8:1, up to 1.9:1, or up to 2.0:1.

[0077] The width of CPODE insulation feature 1002 in the X direction may also affect the preset limit.

[0078] As shown in Figure 11A, the width W1 of the CPODE insulation feature 1002 is defined as the distance between its two opposite sides. In Figure 11A, the width W1 can be measured at the bottom plane 1003 or the top plane 1004, or at a horizontal plane in between. Generally, increasing the width of the CPODE insulation feature 1002 can increase the TVS device 1100 to become an active breakdown voltage.

[0079] In some embodiments, the width W1 is at least 1 nm, such as at least 2 nm, at least 3 nm, at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 12 nm, at least 14 nm, at least 16 nm, at least 18 nm, at least 20 nm, at least 25 nm, at least 30 nm, at least 35 nm, at least 40 nm, at least 45 nm, or at least 50 nm. In some embodiments, the width W1 is at most 1 nm, such as at most 2 nm, at most 3 nm, at most 4 nm, at most 5 nm, at most 6 nm, at most 7 nm, at most 8 nm, at most 9 nm, at most 10 nm, at most 12 nm, at most 14 nm, at most 16 nm, at most 18 nm, at most 20 nm, at most 22 nm, at most 25 nm, at most 30 nm, at most 35 nm, at most 40 nm, at most 45 nm, or at most 50 nm.

[0080] In some embodiments, the device may have a depth D1:width W1 ratio of at least 0.1:1, at least 0.2:1, at least 0.3:1, at least 0.4:1, at least 0.5:1, at least 0.6:1, at least 0.7:1, at least 0.8:1, at least 0.9:1, at least 1.0:1, at least 1.1:1, at least 1.2:1, at least 1.3:1, at least 1.4:1, at least 1.5:1, at least 1.6:1, at least 1.7:1, at least 1.8:1, at least 1.9:1, at least 2.0:1, at least 2.5:1, at least 3.0:1, at least 3.5:1, at least 4.0:1, at least 4.5:1, or at least 5.0:1.

[0081] In some embodiments, the device may have a depth D1:width W1 ratio of up to 0.1:1, up to 0.2:1, up to 0.3:1, up to 0.4:1, up to 0.5:1, up to 0.6:1, up to 0.7:1, up to 0.8:1, up to 0.9:1, up to 1.0:1, up to 1.1:1, up to 1.2:1, up to 1.3:1, up to 1.4:1, up to 1.5:1, up to 1.6:1, up to 1.7:1, up to 1.8:1, up to 1.9:1, up to 2.0:1, up to 2.5:1, up to 3.0:1, up to 3.5:1, up to 4.0:1, up to 4.5:1, or up to 5.0:1.

[0082] In some embodiments, the device may have a width W1:depth D1 ratio of at least 0.05:1, at least 0.1:1, at least 0.2:1, at least 0.3:1, at least 0.4:1, at least 0.5:1, at least 0.6:1, at least 0.7:1, at least 0.8:1, at least 0.9:1, at least 1.0:1, at least 1.1:1, at least 1.2:1, at least 1.3:1, at least 1.4:1, at least 1.5:1, at least 1.6:1, at least 1.7:1, at least 1.8:1, at least 1.9:1, or at least 2.0:1.

[0083] In some embodiments, the device may have a width W1:depth D1 ratio of up to 0.1:1, up to 0.2:1, up to 0.3:1, up to 0.4:1, up to 0.5:1, up to 0.6:1, up to 0.7:1, up to 0.8:1, up to 0.9:1, up to 1.0:1, up to 1.1:1, up to 1.2:1, up to 1.3:1, up to 1.4:1, up to 1.5:1, up to 1.6:1, up to 1.7:1, up to 1.8:1, up to 1.9:1, or up to 2.0:1.

[0084] Figure 13 presents a view similar to Figure 11A of another structure of the CPODE insulating feature 1002 manufactured according to method 200. In Figure 13, the insulating feature 1002 is formed with a depth D2 greater than the depth D1. Furthermore, the insulating feature 1002 is formed with a tapered bottom end, such that the width D2 can be measured at the upper plane 1004 or at the plane defined by the source / drain region 321.

[0085] In the embodiments shown in Figures 11A, 11B, 11C, and 13, the source / drain region 321 has a first dopant type, and the surrounding region of the fin 104 and substrate 302 has a second dopant type. For example, the source / drain region may be doped with an n-type dopant, and the surrounding region of the fin 104 and substrate 302 may be doped with a p-type dopant. In other embodiments, the source / drain region may be doped with a p-type dopant, and the surrounding region of the fin 104 and substrate 302 may be doped with an n-type dopant.

[0086] Figures 14 and 15 present views similar to those in Figures 11A and 13, and illustrate the electrical behavior of the TVS device 1100 during operation of the functional circuit 1200.

[0087] In Figure 14, the first N / P junction 1401 is defined below the first source / drain feature 3211, and the second N / P junction 1402 is defined below the second source / drain feature 3212. Figure 14 illustrates that within the normal range of the signal operating voltage applied to the functional circuit 1200, both junctions 1401 and 1402 intersect with the CPODE insulation feature 1002. Therefore, there is no current path between the source / drain regions 3211 and 3212.

[0088] In Figure 15, a breakdown voltage (Vin) is applied at node 912. The breakdown voltage is greater than the normal range of the signal operating voltage. Therefore, the first N / P junction 1401 and the second N / P junction 1402 are in contact with each other. Consequently, a current path is formed between the source / drain regions 3211 and 3212 and below the CPODE insulation feature 1002.

[0089] Figure 16 shows the current-voltage diagram of TVS device 1100, where current (I) is on the vertical axis and voltage (V) is on the horizontal axis. As shown, no current flows through TVS device 1100 at voltages below the breakdown voltage Vp. At the breakdown voltage Vp, TVS device 1100 is turned on, and current flows through TVS device 1000. Therefore, a voltage greater than the breakdown voltage Vp cannot be applied to the protected functional circuit 1200.

[0090] It should be noted that in the above embodiments, the CPODE insulation feature 1002 extends deeper than the source / drain feature 321; that is, the plane 1003 is located below the source / drain region 321 and does not penetrate the source / drain feature 321. In these embodiments, the CPODE insulation feature 1002 is used to modulate the maximum voltage. In other words, the TVS device 1100 is a V_max modulator.

[0091] Although Figures 9A and 10A illustrate an embodiment in which all semiconductor nanosheet channel layers 306 are removed during the CPODE etching process in block 214, other embodiments are also conceivable.

[0092] For example, Figures 17A, 17B, and 17C illustrate that the CPODE etching process for block 214 can only partially etch through the upper semiconductor nanosheet channel layer 306, while retaining the lower semiconductor nanosheet channel layer 306. Therefore, a CPODE insulating feature 1002 is subsequently formed over the remaining semiconductor nanosheet channel layer 306.

[0093] Figure 17A is a cross-sectional view similar to Figure 11A. Figure 17B is a cross-sectional view similar to Figure 11B. Figure 17C is a top view.

[0094] As shown in Figures 17A, 17B, and 17C, forming a circuit at block 220 includes: forming a first source / drain contact 1011 electrically connected to a first source / drain feature 3211; and forming a second source / drain contact 1012 electrically connected to a second source / drain feature 3212. As further shown, the first source / drain contact 1011 is electrically connected to a first node 911, and the second source / drain contact 1012 is electrically connected to a second node 912.

[0095] A transient voltage suppressor (TVS) device in the form of a shunt path 1100 is formed between the first source / drain feature 3211 and the second source / drain feature 3212. The shunt path 1100 extends through the fin element 104 and / or the substrate 302 and is below the CPODE insulating feature 1002. More specifically, the TVS device 1100 may be located in the remaining semiconductor nanosheet channel layer 306.

[0096] As shown in Figure 17A, the CPODE insulating feature 1002 has a lowermost point or surface defining a horizontal bottom plane 1003. Furthermore, the fin element 104 has a uppermost point or surface defining a horizontal upper plane 1004. In the embodiments shown in Figures 17A to 17C, the upper plane 1004 is defined by the uppermost remaining portion of the semiconductor nanosheet channel layer 306.

[0097] CPODE insulating feature 1002 is formed with a depth D3 from the upper surface plane 1004 to the horizontal bottom plane 1003. As shown, in the embodiment of Figure 17A, the bottom plane 1003 passes through the source / drain feature 321, that is, CPODE insulating feature 1002 does not extend as deep as the source / drain feature 321.

[0098] As shown in Figure 17A, the width W3 of the CPODE insulation feature 1002 is defined as the distance between its two opposite sides. In Figure 11A, the width W3 can be measured at the bottom plane 1003 or the top plane 1004, or at a horizontal plane in between. Generally, increasing the width of the CPODE insulation feature 1002 can increase the TVS device 1100 to become an active breakdown voltage.

[0099] Figure 17D illustrates an alternative structure to the embodiment of Figure 17A. In Figure 17D, the CPODE insulating feature 1002 is formed with a depth D4 from the upper surface plane 1004 to the horizontal bottom plane 1003. As shown, in the embodiment of Figure 17D, the bottom plane 1003 extends through the source / drain feature 321, that is, the CPODE insulating feature 1002 does not extend as deep as the source / drain feature 321.

[0100] In the embodiments shown in Figures 17A, 17B, 17C, and 17D, the source / drain region 321 has a first dopant type, and the surrounding region of the fin 104 and substrate 302 has a second dopant type. For example, the source / drain region may be doped with an n-type dopant, and the surrounding region of the fin 104 and substrate 302 may be doped with a p-type dopant. In other embodiments, the source / drain region may be doped with a p-type dopant, and the surrounding region of the fin 104 and substrate 302 may be doped with an n-type dopant.

[0101] It should be noted that in the above embodiments, the source / drain feature 321 extends deeper than the CPODE insulation feature 1002; that is, the plane 1003 passes through the source / drain feature 321. In these embodiments, the CPODE insulation feature 1002 is used to modulate the maximum current. In other words, the TVS device 1100 is an I_max modulator.

[0102] Although the prior device 300 is described with respect to a single source / drain contact 1011 formed above a single fin element 104 in contact with a single source / drain feature 3211 and a single source / drain contact 1012 formed in contact with a single source / drain feature 3212, other embodiments are also conceivable.

[0103] For example, Figures 18A, 18B, and 18C illustrate an embodiment in which a single source / drain contact 1011 is configured to connect to a source / drain feature 3211 formed in a first fin 1041 and to a source / drain feature 3213 formed in a second fin 1042. Furthermore, a single source / drain contact 1012 is configured to connect to a source / drain feature 3212 formed in the first fin 1041 and to a source / drain feature 3214 formed in the second fin 1042.

[0104] Specifically, in the embodiments shown in Figures 18A, 18B, and 18C, adjacent fins 1041 and 1042 are processed according to method 200. When material is epitaxially grown to form source / drain features 321, the material is fused together. Subsequently, when source / drain contacts 1011 and 1012 are formed, each contact 1011 and 1012 contacts the fused source / drain features.

[0105] While Figures 18A, 18B, and 18C may illustrate a FinFET device 300, Figures 19A, 19B, and 19C illustrate a similar embodiment of a GAA device 300. Specifically, a single source / drain contact 1011 is configured to connect to a source / drain feature 3211 formed in the first fin 1041 and to a source / drain feature 3213 formed in the second fin 1042. Furthermore, a single source / drain contact 1012 is configured to connect to a source / drain feature 3212 formed in the first fin 1041 and to a source / drain feature 3214 formed in the second fin 1042.

[0106] Figures 20A and 20B illustrate an embodiment in which a polysilicon diffusion edge (PODE) insulating structure 1500 is formed at the end 103 of the fin element 104 to further isolate the fin element 104. Figure 20A is a cross-sectional schematic diagram similar to Figure 11A. Figure 20B is a top schematic diagram of the device in Figure 20A. The PODE structure 1500 can be formed in the CPODE forming process of method 200. As shown, the PODE structure 1500 is formed around the end 103 of the fin element 104. Therefore, the fin element 104 is not etched to form trenches in which the PODE structure 150 is formed. Furthermore, the PODE structure 1500 can be formed above the STI feature 317.

[0107] Figures 21A and 21B illustrate another embodiment. Figure 21A is a cross-sectional view similar to Figure 11A. Figure 21B is a top view of the device in Figure 21A.

[0108] In the embodiments shown in Figures 21A and 21B, a plurality of CPODE insulation features are formed. Specifically, method 200 can be performed to form three virtual gate structures 313. Subsequently, method 200 continues to remove all three virtual gate structures 313 and form CPODE insulation features. As shown in Figure 21A, the central CPODE insulation feature 1002 is located between source / drain features 3211 and 3212, and forms a TVS device 1100.

[0109] Adjacent CPODE insulating features 1600 are formed between source / drain features 3211 and adjacent source / drain features 3311, and between source / drain features 3212 and adjacent drain / drain features 3312, respectively. As shown, the CPODE insulating features 1600 extend to a greater depth, for example, to a depth below the STI region 317 into the substrate 302. Therefore, the portions of the fin element 104 between the CPODE insulating features 1600 and below the CPODE insulating feature 1002 are insulated from the adjacent semiconductor regions.

[0110] More specifically, in Figure 21A, the structure has a horizontal uppermost plane 1109, which can be defined by the uppermost surfaces of CPODE insulating feature 1002 and adjacent CPODE insulating features 1600. The central CPODE insulating feature 1002 has a lowermost surface defining the horizontal plane 1008, and the central CPODE insulating feature 1002 extends from plane 1109 to a depth D2 of plane 1008. Similarly, each adjacent CPODE insulating feature 1600 has a lowermost surface defining the horizontal plane 1608, and each adjacent CPODE insulating feature 1600 extends from plane 1109 to a depth D3 of plane 1608.

[0111] In some embodiments, the device may have a depth D2:depth D3 ratio of at least 0.1:1, at least 0.2:1, at least 0.3:1, at least 0.4:1, at least 0.5:1, at least 0.6:1, at least 0.7:1, at least 0.8:1, at least 0.9:1, or at least 0.95:1.

[0112] In some embodiments, the device may have a depth D2:depth D3 ratio of up to 0.2:1, up to 0.3:1, up to 0.4:1, up to 0.5:1, up to 0.6:1, up to 0.7:1, up to 0.8:1, up to 0.9:1, or up to 0.95:1.

[0113] In some embodiments, the device may have a depth D3 to depth D2 ratio of at least 1.05:1, at least 1.1:1, at least 1.2:1, at least 1.3:1, at least 1.4:1, at least 1.5:1, at least 1.6:1, at least 1.7:1, at least 1.8:1, at least 1.9:1, at least 2.0:1, at least 2.1:1, at least 2.2:1, at least 2.3:1, at least 2.4:1, or at least 2.5:1.

[0114] In some embodiments, the device may have a depth D3 to depth D2 ratio of up to 1.05:1, up to 1.1:1, up to 1.2:1, up to 1.3:1, up to 1.4:1, up to 1.5:1, up to 1.6:1, up to 1.7:1, up to 1.8:1, up to 1.9:1, up to 2.0:1, up to 2.1:1, up to 2.2:1, up to 2.3:1, up to 2.4:1, or up to 2.5:1.

[0115] Figures 22A and 22B illustrate another embodiment. Figure 22A is a cross-sectional view similar to Figure 11A. Figure 22B is a top view of the device in Figure 22A.

[0116] In the embodiments of Figures 22A and 22B, the floating virtual gate 1700 can provide insulation. For example, at block 202 of method 200, the floating virtual gate 1700 is formed above the fin element 104. For example, the floating virtual gate 1700 is formed between adjacent source / drain features 3313 and 3311, between adjacent source / drain features 3311 and source / drain feature 3211, between source / drain feature 3212 and adjacent source / drain feature 3312, and between adjacent source / drain features 3312 and 3314.

[0117] After the CPODE insulation feature 1002 is formed, the floating virtual gate 1700 is located between the CPODE insulation feature 1002 and the end 103 of the fin element 104.

[0118] The embodiments herein further provide various layouts for forming the CPODE insulation feature 1002 of the TVS device 1100 according to method 200.

[0119] Figure 23 is a top view schematic diagram of the device 300 formed according to the above description. In Figure 23, a first pair of fin elements 1041 and 1042 (2301) and a second pair of fin elements 1042 and 1041 (2302) are formed. Source / drain features 3211 and 3213 are formed and incorporated in each pair of 2301 and 2302. Similarly, source / drain features 3212 and 3214 are formed and incorporated in each pair of 2301 and 2302.

[0120] As shown, a single CPODE insulation feature 1002 extends through each pair 2301 and 2031 of fin elements 1041 and 1042. Furthermore, in each pair 2301 and 2302, the CPODE insulation feature 1002 separates the combined source / drain features 3211 / 3213 from the combined source / drain features 3212 / 3214.

[0121] Furthermore, a single first source / drain contact 1011 contacts the combined source / drain features 3211 / 3213 of each pair of 2301 and 2302, and a single second source / drain contact 1012 contacts the combined source / drain features 3212 / 3214 of each pair of 2302 and 2301. In other words, each source / drain contact 1011 and 1012 extends through both pairs of 2301 and 2301. Therefore, the device 300 includes two contacts 1011 and 1012.

[0122] As described above, contacts 1011 and 1012 are configured to be electrically connected to form two parallel TVS devices connected in parallel with the functional circuit.

[0123] It should be noted that the CPODE insulation features in Figure 23 have the same constant depth, length and width.

[0124] Figure 24 is a top view of a device 300 similar to the device in Figure 23, formed according to the above description. In Figure 24, a first pair of fin elements 1041 and 1042 (2301) and a second pair of fin elements 1042 and 1041 (2302) are formed. Source / drain features 3211 and 3213 are formed and incorporated in each pair of 2301 and 2302. Similarly, source / drain features 3212 and 3214 are formed and incorporated in each pair of 2301 and 2302.

[0125] As shown, the first CPODE insulation feature 10021 extends across the pair 2301 of fin elements 1041 and 1042, and the second CPODE insulation feature 10022 extends across the pair 2302 of fin elements 1041 and 1042. Furthermore, in each pair 2301 and 2302, the CPODE insulation feature 1002 separates the combined source / drain features 3211 / 3213 from the combined source / drain features 3212 / 3214.

[0126] In addition, the first source / drain contact 1011 is in contact with the combined source / drain features 3211 / 3213 of each pair of 2301 and 2302, and the second source / drain contact 1012 is in contact with the combined source / drain features 3212 / 3214 of each pair of 2302 and 2301.

[0127] As described above, contacts 1011 and 1012 are configured to be electrically connected to form a TVS device in parallel with the functional circuit.

[0128] It should be noted that CPODE insulation features 10021 and 10022 in Figure 24 have the same constant depth and width.

[0129] Figure 25 shows the current-voltage diagram of device 300 in Figures 23 and 24. In the embodiments of Figures 23 and 24, two CPODE-based TVS devices are provided in parallel. The parallel devices have a maximum voltage Ip, which is greater than the maximum current Is of a single CPODE-based TVS device of the same structure. In some embodiments, Ip is twice Is.

[0130] Figure 26 is a top view of a device 300 similar to the device in Figure 23, formed according to the above description. In Figure 26, a first pair of fin elements 1041 and 1042 (2301) and a second pair of fin elements 1042 and 1041 (2302) are formed. Source / drain features 3211 and 3213 are formed and incorporated in each pair of 2301 and 2302. Similarly, source / drain features 3212 and 3214 are formed and incorporated in each pair of 2301 and 2302.

[0131] As shown, a single CPODE insulation feature 1002 extends across each pair 2301 and 2031 of fin elements 1041 and 1042. Furthermore, in each pair 2301 and 2302, the CPODE insulation feature 1002 separates the combined source / drain features 3211 / 3213 from the combined source / drain features 3212 / 3214.

[0132] In the embodiment shown in Figure 26, the first source / drain contact 1011 contacts the combined source / drain features 3211 / 3213 of each pair of 2301 and 2302, and the second source / drain contact 1012 contacts the combined source / drain features 3212 / 3214 of each pair of 2302 and 2301. In other words, each pair of 2301 and 2302 has source / drain contacts 1011 and source / drain contacts 1012. Therefore, the device 300 includes two contacts 1011 and two contacts 1012.

[0133] As described above, contacts 1011 and 1012 are configured to be electrically connected to form a TVS device in parallel with the functional circuit.

[0134] It should be noted that the CPODE insulation features in Figure 23 have the same constant depth, length and width.

[0135] Figure 27 is a top view of a device 300 similar to the device in Figure 24, formed according to the above description. In Figure 27, a first pair of fin elements 1041 and 1042 (2301) and a second pair of fin elements 1042 and 1041 (2302) are formed. Source / drain features 3211 and 3213 are formed and incorporated in each pair of 2301 and 2302. Similarly, source / drain features 3212 and 3214 are formed and incorporated in each pair of 2301 and 2302.

[0136] As shown, the first CPODE insulation feature 10021 extends across the pair 2301 of fin elements 1041 and 1042, and the second CPODE insulation feature 10022 extends across the pair 2302 of fin elements 1041 and 1042. Furthermore, in each pair 2301 and 2302, the CPODE insulation feature 1002 separates the combined source / drain features 3211 / 3213 from the combined source / drain features 3212 / 3214.

[0137] In the embodiment shown in Figure 27, the first source / drain contact 1011 contacts the combined source / drain features 3211 / 3213 of each pair of 2301 and 2302, and the second source / drain contact 1012 contacts the combined source / drain features 3212 / 3214 of each pair of 2302 and 2301. In other words, each pair of 2301 and 2302 has source / drain contacts 1011 and source / drain contacts 1012. Therefore, the device 300 includes two contacts 1011 and two contacts 1012.

[0138] As described above, contacts 1011 and 1012 are configured to be electrically connected to form a TVS device in parallel with the functional circuit.

[0139] It should be noted that CPODE insulation features 10021 and 10022 in Figure 24 have the same constant depth and width.

[0140] Figure 28 shows the current-voltage diagram of device 300 in Figures 26 and 27. In the embodiments of Figures 26 and 27, the terminals of the parallel CPODE-based TVS devices in Figures 24 and 25 are separated to form independent devices. Therefore, as shown, the CPODE-based TVS devices in Figures 26 and 27 are independent but have the same maximum voltage Imax.

[0141] Figure 29 is a top view of a device 300 similar to the device in Figure 23, formed according to the above description. In Figure 29, a single CPODE insulating feature 1002 extends across pairs 2301 and 2031 of fin elements 1041 and 1042. Furthermore, in each pair 2301 and 2302, the CPODE insulating feature 1002 separates the merged source / drain features 3211 / 3213 from the merged source / drain features 3212 / 3214.

[0142] In Figure 29, the CPODE insulation feature 1002 can have the same constant depth, or it can be formed at different depths in different areas. As shown, the CPODE insulation feature 1002 has a width W11 in the area corresponding to 2301. Furthermore, the CPODE insulation feature 1002 has a width W12 in the area corresponding to 2302. As shown, the width W11 is greater than the width W12.

[0143] In some embodiments, the device may have the following width W11 to width W12 ratio: at least 1.05:1, at least 1.1:1, at least 1.2:1, at least 1.3:1, at least 1.4:1, at least 1.5:1, at least 1.6:1, at least 1.7:1, at least 1.8:1, at least 1.9:1, at least 2.0:1, at least 2.5:1, at least 3.0:1, at least 3.5:1, or at least 4.0:1.

[0144] In some embodiments, the device may have the following width W11 to width W12 ratio: up to 1.05:1, up to 1.1:1, up to 1.2:1, up to 1.3:1, up to 1.4:1, up to 1.5:1, up to 1.6:1, up to 1.7:1, up to 1.8:1, up to 1.9:1, up to 2.0:1, up to 2.5:1, up to 3.0:1, up to 3.5:1, up to 4.0:1, or up to 5.0:1.

[0145] In some embodiments, the device may have the following width W12 to width W11 ratio: at least 0.1:1, at least 0.2:1, at least 0.3:1, at least 0.4:1, at least 0.5:1, at least 0.6:1, at least 0.7:1, at least 0.8:1, at least 0.9:1 or at least 0.95:1.

[0146] In some embodiments, the device may have a width W12 to width W11 ratio of up to 0.1:1, up to 0.2:1, up to 0.3:1, up to 0.4:1, up to 0.5:1, up to 0.6:1, up to 0.7:1, up to 0.8:1, up to 0.9:1, or up to 0.95:1.

[0147] Therefore, Figure 29 illustrates that the CPODE insulation feature 1002 can be formed in different areas of the device 100 with different dimensions, such as different widths (and / or different depths). Thus, TVS devices with different breakdown voltages can be formed from the same CPODE insulation feature 1002.

[0148] Figure 30 is a top view of a device 300 similar to the device in Figure 24, formed according to the above description. In Figure 30, the first CPODE insulating feature 10021 extends across the pair 2301 of fin elements 1041 and 1042, and the second CPODE insulating feature 10022 extends across the pair 2302 of fin elements 1041 and 1042. Furthermore, in each pair 2301 and 2302, the CPODE insulating feature 1002 separates the combined source / drain features 3211 / 3213 from the combined source / drain features 3212 / 3214.

[0149] In Figure 30, the first CPODE insulation feature 10021 and the second CPODE insulation feature 10022 have the same depth or different depths. As shown, the first CPODE insulation feature 10021 has a width W11. Furthermore, the second CPODE insulation feature 10022 has a width W12. As shown, the width W11 is greater than the width W12. Therefore, Figure 30 illustrates that the two CPODE insulation features 10021 and 10022 can be formed in different areas of the device 100 with different dimensions, such as different widths (and / or different depths). Therefore, TVS devices with different breakdown voltages can be formed from the two CPODE insulation features 10021 and 10022.

[0150] Figure 31 is a current and voltage diagram of device 300 in Figures 29 and 30.

[0151] The TVS devices in Figures 29 and 30, formed around the CPODE insulation feature 1002 or 10022 (with a smaller width W2), have a smaller maximum voltage Vmax-1 and a smaller maximum current Imax-1. When configured in parallel, the combination of CPODE-based TVS devices has a larger maximum voltage Vmax-2 and a larger maximum current Imax-2.

[0152] Therefore, forming CPODE insulation features with different selected dimensions provides a tunable maximum permissible transient voltage range.

[0153] Figure 32 is a top view of a device 300 similar to the device in Figure 26, formed according to the above description.

[0154] In Figure 32, the CPODE insulation feature 1002 can have the same constant depth, or it can be formed at different depths in different regions. As shown, the CPODE insulation feature 1002 has a width W11 in the region corresponding to 2301. Furthermore, the CPODE insulation feature 1002 has a width W12 in the region corresponding to 2302. As shown, the width W11 is greater than the width W12. Therefore, Figure 32 illustrates that the CPODE insulation feature 1002 can be formed with different dimensions (such as different widths (and / or different depths)) in different regions of the device 100. Therefore, TVS devices with different breakdown voltages can be formed from the same CPODE insulation feature 1002.

[0155] Figure 33 is a top view of a device 300 similar to the device in Figure 27, formed according to the above description.

[0156] In Figure 33, the first CPUDE insulation feature 10021 and the second CPUDE insulation feature 10022 have the same depth or different depths. As shown, the first CPUDE insulation feature 10021 has a width W11. Furthermore, the second CPUDE insulation feature 10022 has a width W12. As shown, the width W11 is greater than the width W12. Therefore, Figure 33 illustrates that the two CPUDE insulation features 10021 and 10022 can be formed in different areas of the device 100 with different dimensions (such as different widths (and / or different depths)). Therefore, TVS devices with different breakdown voltages can be formed by the two CPUDE insulation features 10021 and 10022.

[0157] Figure 34 is a current-voltage diagram of device 300 in Figures 29 and 30. In the embodiments of Figures 32 and 33, the terminals of the parallel CPODE-based TVS devices are separated to form independent devices. Therefore, the CPODE-based TVS devices in Figures 32 and 33 are independent. Each CPODE-based TVS device has the same maximum current Imax. However, because the CPODE insulation features are formed with different dimensions, the CPODE-based TVS devices at 2301 and 2302 in both Figures 32 and 33 have different maximum voltages. Specifically, the CPODE-based TVS device with a CPODE insulation feature having a larger width W11 has a maximum voltage Vmax-2, and the CPODE-based TVS device with a CPODE insulation feature having a smaller width W12 has a maximum voltage Vmax-1 that is less than Vmax-2. This description shows that several independent CPODE-based devices with different maximum permissible transient voltages can be formed.

[0158] Figures 35 and 36 illustrate that the CPODE insulation feature 1002 does not need to be formed along a single linear direction, such as along the Y-Y' axis in Figure 1.

[0159] For example, in Figure 35, the CPODE insulation feature 1002 is formed having a first insulation feature segment 3601 and a second insulation feature segment 3602 interconnected by a third insulation feature segment 3603.

[0160] The first insulating feature segment 3601 extends in direction 610 and is located between the source / drain features 321.

[0161] The second insulating feature segment 3602 extends in direction 610, that is, parallel to the first insulating feature segment 3601. The second insulating feature segment 3602 is located between the source / drain feature 321.

[0162] The third insulating feature segment 3603 extends in direction 620 between the first insulating feature segment 3601 and the second insulating feature segment 3602. In some embodiments, direction 620 is perpendicular to direction 610.

[0163] The non-linear layout of the CPODE insulation feature 1002 allows for the formation of CPODE-based TVS devices in areas that are not aligned along linear directions. For example, as shown, a first circuit design area 3651 may be adjacent to a first insulation feature segment 3601 in direction 610, and a second circuit design area 3652 may be adjacent to a first insulation feature segment 3601 in direction 620.

[0164] In Figure 35, the uninterrupted single CPODE insulation feature 1002 includes segments 3601, 3602 and 3603.

[0165] Figure 36 illustrates an embodiment similar to Figure 35, but in which CPODE insulation feature 1002 includes an interruption. Specifically, segment 3601 is interrupted such that segment 3601 includes CPODE insulation features 10021 and CPODE insulation feature 10022.

[0166] As shown in Figures 35 and 36, a CPODE-based device can be formed with any of the above features, including the same or different CPODE insulation width and depth, dedicated or shared source / drain contacts, or other features, to provide a CPODE-based device with the desired characteristics.

[0167] Figure 37 illustrates method 3700. Method 3700 includes designing a functional integrated circuit at block 3702 that is electrically connected to the first node and the second node. In some embodiments, a plurality of functional integrated circuits are designed.

[0168] At block 3704, method 3700 includes determining the maximum voltage threshold value of each functional unit circuit.

[0169] At block 3706, method 3700 includes designing individual transient voltage suppressors as shunt paths between a first node and a second node of each circuit to release current having a voltage exceeding a maximum voltage threshold, wherein each shunt path passes through semiconductor material beneath an individual insulating feature having a selected width and a selected depth in a first direction from a first source / drain feature to a second source / drain feature.

[0170] Method 3700 can continue at block 3708, forming each first source / drain feature and a second source / drain feature above the semiconductor material, wherein each individual first source / drain feature is spaced apart from each individual second source / drain feature in a first direction.

[0171] Method 3700 can continue at block 3710, forming insulation features with individually selected widths and selected depths between the first and second source / drain features to define individual shunt paths.

[0172] Blocks 3708 and 3710 can be combined with blocks from method 200.

[0173] Therefore, various embodiments are described herein. In some embodiments, the two terminals are located on opposite sides of the CPODE structure and connected in parallel to the protected circuit. The CPODE dimensions (length / width / depth) can be used to tune the maximum permissible transient voltage / current.

[0174] In some embodiments, more than one CPODE-based TVS device can be connected in parallel with another (or a parallel one) device via a common (or different but of the same size) CPODE to increase the allowable transient current.

[0175] In some embodiments, the terminals of parallel CPODE-based TVS devices are spaced apart to form a plurality of independent CPCODE-based TVS devices having the same maximum permissible transient voltage.

[0176] In some embodiments, the CPODE sizes of the parallel CPODE-based TVS devices may differ, which allows for the formation of tunable permissible transient currents (in terms of the number of parallel units) for different permissible transient voltage ranges (in terms of CPODE size).

[0177] In some embodiments, the CPODE dimensions of the parallel CPODE-based TVS devices can be different to obtain the desired maximum permissible transient voltage.

[0178] In some embodiments, the CPODE shape may be vertical or any other arbitrary shape, such as Z-shaped, depending on the wafer layout.

[0179] In one embodiment of this document, a method includes: forming a first source / drain feature and a second source / drain feature over a substrate, wherein the first source / drain feature and the second source / drain feature are separated by a gate structure; removing the gate structure to form a trench; forming an insulating feature in the trench; and forming a functional circuit over the substrate, wherein a shunt path connected in parallel with the functional circuit is defined below the insulating feature and between the first source / drain feature and the second source / drain feature.

[0180] In some embodiments of the method, a first source / drain feature and a second source / drain feature define a first axis; the method further includes forming a third source / drain feature and a fourth source / drain feature separated by a gate structure; and the third source / drain feature and the fourth source / drain feature define a second axis parallel to the first axis.

[0181] In some embodiments of the method, the shunt path is defined below the insulation feature, between the first source / drain feature and the second source / drain feature, and between the third source / drain feature and the fourth source / drain feature.

[0182] In some embodiments of the method, the functional circuit is a first functional circuit; the method includes forming a second functional circuit above a substrate; and defining a second shunt path connected in parallel with the second functional circuit below an insulating feature and between a third source / drain feature and a fourth source / drain feature.

[0183] In another embodiment, a method includes: designing a functional integrated circuit electrically connected to a first node and a second node; determining a maximum voltage threshold or a maximum current threshold of the functional integrated circuit; designing a transient voltage suppressor as a shunt path between the first node and the second node to release current exceeding the maximum current threshold and / or having a voltage exceeding the maximum voltage threshold, wherein the shunt path passes through a semiconductor material beneath an insulating feature from a first source / drain feature to a second source / drain feature, the insulating feature having a selected width and a selected depth in a first direction; forming the first source / drain feature and the second source / drain feature above the semiconductor material, wherein the first source / drain feature is spaced apart from the second source / drain feature in the first direction; and forming an insulating feature between the first source / drain feature and the second source / drain feature with a selected width and a selected depth to define the shunt path.

[0184] In some embodiments of the method, the shunt path is a first shunt path that transmits current from the first source / drain feature to the second source / drain feature; the transient voltage suppressor includes a first shunt path and a second shunt path between the first node and the second node, wherein the second shunt path transmits current from the third source / drain feature to the fourth source / drain feature through the semiconductor material below the insulating feature; the method further includes forming the third source / drain feature and the fourth source / drain feature above the semiconductor material, wherein the third source / drain feature is spaced apart from the fourth source / drain feature in a first direction; and forming the insulating feature includes forming an insulating feature between the third source / drain feature and the fourth source / drain feature.

[0185] In some embodiments of the method, the functional integrated circuit is a first functional integrated circuit; the transient voltage suppressor is a first transient voltage suppressor; and the method further includes: designing a second functional integrated circuit electrically connected to a third node and a fourth node; determining a second maximum voltage threshold value for the second functional integrated circuit; designing the second transient voltage suppressor as a second shunt path between the third node and the fourth node to release a second current having a second voltage exceeding the second maximum voltage threshold value, wherein the second shunt path passes through semiconductor material below an insulating feature from a third source / drain feature to a fourth source / drain feature, the insulating feature having a selected width and a selected depth in a first direction; forming a third source / drain feature and a fourth source / drain feature above the semiconductor material, wherein the third source / drain feature is spaced apart from the fourth source / drain feature in the first direction; and forming an insulating feature between the third source / drain feature and the fourth source / drain feature with a second selected width and a second selected depth to define the second shunt path.

[0186] In some embodiments of the method, the insulation feature includes a first segment between the first source / drain feature and the second source / drain feature; the functional integrated circuit is a first functional integrated circuit; the transient voltage suppressor is a first transient voltage suppressor; and the method further includes: designing a second functional integrated circuit electrically connected to the third node and the fourth node; determining a second maximum voltage threshold value of the second functional integrated circuit; designing the second transient voltage suppressor as a second shunt path between the third node and the fourth node to release a second current having a second voltage exceeding the second maximum voltage threshold value, wherein the second The shunt path passes through the semiconductor material below the second segment of the insulating feature, transferring from the third source / drain feature to the fourth source / drain feature. The insulating feature has a second selected width and a second selected depth in a first direction. The third source / drain feature and the fourth source / drain feature are formed above the semiconductor material, wherein the third source / drain feature is spaced apart from the fourth source / drain feature in the first direction. A second segment of the insulating feature is formed between the third source / drain feature and the fourth source / drain feature with a second selected width and a second selected depth to define the second shunt path.

[0187] In some embodiments of the method, the insulation feature includes a first segment between the first source / drain feature and the second source / drain feature; the functional integrated circuit is a first functional integrated circuit; the transient voltage suppressor is a first transient voltage suppressor; and the method further includes: designing a second functional integrated circuit electrically connected to the third node and the fourth node; determining a second maximum voltage threshold value of the second functional integrated circuit; designing the second transient voltage suppressor as a second shunt path between the third node and the fourth node to release a second current having a second voltage exceeding the second maximum voltage threshold value, wherein the second The shunt path passes through the semiconductor material below the second segment of the insulating feature, transferring from the third source / drain feature to the fourth source / drain feature; the third source / drain feature and the fourth source / drain feature are formed above the semiconductor material, wherein the third source / drain feature is spaced apart from the fourth source / drain feature in a first direction; and the second segment of the insulating feature is formed between the third source / drain feature and the fourth source / drain feature, and the third segment of the insulating feature is formed, wherein the third segment is perpendicular to the first segment and the second segment, and wherein the third segment interconnects the first segment and the second segment.

[0188] In another embodiment, a semiconductor device is provided, comprising: a first source / drain feature of a first dopant type formed in a substrate of a second dopant type opposite to the first dopant type; a second source / drain feature of the first dopant type formed in the substrate; an insulating feature located between the first source / drain feature and the second source / drain feature and extending toward the substrate to a selected depth; a first contact electrically connected to the first source / drain feature and a first node; a second contact electrically connected to the second source / drain feature and a second node; a functional circuit formed above the substrate; and a voltage discharge circuit extending below the insulating feature and between the first source / drain feature and the second source / drain feature, wherein the voltage discharge circuit is connected in parallel with the functional circuit.

[0189] In some embodiments, the apparatus further includes: a first shallow trench isolation (STI) feature; and a second shallow trench isolation (STI) feature; wherein the first source / drain feature is located between the first STI feature and the insulating feature; and the second source / drain feature is located between the second STI feature and the insulating feature.

[0190] In some embodiments, the device further includes: a first poly on oxide definition edge (PODE) structure; and a second poly on oxide definition edge (PODE) structure; wherein the insulating feature is a continuous poly on oxide definition edge (CPODE) structure; a first source / drain feature is located between the first PODE feature and the CPODE feature; and a second source / drain feature is located between the second PODE feature and the CPODE feature.

[0191] In some embodiments, the device further includes: a first continuous poly on oxide definition edge (CPODE) structure; and a second continuous poly on oxide definition edge (CPODE) structure; wherein the insulating feature is a central continuous poly on oxide definition edge (CPODE) structure; a first source / drain feature is located between the first CPODE feature and the central CPODE feature; and a second source / drain feature is located between the second CPODE feature and the central CPODE feature.

[0192] In some embodiments, the apparatus further includes: a first floating virtual gate; and a second floating virtual gate; wherein the first source / drain feature is located between the first floating virtual gate and the insulation feature; and the second source / drain feature is located between the second floating virtual gate and the insulation feature.

[0193] In some embodiments of the device, a first source / drain feature and a second source / drain feature are spaced apart from each other in a first direction and define a first axis; the semiconductor device further includes a third source / drain feature and a fourth source / drain feature, the third source / drain feature and the fourth source / drain feature being spaced apart from each other in the first direction and defined on a second axis spaced apart from the first axis in a second direction perpendicular to the first direction; a first contact is electrically connected to the third source / drain feature; a second contact is electrically connected to the fourth source / drain feature; and an insulating feature is located between the third source / drain feature and the fourth source / drain feature.

[0194] In some embodiments of the device, the first source / drain feature and the third source / drain feature are combined together; and the second source / drain feature and the fourth source / drain feature are combined together.

[0195] In some embodiments of the device, the first source / drain feature and the third source / drain feature are spaced apart from each other; and the second source / drain feature and the fourth source / drain feature are spaced apart from each other.

[0196] In some embodiments of the device, a first source / drain feature and a second source / drain feature are spaced apart from each other in a first direction and define a first axis; the semiconductor device further includes a third source / drain feature and a fourth source / drain feature, which are spaced apart from each other in the first direction and define a second axis spaced apart from the first axis in a second direction perpendicular to the first direction; an insulating feature is a first insulating feature; and the semiconductor device further includes a second insulating feature located between the third source / drain feature and the fourth source / drain feature and extending toward the substrate to a second selected depth.

[0197] In some embodiments of the device, a first source / drain feature and a second source / drain feature are spaced apart from each other in a first direction and define a first axis; the semiconductor device further includes a third source / drain feature and a fourth source / drain feature, the third source / drain feature and the fourth source / drain feature being spaced apart from each other in a first direction and defining a second axis parallel to the first axis; the insulating feature includes a first insulating feature segment and a second insulating feature segment; the first insulating feature segment has a first width in the first direction; the second insulating feature segment has a second width in the first direction; the first insulating feature segment is located between the first source / drain feature and the second source / drain feature; and the second insulating feature segment is located between the third source / drain feature and the fourth source / drain feature.

[0198] In some embodiments of the device, a first source / drain feature and a second source / drain feature are spaced apart from each other in a first direction and define a first axis; the semiconductor device further includes a third source / drain feature and a fourth source / drain feature, the third source / drain feature and the fourth source / drain feature being spaced apart from each other in the first direction and defined on a second axis spaced apart from the first axis in a second direction perpendicular to the first direction; an insulating feature includes a first insulating feature segment and a second insulating feature segment interconnected by a third insulating feature segment; the first insulating feature segment extends in the second direction and is located between the first source / drain feature and the second source / drain feature; the second insulating feature segment extends in the second direction and is located between the third source / drain feature and the fourth source / drain feature; and the third insulating feature segment extends in the first direction between the first insulating feature segment and the second insulating feature segment.

[0199] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0200] 100: Semiconductor devices 103:End 104: Fin element 105: Source / Drain Characteristics 107: Source / Drain Characteristics 200: Method 202: Block 204: Block 206: Block 208: Block 210: Block 212: Block 214: Block 216: Block 218: Block 220: Block 300: Semiconductor Devices 302:Substrate 302A: Substrate portion 303: First Active Zone 304: Fins 305: Second Active Zone 306: Channel layer of semiconductor nanosheet 307: Active Edge 309: First GAA device 310: Gate dielectric layer 311: Second GAA device 312: Metal layer / gate electrode material 313: Virtual GAA Structure / Sacrificial Gate Structure 315: Sidewall spacers 317: STI Characteristics 319: Internal spacers 321: Source / Drain Characteristics 323: Dielectric 325: Gate cover layer / hard shield layer / gate cover 327: Dielectric Pad 329: Metal layer 331: Material layer 333: Dielectric layer 350: Trench 355: Cutting the metal gate region 402: Dielectric layer 502: Patterned resist layer 504: Opening 506: CPODE area 604: Opening 610: Direction 620: Direction 704: Opening 804: Opening 904: Trench 906: Extension Section 911: First Node 912: Second Node 1002:CPODE insulation characteristics 1003: Horizontal bottom plane 1004: Horizontal upper plane 1008: Plane 1011: Source / Drain Contact 1012: Source / Drain Contact 1041: First fin / fin element 1042: Second fin / fin element 1100: Diversion Path / TVS Device 1109: Plane 1200: Functional Circuit 1300: Ground 1400: Voltage source 1401: First N / P Junction 1402: Second N / P junction 1500: PODE insulation structure 1600:CPODE insulation characteristics 1608: Plane 1700: Floating Virtual Gate 2301: Fin element pair 2302: Fin element pair 3211: Source / Drain Characteristics 3212: Source / Drain Characteristics 3213: Source / Drain Characteristics 3214: Source / Drain Characteristics 3218: Horizontal bottom plane 3219: Horizontal upper plane 3311: Source / Drain Characteristics 3312: Draining pole / Draining pole characteristics 3313: Source / Drain Characteristics 3314: Source / Drain Characteristics 3601: First Insulation Characteristic Section 3602: Second insulation characteristic section 3603: Third Insulation Characteristic Section 3651: First Circuit Design Area 3652: Second Circuit Design Area 3700: Method 3702: Block 3704: Block 3706: Block 3708: Block 3710: Block 10021: First CPODE insulation characteristic 10022: Second CPODE insulation characteristic B-B': Plane D1: Depth D2: Depth D3: Depth D4: Depth H1: Height I: Current Imax: Maximum current Imax-1: Maximum current Imax-2: Maximum current Ip: Maximum voltage Is: Maximum Current V: Voltage Vmax-1: Maximum voltage Vmax-2: Maximum voltage Vp: Breakdown voltage W1: Width W2: Width W3: Width W11: Width W12: Width X-X': Cross section Y-Y': Cross section

[0201] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: forming a first source / drain feature and a second source / drain feature on a substrate, wherein the first source / drain feature and the second source / drain feature are separated by a first gate structure; forming a third source / drain feature and a fourth source / drain feature on the substrate, wherein the third source / drain feature and the fourth source / drain feature are separated by a second gate structure; removing the first gate structure and the second gate structure to form a first trench and a second trench respectively; forming a first insulating feature and a second insulating feature in the first trench and the second trench respectively; A first functional circuit is formed above the substrate, wherein a first shunt path connected in parallel with the first functional circuit is defined below the first insulating feature and between the first source / drain feature and the second source / drain feature; and a second functional circuit is formed above the substrate, wherein a second shunt path connected in parallel with the second functional circuit is defined below the second insulating feature and between the third source / drain feature and the fourth source / drain feature.

2. A method for manufacturing a semiconductor device as described in claim 1, wherein: The first source / drain feature and the second source / drain feature define a first axis; and the third source / drain feature and the fourth source / drain feature define a second axis parallel to the first axis.

3. A method of manufacturing a semiconductor device, comprising the steps of: designing a functional integrated circuit electrically connected to a first node and a second node; determining a maximum voltage threshold or a maximum current threshold of the functional integrated circuit; designing a transient voltage suppressor as a shunt path between the first node and the second node to release a current exceeding the maximum current threshold and / or having a voltage exceeding the maximum voltage threshold, wherein the shunt path passes through a semiconductor material beneath an insulating feature from a first source / drain feature to a second source / drain feature, the insulating feature having a selected width and a selected depth in a first direction; forming the first source / drain feature and the second source / drain feature above the semiconductor material, wherein the first source / drain feature is spaced apart from the second source / drain feature in the first direction; and forming the insulating feature between the first source / drain feature and the second source / drain feature with the selected width and the selected depth to define the shunt path.

4. A method for manufacturing a semiconductor device as described in claim 3, wherein: The shunt path is a first shunt path that transmits current from the first source / drain feature to the second source / drain feature; the transient voltage suppressor includes the first shunt path and a second shunt path between the first node and the second node, wherein the second shunt path transmits current from a third source / drain feature to a fourth source / drain feature through the semiconductor material below the insulating feature; the method further includes the step of forming the third source / drain feature and the fourth source / drain feature above the semiconductor material, wherein the third source / drain feature is spaced apart from the fourth source / drain feature in the first direction; and the step of forming the insulating feature includes the step of forming the insulating feature between the third source / drain feature and the fourth source / drain feature.

5. A method for manufacturing a semiconductor device as described in claim 3, wherein: The functional integrated circuit is a first functional integrated circuit; the transient voltage suppressor is a first transient voltage suppressor; and the method further includes the following steps: designing a second functional integrated circuit electrically connected to a third node and a fourth node; determining a second maximum voltage threshold value of the second functional integrated circuit; designing a second transient voltage suppressor as a second shunt path between the third node and the fourth node to release a second current having a second voltage exceeding the second maximum voltage threshold value, wherein the second shunt path passes through the semiconductor material below the insulating feature from a third source / drain feature to a fourth source / drain feature, the insulating feature having a selected width and a selected depth in the first direction; The third source / drain feature and the fourth source / drain feature are formed above the semiconductor material, wherein the third source / drain feature is spaced apart from the fourth source / drain feature in the first direction; and the insulating feature is formed between the third source / drain feature and the fourth source / drain feature with a second selected width and a second selected depth to define the second shunt path.

6. A method of manufacturing a semiconductor device as claimed in claim 3, wherein the insulating feature includes a first segment between the first source / drain feature and the second source / drain feature; the functional integrated circuit is a first functional integrated circuit; the transient voltage suppressor is a first transient voltage suppressor; and the method further includes the steps of: designing a second functional integrated circuit electrically connected to a third node and a fourth node; determining a second maximum voltage threshold of the second functional integrated circuit; designing a second transient voltage suppressor as a second shunt path between the third node and the fourth node to release a second current having a second voltage exceeding the second maximum voltage threshold, wherein the second shunt path passes through the semiconductor material below the second segment of the insulating feature from a third source / drain feature to a fourth source / drain feature, the insulating feature having a second selected width and a second selected depth in the first direction; The third source / drain feature and the fourth source / drain feature are formed above the semiconductor material, wherein the third source / drain feature is spaced apart from the fourth source / drain feature in the first direction; and the second segment of the insulating feature is formed between the third source / drain feature and the fourth source / drain feature with the second selected width and the second selected depth to define the second shunt path.

7. A semiconductor device comprising: a first source / drain feature of a first dopant type formed in a substrate of a second dopant type opposite to the first dopant type; a second source / drain feature of the first dopant type formed in the substrate; an insulating feature located between the first source / drain feature and the second source / drain feature and extending toward the substrate to a selected depth; a first contact electrically connected to the first source / drain feature and a first node; a second contact electrically connected to the second source / drain feature and a second node; a functional circuit formed above the substrate; and a voltage discharge circuit extending below the insulating feature and between the first source / drain feature and the second source / drain feature, wherein the voltage discharge circuit is connected in parallel with the functional circuit.

8. The semiconductor device as claimed in claim 7, further comprising: a first shallow trench isolation feature; and a second shallow trench isolation feature; wherein: The first source / drain feature is located between the first shallow trench isolation feature and the insulation feature; and the second source / drain feature is located between the second shallow trench isolation feature and the insulation feature.

9. The semiconductor device as claimed in claim 7, further comprising: a first polysilicon-on-oxide (PSO) defining edge structure; and a second PSO defining edge structure; wherein: The insulating feature is a continuous oxide-polysilicon-defined edge structure; the first source / drain feature is located between the first oxide-polysilicon-defined edge structure and the continuous oxide-polysilicon-defined edge structure; and the second source / drain feature is located between the second oxide-polysilicon-defined edge structure and the continuous oxide-polysilicon-defined edge structure.

10. The semiconductor device as claimed in claim 7, further comprising: a first continuous oxide-on-polysilicon defining edge structure; and a second continuous oxide-on-polysilicon defining edge structure; wherein: The insulating feature is a central continuous oxide-polysilicon-defined edge structure; the first source / drain feature is located between the first continuous oxide-polysilicon-defined edge structure and the central continuous oxide-polysilicon-defined edge structure; and the second source / drain feature is located between the second continuous oxide-polysilicon-defined edge structure and the central continuous oxide-polysilicon-defined edge structure.

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