Analog to digital conversion device and analog to digital conversion method

Abstract

The analog-to-digital converter includes a slope signal generator and a comparator. The slope signal generator generates a slope signal based on a first current source in a first sub-voltage range of the voltage range, and generates a slope signal based on a second current source in a second sub-voltage range of the voltage range, wherein the slope signal rises and falls back within the voltage range with at least one slope. The comparator generates an output signal based on the slope signal and an input signal.

Description

Technical Field

[0001] This case relates to analog-to-digital conversion devices and methods, particularly to analog-to-digital conversion devices and methods that can improve the nonlinearity of the current source of a slope signal generator. Prior Technology

[0002] Analog-to-digital converters (ADCs) are commonly used in electronic devices to convert analog signals into digital signals that the device can process. A time-interleaved slope ADC is one type of ADC. The slope generator of a time-interleaved slope ADC typically uses a metal-oxide-semiconductor (MOSFET) as its current source. Due to channel length modulation and short channel effects, the current provided by this current source is related to VSD (source-drain voltage). Taking a PMOS (P-type MOSFET) current source as an example, the higher the slope signal, the smaller the VSD and the smaller the current |IDS|. The formula for the slope signal is as follows:

[0003] …Formula 1

[0004] In Formula 1, The slope signal For current, For time, This is the capacitance value. Assuming time... With capacitance value If the current is fixed, Not a fixed value, current If it changes with VSD, the slope signal It is not a charging curve with a fixed slope; it incorporates nonlinear components. Summary of the Invention

[0005] In view of the shortcomings of prior art, one of the objectives of this application is (but not limited to) to provide an analog-to-digital conversion device and an analog-to-digital conversion method to improve the shortcomings of prior art.

[0006] In some embodiments, the analog-to-digital converter includes a slope signal generator and a comparator. The slope signal generator generates a slope signal based on a first current source in a first sub-voltage range of the voltage range, and generates a slope signal based on a second current source in a second sub-voltage range of the voltage range, wherein the slope signal rises and falls back within the voltage range with at least one slope. The comparator generates an output signal based on the slope signal and an input signal.

[0007] In some implementations, the analog-to-digital conversion method includes: generating a slope signal in a first sub-voltage range of a voltage range based on a first current source using a slope signal generator, and generating a slope signal in a second sub-voltage range of the voltage range based on a second current source, wherein the slope signal rises and falls back and forth in the voltage range with at least one slope; and generating an output signal using a comparator based on the slope signal and an input signal.

[0008] The technical means embodied in the embodiments of this invention can improve at least one of the shortcomings of the prior art. The analog-to-digital conversion device and analog-to-digital conversion method of this invention can improve the nonlinearity of the current source of the slope signal generator.

[0009] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Simple Explanation of the Diagram

[0010] Figure 1 is a schematic diagram of an analog-to-digital converter according to some embodiments of this invention; Figure 2 is a flowchart illustrating an analog digit conversion method based on some embodiments of this case; Figure 3 is a timing diagram of an analog-to-digital converter based on some embodiments of this invention. Figure 4 is a schematic diagram of a current source according to some embodiments of this case; Figure 5 is a schematic diagram of the current and voltage of a slope signal generator according to some embodiments of this case; and Figure 6 is a schematic diagram of a current source based on some embodiments of this case. Implementation

[0011] All terms used herein have their common meanings. The definitions of the terms mentioned above in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0012] As used herein, "coupling" or "connection" can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used herein, the term "circuit" can refer to a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.

[0013] As used herein, the term "and / or" includes any combination of one or more of the listed related items. In this document, the terms first, second, third, etc., are used to describe and distinguish individual elements. Therefore, a first element in this document may also be referred to as a second element without departing from the intent of this case. For ease of understanding, similar elements in the various diagrams will be assigned the same reference numerals.

[0014] To improve the nonlinearity of slope signals in prior art, this invention proposes an analog-to-digital converter and an analog-to-digital converter method, which are described in detail below.

[0015] Figure 1 is a schematic diagram of an analog-to-digital converter 100 according to some embodiments of this invention. As shown, the analog-to-digital converter 100 includes a slope signal generator 110, a comparator 120, a capacitor Cs3, and a flip-flop DFFN.

[0016] In some embodiments, the analog-to-digital converter 100 may be, but is not limited to, a time-interlaced slope analog-to-digital converter, the operation of which is described below. The analog-to-digital converter 100 may sample the input signal using capacitor Cs3, and then comparator 120 compares the sampled signal with the slope signal Vslope generated by slope signal generator 110. Before comparator 120 generates a comparison result, the counter value Dcnt[3:0] continues to count until comparator 120 generates a comparison result. When the positive terminal of comparator 120 is greater than the negative terminal, the output signal cmpN generated by comparator 120 changes from negative to positive. The rising edge of the output signal cmpN changing from negative to positive triggers flip-flop DFFN, which stores the current counting result Dcnt[3:0] and subsequently outputs the data signal D[3:0]. As described above, the analog-to-digital converter 100 completes one conversion process.

[0017] To illustrate how the analog-to-digital converter 100 of this invention improves the nonlinearity of the slope signal Vslope, please refer to Figures 2 and 3. Figure 2 is a flowchart illustrating an analog-to-digital converter method 200 according to some embodiments of this invention. Figure 3 is a timing diagram illustrating an analog-to-digital converter 100 according to some embodiments of this invention.

[0018] Please refer to step 210 in Figure 2. A slope signal generator generates a slope signal in the first sub-voltage interval of the voltage range based on a first current source, and in the second sub-voltage interval of the voltage range based on a second current source. The slope signal rises and falls back and forth within the voltage range with at least one slope. For example, referring to Figures 1 and 3, the slope signal generator 110 generates a slope signal Vslope (as shown by the dashed line portion of the slope signal Vslope) in the first sub-voltage interval Vr1 of the voltage range Vr based on the first current source CS1, and in the second sub-voltage interval Vr2 of the voltage range Vr based on the second current source CS2 (as shown by the solid line portion of the slope signal Vslope). This slope signal Vslope rises with one slope and falls with another slope within the voltage range Vr, completing one round of rise and fall, and the slope signal Vslope rises and falls back and forth repeatedly within the voltage range Vr.

[0019] Please refer to step 220 in Figure 2, where the comparator generates an output signal based on the slope signal and the input signal. For example, referring to Figures 1 and 3, with the input signal Vi,1 as an example, comparator 120 generates an output signal cmp1 based on the slope signal Vslope and the input signal Vi,1.

[0020] In some embodiments, the voltage range Vr includes a low voltage level V1 and a high voltage level V3, and at least one slope of the slope signal Vslope includes a positive slope and a negative slope. The slope signal Vslope rises from the low voltage level V1 to the high voltage level V3 with a positive slope, and then falls from the high voltage level V3 to the low voltage level V1 with a negative slope.

[0021] In some embodiments, the first sub-voltage interval Vr1 includes a low voltage level V1, the boundary between the first sub-voltage interval Vr1 and the second sub-voltage interval Vr2 includes an intermediate voltage level V2, and at least one slope of the slope signal Vslope includes a positive slope and a negative slope. During a first period A1, the slope signal Vslope is raised from the low voltage level V1 to the intermediate voltage level V2 with a positive slope according to the first current source CS1 (as shown by the dashed line portion of the slope signal Vslope).

[0022] In some embodiments, the second sub-voltage range Vr2 includes a high voltage level V3. During the second period A2, the slope signal Vslope is raised from the intermediate voltage level V2 to the high voltage level V3 with a positive slope according to the second current source CS2 (as shown by the solid line portion of the slope signal Vslope).

[0023] In some embodiments, the slope signal Vslope decreases from a high voltage level V3 to an intermediate voltage level V2 with a negative slope during a third period A3, based on a second current source CS2 (as shown by the solid line portion of the slope signal Vslope). In another embodiment, the slope signal Vslope decreases from an intermediate voltage level V2 to a low voltage level V1 with a negative slope during a fourth period A4, based on a first current source CS1 (as shown by the dashed line portion of the slope signal Vslope). In some embodiments, the first period A1, the second period A2, the third period A3, and the fourth period A4 are executed sequentially.

[0024] In some embodiments, referring to FIG1, the slope signal generator 110 includes a first current source CS1, an output terminal Out, a first switch SW1, and a second switch SW2. In some embodiments, the first current source CS1 may be implemented by a transistor. The first switch SW1 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the first switch SW1 is coupled to the first current source CS1. The second terminal (as shown below) of the first switch SW1 is coupled to the output terminal Out. The second switch SW2 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the second switch SW2 is coupled to the output terminal Out. The second terminal (as shown below) of the second switch SW2 is used to receive the low voltage level V1 shown in FIG3. The first switch SW1 and the second switch SW2 output a slope signal Vslope according to a first control signal Scon1 and a reset signal Sre. In some embodiments, the timing diagram of the first control signal Scon1 and the reset signal Sre is shown in FIG1. However, this case is not limited to the above embodiments, which are only used to illustrate one of the implementation methods of this case. Other suitable circuit architectures and timings may also be used, depending on the actual needs.

[0025] In some embodiments, referring to FIG1, the slope signal generator 110 includes a second current source CS2 and a third switch SW3. In some embodiments, the second current source CS2 may be implemented by a transistor. The third switch SW3 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the third switch SW3 is coupled to the second current source CS2. The second terminal (as shown below) of the third switch SW3 is coupled to the output terminal Out. The third switch SW3 outputs a slope signal Vslope according to a second control signal Scon2. In some embodiments, the timing diagram of the second control signal Scon2 is shown in FIG1. ​​However, this invention is not limited to the above embodiments, which are only used to illustrate one implementation method of this invention. Other suitable circuit architectures and timings may also be used, depending on actual needs.

[0026] In some embodiments, referring to Figure 3, the first sub-voltage interval Vr1 and the second sub-voltage interval Vr2 do not overlap. For example, the first sub-voltage interval Vr1 includes a low voltage level V1 and an intermediate voltage level V2. Furthermore, the second sub-voltage interval Vr2 includes an intermediate voltage level V2 and a high voltage level V3. In this embodiment, the upper limit voltage level of the first sub-voltage interval Vr1 (e.g., the intermediate voltage level V2) is the same as the lower limit voltage level of the second sub-voltage interval Vr2 (e.g., the intermediate voltage level V2). Therefore, the first sub-voltage interval Vr1 and the second sub-voltage interval Vr2 do not overlap. For example, the aforementioned intermediate voltage level V2 can be taken as the midpoint between the low voltage level V1 and the high voltage level V3, and the formula for voltage level V2 is as follows:

[0027] …Formula 2

[0028] However, the intermediate voltage level V2 in this case is not limited to the above embodiment, and other suitable values ​​can be adopted depending on actual needs.

[0029] Figure 4 is a schematic diagram of the current sources of the slope signal generator 110 shown in Figure 1, according to some embodiments of this invention. The current sources CS1 and CS2 of the slope signal generator 110 in Figure 1 can be implemented using metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, referring to Figure 4, the current source CS1 or CS2 of the slope signal generator 110 can be a current source CSA implemented by MOSFETs M1 and M2, or the current source CS1 or CS2 of the slope signal generator 110 can be a current source CSB implemented by MOSFETs M3 to M6. In some embodiments, the slope signal Vslope of this invention is not limited to a rising slope or a falling slope. If the slope signal Vslope is a falling slope, an NMOS (N-type metal-oxide-semiconductor field-effect transistor) can be used as the current source.

[0030] Figure 5 is a schematic diagram of the current and voltage of the slope signal generator 110 shown in Figure 1, based on some embodiments of this invention. As shown in the figure, if only a single current source is used, the current Ib will generate a current difference ΔI1' due to the change in VDS (source voltage). Furthermore, if divided into periods C1 and C2, period C1 generates a current difference ΔI1 from one current source, and period C2 generates a current difference ΔI2 from another current source. As can be seen from the figure, the total current difference generated by the two current sources is the sum of the current difference ΔI1 and the current difference ΔI2. This total current difference (ΔI1 + ΔI2) is less than the current difference ΔI1' generated by a single current source. Therefore, the analog-to-digital converter 100 of this invention can reduce the aforementioned current difference by using two current sources, thereby improving the nonlinearity of the current source of the slope signal generator 110.

[0031] For example, the current Ib in Figure 5 can be provided by the current source CSB in Figure 4. The current source CSB is a cascode current source. The current source CSB requires a large |VDS| to operate in the saturation region and has a slight channel length modulation effect, therefore, the slope is gentler. The current Ia in Figure 5 can be provided by the current source CSA in Figure 4. The current source CSA is a simple current source with a more obvious channel length modulation effect, therefore, the slope is steeper, but it only requires a small |VDS| to operate in the saturation region. Furthermore, the currents Ia and Ib in Figure 5 can also be provided by the current sources CSC and CSD in Figure 6. In this case, metal-oxide-semiconductor field-effect transistors M2 and M4 of the current sources CSC and CSD can be designed to have different Vsg (source-gate voltage) and different W / L (width-to-length ratio) to provide currents Ia and Ib. Among them, Vsg1 of the current source CSC is not equal to Vsg2 of the current source CSD, and (W / L)2 of the current source CSC is not equal to (W / L)4 of the current source CSD.

[0032] It should be noted that this application is not limited to the embodiments shown in Figures 1 to 6, but is merely used to illustrate one implementation method of this application to facilitate understanding of the technology. The scope of this application shall be determined by the scope of the invention application. Modifications and refinements made by those skilled in the art to the embodiments of this application without departing from the spirit of this application still fall within the scope of the invention application.

[0033] In summary, the technical means embodied in the embodiments of this invention can improve at least one of the shortcomings of the prior art. The analog-to-digital conversion device and analog-to-digital conversion method of this invention can improve the nonlinearity of the current source of the slope signal generator.

[0034] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0035] 100: Analog-to-digital converter 110: Slope signal generator 120: Comparator 200: Method 210~220: Steps A1~A4: Period C1, C2: Period CS1: First current source CS2: Second current source Cs3: Capacitor CSA, CSB, CSC, CSD: Current Source cmpN: Output signal DFFN: Flip-Flipper D[3:0]: Data signal Dcnt[3:0]: Count value D1~DN: Data signals Dout: Data signal Ia, Ib: Current Id1, Id2: Current Iref: Current M1~M6: Metal-Oxide-Semiconductor Field-Effect Transistors P1~P4: Points Out: Output terminal SW1: First switch SW2: Second switch SW3: Third switch Scon1: First control signal Scon2: Second control signal Sre: Reset signal T1~T3: Period Vslope: Slope signal Vi,1, Vi,2, Vi,N, Vi,p, Vi,n: input signal VDD: Current source supply voltage Vref: Reference voltage V1~V3: Voltage Levels Vr: Voltage range Vr1: First sub-voltage range Vr2: Second sub-voltage range ΔI1, ΔI1', ΔI2: Current difference

Claims

1. An analog-to-digital converter, comprising: a slope signal generator for generating a slope signal in a first sub-voltage range of a voltage range based on a first current source, and generating the slope signal in a second sub-voltage range of the voltage range based on a second current source, wherein the slope signal rises and falls within the voltage range with at least one slope; and a comparator for generating an output signal based on the slope signal and an input signal; wherein the first sub-voltage range includes a low voltage level, an intermediate voltage level is included at a boundary between the first sub-voltage range and the second sub-voltage range, and the at least one slope includes a positive slope and a negative slope, wherein the slope signal rises from the low voltage level to the intermediate voltage level with the positive slope based on the first current source during a first period; wherein the second sub-voltage range includes a high voltage level, wherein the slope signal rises from the intermediate voltage level to the high voltage level with the positive slope based on the second current source during a second period; The slope signal is reduced from the high voltage level to the intermediate voltage level with the negative slope according to the second current source during a third period.

2. The analog-to-digital converter as claimed in claim 1, wherein the voltage range includes the low voltage level and the high voltage level, wherein the slope signal is raised from the low voltage level to the high voltage level with the positive slope and then lowered from the high voltage level to the low voltage level with the negative slope.

3. The analog-to-digital converter as claimed in claim 1, wherein the slope signal is reduced from the intermediate voltage level to the low voltage level with the negative slope according to the first current source during a fourth period.

4. The analog-to-digital converter as described in claim 3, wherein the first period, the second period, the third period, and the fourth period are executed sequentially.

5. The analog-to-digital converter as claimed in claim 2, wherein the slope signal generator includes the first current source, the first current source including at least one first transistor, and the slope signal generator further includes: an output terminal; a first switch including: a first terminal coupled to the first current source; and a second terminal coupled to the output terminal; and a second switch including: a first terminal coupled to the output terminal; and a second terminal for receiving the low voltage level; wherein the first switch and the second switch output the slope signal according to a first control signal and a reset signal.

6. The analog-to-digital converter as claimed in claim 5, wherein the slope signal generator includes the second current source, the second current source includes at least one second transistor, and the slope signal generator further includes: a third switch, including: a first terminal coupled to the second current source; and a second terminal coupled to the output terminal; wherein the third switch outputs the slope signal according to a second control signal.

7. An analog-to-digital conversion method, comprising: generating a slope signal in a first sub-voltage range of a voltage range according to a first current source using a slope signal generator, and generating the slope signal in a second sub-voltage range of the voltage range according to a second current source, wherein the slope signal rises and falls back and forth in the voltage range with at least one slope; and generating an output signal using a comparator based on the slope signal and an input signal; wherein the first sub-voltage range includes a low voltage level, an intermediate voltage level is included at a boundary between the first sub-voltage range and the second sub-voltage range, and the at least one slope includes a positive slope and a negative slope, wherein the slope signal is raised from the low voltage level to the intermediate voltage level with the positive slope according to the first current source during a first period; wherein the second sub-voltage range includes a high voltage level, and the slope signal is raised from the intermediate voltage level to the high voltage level with the positive slope according to the second current source during a second period; The slope signal is reduced from the high voltage level to the intermediate voltage level with the negative slope according to the second current source during a third period.

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