Semiconductor device structure and method for forming the same

Abstract

This document provides a multi-gate device with a bottom insulating layer and a method for manufacturing the same. An exemplary method includes forming first and second source / drain recesses in first and second device regions, forming first and second source / drain structures in the first and second source / drain recesses, and forming the second source / drain structure. The step of forming the second source / drain structure includes forming an insulating layer in the second source / drain recess, forming a mask over the first source / drain structure after performing a first nitrogen thermal treatment on the insulating layer, and forming a doped semiconductor layer over the insulating layer after performing a second nitrogen thermal treatment on the mask. The first nitrogen thermal treatment can increase the thickness of the insulating layer and / or reduce the etching rate of the insulating layer. The first device region can be a p-type transistor region, and the second device region can be an n-type transistor region.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to semiconductor technology, and more particularly to the structure of a semiconductor device and a method of forming the same. [Previous Technology]

[0002] Recently, multi-gate devices have been introduced to improve gate control. These devices have gates that extend partially or completely around a channel to provide paths to the channel on at least two sides. Exemplary multi-gate devices include fin-like field-effect transistors (FinFETs) and gate-all-around (GAA) transistors, such as nanowire transistors. Multi-gate devices can significantly miniaturize integrated circuit (IC) technology, maintain gate control, and mitigate short-channel effects (SCE), while seamlessly integrating with conventional IC manufacturing processes. As multi-gate devices continue to miniaturize, advanced technologies are needed to optimize their reliability and / or performance. [Summary of the Invention]

[0003] In some embodiments, a method of forming a semiconductor device structure is provided, the method comprising forming a source / drain recess; forming an insulating layer that partially fills the source / drain recess, wherein the insulating layer is formed at the bottom of the source / drain recess; treating the insulating layer with nitrogen thermal treatment; and forming a doped semiconductor layer over the treated insulating layer, wherein the doped semiconductor layer fills the remaining portion of the source / drain recess.

[0004] In some embodiments, a method for forming a semiconductor device structure is provided. This method includes forming a first source / drain recess in a first device region; forming a second source / drain recess in a second device region; forming a first source / drain structure in the first source / drain recess; and forming a second source / drain structure in the second source / drain recess. The step of forming the second source / drain structure includes: forming an insulating layer in the second source / drain recess; forming a mask over the first source / drain structure after performing a first nitrogen thermal treatment on the insulating layer; and forming a doped semiconductor layer over the insulating layer after performing a second nitrogen thermal treatment on the mask.

[0005] In some other embodiments, a semiconductor device structure is provided, the semiconductor device structure including a first type of transistor including a first source / drain structure, the first source / drain structure having a first insulating layer and a first doped epitaxial layer disposed on the first insulating layer; and a second type of transistor including a second source / drain structure, the second source / drain structure having a second insulating layer and a second doped epitaxial layer disposed on the second insulating layer, wherein the nitrogen concentration of the second insulating layer is greater than the nitrogen concentration of the first insulating layer, and wherein the thickness of the second insulating layer is at least 3 nm.

Implementation Method

[0007] The embodiments of the present invention generally relate to multi-gate devices and methods of manufacturing the same, and particularly to reducing leakage current in multi-gate devices.

[0008] It is important to understand that the following content provides many different embodiments or examples for implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the explanation. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, the size of the components is not limited to the range or values ​​of one embodiment disclosed herein, but may depend on the processing conditions and / or required nature of the components. Furthermore, in the following description, embodiments in which the first component is formed above or on the second component include those where the first and second components are formed in direct contact, and embodiments in which additional components may be formed between the first and second components so that the first and second components are not in direct contact. In addition, to facilitate the description of the relationship between one component and another in the drawings, spatially related terms such as "lower," "upper," "horizontal," "vertical," "above," "above," "below," "below," "top," "bottom," etc., and the aforementioned derived terms (e.g., "horizontally," "downward," "upward," etc.) are used. Spatially related terms are used to cover orientations different from those of the depicted device containing components. Furthermore, when using terms such as “about,” “approximately,” “roughly,” and similar terms to describe numbers or ranges of numbers, the purpose of these terms is to encompass numbers within a reasonable range that takes into account the variations inherent in manufacturing processes as understood by those skilled in the art. For example, a number or range of numbers encompasses a reasonable range including the described number, such as within + / -10% of the described number, based on known manufacturing tolerances associated with the features having characteristics related to the number. For example, a material layer having a thickness of “about 5 nm” can encompass a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / -15%. Additionally, different examples in the disclosure may use repeated reference numerals and / or wording. These repeated numerals or wording are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0009] A multi-gate device includes a gate structure that extends partially or completely around a channel region to provide a path to the channel region on at least two sides. One such multi-gate device is a gate-all-around (GAA) device, which includes vertically or horizontally stacked channel layers and is suspended in a manner above a substrate to allow the gate stack to surround (or encircle) and engage the channel layers. The channel layers extend between the source region and the drain region (e.g., epitaxial source / drain), and a voltage can be applied to the gate stack, the source region, and / or the drain region to control the current between the source and drain regions. The GAA device can significantly increase the contact area between the gate stack and the channel region, and has been observed to reduce subthreshold swing (SS), reduce short channel effects (SCEs), increase drive current, and / or improve channel control compared to other multi-gate devices (e.g., fin field-effect transistors).

[0010] However, with the miniaturization of integrated circuit (IC) technology nodes (i.e., by increasing device density (i.e., the number of interconnect devices in a given wafer area) and / or reducing geometry (i.e., the size and / or dimensions of device components and / or the spacing between them)), leakage current in fully wound gate devices has become a significant challenge. For example, parasitic transistors may form between the gate stack, the raised portion of the substrate (on which the channel layer and gate stack are disposed), and the epitaxial source / drain, and current may undesirably flow through / leak through the raised portion of the substrate between the epitaxial source / drain. Because the gate stack surrounds the raised portion of the substrate in a conventional fully wound gate device, rather than surrounding the substrate as a channel layer, the gate stack's control over the off-state leakage current in the raised portion of the substrate is limited to three sides (e.g., three-gate control). This has proven insufficient as integrated circuit technology nodes have miniaturized, and has been observed to induce and / or exacerbate drain voltage-induced barrier-lowering (DIBL) in fully wound gate devices.

[0011] Embodiments of the present invention provide bottom isolation technology (also referred to as substrate isolation technology and / or pedestal isolation technology) to improve leakage current through an underlying substrate (e.g., a pedestal of the substrate), and provide passivation technology to reduce source / drain losses during the fabrication of source / drain structures of different types of transistors. The substrate isolation technology of the present invention undergoes nitrogen thermal treatment to improve the quality of the bottom source / drain insulating layer, and the passivation technology of the present invention undergoes nitrogen thermal treatment to improve the quality of the source / drain mask. A nitrogen-treated bottom source / drain insulating layer with a thickness of at least 3 nm and / or more uniform thickness is provided, and a thickness of at least 3 nm and / or more uniform thickness can improve bottom source / drain isolation. The nitrogen-treated bottom source / drain insulating layer also has a reduced etch rate to a given etchant, thereby reducing the removal of the bottom source / drain insulating layer during subsequent processing. Nitrogen-treated source / drain masks exhibit greater density and / or reduced etch rates for a given etchant, thereby reducing the need for source / drain mask removal during subsequent processing. This improves protection for one type of source / drain structure while simultaneously forming another type of source / drain structure. In some embodiments, the substrate isolation technique of this invention further incorporates a silicon implantation process to improve the quality of the bottom source / drain insulation layer. Silicon-treated bottom source / drain insulation layers with greater thickness and / or reduced etch rates can be provided. The bottom source / drain isolation and passivation processes of this invention are seamlessly and easily integrated into existing multi-gate device manufacturing processes. The bottom source / drain isolation and passivation techniques of this invention are further described below. As will be apparent from the following description, the multi-gate devices described in the embodiments of this invention offer advantages over conventional multi-gate devices. However, it is understood that other embodiments may offer additional advantages, and it is not necessary to mention all advantages herein, nor is it necessary for any particular advantage to be present in any of the embodiments.

[0012] Figure 1 is a flowchart of a method 10 for manufacturing a source / drain structure having bottom insulation, according to various aspects of embodiments of the present invention. In block 15, method 10 includes forming a first source / drain recess in a first device region and forming a second source / drain recess in a second device region. In some embodiments, the first device region is a p-type device region and the second device region is an n-type device region. In block 20, method 10 includes forming a first undoped semiconductor layer in the first source / drain recess and forming a second undoped semiconductor layer in the second source / drain recess. The first undoped semiconductor layer and the second undoped semiconductor layer may be formed simultaneously. In blocks 25, 30, and 35, method 10 includes forming a first mask over the second device region, forming a first insulating layer in the first source / drain recess above the first undoped semiconductor layer, forming a first doped semiconductor layer in the first source / drain recess above the first insulating layer, and removing the first mask. In some embodiments, the first doped semiconductor layer is a p-type doped semiconductor layer, such as a boron-doped silicon-germanium layer. In some embodiments, the first insulating layer is a nitride layer. In some embodiments, the processing associated with blocks 25, 30, 35 may be performed after the processing associated with blocks 40, 45, 50, 55, 60, 65, 70.

[0013] In blocks 40 and 45, method 10 includes forming a second insulating layer in a second source / drain recess above the second undoped semiconductor layer and subjecting the second insulating layer to a nitrogen thermal treatment. In some embodiments, the second insulating layer is a nitride layer, such as a silicon nitride layer. In some embodiments, the nitrogen thermal treatment is an annealing process performed in a nitrogen-containing environment, such as N2 annealing. In some embodiments, the nitrogen thermal treatment increases the thickness of the second insulating layer. In some embodiments, the nitrogen thermal treatment alters the composition of the second insulating layer, which may increase the resistance of the second insulating layer to a given etchant (e.g., by reducing the etch rate of the given etchant on the second insulating layer). In some embodiments, the first device region is shielded when the second insulating layer is formed and / or when the second insulating layer is nitrogen thermally treated. In some embodiments, the first device region is not shielded when the second insulating layer is formed and / or when the second insulating layer is nitrogen thermally treated, such that the second insulating layer can be formed above the first doped semiconductor layer. The thickness of the second insulating layer in the first device region may also be increased by the nitrogen thermal treatment. In some embodiments, method 10 may include performing a silicon implantation process on the second insulating layer before or after a nitrogen heat treatment. In some embodiments, the silicon implantation process increases the thickness of the second insulating layer. In some embodiments, the silicon implantation process alters the composition of the second insulating layer, which may increase the resistance of the second insulating layer to a given etchant (e.g., by reducing the etch rate of the given etchant on the second insulating layer).

[0014] In blocks 50, 55, and 60, method 10 includes forming a second mask over the first device region and the second device region, removing the second mask from the second device region, and performing a nitrogen thermal treatment on the second mask. In some embodiments, the second mask is a metal oxide layer, such as an aluminum oxide layer. In some embodiments, the nitrogen thermal treatment is an annealing process performed in a nitrogen-containing environment, such as N2 annealing. In some embodiments, the nitrogen thermal treatment alters the composition of the second mask (e.g., the nitrogen thermal treatment can make the second mask denser), which can increase the resistance of the second mask to a given etchant (e.g., by reducing the etch rate of the given etchant on the second mask). In block 65, method 10 includes forming a second doped semiconductor layer in a second source / drain recess over the second insulating layer. In some embodiments, the second doped semiconductor layer is an n-type doped semiconductor layer, such as a phosphorus-doped silicon layer. In some embodiments, method 10 includes performing a pre-cleaning process before forming the second doped semiconductor layer over the second insulating layer. In block 70, method 10 includes removing the second mask from the first device region. Embodiments of the invention consider additional processing. Additional steps may be provided before, during, and after method 10, and for additional embodiments of method 10, some described steps may be moved, substituted, or eliminated. The following discussion illustrates a device having a source / drain structure manufactured according to method 10.

[0015] Figures 2A to 2I are partial or complete cross-sectional views of the apparatus 100 at various manufacturing stages associated with the method 10 of Figure 1, according to various aspects of embodiments of the present invention. Figures 3A to 3F are partial or complete perspective views of the apparatus 100 at various manufacturing stages associated with the method 10 of Figure 1, according to various aspects of embodiments of the present invention. Figure 3A corresponds to the manufacturing stage of Figure 2C, wherein Figure 2C is taken along lines 1-1' and 2-2' of Figure 3A to provide cross-sectional views of apparatus region 102A and apparatus region 102B, respectively. Figure 3B corresponds to the manufacturing stage of Figure 2E, wherein Figure 2E is taken along lines 1-1' and 2-2' of Figure 3B to provide cross-sectional views of apparatus region 102A and apparatus region 102B, respectively. Figure 3C corresponds to the manufacturing stage of Figure 2F, wherein Figure 2F is taken along lines 1-1' and 2-2' of Figure 3C to provide cross-sectional views of device region 102A and device region 102B, respectively. Figures 3D and 3E correspond to the manufacturing stage of Figure 2G, wherein Figure 2G is taken along lines 1-1' and 2-2' of Figure 3E to provide cross-sectional views of device region 102A and device region 102B, respectively. Figure 3F corresponds to the manufacturing stage of Figure 2H, wherein Figure 2H is taken along lines 1-1' and 2-2' of Figure 3F to provide cross-sectional views of device region 102A and device region 102B, respectively. Figure 4 provides a partial or complete cross-sectional schematic diagram of a source / drain structure having an untreated bottom insulating layer, and a partial or complete cross-sectional schematic diagram of a source / drain structure having a treated bottom insulating layer (e.g., treated with nitrogen and / or silicon as described herein), according to various aspects of embodiments of the present invention. These contents are also discussed herein for ease of description and understanding of Figures 2A to 2I, 3A to 3F, and Figure 4. For clarity, Figures 2A to 2I, 3A to 3F, and Figure 4 have been simplified to better understand the inventive concept of embodiments of the present invention. Additional components may be added to device 100, and in other embodiments of device 100, some components described below may be replaced, modified, or eliminated.

[0016] After processing associated with Figures 2A to 2I, device 100 may include at least one fully wound gate transistor (i.e., a transistor having a gate that at least partially surrounds a suspended channel (e.g., nanowire, nanosheet, nanorod, or the like) extending between the source and drain). For example, device 100 may be processed to form a first transistor in device region 102A and a second transistor in device region 102B. In the illustrated embodiment, device 100 is processed to form an n-type transistor in device region 102A and a p-type transistor in device region 102B. In these embodiments, device 100 may include complementary metal-oxide-semiconductor (CMOS) transistors, such as n-type and p-type transistors. In some embodiments, both the first and second transistors are n-type transistors or both are p-type transistors. Device 100 may be included in a microprocessor, memory, other integrated circuit devices, or a combination thereof. In some embodiments, device 100 is part of an integrated circuit chip, a system on chip (SoC), or a part of the foregoing, and device 100 may include various passive and / or active electronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0017] Referring to Figure 2A, the fabrication of device 100 may include forming and / or receiving a device precursor comprising a substrate 105, a multilayer stack 110 (including, for example, a base 105', a sacrificial layer 115, and a semiconductor layer 120), a substrate isolation structure 125, a gate structure 130A, and a gate structure 130B. In the illustrated embodiment, gate structure 130A and gate structure 130B each comprise a corresponding dummy gate stack 132 and a corresponding gate spacer 134, and each dummy gate stack 132 may comprise a corresponding dummy gate 136 and a corresponding hard mask 138. After forming and / or receiving the device precursor, the fabrication of device 100 may include forming a source / drain recess 140A in device region 102A and forming a source / drain recess 140B in device region 102B, as further described below. Before forming the source / drain notches 140A and 140B, the multilayer stack 110 extends generally continuously along the x-direction, has a length along the x-direction, a width along the y-direction, and a height along the z-direction. The multilayer stack 110 may be referred to as a fin, fin element, active fin region, active region, etc. In some embodiments, the base 105' is a patterned, protruding portion, and / or extension of the substrate 105, and the base 105' may be referred to as a substrate extension, substrate fin portion, fin portion, etched substrate portion, etc.

[0018] The substrate 105 comprises elemental semiconductors (e.g., silicon and / or germanium), compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof), or combinations thereof. In some embodiments, the substrate 105 is a silicon substrate. In some embodiments, the substrate 105 is a semiconductor-on-insulator substrate, such as a semiconductor-on-silicon (SOI) substrate, a semiconductor-on-silicon germanium (SGOI) substrate, or a semiconductor-on-germanium (GOI) substrate. The substrate 105 (and the base 105') may comprise various doped regions, such as p-type doped regions (e.g., p-type wells), n-type doped regions (e.g., n-type wells), or combinations thereof. The n-type doped region contains an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The p-type doped region contains a p-type dopant, such as boron, indium, gallium, other p-type dopants, or combinations thereof. In some embodiments, the doped region contains both p-type and n-type dopants. The doped region may be formed on and / or in the substrate 105, for example, providing a p-type well structure, an n-type well structure, a dual-well structure, a raised structure, other suitable structures, or combinations thereof. In some embodiments, the substrate 105 and / or the pedestal 105' and the semiconductor layer thereon may contain n-type wells and / or p-type wells. For example, the pedestal 105' may contain a p-type well in device region 102A (e.g., an n-type transistor formed in the p-type well) and an n-type well in device region 102B (e.g., a p-type transistor formed in the n-type well), or vice versa.

[0019] The sacrificial layer 115 and the semiconductor layer 120 are vertically stacked from the top of the substrate 105 in an alternating and / or staggered configuration (e.g., along the z-direction). The composition of the sacrificial layer 115 differs from that of the semiconductor layer 120 to achieve etch selectivity. For example, the sacrificial layer 115 and the semiconductor layer 120 may contain different materials, atomic percentages of components, weight percentages of components, other properties, or combinations thereof to achieve etch selectivity. In some embodiments, the sacrificial layer 115 contains silicon germanium, the semiconductor layer 120 contains silicon, and for a given etchant, the etch rate of the semiconductor layer 120 differs from the etch rate of the sacrificial layer 115. In some embodiments, the sacrificial layer 115 and the semiconductor layer 120 may contain the same material but have different atomic percentages. For example, the sacrificial layer 115 and the semiconductor layer 120 may contain silicon germanium, and the sacrificial layer 115 and the semiconductor layer 120 may have different percentages of germanium atoms to achieve etch selectivity. The sacrificial layer 115 and the semiconductor layer 120 may comprise any combination of materials that provide desired etch selectivity, desired oxidation rate differences and / or desired performance characteristics (e.g., materials that maximize current), including any materials mentioned in embodiments of the present invention.

[0020] Semiconductor layer 120 and a portion thereof may form channels for the transistors of device 100. In Figure 2A, the multilayer stack 110 includes three sacrificial layers 115 and three semiconductor layers 120. Thus, the multilayer stack 110 includes three pairs of semiconductor layers disposed over substrate 105, each pair having a corresponding sacrificial layer 115 and a corresponding semiconductor layer 120. After processing of the multilayer stack 110, this configuration may form a transistor with three channels. However, in some embodiments, the multilayer stack 110 includes a different number of semiconductor layers 120, depending on, for example, the desired number of channels for the transistors of device 100 and / or the design requirements of device 100. For example, the multilayer stack 110 may include two to six pairs of semiconductor layers, each pair having a corresponding sacrificial layer 115 and a corresponding semiconductor layer 120.

[0021] The substrate isolation structure 125 may be formed adjacent to and surrounding the lower portion of the multilayer stack 110 (e.g., the base 105' of the multilayer stack 110), and the multilayer stack 110 may be separated from other multilayer stacks and / or other devices through the substrate isolation structure 125. The substrate isolation structure 125 may electrically isolate the active device region (e.g., the multilayer stack 110) from other device regions (e.g., other multilayer stacks). The substrate isolation structure 125 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including silicon, oxygen, nitrogen, carbon, other suitable isolation components, or combinations thereof) or combinations thereof. The substrate isolation structure 125 may have a multilayer structure. For example, the substrate isolation structure 125 may include a bulk dielectric (e.g., an oxide layer) above a dielectric pad (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbon oxide, or combinations thereof). In another example, the substrate isolation structure 125 may comprise a bulk dielectric over a doped pad (e.g., a borosilicate glass (BSG) pad and / or a phosphosilicate glass (PSG) pad). The dimensions and / or characteristics of the substrate isolation structure 125 may be configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or combinations thereof.

[0022] Gate structures 130A and 130B may be formed above the channel region (C) of the multilayer stack 110 and between the corresponding source / drain regions (S / D) of the multilayer stack 110. A dummy gate stack 132 extends longitudinally in a direction different from (e.g., perpendicular to) the longitudinal direction of the multilayer stack 110. For example, the dummy gate stack 132 extends in the y-direction, having a length in the y-direction, a width in the x-direction, and a height in the z-direction. The dummy gate stack 132 may extend substantially parallel to each other. In Figure 2A (e.g., the XZ plane), the dummy gate stack 132 is disposed on top of the corresponding channel region and between the corresponding source / drain regions. In the cross-sectional view along the YZ plane, the dummy gate stack 132 can surround the corresponding channel area (e.g., disposed above the top and sidewalls of the channel area), and the dummy gate stack 132 can be disposed above the top of the base isolation structure 125.

[0023] The dummy gate 136 may include a dummy gate dielectric and a dummy gate electrode. The dummy gate dielectric includes a dielectric material, such as silicon oxide and / or other suitable dielectric materials. The dummy gate electrode includes a suitable dummy gate material, such as polysilicon. A hard mask 138 may be configured to protect the dummy gate 136 during processing. For example, the hard mask 138 may include a material resistant to etching processes (e.g., source / drain etching) to protect the dummy gate 136 from the effects of the etching process. In some embodiments, the hard mask 138 has a multilayer structure, such as a first mask layer disposed above a second mask layer. The hard mask 138 includes any suitable hard mask material.

[0024] A gate spacer wall 134 is formed adjacent to the dummy gate stack 132 and extends along the sidewall of the dummy gate stack 132. The gate spacer wall 134 comprises a dielectric material, which may comprise silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, silicon oxycarbonate, silicon oxynitride nitride, or combinations thereof). In some embodiments, the gate spacer wall 134 has a multilayer structure, such as two or more dielectric layers with different compositions. In some embodiments, the gate spacer wall 134 comprises more than one set of spacer walls, such as sealing spacer walls, offset spacer walls, sacrificial spacer walls, dummy spacer walls, primary spacer walls, or combinations thereof. In some embodiments, each set of spacer walls may have a different composition.

[0025] In Figure 2A, source / drain etching removes portions of the multilayer stack 110 not covered by gate structures 130A and 130B, thereby forming source / drain recesses 140A and 140B (collectively referred to as source / drain recesses 140) (source / drain recesses are sometimes also referred to as source / drain trenches). For example, source / drain etching removes the semiconductor layer 120 and sacrificial layer 115 in the source / drain regions of the multilayer stack 110, thereby exposing the substrate 105'. Source / drain etching may further remove some, but not all, of the substrate 105' in the source / drain regions of the multilayer stack 110, such that the source / drain recesses 140 extend to the substrate 105', but not through the substrate 105'. After source / drain etching, the sacrificial layer 115, the semiconductor layer 120, and the protrusion formed by the base 105' (hereinafter also referred to as base 105P') remain in the channel region of the multilayer stack 110, and the source / drain notch 140 exposes the sidewalls of the sacrificial layer 115, the semiconductor layer 120, and the base 105P' retained in the channel region. In the illustrated embodiment, the source / drain notch 140 extends through the multilayer stack 110 to a depth d in the base 105', has a depth D between the top of the multilayer stack 110 and the bottom of the source / drain notch 140, and has a width W. The depth D may be the sum of the height h of the multilayer stack 110 and the depth d of the source / drain notch 140.

[0026] The source / drain etching is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the source / drain etching is a multi-step etching process that may use alternating etchants to remove the sacrificial layer 115 and the semiconductor layer 120 separately and alternately. In some embodiments, the source / drain etching parameters (e.g., the etchant used in the source / drain etching) are adjusted to selectively remove semiconductor materials (e.g., semiconductor layer 120, sacrificial layer 115, and substrate 105') while negligible (or even no) removal of dielectric materials (e.g., hard mask 138, gate spacer 134, substrate isolation structure 125, etc.).

[0027] Referring to Figure 2B, an internal spacer wall 145 may be formed below the gate spacer wall 134 along the sidewall of the sacrificial layer 115. The internal spacer wall 145 may replace the edge / end of the sacrificial layer 115 disposed below the gate spacer wall 134. In the illustrated embodiment, the remaining portion of the sacrificial layer 115 is disposed between the corresponding internal spacer walls 145 along the x-direction, the top internal spacer wall 145 and the middle internal spacer wall 145 are disposed between the ends of the corresponding semiconductor layer 120 along the z-direction, and the bottom internal spacer wall 145 is disposed between the end of the bottom semiconductor layer 120 and the base 105P' along the z-direction.

[0028] The step of forming the internal spacer wall 145 may include a first etching process, a deposition process, and a second etching process. The first etching process may selectively etch the sacrificial layer 115 while ignoring (or even not etching) the semiconductor layer 120, the substrate 105P', the dummy gate stack 132 (e.g., a hard mask 138 of the dummy gate stack 132), the gate spacer wall 134, the substrate isolation structure 125, or a combination thereof. The first etching process may be configured to laterally etch (e.g., along the x-direction and / or y-direction) the sacrificial layer 115 to reduce the length of the sacrificial layer 115 along the x-direction, such that the length of the sacrificial layer 115 is less than the length of the semiconductor layer 120. The first etching process may form internal spacer wall notches between the semiconductor layers 120 and between the semiconductor layer 120 and the substrate 105P'. In some embodiments, the internal spacer wall notches extend laterally (e.g., along the x-direction) below the dummy gate stack 132. The first etching process may be dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the first etching process is anisotropic etching.

[0029] A deposition process forms an internal spacer layer above the apparatus 100 that can fill the internal spacer wall recesses. In some embodiments, a single deposition process is performed to form the internal spacer layer that fills the internal spacer wall recesses. In some embodiments, the internal spacer wall 145 has a multilayer structure. For example, more than one deposition process may be performed to form the internal spacer layer, such as a first deposition process forming a first internal spacer wall sublayer and a second deposition process forming a second internal spacer wall sublayer. The first internal spacer wall sublayer partially fills the internal spacer wall recesses, and the second internal spacer wall sublayer partially or completely fills the internal spacer wall recesses. The composition and / or material of the first internal spacer wall sublayer may be the same as or different from the composition and / or material of the second internal spacer wall sublayer. In some embodiments, the internal spacer wall 145 includes air gaps (voids).

[0030] The second etching process may selectively etch the internal spacer layer while ignoring (or even not etching) the semiconductor layer 120, the substrate 105P', the dummy gate stack 132 (e.g., a hard mask 138 of the dummy gate stack 132), the gate spacer wall 134, the substrate isolation structure 125, or combinations thereof. The remaining portion of the internal spacer layer provides internal spacer walls 145, as shown. To achieve the desired etching selectivity, the internal spacer layer (and consequently the internal spacer walls 145) has a composition different from that of the semiconductor layer 120, the substrate 105P', the dummy gate stack 132, the gate spacer wall 134, the substrate isolation structure 125, or combinations thereof. In some embodiments, the internal spacer layer comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof. For example, the internal spacer layer may be a silicon carbide layer, a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, or a combination thereof. The second etching process may be dry etching, wet etching, other suitable etching, or a combination thereof.

[0031] Referring to Figures 2B to 2H, a source / drain structure 150A is formed in a source / drain recess 140A, and a source / drain structure 150B is formed in a source / drain recess 140B. The source / drain structures 150A and 150B herein may be collectively referred to as source / drain structure 150. Source / drain structure 150A may include a corresponding undoped semiconductor layer 152, a corresponding insulating layer 154A, and a corresponding doped semiconductor layer 156A. In some embodiments, the doped semiconductor layer 156A has a multilayer structure, such as a doped semiconductor layer 158A and a doped semiconductor layer 160A. Source / drain structure 150B may include a corresponding undoped semiconductor layer 152, a corresponding insulating layer 154B, and a corresponding doped semiconductor layer 156B. In some embodiments, the doped semiconductor layer 156B has a multilayer structure, such as a doped semiconductor layer 158B and a doped semiconductor layer 160B. In the illustrated embodiment, device region 102A is an n-type transistor region and device region 102B is a p-type transistor region. Source / drain structure 150A forms the source / drain of the n-type transistor, and source / drain structure 150B forms the source / drain of the p-type transistor. In these embodiments, source / drain structure 150A may comprise a semiconductor material doped with an n-type dopant (e.g., carbon, phosphorus, arsenic, antimony, other n-type dopants, or combinations thereof), while source / drain structure 150B may comprise a semiconductor material doped with a p-type dopant (e.g., boron, gallium, other p-type dopants, or combinations thereof). As described in more detail below, the source / drain structure fabrication process described herein includes processing steps such as nitrogen thermal treatment (e.g., nitrogen-containing annealing) to improve bottom source / drain insulation, thereby reducing leakage current, and / or to improve passivation during source / drain patterning, thereby reducing unwanted wear on the source / drain structure.

[0032] Referring again to Figure 2B, an undoped semiconductor layer 152 may be formed in source / drain recess 140A (e.g., at the bottom of source / drain recess 140A) and source / drain recess 140B (e.g., at the bottom of source / drain recess 140B). In the illustrated embodiment, the undoped semiconductor layer 152 is formed simultaneously in device region 102A and device region 102B. In some embodiments, the undoped semiconductor layer 152 is formed in device region 102A before or after the undoped semiconductor layer 152 is formed in device region 102B. The undoped semiconductor layer 152 is free of dopants (i.e., substantially free of n-type and p-type dopants). For example, no deliberate doping is performed when the undoped semiconductor layer 152 is formed. The undoped semiconductor layer 152 may provide a high-resistance path at the bottom of the source / drain recess 140, thereby suppressing leakage current into the substrate 105. The undoped semiconductor layer 152 comprises silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, the undoped semiconductor layer 152 is a doped silicon layer or a doped silicon-germanium layer. In some embodiments, semiconductor materials having a dopant concentration of less than about 5 x 10¹⁸ cm⁻³ (e.g., about 1 x 10¹⁸ cm⁻³ to about 5 x 10¹⁸ cm⁻³) are considered undoped and / or unintentionally doped (UID).

[0033] An undoped semiconductor layer 152 is disposed on the substrate 105P' and / or the substrate 105'. In the illustrated embodiment, the undoped semiconductor layer 152 has a recessed top surface (e.g., a concave and / or grooved top surface), and at least a portion of the thickness of the undoped semiconductor layer 152 (e.g., the central portion of the undoped semiconductor layer 152) is less than the height of the substrate 105P', such that the source / drain recess 140 still extends to a certain depth in the substrate 105P'. This depth can be determined by the difference between the initial depth d of the source / drain recess 140 and the minimum thickness of the undoped semiconductor layer 152. Furthermore, in the illustrated embodiment, the undoped semiconductor layer 152 has a thickness less than or equal to the height of the substrate 105P', but greater than the minimum thickness at the edge / end portions. In these embodiments, the undoped semiconductor layer 152 may not extend above the top of the substrate 105P'. In some embodiments, the thickness of the edge / end portion of the undoped semiconductor layer 152 is the maximum thickness of the undoped semiconductor layer 152. This document considers embodiments in which the undoped semiconductor layer 152 completely fills the bottom of the source / drain recess 140 and / or extends over the top of the base 105P'.

[0034] The undoped semiconductor layer 152 may be deposited on and / or grown from the substrate 105, substrate 105', substrate 105P', or a combination thereof. In some embodiments, the undoped semiconductor layer 152 is formed by a selective epitaxial growth (SEG) process, which selectively deposits / grows a semiconductor material (e.g., silicon) on or from an exposed top surface. In these embodiments, the undoped semiconductor layer 152 may be referred to as an undoped epitaxial layer. Selective epitaxial growth processes can utilize chemical vapor deposition (CVD) techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or similar methods), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, the undoped semiconductor layer 152 is formed through a bottom-up deposition process (which may be a selective epitaxial growth process) such that semiconductor material is deposited on the substrate 105P', the substrate 105', and / or the base 105 (i.e., deposited in the bottom of the source / drain recess 140), minimizing (or even eliminating) the deposition of semiconductor material on the semiconductor layer 120. In some embodiments, an etching process may be performed after the bottom-up deposition process to remove any semiconductor material formed on the semiconductor layer 120. This post-deposition etching can be dry etching, wet etching, other suitable etching, or a combination thereof.

[0035] Referring to Figure 2C, the fabrication of device 100 may include forming a mask 162 that covers device region 102A (e.g., an n-type transistor region) but does not cover device region 102B (e.g., a p-type transistor region), and forming an additional layer of source / drain structure 150B in device region 102B. For example, mask 162 has an opening 163 therein, which overlaps with device region 102B. In some embodiments, mask 162 is formed by depositing a hard mask material over device regions 102A and 102B and performing a patterning process to remove the hard mask material from device region 102B, thereby exposing source / drain notches 140B. The patterning process may include performing a photolithography process to form a patterned photoresist layer that covers the hard mask material above device region 102A and exposes the hard mask material above device region 102B (e.g., the patterned photoresist layer has an opening therein that overlaps with device region 102B), and performing an etching process to selectively remove the exposed hard mask material. The composition of mask 162 differs from that of source / drain structure 150A (e.g., the undoped semiconductor layer 152 of source / drain structure 150A), semiconductor layer 120, gate structure 130A, gate structure 130B, internal spacer 145, or combinations thereof, to achieve selective removal / etching therebetween. In some embodiments, mask 162 comprises metal and oxygen and / or nitrogen (e.g., mask 162 is a metal oxide mask and / or a metal nitride mask). For example, mask 162 may contain aluminum and oxygen and / or nitrogen, and mask 162 may be an aluminum oxide mask, an aluminum oxynitride mask, an aluminum nitride mask, or a combination thereof. In some embodiments, mask 162 is a patterned photoresist layer.

[0036] An insulating layer 154B may be formed in the source / drain recess 140B above the undoped semiconductor layer 152, while a mask 162 covers the device region 102A. The insulating layer 154B partially fills the source / drain recess 140B, and the insulating layer 154B may be disposed on the bottommost inner spacer wall 145 and / or the base 105P'. In some embodiments, the insulating layer 154B fills the remaining portion of the bottom of the source / drain recess 140B, and the insulating layer 154B is at least partially disposed above the top of the base 105P'. The insulating layer 154B comprises an electrically insulating material, such as a dielectric material, which reduces unwanted leakage currents, such as currents that may undesirably flow through the base 105P' between the doped semiconductor layers 156B. In some embodiments, insulating layer 154B comprises a dielectric material including silicon, such as silicon nitride, silicon oxynitride, silicon oxynitrogenate, silicon oxycarbonate, silicon oxycarbonate, silicon oxycarbide, other dielectric materials including silicon (which may comprise silicon and nitrogen, carbon, oxygen, other suitable dielectric components, or combinations thereof) or combinations thereof. In some embodiments, insulating layer 154B comprises a dielectric material including metal, such as a metal oxide material and / or a metal nitride material. In some embodiments, insulating layer 154B comprises a doped semiconductor material comprising a dopant of the same type as that of doped semiconductor layer 156B. For example, in the illustrated embodiment, where doped semiconductor layer 156B is part of the source / drain of a p-type transistor (e.g., a p-type doped semiconductor layer), insulating layer 154B may comprise an n-type doped semiconductor material, such as phosphorus-doped silicon.

[0037] The insulating layer 154B can be formed by depositing and etching an insulating material over the device 100, such that the remaining portion of the insulating material fills the bottom of the source / drain recess 140B. The deposited insulating material can be disposed on the top of the gate structure 130B (e.g., the top of the gate gap wall 134 and the dummy gate stack 132), the sidewalls of the gate structure 130B (e.g., the sidewalls of the gate gap wall 134), the sidewalls of the semiconductor layer 120, the sidewalls of the internal gap wall 145, the sidewalls of the base 105P', and the top of the base 105' in the source / drain region. In some embodiments, due to the nature of the deposition process (e.g., physical vapor deposition, PVD), the thickness of the insulating material above the horizontally oriented surfaces (e.g., the top of the undoped semiconductor layer 152 in the source / drain region and the top of the gate structure 130B) can be greater than the thickness of the insulating material above the vertically oriented surfaces (e.g., the sidewalls of the gate structure 130B, the sidewalls of the semiconductor layer 120, and the sidewalls of the internal spacer wall 145). Therefore, etching parameters can be adjusted to remove the vertically oriented portions of the insulating material, such as those on the sidewalls of the gate structure 130B, the semiconductor layer 120, and the internal spacer wall 145. In these embodiments, due to the etch load effect, etching may also remove horizontally oriented portions of the insulating material on top of the gate structure 130B, but without removing (or minimizing removal of) horizontally oriented and / or vertically oriented portions of the insulating material at the bottom of the source / drain recess 140B, such as portions disposed on the undoped semiconductor layer 152 (i.e., the etching process may thin these, but generally does not remove these portions). In some embodiments, the deposited insulating material fills the source / drain recess 140B, and etching recesses the insulating material into at least the bottom sacrificial layer 115 and / or the bottom internal spacer wall 145. This etching may be dry etching, wet etching, other suitable etching, or a combination thereof.

[0038] A doped semiconductor layer 156B may also be formed in the source / drain recess 140B above the insulating layer 154B and / or the undoped semiconductor layer 152, while the mask 162 covers the device region 102A. The doped semiconductor layer 156B fills the remaining portion of the source / drain recess 140B and is coupled to the edge / end portion of the semiconductor layer in the device region 102B. In the illustrated embodiment, the doped semiconductor layer 156B includes a doped semiconductor layer 158B and a doped semiconductor layer 160B. The doped semiconductor layer 158B may be formed above the semiconductor layer 120 (e.g., above the sidewalls and / or ends of the semiconductor layer 120) and partially fills the source / drain recess 140B, and the doped semiconductor layer 160B may be formed above the doped semiconductor layer 158B and / or the insulating layer 154B and fill the remaining portion of the source / drain recess 140B. The doped semiconductor layer 160B is separated from the semiconductor layer 120 through the doped semiconductor layer 158B, and is also separated from the undoped semiconductor layer 152 through the insulating layer 154B. In the illustrated embodiment, the doped semiconductor layer 158B is discontinuous and formed by discrete and spaced portions, each doped semiconductor layer 158B being disposed at the end of a corresponding semiconductor layer 120, i.e., portions of the doped semiconductor layers 158B disposed on adjacent semiconductor layers 120 are not connected to each other. In these embodiments, the doped semiconductor layer 160B may surround the doped semiconductor layer 158B, and the doped semiconductor layer 160B may extend to the internal spacer wall 145. In some embodiments, discrete and spaced portions of one or more doped semiconductor layers 158B may surround the semiconductor layer 120, such that the discrete and spaced portions are formed above the top and / or bottom of the corresponding semiconductor layer 120. In some embodiments, the discrete and spaced portions extend above and / or to the internal spacer wall 145. In some embodiments, discrete and spaced portions of one or more doped semiconductor layers 158B are connected. In these embodiments, the doped semiconductor layers 158B may form sidewalls of the source / drain structure 150B above the base 105P'. Furthermore, in these embodiments, the doped semiconductor layer 160B may be spaced from the internal spacer wall 145 through the doped semiconductor layers 158B.

[0039] Doped semiconductor layer 158B and doped semiconductor layer 160B comprise silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, doped semiconductor layer 158B and doped semiconductor layer 160B comprise the same semiconductor material but have different concentrations. For example, doped semiconductor layer 158B and doped semiconductor layer 160B may comprise silicon-germanium and p-type dopant (e.g., boron and / or gallium), but have different germanium concentrations and / or different p-type dopant concentrations. In some embodiments, doped semiconductor layer 158B has a smaller germanium concentration (e.g., Ge%) and / or a smaller p-type dopant concentration (e.g., B%) than doped semiconductor layer 160B, which can reduce crystal dislocations, reduce other crystal defects, maximize strain (and thus enhance carrier mobility, and thus increase drive current), or combinations thereof. In some embodiments, the germanium concentration in doped semiconductor layer 158B is from about 10% to about 20%, and the germanium concentration in doped semiconductor layer 160B is from about 30% to about 60%. In some embodiments, doped semiconductor layer 158B has a p-type dopant concentration (e.g., boron concentration) of about 1 x 10²⁰ cm⁻³ to about 5 x 10²⁰ cm⁻³, and doped semiconductor layer 160B has a p-type dopant concentration (e.g., boron concentration) of about 5 x 10²⁰ cm⁻³ to about 2 x 10²¹ cm⁻³. In these embodiments, doped semiconductor layer 160B may be referred to as a heavily doped semiconductor layer, and doped semiconductor layer 158B may be referred to as a lightly doped semiconductor layer. In some embodiments, doped semiconductor layer 158B and doped semiconductor layer 160B have different semiconductor materials, which may have the same or different composition concentrations. In some embodiments, doped semiconductor layer 156B includes a material and / or dopants that provide the desired compressive stress in the channel region (e.g., semiconductor layer 120).

[0040] The doped semiconductor layer 158B may be deposited on and / or grown from the semiconductor layer 120, and the doped semiconductor layer 160B may be deposited on and / or grown from the doped semiconductor layer 158B. In some embodiments, the doped semiconductor layer 158B and the doped semiconductor layer 160B are formed through individual selective epitaxial growth processes. The selective epitaxial growth process may be a chemical vapor deposition technique (e.g., vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), low-pressure chemical vapor deposition (LPCVD), plasma-assisted chemical vapor deposition (PECVD), or similar methods), molecular beam epitaxy, other suitable selective epitaxial growth processes, or combinations thereof. The selective epitaxial growth process may use gaseous and / or liquid precursors that react with the composition of the semiconductor layer 120, the doped semiconductor layer 158B, or combinations thereof. Epitaxial growth / deposition conditions, such as those described herein, are adjusted to selectively deposit (grow) semiconductor materials (e.g., silicon-germanium) on semiconductor surfaces (e.g., semiconductor layer 120 and / or doped semiconductor layer 158B), while limiting (or preventing) the growth of semiconductor materials from dielectric surfaces and / or non-semiconductor surfaces (e.g., internal spacers 145, dummy gate stacks 132, gate spacers 134, and / or substrate isolation structures 125). In some embodiments, doped semiconductor layers 158B and / or doped semiconductor layers 160B are doped during deposition (i.e., in-situ doping), for example, by adding dopants to the source material of a selective epitaxial growth process. In some embodiments, doped semiconductor layers 158B and / or doped semiconductor layers 160B are doped after deposition, for example, by an ion implantation process. In some embodiments, annealing is performed to activate the dopants in doped semiconductor layers 158B, doped semiconductor layers 160B, other source / drain regions (e.g., source / drain junction implantation regions), or combinations thereof.

[0041] Referring to Figure 3A, after the formation of the additional layer of source / drain structure 150B, mask 162 can be removed by any suitable process, such as etching and / or photoresist stripping. Referring to Figures 2D to 2H and 3B to 3F, the fabrication of device 100 may include forming additional layers of the source / drain structure 150A in device region 102A, such as insulating layer 154A and doped semiconductor layer 156A. When insulating layer 154A is formed, device region 102B may be exposed, and when doped semiconductor layer 156A is formed, device region 102B may be covered, as described herein.

[0042] Referring to Figures 2D, 2E, and 3B, an insulating layer 154A may be formed in the source / drain recess 140A above the undoped semiconductor layer 152. The insulating layer 154A partially fills the source / drain recess 140A, and the insulating layer 154A may be disposed on the bottommost inner spacer wall 145 and / or the base 105P'. In some embodiments, the insulating layer 154A fills the remaining portion of the bottom of the source / drain recess 140A, and the insulating layer 154A is at least partially disposed above the top of the base 105P'. The insulating layer 154A comprises an electrically insulating material, such as a dielectric material, which reduces unwanted leakage currents, such as currents that may undesirably flow through the base 105P' between the doped semiconductor layers 156A. In the illustrated embodiment, the insulating layer 154A is a nitride layer. The nitride layer may comprise silicon and nitrogen, including dielectric materials, such as silicon nitride, silicon oxynitride, silicon oxynitrogen oxide, silicon oxynitride, silicon carbide, other suitable silicon and nitrogen comprising dielectric materials, or combinations thereof. For example, insulating layer 154A may be a silicon nitride layer. In some embodiments, the nitride layer comprises a metal comprising dielectric materials and nitrogen, and insulating layer 154A may be a metal nitride layer.

[0043] Referring to Figure 2D, the insulating layer 154A can be formed by depositing and etching an insulating material over the device 100, such that the remaining portion of the insulating material provides an insulating layer 154A' having a first nitrogen concentration. For example, the insulating layer 154A' has a thickness t1 that can fill the bottom of the source / drain recess 140A, and the insulating layer 154A' has a thickness t2 that can be disposed over the source / drain structure 150B. The deposited insulating material can be disposed on the top of the gate structures 130A and 130B (e.g., the top of the gate gap wall 134 and the dummy gate stack 132), the sidewalls of the gate structures 130A and 130B (e.g., the sidewalls of the gate gap wall 134), the top and / or sidewalls of the source / drain structure 150B (e.g., the doped semiconductor layer 160B of the source / drain structure 150B), the sidewalls of the semiconductor layer 120, the sidewalls of the internal gap wall 145, the sidewalls of the base 105P', and the top of the base 105'. In some embodiments, due to the nature of the deposition process (e.g., physical vapor deposition), the thickness of the insulating material above horizontally oriented surfaces (e.g., the top of the undoped semiconductor layer 152, the top of the gate structure 130A, the top of the gate structure 130B, and the top of the source / drain structure 150B) may be greater than the thickness of the insulating material above vertically oriented surfaces (e.g., the sidewalls of the gate structure 130A, the sidewalls of the gate structure 130B, the sidewalls of the semiconductor layer 120, and the sidewalls of the internal spacer wall 145). In these embodiments, etching parameters can be adjusted to remove vertically oriented portions of the insulating material, such as portions on the sidewalls of gate structure 130A, gate structure 130B, semiconductor layer 120, and internal spacer wall 145. Due to the etching load effect, etching can also remove horizontally oriented portions of the insulating material on the top of gate structure 130A and gate structure 130B, but without removing (or minimizing removal of) horizontally and / or vertically oriented portions of the insulating material at the bottom of source / drain recess 140A. For example, this etching process can thin the portions of the insulating material at the bottom of source / drain recess 140, but without substantially removing these portions. Furthermore, due to the etching load effect, this etching process can make the insulating material disposed above source / drain structure 150B thinner than the insulating material disposed above the undoped semiconductor layer 152 of source / drain structure 150A, such that in the illustrated embodiment, thickness t2 is less than thickness t1. In some embodiments, thickness t2 is approximately the same as thickness t1. In some embodiments, the etching process completely removes the insulating material disposed above the source / drain structure 150B, and the device region 102B has no insulating layer 154A' / insulating layer 154A. In some embodiments, the deposited insulating material fills the source / drain recess 140A, and the etching recesses the insulating material into at least the bottom sacrificial layer 115 and / or the bottom internal spacer wall 145.In these embodiments, the etching process may partially (e.g., thin) or completely remove the insulating material disposed above the source / drain structure 150B. This etching may be dry etching, wet etching, other suitable etching, or a combination thereof.

[0044] This embodiment of the invention recognizes that subsequent processing of the device 100 may undesirably reduce the thickness t1 of the insulating layer 154A'. For example, performing an etching process to remove the mask and / or patterned layer from the device region 102a, as described with reference to Figures 2G and 3D, may undesirably etch the insulating layer 154A'. In some examples, the thickness t1 is reduced to less than 3 nm. It has been observed that an insulating layer 154A' with a thickness less than 3 nm can negligibly reduce and / or prevent leakage current, even if present, thus negating the purpose of incorporating the insulating layer 154A' into the source / drain structure 150A. This problem is exacerbated when the thickness t1 of the insulating layer 154A' is non-uniform. For example, the thickness t1 of the edge / end portion of the insulating layer 154A' may be less than the thickness t1 of the central portion of the insulating layer 154A', making the edge / end portion of the insulating layer 154A' more susceptible to the effects of subsequent etching processes. In some examples, subsequent etching processes can completely remove the thinner edges of the insulating layer 154A' in device region 102A, undesirably exposing and / or damaging the undoped semiconductor layer 152 and / or substrate 105P' beneath device region 102A. Therefore, an insulating layer 154A' with a thickness less than 3 nm may cause, rather than prevent, leakage current. It has been observed that simply increasing the thickness t1 to compensate for and / or address thickness reduction that may occur during subsequent fabrication by increasing the thickness of the deposited insulating material and / or etching less of the deposited insulating material leaves residual insulating material along the sidewalls of the source / drain recess 140A (e.g., along the sidewalls of semiconductor layer 120 and / or the internal spacer wall 145), which inhibits the growth and / or deposition of the doped semiconductor layer 156A, thereby reducing source / drain strain.

[0045] Referring to Figures 2E and 3B, an embodiment of the present invention proposes a processing step 165 for insulating layer 154A'. Processing step 165 is configured to change the composition and / or quality of insulating layer 154A', thereby forming insulating layer 154A. For example, processing step 165 is configured to provide that the thickness t3 of insulating layer 154A is greater than the thickness t1 of insulating layer 154A', the second nitrogen concentration of insulating layer 154A is greater than the first nitrogen concentration of insulating layer 154A', the etching rate (e.g., wet etching rate) of insulating layer 154A to a given etchant (e.g., a fluorine-based etchant, such as diluted hydrofluoric acid) is less than the etching rate of insulating layer 154A' to a given etchant, or a combination of the aforementioned characteristics of insulating layer 154A. Figure 4 shows another embodiment of insulating layer 154A' (Before Treatment) and insulating layer 154A (After Treatment), wherein processing step 165 increases the thickness of the bottom insulating layer. In Figure 4, the undoped semiconductor layer 152, insulating layer 154A', and insulating layer 154A have convex top surfaces rather than concave top surfaces. In some embodiments, source / drain structures 150 having these appearances are considered herein.

[0046] Process 165 includes nitrogen heat treatment, such as an annealing process performed in a nitrogen-containing environment. In the illustrated embodiment, the nitrogen-containing environment is N2, and the nitrogen heat treatment is N2 annealing. In some embodiments, the annealing process is rapid thermal annealing (RTA), such as N2 rapid thermal annealing. In some embodiments, the annealing process is peak annealing, such as N2 peak annealing (e.g., peak rapid thermal annealing). In some embodiments, the annealing process is in-furnace annealing, such as N2 in-furnace annealing. Parameters of the annealing process (e.g., annealing temperature, annealing time, annealing environment, pressure, etc.) can be configured to increase the thickness of the insulating layer 154A', increase the nitrogen concentration of the insulating layer 154A', increase the silicon-nitrogen bonds of the insulating layer 154A', reduce the nitrogen-hydrogen bonds of the insulating layer 154A', or a combination thereof. In some embodiments, the annealing temperature is from about 600°C to about 900°C. In some embodiments, the annealing time is from about 1 second to about 5 minutes. In some embodiments, the pressure maintained in the process chamber during annealing is from about 1 to 100 torr. In some embodiments, nitrogen heat treatment heats the device 100, components of the device 100 (e.g., insulating layer 154A'), the surrounding / environment containing the device 100, or a combination thereof, to a temperature (e.g., annealing temperature) to increase the thickness of the insulating layer 154A', the nitrogen concentration in the insulating layer 154A', the silicon-nitrogen bonding in the insulating layer 154A', or a combination thereof. In some embodiments, nitrogen heat treatment introduces (diffuseds) nitrogen into the insulating layer 154A'.

[0047] In some embodiments, the processing step 165 further includes a silicon implantation process, which implants and / or introduces silicon into the insulating layer 154A'. The silicon implantation process can be performed before or after the nitrogen heat treatment. The silicon implantation process can provide the insulating layer 154A with a silicon concentration greater than that of the insulating layer 154A', and / or further reduce the etching rate of the insulating layer 154A to a given etchant (e.g., a fluorine-based etchant, such as diluted hydrofluoric acid) compared to the etching rate of the insulating layer 154A' to a given etchant. Parameters of the silicon implantation process (e.g., implantation energy, implantation dose / concentration, implantation angle (e.g., tilt angle and / or twist angle), implantation temperature, implantation time, implantation environment, pressure, etc.) can be configured to increase the silicon concentration and / or increase the silicon-nitrogen bonds in the insulating layer 154A'. In some embodiments, the silicon implantation energy is from about 3 keV to about 19 keV. In some embodiments, the silicon implantation dose is from about 1 x 10¹⁹ cm⁻² to about 1 x 10²⁰ cm⁻². In some embodiments, after the silicon implantation process, the insulating layer 154A is silicon-rich. In some embodiments, the parameters of the nitrogen heat treatment may depend on whether the processing process 165 also includes the silicon implantation process. For example, when the processing process 165 includes the silicon implantation process, the nitrogen heat treatment can be performed at a higher temperature for a shorter time. In some embodiments, the nitrogen heat treatment can be performed at a temperature of about 800°C to about 950°C for about 1.5 seconds to about 2 seconds. In these embodiments, the nitrogen heat treatment may be a rapid N₂ spike annealing. Furthermore, in these embodiments, the nitrogen heat treatment may introduce a low concentration of oxygen, and the annealing process can be performed in a nitrogen- and oxygen-containing environment. For example, the concentration of oxygen (e.g., O2) in a nitrogen- and oxygen-containing environment can be less than about 500 parts per million (ppm).

[0048] Process 165 provides an insulating layer 154A having a thickness (e.g., thickness t3) of at least 3 nm. In some embodiments, the thickness t3 is from about 3 nm to about 8 nm. For example, the thickness t3 is from about 3.5 nm to about 4.5 nm. The bottom insulating layer having a thickness of at least 3 nm can withstand subsequent processing such that even if the bottom insulating layer is etched and / or thinned during subsequent processing, a sufficient amount of bottom insulating layer remains between the doped semiconductor layer 156A and the underlying undoped semiconductor layer 152 / base 105P', and provides the source / drain structure 150A with sufficient bottom source / drain isolation to suppress and / or prevent leakage current. Reducing source / drain-base leakage current improves the performance of device 100, for example, by improving the transistor gain in device region 102A. In some embodiments, process 165 increases the thickness of the insulating layer by about 0.4 nm to about 1.4 nm (i.e., increases the thickness t1 by about 0.4 nm to about 1.4 nm), such that the thickness t3 is at least 3 nm. In some embodiments, the increased insulation layer thickness (e.g., from about 0.7 nm to about 1.4 nm) resulting from the nitrogen thermal treatment combined with the silicon fabric implantation process is greater than the increased insulation layer thickness (e.g., from about 0.4 nm to about 0.6 nm) resulting from the nitrogen thermal treatment alone. In some embodiments, the thickness t3 of the edge / end portion of the insulation layer 154A is less than the thickness t3 of the center portion of the insulation layer 154A, and at least the thickness t3 of the center portion of the insulation layer 154A is greater than 3 nm. In some embodiments, both the thickness t3 of the edge / end portion of the insulation layer 154A and the thickness t3 of the center portion of the insulation layer 154A are greater than 3 nm. Processing 165 may also provide the insulation layer 154A with a more consistent thickness compared to the insulation layer 154A'. For example, the difference between the thickness t3 of the edge / end portion of the insulation layer 154A and the thickness t3 of the center portion of the insulation layer 154A may be less than the difference between the thickness t1 of the edge / end portion of the insulation layer 154A' and the thickness t1 of the center portion of the insulation layer 154A'. Therefore, process 165 can also improve the bottom source / drain insulation by improving the uniformity of the bottom insulating layer (e.g., by reducing the thickness difference from its center to the edge) (see, for example, Figure 4). In some embodiments, process 165 increases the thickness of the edge / end portion of the bottom source / drain insulating layer to be greater than the thickness of the center portion of the bottom source / drain insulating layer. For example, the difference between the thickness t1 of the edge / end portion of insulating layer 154A' and the thickness t3 of the edge / end portion of insulating layer 154A can be greater than the difference between the thickness t1 of the center portion of insulating layer 154A' and the thickness t3 of the center portion of insulating layer 154A, see, for example, Figure 4.

[0049] Process 165 may also generate, repair, and / or enhance silicon-nitrogen bonds (e.g., Si-N bonds) and reduce nitrogen-hydrogen bonds (e.g., N(-H)x bonds) in insulating layer 154A', such that insulating layer 154A may have more Si-N bonds and fewer NH bonds (e.g., N(-H)x bonds) compared to insulating layer 154A'. Increasing silicon-nitrogen bonds and reducing nitrogen-hydrogen bonds can increase the insulating layer thickness and / or decrease the etch rate of insulating layer 154A to a given etchant compared to the etch rate of insulating layer 154A' to a given etchant, as further described below. In some embodiments, processing process 165 on insulating layer 154A' may provide a wet etch rate of insulating layer 154A to a given etchant (e.g., a fluorine-based etchant, such as diluted hydrofluoric acid) that is about 35% to about 75% lower than the wet etch rate of insulating layer 154A' to a given etchant. For example, the amount of insulating layer 154 Å removed per minute by the etchant (e.g., angstroms (Å)) is less than the amount of insulating layer 154 Å' removed per minute by the etchant. Therefore, the bottom source / drain insulation layer has greater resistance to subsequent processing (i.e., a lower etch rate means less removal of the bottom source / drain insulation layer during subsequent processing), thereby improving the bottom source / drain insulation.

[0050] Referring to Figures 2F and 3C, the fabrication of device 100 may include forming a mask 168 over device regions 102A and 102B. The composition of mask 168 differs from that of source / drain structures 150A (e.g., the insulating layer 154A of source / drain structure 150A), source / drain structures 150B (e.g., the doped semiconductor layer 160B of source / drain structure 150B), semiconductor layer 120, gate structure 130A, gate structure 130B, internal spacer 145, or combinations thereof, to achieve selective removal / etching therebetween. In some embodiments, mask 168 comprises metal and oxygen and / or nitrogen (i.e., mask 168 is a metal oxide mask and / or metal nitride mask). For example, mask 168 may comprise aluminum and oxygen and / or nitrogen, and mask 168 may be an aluminum oxide mask, an aluminum oxynitride mask, or an aluminum nitride mask. In the illustrated embodiment, the mask 168 is an aluminum oxide mask (e.g., an Al2O3 mask). The mask 168 may be a passivation layer over the source / drain structure 150B. The passivation layer protects the source / drain structure 150B when an additional layer is formed for the source / drain structure 150A. For example, the passivation layer may prevent the deposition and / or growth of semiconductor material (e.g., epitaxial material) on the doped semiconductor layer 156B when the doped semiconductor layer 156A is formed in the source / drain recess 140A, prevent unwanted doping of the source / drain structure 150B (e.g., n-type dopant), prevent other alterations and / or defects in the source / drain structure 150B, or combinations thereof.

[0051] It is understood in this embodiment of the invention that the composition and / or quality of the deposited mask 168 may be insufficient to withstand the processing associated with the formation of the additional layer of the source / drain structure 150A. For example, the mask 168 may be damaged and / or undesirably removed / thinned during a pre-cleaning process (e.g., an etching process) of the source / drain recess 140A prior to the formation of the doped semiconductor layer 156A in the source / drain recess 140A. In embodiments where the pre-cleaning process is wet etching, the etching solution (e.g., containing ammonia (NH3) and / or hydrogen fluoride (HF)) may undesirably react with the mask 168, resulting in unwanted etching of the mask 168. This undesirable reaction is particularly common when the mask 168 is an alumina mask, as the etchant (e.g., NH3 and / or HF) may react with the mask 168 (e.g., Al(OH)3 bonds that may be present on its surface) and form (NH4)3AlF6 and venting. In some examples, the etchant may completely remove a portion of the mask 168, exposing the underlying source / drain structure 150B. This can lead to unwanted etching and / or wear of the source / drain structure 150B (e.g., the doped semiconductor layer 160B) and / or undesirable deposition / growth of semiconductor material for device region 102A on the source / drain structure 150B. It has been observed that simply increasing the thickness of the deposition mask 168 to compensate for and / or address thickness reduction, and thus potentially during pre-cleaning processes and / or other processes associated with the formation of the doped semiconductor layer 156A, leaves residual masking material (e.g., aluminum oxide) in the source / drain recess 140A. This residual masking material inhibits the growth and / or deposition of the doped semiconductor layer 156A, thereby reducing source / drain strain.

[0052] This embodiment of the invention therefore proposes a processing step 170 for mask 168. Processing step 170 is configured to modify the composition and / or quality of mask 168, such that mask 168 can better withstand source / drain pre-cleaning processes and / or other subsequent processing. For example, processing step 170 is configured to increase density, reduce hydrogen concentration (e.g., on the surface of mask 168), improve hydrogen bonding, reduce the etch rate (e.g., wet etch rate) for a given etchant (e.g., NH3 and / or HF), or a combination thereof. Increasing the density of mask 168, reducing the hydrogen content of mask 168, and / or improving hydrogen bonding can reduce the etch rate of mask 168 for a given etchant (compared to the etch rate of mask 168 without processing). In some embodiments, processing step 170 on mask 168 reduces the hydrogen concentration (H%) of mask 168 by more than about 20%. In some embodiments, the mask 168 is processed by process 170 such that the density of the mask 168 is increased by more than about 2%. In some embodiments, the mask 168 is processed by process 170 such that the wet etching rate of the mask 168 to a given etchant (e.g., NH3 and / or HF) is reduced by more than about 10%. For example, the amount of processed mask 168 removed per minute (e.g., Å) by the etchant is less than the amount of unprocessed mask 168 removed per minute by the etchant. Therefore, the mask 168 has greater etch resistance to source / drain pre-cleaning processes and / or other processes associated with the additional layers forming the source / drain structure 150A, thereby reducing and / or preventing wear of the mask 168 and damage to the source / drain structure 150B.

[0053] Process 170 includes nitrogen heat treatment, such as an annealing process performed in a nitrogen-containing environment. In the illustrated embodiment, the nitrogen-containing environment is N2, and the nitrogen-containing heat treatment is N2 annealing. In some embodiments, the annealing process is rapid thermal annealing, such as N2 rapid thermal annealing. In some embodiments, the annealing process is peak annealing, such as N2 peak annealing (e.g., peak rapid thermal annealing). In some embodiments, the annealing process is in-furnace annealing, such as N2 in-furnace annealing. Configurable annealing process parameters (e.g., annealing temperature, annealing time, annealing environment, pressure, etc.) can be used to increase the density of the mask 168, reduce the hydrogen concentration of the mask 168 (e.g., on the surface of the mask 168), improve hydrogen bonding in the mask 168 (e.g., improve the strength of hydrogen bonding in and / or on the surface of the mask 168, which may slow down the reaction of the etchant (e.g., NH3 and / or HF) with the hydrogen components of the mask 168 (e.g., Al(OH)3 bonds), thereby slowing down the removal of hydrogen and a portion of the mask 168), or a combination thereof. In some embodiments, nitrogen heat treatment heats the device 100, components of the device 100 (e.g., the mask 168), the surrounding / environment containing the device 100, or a combination thereof to a temperature (e.g., the annealing temperature). In some embodiments, nitrogen heat treatment introduces (diffuses) nitrogen into the mask 168. In some embodiments, the annealing temperature is from about 600°C to about 900°C. While such a high annealing temperature (e.g., greater than about 700°C) reduces the thickness of the mask 168, the increased density achieved through this high annealing temperature significantly improves the composition of the mask 168, making it more resistant to pre-cleaning processes and / or other subsequent processes. In some embodiments, the annealing time is from about 1 second to about 5 minutes. In some embodiments, the pressure maintained in the process chamber during nitrogen heat treatment is from about 1 tor to about 100 tor.

[0054] Referring to Figures 2G and 3D, the mask 168 is removed from the device region 102A through a patterning process, thereby exposing the source / drain notch 140A (e.g., exposing the insulating layer 154A). For example, the mask 168 has an opening 169 therein, which overlaps with the device region 102A, such that the mask 168 covers the device region 102B (e.g., a p-type transistor region) but does not cover the device region 102A (e.g., an n-type transistor region). The patterning process may include performing a photolithography process to form a patterned photoresist layer that covers the mask 168 above the device region 102B and exposes the mask 168 above the device region 102A (e.g., the patterned photoresist layer has an opening therein that overlaps with the device region 102A), and performing an etching process to selectively remove the exposed mask 168. In the illustrated embodiment, the etching process is configured to selectively remove the mask 168 (e.g., nitrogen-treated alumina material), while negligibly (or even not at all) etching the source / drain structure 150A (e.g., the insulating layer 154A of the source / drain structure 150A (e.g., nitrogen-treated silicon nitride material)), gate structure 130A, substrate isolation structure 125, or combinations thereof. The etching process can be dry etching, wet etching, other suitable etching, or combinations thereof. For example, the etching process can be wet etching using a hydrofluoric acid (HF) solution or a diluted hydrofluoric acid (DHF) solution. As described above, since the insulating layer 154A (e.g., nitrogen-treated silicon nitride material) has become thicker through the processing process 165 and / or the NH bonds (e.g., N(-H)x bonds) in the insulating layer 154A have been reduced through the processing process 165, the insulating layer 154A has greater resistance to wet etching, allowing the insulating layer 154A to be etched (or negligibly) by wet etchants (e.g., diluted hydrofluoric acid solution). For example, an HF-based etchant can react with the Si-N bonds and / or NH bonds (e.g., N(-H)x bonds) of the insulating layer 154A to break its Si-N bonds and replace the Si-NH2 bonds with Si-F bonds, thereby slightly etching and / or modifying the insulating layer 154A. However, because insulating layer 154A has fewer NH bonds (e.g., N(-H)x bonds) than insulating layer 154A', HF-based etchants are less likely to react with insulating layer 154A, disrupt Si-N bonds, and replace Si-NH2 bonds with Si-F bonds. Furthermore, since insulating layer 154A is at least 3 nm thick, it can withstand some etching while remaining thick enough to provide sufficient bottom source / drain insulation. Therefore, due to the source / drain fabrication process described herein using process 165, any removal of insulating layer 154A is negligible, and insulating layer 154A can still provide bottom source / drain insulation to reduce / prevent leakage current.

[0055] Referring to Figures 2G and 3E, a doped semiconductor layer 156B may be formed in a source / drain recess 140B above an insulating layer 154B and / or an undoped semiconductor layer 152, while a mask 168 (e.g., a nitrogen-doped alumina mask) covers the device region 102B. The doped semiconductor layer 156A fills the remaining portion of the source / drain recess 140A and is coupled to the edge / end portion of the semiconductor layer 120 in the device region 102A. In the illustrated embodiment, the doped semiconductor layer 156A includes a doped semiconductor layer 158A and a doped semiconductor layer 160A. A doped semiconductor layer 158A may be formed above semiconductor layer 120 (e.g., above the sidewalls and / or ends of semiconductor layer 120) and partially fills the source / drain recess 140A. A doped semiconductor layer 160A may be formed above doped semiconductor layer 158A and / or insulating layer 154A and fills the remaining portion of the source / drain recess 140A. Doped semiconductor layer 160A is separated from semiconductor layer 120 through doped semiconductor layer 158A and separated from undoped semiconductor layer 152 through insulating layer 154A. In the illustrated embodiment, doped semiconductor layer 158A is discontinuous and formed by discrete and spaced portions, with each doped semiconductor layer 158A disposed at the end of the corresponding semiconductor layer 120, meaning that portions of doped semiconductor layers 158A disposed on adjacent semiconductor layers 120 are not connected to each other. In these embodiments, a doped semiconductor layer 160A may surround a doped semiconductor layer 158A, and the doped semiconductor layer 160A may extend to an internal spacer wall 145. In some embodiments, discrete and spaced portions of one or more doped semiconductor layers 158A may surround a semiconductor layer 120, such that the discrete and spaced portions are formed over the top and / or bottom of a corresponding semiconductor layer 120. In some embodiments, the discrete and spaced portions extend over and / or to the internal spacer wall 145. In some embodiments, the discrete and spaced portions of one or more doped semiconductor layers 158A are connected such that the doped semiconductor layer 158A may form a sidewall of a source / drain structure 150A above a base 105P', and / or the doped semiconductor layer 160A may be spaced from the internal spacer wall 145 through the doped semiconductor layer 158A.

[0056] Doped semiconductor layer 158A and doped semiconductor layer 160A comprise silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, doped semiconductor layer 158A and doped semiconductor layer 160A comprise the same semiconductor material but have different concentrations. For example, doped semiconductor layer 158A and doped semiconductor layer 160A may comprise silicon and n-type dopants (e.g., phosphorus and / or arsenic) but have different n-type dopant concentrations. In some embodiments, doped semiconductor layer 158A has a smaller n-type dopant concentration (e.g., P%) than doped semiconductor layer 160A, which can reduce crystal dislocations, reduce other crystal defects, maximize strain (and thus enhance carrier mobility, and thus increase drive current), or combinations thereof. In some embodiments, doped semiconductor layer 158A has an n-type dopant concentration (e.g., phosphorus concentration) of about 1 x 10²⁰ cm⁻³ to about 5 x 10²⁰ cm⁻³, and doped semiconductor layer 160A has an n-type dopant concentration (e.g., phosphorus concentration) of about 5 x 10²⁰ cm⁻³ to about 2 x 10²¹ cm⁻³. In these embodiments, doped semiconductor layer 160A may be referred to as a heavily doped semiconductor layer, and doped semiconductor layer 158A may be referred to as a lightly doped semiconductor layer. In some embodiments, doped semiconductor layer 158A and doped semiconductor layer 160A have different semiconductor materials, which may have the same or different component concentrations. In some embodiments, doped semiconductor layer 156A includes a material and / or dopants that provide the desired tensile stress in the channel region (e.g., semiconductor layer 120) of device region 102A.

[0057] The doped semiconductor layer 158A may be deposited on and / or grown from the semiconductor layer 120, and the doped semiconductor layer 160A may be deposited on and / or grown from the doped semiconductor layer 158A. In some embodiments, the doped semiconductor layer 158A and the doped semiconductor layer 160A are formed through individual selective epitaxial growth processes. The selective epitaxial growth process may be a chemical vapor deposition technique (e.g., vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), low-pressure chemical vapor deposition (LPCVD), plasma-assisted chemical vapor deposition (PECVD), or similar methods), molecular beam epitaxy, other suitable selective epitaxial growth processes, or combinations thereof. The selective epitaxial growth process may use gaseous and / or liquid precursors that react with the composition of the semiconductor layer 120, the doped semiconductor layer 158A, or combinations thereof. Epitaxial growth / deposition conditions, such as those described herein, are adjusted to selectively deposit (grow) semiconductor materials (e.g., silicon) on semiconductor surfaces (e.g., semiconductor layer 120 and / or doped semiconductor layer 158A), while limiting (or preventing) the growth of semiconductor materials from dielectric surfaces and / or non-semiconductor surfaces (e.g., internal spacer 145, dummy gate stack 132, gate spacer 134, and / or substrate isolation structure 125). In some embodiments, doped semiconductor layers 158A and / or doped semiconductor layers 160A are doped during deposition (i.e., in-situ doping), for example, by adding dopants to the source material of a selective epitaxial growth process. In some embodiments, doped semiconductor layers 158A and / or doped semiconductor layers 160A are doped after deposition, for example, through an ion implantation process. In some embodiments, annealing is performed to activate the dopants in doped semiconductor layers 158A, doped semiconductor layers 160A, other source / drain regions (e.g., source / drain junction implantation regions), or combinations thereof.

[0058] In some embodiments, the source / drain recess 140A is etched, for example, pre-cleaned, before forming the doped semiconductor layer 156A in the source / drain recess 140A. For example, the etching process may be wet etching using NH3 solution and / or HF solution. As described above, since the mask 168 (e.g., nitrogen-treated alumina material) has become denser through the processing process 170, the hydrogen content (H%) in the mask 168 has been reduced through the processing process 170, and / or the hydrogen bonds in the mask 168 have been improved through the processing process 170 (e.g., the hydrogen bond strength in the mask 168 and / or at the surface of the mask 168 is greater), the mask 168 has greater resistance to wet etching, so that the mask 168 is not (or negligibly) etched by the wet etchant (e.g., NH3+HF solution). For example, NH3-based and / or HF-based etchants can react with the hydrogen components (e.g., Al(OH)3 bonds) of mask 168, thereby slightly etching and / or altering mask 168. However, because the treated mask 168 is denser, has less hydrogen content, and has stronger hydrogen bonds, the etching reaction can occur less and / or more slowly, thereby reducing any etching / removal of mask 168. Therefore, since the source / drain manufacturing process of this embodiment of the invention performs process 170, any removal of mask 168 is negligible, and mask 168 can still provide sufficient passivation and protection for source / drain structure 150B, thereby preventing or reducing any wear and tear of source / drain structure 150B during the formation of source / drain structure 150A.

[0059] Referring to Figures 2H and 3F, after forming an additional layer of the source / drain structure 150A through any suitable process (e.g., etching), the mask 168 can be removed. In the illustrated embodiment, the etching process is configured to selectively remove the mask 168 (e.g., nitrogen-doped alumina material) while ignoring (or even not etching) the source / drain structure 150A, source / drain structure 150B, gate structure 130A, gate structure 130B, substrate isolation structure 125, or combinations thereof. The etching process can be dry etching, wet etching, other suitable etching, or combinations thereof, and the etching process can use an etchant that is the same as or different from the etchant used to pattern the mask 168 (i.e., when a portion of the mask 168 is removed to expose the device region 102A in Figures 2G and 3D). In the illustrated embodiment, a different etchant is used to remove the mask 168 from the device region 102B. For example, the etching process can use a sulfur peroxide mix (SPM) solution (i.e., a mixture of H2SO4 and H2O2).

[0060] Referring to Figure 2I, the fabrication of device 100 may include forming a dielectric layer 175 over source / drain structure 150 and substrate isolation structure 125. Dielectric layer 175 may fill the space between adjacent gate structures, such as the space between gate spacer 134 of gate structure 130A and gate spacer 134 of gate structure 130B, and the space between adjacent source / drain structures 150. The formation of dielectric layer 175 may include depositing a contact etch stop layer (CESL), depositing an interlayer dielectric (ILD) over the CESL, and performing chemical mechanical polishing and / or planarization processes until reaching the dummy gate stack 132. The planarization process may partially remove the dummy gate stack 132, such as the hard mask 138 of the dummy gate stack 132, to expose the underlying dummy gate 136 (e.g., a polysilicon gate). The planarization process can reduce the height of the dummy gate stack 132 and / or the gate gap wall 134.

[0061] The interlayer dielectric comprises a dielectric material, which includes, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethyl orthosilicate (TEOS), borosilicate glass, phosphosilicate glass, borosilicate phosphosilicate glass, fluorosilicate glass, degel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB)-based dielectric materials, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the interlayer dielectric layer comprises a low dielectric constant dielectric material having a dielectric constant smaller than that of silicon dioxide (e.g., k < 3.9). In some embodiments, the interlayer dielectric layer comprises a dielectric material having a dielectric constant of less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as porous silicon dioxide, silicon carbide, carbon-doped oxides (e.g., SiCOH-based materials having, for example, Si-CH3 bonds), or combinations thereof, with each material adjusted / configured to achieve a dielectric constant of less than about 2.5. The contact etch stop layer comprises a material different from that of the interlayer dielectric layer, for example, a dielectric material different from that of the interlayer dielectric layer. For instance, the interlayer dielectric layer may comprise silicon and carbon, both low-k dielectric materials, while the contact etch stop layer may comprise silicon and nitrogen, such as silicon nitride or silicon oxynitride. The interlayer dielectric layer and / or the contact etch stop layer may have a multilayer structure and / or comprise multiple dielectric materials.

[0062] Next, a gate replacement process can be performed to replace the dummy gate 136 with gate stacks 180A and 180B. For example, the dummy gate 136 is removed to form a gate opening (formed between gate spacer 134 and / or internal spacer 145), which exposes a channel region of the multilayer stack 110 (e.g., semiconductor layer 120 and sacrificial layer 115). In some embodiments, the etching process may selectively remove the dummy gate 136 relative to dielectric layer 175, gate spacer 134, internal spacer 145, sacrificial layer 115, semiconductor layer 120, or a combination thereof. In other words, the etching process removes the dummy gate 136 while negligibly (or even not at all) removing dielectric layer 175, gate spacer 134, internal spacer 145, sacrificial layer 115, semiconductor layer 120, or a combination thereof. The etching process may be dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the dielectric layer 175 and / or the gate spacer 134.

[0063] During the gate replacement process, before forming the gate stacks 180A and 180B in the gate openings, a channel release process may be performed to form suspended channel layers. For example, the sacrificial layer 115 exposed by the gate openings may be selectively removed to form air gaps between the semiconductor layers 120 and between the semiconductor layer 120 and the substrate 105P', thereby suspending the channel layers in the channel regions. In the illustrated embodiment, each channel region has three suspended channel layers, which are also referred to as channel layers 120' after suspension. The channel layers 120' are stacked vertically along the z-direction to provide three channels through which current can flow between the corresponding source / drain structures 150 during transistor operation of the device 100. In some embodiments, the etching process selectively etches the sacrificial layer 115 while minimizing (or even eliminating) etching of the semiconductor layer 120, the substrate 105P', the gate spacer wall 134, the internal spacer wall 145, the dielectric layer 175, or combinations thereof. In some embodiments, the etchant used in the etching process is selected such that the etching rate of silicon germanium (i.e., sacrificial layer 115) is faster than the etching rate of silicon (i.e., semiconductor layer 120 and substrate 105P') and dielectric materials (i.e., gate spacer 134, internal spacer 145, and / or dielectric layer 175) (i.e., the etchant has high etch selectivity for silicon germanium). The etching process may be dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, an oxidation process may be performed prior to the etching process to transform the sacrificial layer 115 into a silicon germanium oxide component, wherein the etching process removes the silicon germanium oxide component. In some embodiments, the etching process may be performed during and / or after the removal of the sacrificial layer 115 to alter the contour of the semiconductor layer 120 to achieve a target size and / or target shape for the channel layer 120'.

[0064] Next, gate stacks 180A and 180B of gate structure 130A and gate structure 130B may be formed in the gate opening. Gate stacks 180A and 180B (also referred to as high dielectric constant / metallic gates) are disposed between corresponding gate spacer walls 134, between corresponding internal spacer walls 145, between corresponding channel layers 120', and between corresponding channel layers 120' and corresponding bases 105P'. In the illustrated embodiment, the device 100 includes a fully wound gate transistor, for example, in the YZ plane, gate stacks 180A and 180B may surround the corresponding channel layer 120'. In some embodiments, gate stacks 180A and 180B may surround and / or partially surround the corresponding channel layer 120' (i.e., disposed on at least both sides of the channel layer 120'), for example, where the device 100 includes a fork-sheet transistor.

[0065] Gate stack 180A includes gate dielectric 182A, and gate stack 180B includes gate dielectric 182B. Gate dielectric 182A and gate dielectric 182B are disposed on a corresponding channel layer 120', a corresponding internal spacer 145, a corresponding gate spacer 134, a substrate isolation structure 125, or a combination thereof. The composition and / or configuration of gate dielectric 182A and gate dielectric 182B may be the same or different. For example, the composition and / or configuration of gate dielectric 182A may differ from the composition and / or configuration of gate dielectric 182B, for example, where device regions 102A and 102B are configured for different types of transistors. Gate dielectric 182A and gate dielectric 182B each include at least one dielectric layer, such as an interface layer and / or a high dielectric constant dielectric layer. The interface layer contains dielectric materials such as SiO2, SiGeOx, HfSiO, SiON, other dielectric materials, or combinations thereof. The high dielectric constant dielectric layer contains a high dielectric constant dielectric material, which refers to a dielectric material with a dielectric constant greater than that of silicon dioxide, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3(BTO), (Ba,Sr)TiO3(BST), HfO2-Al2O3, other high dielectric constant dielectric materials, or combinations thereof. In some embodiments, gate dielectric 182A and gate dielectric 182B each comprise a hafnium oxide (e.g., HfO2) layer and / or a zirconium oxide (e.g., ZrO2) layer.

[0066] Furthermore, gate stack 180A includes a gate electrode 184A disposed above gate dielectric 182A, and gate stack 180B includes a gate electrode 184B disposed above gate dielectric 182B. The composition and / or configuration of gate electrode 184A and gate electrode 184B may be the same or different. For example, the composition and / or configuration of gate electrode 184A may differ from the composition and / or configuration of gate electrode 184B, for example, where device regions 102A and 102B are configured for different types of transistors. In some embodiments, gate electrode 184A and gate electrode 184B each include a conductive layer formed of a conductive material, such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the conductive layer includes a work function layer, which can be adjusted to have a desired work function (e.g., an n-type work function or a p-type work function). The work function layer includes a work function metal and / or an alloy of work function metals, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. In some embodiments, the conductive layer includes a bulk layer above the gate dielectric and / or the work function layer. The bulk layer may include Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metals and / or alloys of other suitable metals, or combinations thereof. In some embodiments, the conductive layer includes a barrier layer above the work function layer and / or the gate dielectric. The barrier layer comprises a material that can prevent the diffusion and / or reaction of components between adjacent layers and / or promote adhesion between adjacent layers (e.g., between a work function layer and a bulk layer). In some embodiments, the barrier layer comprises a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides, or combinations thereof.

[0067] Gate stacks 180A and 180B are configured to perform the desired functions according to the design requirements of device 100, and gate stacks 180A and 180B may have different layers in different device regions depending on their configuration. For example, the number, configuration, material, or combination of the layers of gate dielectric 182A and / or gate electrode 184A corresponding to device region 102A (e.g., n-type transistor region) may differ from the number, configuration, material, or combination of the layers of gate dielectric 182B and / or gate electrode 184B corresponding to device region 102B (e.g., p-type transistor region). Forming gate stacks 180A and 180B may involve depositing gate dielectric material (e.g., an interface layer, a high dielectric constant dielectric layer, etc.), partially filling the gate opening with the gate dielectric material, depositing gate electrode material (e.g., a work function layer, a barrier layer, a bulk layer, etc.) to fill the remaining portion of the gate opening, and performing a planarization process to remove the portion of the gate dielectric material and / or gate electrode material above the dielectric layer 175. Gate stacks 180A and 180B of gate structure 130A and gate structure 130B may be formed simultaneously, partially simultaneously, or individually. For example, gate dielectric 182A and gate dielectric 182B (or the aforementioned sublayers) may be formed simultaneously. In another example, the bulk layers of gate electrodes 184A and 184B may be formed simultaneously, while the work function layers (or the aforementioned sublayers) of gate electrodes 184A and 184B may be formed individually. Although the illustrated embodiments manufacture gate stacks 180A and 180B according to a gate-after process, embodiments in which the metal gate stack of device 100 can be manufactured according to a gate-before process or a hybrid gate-after / gate-before process are considered herein.

[0068] Fabrication of device 100 may further include etching back gate stacks 180A and 180B, and forming a hard mask (e.g., a self-aligning cap structure) over the etched-back gate stacks 180A and 180B. The hard mask comprises a material different from dielectric layer 175 and / or subsequently formed dielectric layers to achieve etch selectivity. In some embodiments, the hard mask comprises silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon oxynitride, silicon oxynitride, or combinations thereof. In some embodiments, the hard mask comprises a metal and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, hafnium oxide, hafnium aluminum oxide, or combinations thereof.

[0069] The device may include various transistors, such as an n-type transistor in device region 102A and a p-type transistor in device region 102B. The n-type transistor may include a corresponding channel (e.g., channel layer 120'), a source / drain (e.g., source / drain structure 150A), and a corresponding gate (e.g., gate stack 180A). The gate stack 180A is disposed along the x-direction between the corresponding source / drain (e.g., source / drain structure 150A), and an internal spacer wall 145 is disposed between the gate stack 180A and its corresponding source / drain. Furthermore, the gate stack 180A connects the corresponding channel (e.g., channel layer 120') and the corresponding channel extending along the x-direction between the corresponding source / drain (e.g., source / drain structure 150A). Gate stacks 180A may surround their corresponding channel layers, and along the gate longitudinal direction, each gate may include a gate dielectric (e.g., gate dielectric 182A) and a gate electrode (e.g., gate electrode 184A) surrounding its corresponding channel. Furthermore, in the illustrated embodiment, the n-type transistor includes bottom source / drain insulation (e.g., insulating layer 154A and undoped semiconductor layer 152), which isolates and / or isolates the source / drain structure 150A from the underlying substrate (e.g., substrate 105, base 105', base 105P', or a combination thereof). This reduces and / or eliminates leakage current into the underlying substrate, such as leakage current flowing from the source / drain. Reducing and / or eliminating unwanted leakage current improves overall transistor performance. As described herein, because the source / drain manufacturing process described herein uses process 165, the provided n-type transistor has improved bottom source / drain insulation, thereby improving leakage current suppression.

[0070] A p-type transistor may include a corresponding channel (e.g., channel layer 120'), a source / drain (e.g., source / drain structure 150B), and a corresponding gate (e.g., gate stack 180B). The gate stack 180B is disposed along the x-direction between the corresponding source / drain (e.g., source / drain structure 150B), and an internal spacer 145 is disposed between the gate stack 180B and its corresponding source / drain. Furthermore, the gate stack 180B connects the corresponding channel (e.g., channel layer 120') and the corresponding channel extending along the x-direction between the corresponding source / drain (e.g., source / drain structure 150B). The gate stack 180B may surround its corresponding channel layer, and along the longitudinal direction of the gate, each gate may include a gate dielectric (e.g., gate dielectric 182B) and a gate electrode (e.g., gate electrode 184B) surrounding its corresponding channel. Furthermore, in the illustrated embodiment, the p-type transistor includes bottom source / drain insulation (e.g., insulating layer 154B and undoped semiconductor layer 152), which isolates and / or isolates the source / drain structure 150B from the underlying substrate (e.g., substrate 105, base 105', base 105P', or a combination thereof). This reduces and / or eliminates leakage current into the underlying substrate, such as leakage current that could flow from the source / drain into the underlying substrate. Reducing and / or eliminating unwanted leakage current improves overall transistor performance.

[0071] Due to the source / drain manufacturing process described herein, the composition and / or configuration of the bottom source / drain insulation of an n-type transistor may differ from that of a p-type transistor. For example, the composition and / or configuration of insulating layer 154A may differ from that of insulating layer 154B. In some embodiments, the nitrogen concentration of insulating layer 154A is greater than that of insulating layer 154B. In some embodiments, the silicon concentration of insulating layer 154A is greater than that of insulating layer 154B. In some embodiments, the thickness of insulating layer 154A is greater than that of insulating layer 154B, for example, insulating layer 154A undergoes processing 165, but insulating layer 154B does not undergo processing 165. In some embodiments, insulating layers 154A and 154B are formed of the same material (e.g., silicon nitride). In some embodiments, insulating layers 154A and 154B are formed of different materials. Furthermore, due to the source / drain fabrication process described herein, the source / drain structure 150B may have an insulating layer 154A disposed above the doped semiconductor layer 156B (e.g., a doped semiconductor layer 160B of the doped semiconductor layer 156B), and the doped semiconductor layer 160B may be disposed between nitride layers with different nitrogen concentrations, for example, the nitrogen concentration of the insulating layer 154A is greater than that of the insulating layer 154B. In these embodiments, the thickness of the insulating layer 154A of the source / drain structure 150A may be greater than the thickness of the insulating layer 154A of the source / drain structure 150B. Furthermore, in these embodiments, after the source / drain contact is formed, a residual portion of the insulating layer 154A may remain between the dielectric layer 175 and the doped semiconductor layer 160B. In some embodiments, when the insulating layer 154A is formed and / or the insulating material formed above the source / drain structure 150B is removed, the shielding device region 102B is shielded so that the p-type transistor does not contain the insulating layer 154A above the doped semiconductor layer 156B.

[0072] In some embodiments, the fabrication of device 100 may include replacing sacrificial layer 115 with a different sacrificial layer after forming source / drain notches 140 and before forming internal spacer walls 145. In these embodiments, after forming source / drain notches 140, the fabrication of device 100 may include performing an etching process to selectively remove the sacrificial layer 115 exposed by the source / drain notches 140, thereby forming a gap in the channel region, and after removing the sacrificial layer 115, the semiconductor layer 120 remaining in the channel region provides a channel layer 120' suspended above the substrate 105P'. The etching process may selectively remove the sacrificial layer 115 relative to the substrate 105, semiconductor layer 120, gate structure 130A, gate structure 130B, or a combination thereof. In some embodiments, the etchant used in the etching process is selected such that the etching rate of silicon germanium (e.g., sacrificial layer 115) is greater than the etching rate of silicon (e.g., semiconductor layer 120 and substrate 105') and dielectric material (e.g., gate spacer 134 and hard mask 138). The etching process may be dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, an oxidation process may be performed prior to the etching process to transform the sacrificial layer 115 into a semiconductor oxide layer (e.g., silicon germanium oxide). In these embodiments, the etching process removes the semiconductor oxide layer to form gaps.

[0073] In these embodiments, the fabrication of device 100 may then include forming a second sacrificial layer in the gap before forming the internal spacer wall 145. The composition of the second sacrificial layer differs from that of the channel layer 120' to achieve etch selectivity. For example, the second sacrificial layer and the channel layer 120' may contain different materials, atomic percentages of components, weight percentages of components, other properties, or combinations thereof. In some embodiments, the second sacrificial layer may contain a dielectric material, which may contain silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof. For example, the dielectric material may contain oxygen, and the second sacrificial layer may be an oxide layer (which may be referred to as dummy oxide interposers (DOIs)). In some embodiments, the dummy oxide interposers may be a silicon oxide layer.

[0074] In some embodiments, a second sacrificial layer is formed by depositing a dielectric layer over device 100 and then etching the dielectric layer, such that the dielectric layer is removed from the source / drain region of device 100 but not from the channel region. In some embodiments, the deposited dielectric layer may fill gaps. In some embodiments, the dielectric layer is formed by a compliant deposition process and has a compliant thickness. In some embodiments, etching may remove exposed portions of the dielectric layer (e.g., portions that do not fill gaps), such as portions of the dielectric layer disposed on the sidewalls of channel layer 120', the sidewalls of base 105P', the surface of base 105' forming the bottom of source / drain recess 140, the sidewalls and top of gate gap wall 134, and the top of dummy gate stack 132 (e.g., the hard mask 138 of dummy gate stack 132). The dielectric material may be removed by dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the second sacrificial layer (e.g., a dielectric layer) is formed through an oxidation process, such as a thermal oxidation process. In some embodiments, the second sacrificial layer is formed through atomic layer deposition (ALD), plasma-assisted chemical vapor deposition (PECVD), other suitable deposition processes, or a combination thereof.

[0075] In these embodiments, in Figure 2B, the first etching process performed when forming the internal spacer wall 145 may selectively etch the second sacrificial layer, while the etching of the semiconductor layer 120, the substrate 105P', the dummy gate stack 132 (e.g., the hard mask 138 of the dummy gate stack 132), the gate spacer wall 134, the substrate isolation structure 125, or combinations thereof may be negligible (or even nonexistent). Furthermore, in these embodiments, in Figure 2I, the fabrication of the device 100 may include removing the second sacrificial layer instead of the sacrificial layer 115, thereby forming a gap (opening) exposing the channel layer 120'. Thus, the gate opening extends between the channel layers 120' and between the channel layer 120' and the substrate 105P'. In these embodiments, the etching process removes the second sacrificial layer, while the removal of the channel layer 120', the internal spacer wall 145, the gate spacer wall 134, the dielectric layer 175, or combinations thereof may be negligible (or even nonexistent). For example, the etchant used in the etching process is selected such that the etching rate of a dielectric material having a first composition (e.g., a second sacrificial layer) is greater than the etching rate of silicon (e.g., channel layer 120') and dielectric materials having a composition different from the first composition (e.g., internal spacer 145, gate spacer 134, dielectric layer 175, etc.), that is, the etchant has high etching selectivity relative to the dielectric material having the first composition. The etching process is dry etching, wet etching, other suitable etching, or a combination thereof.

[0076] Introducing a second sacrificial layer into the fabrication of apparatus 100 can increase the thermal budget margin associated with the fabrication apparatus 100. For example, when the sacrificial layer 115 is a semiconductor layer (e.g., a silicon-germanium layer), the temperature used when forming source / drain structures 150A and / or source / drain structures 150B can be limited to a lower temperature to avoid undesirable diffusion and / or mixing of the components of sacrificial layer 115 (e.g., germanium) with semiconductor layer 120. When forming source / drain structures 150A and / or source / drain structures 150B, replacing sacrificial layer 115 with sacrificial oxide layers eliminates mixing problems (e.g., because these layers will not contain germanium) and allows for the use of higher temperatures, thereby enabling the use of a wider temperature range and increasing process flexibility.

[0077] This document provides numerous different embodiments, with exemplary methods including forming a source / drain recess; forming an insulating layer that partially fills the source / drain recess; treating the insulating layer with a nitrogen thermal treatment; and forming a doped semiconductor layer over the treated insulating layer. The insulating layer is formed at the bottom of the source / drain recess, and the doped semiconductor layer fills the remaining portion of the source / drain recess. In some embodiments, this method includes treating the insulating layer with a silicon implantation process prior to forming the doped semiconductor layer. In some embodiments, this method includes adjusting the parameters of the nitrogen thermal treatment to increase the thickness of the insulating layer to at least 3 nm. In some embodiments, this method includes adjusting the parameters of the nitrogen thermal treatment to reduce the etch rate of the insulating layer to a fluorine-based etchant. In some embodiments, this method includes forming an undoped semiconductor layer in the bottom of the source / drain recess prior to forming the insulating layer. In these embodiments, the insulating layer is formed over the undoped semiconductor layer, and the undoped semiconductor layer partially fills the source / drain recess.

[0078] In some embodiments, the step of forming an insulating layer includes forming a nitride layer, and the nitrogen thermal treatment is N2 annealing. In some embodiments, the nitrogen thermal treatment is a first nitrogen thermal treatment, and this method further includes forming a metal oxide mask over the treated insulating layer; treating the metal oxide mask with a second nitrogen thermal treatment; and removing the metal oxide mask before forming the doped semiconductor layer. In some embodiments, the step of forming the metal oxide mask includes forming an aluminum oxide mask, and the second nitrogen thermal treatment is N2 annealing. In some embodiments, the source / drain notch is located in a first device region, and this method includes forming a metal oxide mask over a source / drain structure, the source / drain structure being disposed in a second device region different from the first device region; removing the metal oxide mask from over the treated insulating layer before forming the doped semiconductor layer; and removing the metal oxide mask from over the source / drain structure after forming the doped semiconductor layer.

[0079] Another exemplary method includes forming a first source / drain recess in a first device region; forming a second source / drain recess in a second device region; forming a first source / drain structure in the first source / drain recess; and forming a second source / drain structure in the second source / drain recess. The step of forming the second source / drain structure includes forming an insulating layer in the second source / drain recess; forming a mask over the first source / drain structure after performing a first nitrogen thermal treatment on the insulating layer; and forming a doped semiconductor layer over the insulating layer after performing a second nitrogen thermal treatment on the mask. In some embodiments, this method includes performing a silicon implantation process on the insulating layer before forming the mask over the first source / drain structure. In some embodiments, the step of performing the first nitrogen thermal treatment includes increasing the thickness of the insulating layer. In some embodiments, the step of performing the first nitrogen thermal treatment includes performing a first N2 annealing, and the step of performing the second nitrogen thermal treatment includes performing a second N2 annealing.

[0080] In some embodiments, the first device region is a p-type transistor region and the second device region is an n-type transistor region. In some embodiments, the step of forming a mask includes: depositing an aluminum oxide layer over a first source / drain structure in the first device region and over an insulating layer in the second device region; and removing the aluminum oxide layer from the insulating layer in the second device region after performing a second nitrogen thermal treatment.

[0081] In some embodiments, the insulating layer is a first insulating layer; when the first insulating layer is formed, the first device region is unshielded, and the method includes forming a second insulating layer over the first source / drain structure when the first insulating layer is formed. In some embodiments, the insulating layer is a first insulating layer; the doped semiconductor layer is a first doped semiconductor layer. In these embodiments, the step of forming the first source / drain structure includes: forming a second insulating layer in the first source / drain recess; and forming a second doped semiconductor layer over the second insulating layer, wherein the second insulating layer is not subjected to nitrogen thermal treatment prior to forming the second doped semiconductor layer.

[0082] An exemplary device structure includes a first type of transistor (e.g., a p-type transistor) and a second type of transistor (e.g., an n-type transistor). The first type of transistor includes a first source / drain structure having a first insulating layer and a first doped epitaxial layer disposed on the first insulating layer. The second type of transistor includes a second source / drain structure having a second insulating layer and a second doped epitaxial layer disposed on the second insulating layer. The nitrogen concentration of the second insulating layer is greater than the nitrogen concentration of the first insulating layer, and the thickness of the second insulating layer is at least 3 nm. In some embodiments, the first source / drain structure further includes a third insulating layer, the first doped epitaxial layer being disposed between the third insulating layer and the first insulating layer, and the nitrogen concentration of the third insulating layer is greater than the nitrogen concentration of the first insulating layer. In some embodiments, the thickness of the third insulating layer is less than the thickness of the second insulating layer.

[0083] The foregoing outlines features of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments of the present invention. [Simplified Explanation of the Diagram]

[0006] The embodiments of the present invention can be better understood from the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Figure 1 is a flowchart of a method for manufacturing part or all of a source / drain structure having bottom insulation according to various aspects of the present invention. Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, and 2I are partial or complete cross-sectional schematic diagrams of the apparatus at various manufacturing stages of the method in Figure 1 according to various aspects of the present invention. Figures 3A, 3B, 3C, 3D, 3E, and 3F are partial or complete perspective views of the apparatus at various manufacturing stages of the method in Figure 1 according to various aspects of the present invention. Figure 4 provides a partial or complete cross-sectional schematic diagram of a source / drain structure having an untreated bottom insulation layer and a treated bottom insulation layer according to various aspects of the present invention.

Claims

1. A method of forming a semiconductor device structure, comprising: forming a source / drain recess; forming an insulating layer that partially fills the source / drain recess, wherein the insulating layer is formed at the bottom of the source / drain recess; treating the insulating layer with a nitrogen thermal treatment; and forming a doped semiconductor layer over the treated insulating layer, wherein the doped semiconductor layer fills the remaining portion of the source / drain recess, wherein the insulating layer extends continuously from the left edge of the bottom surface of the doped semiconductor layer to the right edge of the bottom surface of the doped semiconductor layer.

2. The method for forming a semiconductor device structure as claimed in claim 1 further includes: processing the insulating layer with a silicon implantation process before forming the doped semiconductor layer.

3. The method of forming a semiconductor device structure as claimed in claim 1 or 2, wherein the nitrogen thermal treatment is a first nitrogen thermal treatment, and the method of forming the semiconductor device structure further includes: forming a metal oxide mask over the treated insulating layer; treating the metal oxide mask with a second nitrogen thermal treatment; and removing the metal oxide mask before forming the doped semiconductor layer.

4. A method for forming a semiconductor device structure as claimed in claim 3, wherein: the source / drain notch is located in a first device region, and the method for forming the semiconductor device structure further includes: forming a metal oxide mask over a source / drain structure, wherein the source / drain structure is located in a second device region; removing the metal oxide mask from the treated insulating layer before forming the doped semiconductor layer; and removing the metal oxide mask from the source / drain structure after forming the doped semiconductor layer.

5. The method of forming a semiconductor device structure as claimed in claim 1 or 2 further includes forming an undoped semiconductor layer in the bottom of the source / drain recess before forming the insulating layer, wherein the insulating layer is formed above the undoped semiconductor layer and the undoped semiconductor layer partially fills the source / drain recess.

6. A method of forming a semiconductor device structure, comprising: forming a first source / drain recess in a first device region; forming a second source / drain recess in a second device region; forming a first source / drain structure in the first source / drain recess; and forming a second source / drain structure in the second source / drain recess, wherein the step of forming the second source / drain structure comprises: forming an insulating layer in the second source / drain recess; forming a mask over the first source / drain structure after performing a first nitrogen thermal treatment on the insulating layer; and forming a doped semiconductor layer over the insulating layer after performing a second nitrogen thermal treatment on the mask.

7. The method for forming a semiconductor device structure as claimed in claim 6, wherein the step of performing the first nitrogen thermal treatment includes increasing the thickness of the insulating layer.

8. A method for forming a semiconductor device structure as claimed in claim 6 or 7, wherein: the insulating layer is a first insulating layer; when the first insulating layer is formed, the first device region is unshielded, and the method for forming the semiconductor device structure further includes forming a second insulating layer above the first source / drain structure when the first insulating layer is formed.

9. A method for forming a semiconductor device structure as claimed in claim 6 or 7, wherein: the insulating layer is a first insulating layer; the doped semiconductor layer is a first doped semiconductor layer, and the step of forming the first source / drain structure includes: forming a second insulating layer in the first source / drain recess; and forming a second doped semiconductor layer over the second insulating layer, wherein the second insulating layer is not subjected to nitrogen thermal treatment before forming the second doped semiconductor layer.

10. A semiconductor device structure, comprising: a first type transistor including a first source / drain structure having a first insulating layer and a first doped epitaxial layer disposed on the first insulating layer; and a second type transistor including a second source / drain structure having a second insulating layer and a second doped epitaxial layer disposed on the second insulating layer, wherein the nitrogen concentration of the second insulating layer is greater than the nitrogen concentration of the first insulating layer, and wherein the second insulating layer extends continuously from the left edge of the bottom surface of the second doped epitaxial layer to the right edge of the bottom surface of the second doped epitaxial layer.

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